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rev.0.01, jul.29.2003, page 1 of 29 hn58x2502i HN58X2504I serial peripheral interface 2k eeprom (256-kword 8-bit) 4k eeprom (512-kword 8-bit) electrically erasable and programmable read only memory rej03c0061-0001z preliminary rev. 0.01 jul. 29, 2003 description hn58x25xxx series is the serial peripheral interface (spi) eeprom (electrically erasable and programmable rom). it realizes high speed, low power consumption and a high level of reliability by employing advanced monos memory technology and cmos process and low voltage circuitry technology. it also has a 16-byte page programming function to make it?s write operation faster. note: renesas technology?s serial eeprom are authorized for using consumer applications such as cellular phones, camcorders, audio equipments. therefore, please contact renesas technology?s sales office before using industrial applications such as automotive systems, embedded controllers, and meters. preliminary: the specifications of this device are subject to change without notice. please contact your nearest renesas technology?s sales dept. regarding specifications.
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 2 of 29 features ? single supply: 1.8 v to 5.5 v ? serial peripheral interface (spi bus) ? spi mode 0 (0,0), 3 (1,1) ? clock frequency: 5 mhz (2.5 v to 5.5 v), 3 mhz (1.8 v to 5.5 v) ? power dissipation: ? standby: 3 a (max) ? active (read): 2 ma (max) ? active (write): 2.5 ma (max) ? automatic page write: 16-byte/page ? write cycle time: 5 ms (2.5 v min), 8 ms (1.8 v min) ? endurance: 10 5 cycles ? data retention: 10 years ? small size packages: sop-8pin, tssop-8pin, and son-8pin ? shipping tape and reel ? tssop-8pin : 3,000 ic/reel ? sop-8pin : 2,500 ic/reel ? son-8pin : 3,000 ic/reel ? temperature range: ? 40 to + 85 c ordering information type no. internal organization operating voltage frequency package hn58x2502fpi 2-kbit (256 8-bit) 1.8 v to 5.5 v 5 mhz (2.5 v to 5.5 v) 150mil 8-pin plastic sop (fp-8db) hn58x2504fpi 4-kbit (512 8-bit) 3 mhz (1.8 v to 5.5v) hn58x2502ti 2-kbit (256 8-bit) 1.8 v to 5.5 v 5 mhz (2.5 v to 5.5 v) 8-pin plastic tssop (ttp-8d) hn58x2504ti 4-kbit (512 8-bit) 3 mhz (1.8 v to 5.5 v) hn58x2502ni 2-kbit (256 8-bit) 1.8 v to 5.5 v 5 mhz (2.5 v to 5.5v) 8-pin plastic son (tnp-8da) hn58x2504ni 4-kbit (512 8-bit) 3 mhz (1.8 v to 5.5 v)
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 3 of 29 pin arrangement 8-pin sop/tssop/son (top view) 1 2 3 4 8 7 6 5 v cc hold c d s q w v ss pin description pin name function c serial clock d serial data input q serial data output s chip select w write protect hold hold v cc supply voltage v ss ground
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 4 of 29 block diagram high voltage generator memory array y-select & sense amp. serial-parallel converter address generator control logic y decoder x decoder v cc v ss s w c hold d q
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 5 of 29 absolute maximum ratings parameter symbol value unit supply voltage relative to v ss v cc ?0.6 to + 7.0 v input voltage relative to v ss v in ?0.5* 2 to +7.0* 3 v operating temperature range* 1 topr ?40 to +85 c storage temperature range tstg ?65 to +125 c notes: 1. including electrical characteristics and data retention. 2. v in (min): ?3.0 v for pulse width 50 ns. 3. should not exceed v cc + 1.0 v. dc operating conditions parameter symbol min typ max unit supply voltage v cc 1.8 ? 5.5 v v ss 0 0 0 v input voltage v ih v cc 0.7 ? v cc + 0.5* 2 v v il ?0.3* 1 ? v cc 0.3 v operating temperature range topr ?40 ? + 85 c notes: 1. v in (min): ?1.0 v for pulse width 50 ns. 2. v in (max): v cc + 1.0 v for pulse width 50 ns.
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 6 of 29 dc characteristics parameter symbol min max unit test conditions input leakage current i li ? 2 a v cc = 5.5 v, v in = 0 to 5.5 v ( s , d, c, hold , w ) output leakage current i lo ? 2 a v cc = 5.5 v, v out = 0 to 5.5 v (q) v cc current standby i sb ? 3 a v in = v ss or v cc , v cc = 5.5 v active i cc1 ? 2 ma v cc = 5.5 v, read at 5 mhz v in = v cc 0.1/v cc 0.9 q = open i cc2 ? 2.5 ma v cc = 5.5 v, write at 5 mhz v in = v cc 0.1/v cc 0.9 output voltage v ol1 ? 0.4 v v cc = 5.5 v, i ol = 2 ma v ol2 ? 0.4 v v cc = 2.5 v, i ol = 1.5 ma v oh1 v cc 0.8 ? v v cc = 5.5 v, i ol = ? 2 ma v oh2 v cc 0.8 ? v v cc = 2.5 v, i ol = ? 0.4 ma
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 7 of 29 ac characteristics test conditions input pules levels: ? v il = v cc 0.2 ? v ih = v cc 0.8 input rise and fall time: 10 ns input and output timing reference levels: v cc 0.3, v cc 0.7 output reference levels: v cc 0.5 output load: 100 pf
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 8 of 29 (ta = ? 40 to + 85 c, v cc = 2.5 v to 5.5 v) parameter symbol alt min max unit notes clock frequency f c f sck ? 5 mhz s active setup time t slch t css1 90 ? ns s not active setup time t shch t css2 90 ? ns s deselect time t shsl t cs 90 ? ns s active hold time t chsh t csh 90 ? ns s not active hold time t chsl ? 90 ? ns clock high time t ch t clh 90 ? ns 1 clock low time t cl t cll 90 ? ns 1 clock rise time t clch t rc ? 1 s 2 clock fall time t chcl t fc ? 1 s 2 data in setup time t dvch t dsu 20 ? ns data in hold time t chdx t dh 30 ? ns clock low hold time after hold not active t hhch ? 70 ? ns clock low hold time after hold active t hlch ? 40 ? ns clock high setup time before hold active t chhl ? 60 ? ns clock high setup time before hold not active t chhh ? 60 ? ns output disable time t shqz t dis ? 100 ns 2 clock low to output valid t clqv t v ? 70 ns output hold time t clqx t ho 0 ? ns output rise time t qlqh t ro ? 50 ns 2 output fall time t qhql t fo ? 50 ns 2 hold high to output low-z t hhqx t lz ? 50 ns 2 hold low to output high-z t hlqz t hz ? 100 ns 2 write time t w t wc ? 5 ms notes: 1. t ch + t cl 1/f c 2. value guaranteed by characterization, not 100 % tested in production.
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 9 of 29 (ta = ? 40 to + 85 c, v cc = 1.8 v to 5.5 v) parameter symbol alt min max unit notes clock frequency f c f sck ? 3 mhz s active setup time t slch t css1 100 ? ns s not active setup time t shch t css2 100 ? ns s deselect time t shsl t cs 150 ? ns s active hold time t chsh t csh 100 ? ns s not active hold time t chsl ? 100 ? ns clock high time t ch t clh 150 ? ns 1 clock low time t cl t cll 150 ? ns 1 clock rise time t clch t rc ? 1 s 2 clock fall time t chcl t fc ? 1 s 2 data in setup time t dvch t dsu 30 ? ns data in hold time t chdx t dh 50 ? ns clock low hold time after hold not active t hhch ? 140 ? ns clock low hold time after hold active t hlch ? 90 ? ns clock high setup time before hold active t chhl ? 120 ? ns clock high setup time before hold not active t chhh ? 120 ? ns output disable time t shqz t dis ? 200 ns 2 clock low to output valid t clqv t v ? 120 ns output hold time t clqx t ho 0 ? ns output rise time t qlqh t ro ? 100 ns 2 output fall time t qhql t fo ? 100 ns 2 hold high to output low-z t hhqx t lz ? 100 ns 2 hold low to output high-z t hlqz t hz ? 100 ns 2 write time t w t wc ? 8 ms notes: 1. t ch + t cl 1/f c 2. value guaranteed by characterization, not 100 % tested in production.
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 10 of 29 timing waveforms serial input timing s c t chsl t slch t chdx t clch t chcl t shch t chsh t shsl t dvch msb in lsb in d q high impedance hold timing t chhl s hold c d q t hlch t chhh t hlqz t hhqx t hhch
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 11 of 29 output timing s c d q lsb out addr lsb in t qlqh t qhql t shqz t ch t cl t clqv t clqx t clqv t clqx
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 12 of 29 pin function serial data output (q) this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (c). serial data input (d) this input signal is used to transfer data serially into the device. it receives instructions, addresses, and the data to be written. values are latched on the rising edge of serial clock (c). serial clock (c) this input signal provides the timing of the serial interface. instructions, addresses, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) changes after the falling edge of serial clock (c). chip select ( s s s s ) when this input signal is high, the device is deselected and serial data output (q) is at high impedance. unless an internal write cycle is in progress, the device will be in the standby mode. driving chip select ( s ) low enables the device, placing it in the active power mode. after power-up, a falling edge on chip select ( s ) is required prior to the start of any instruction. hold ( hold hold hold hold ) the hold ( hold ) signal is used to pause any serial communications with the device without deselecting the device. during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. to start the hold condition, the device must be selected, with chip select ( s ) driven low. write protect ( w w w w ) this input signal is used to protect the memory against write instructions. when write protect ( w ) is held low, write instructions (wrsr, write) are ignored. no action on this signal can interrupt a write cycle that has already started.
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 13 of 29 functional description status register the following figure shows the status register format. the status register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. status register format 1 1 1 1 bp1 bp0 wel wip block protect bits write enable latch bits write in progress bits b0 b7 wip bit: the write in progress (wip) bit indicates whether the memory is busy with a write or write status register cycle. wel bit: the write enable latch (wel) bit indicates the status of the internal write enable latch. bp1, bp0 bits: the block protect (bp1, bp0) bits are non-volatile. they define the size of the area to be protected against write instructions.
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 14 of 29 instructions each instruction starts with a single-byte code, as summarized in the following table . if an invalid instruction is sent (one not contained in the following table), the device automatically deselects itself. instruction set instruction description instruction format wren write enable 0000 110 wrdi write disable 0000 100 rdsr read status register 0000 101 wrsr write status register 0000 001 read read from memory array 0000 a011 write write to memory array 0000 a010 notes: 1. ? ? is don?t care. 2. ?a? is a 8 address on the hn58x2504, and don?t care on the hn58x2502.
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 15 of 29 write enable (wren): the write enable latch (wel) bit must be set prior to each write and wrsr instruction. the only way to do this is to send a write enable instruction to the device. as shown in the following figure, to send this instruction to the device, chip select ( s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait state. it waits for the device to be deselected, by chip select ( s ) being driven high. write enable (wren) sequence s w c d q instruction 0123456 high-z v ih v il v ih v il v ih v il v ih v il 7
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 16 of 29 write disable (wrdi): one way of resetting the write enable latch (wel) bit is to send a write disable instruction to the device. as shown in the following figure, to send this instruction to the device, chip select ( s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait state. it waits for the device to be deselected, by chip select ( s ) being driven high. the write enable latch (wel) bit, in fact, becomes reset by any of the following events: ? power-up ? wrdi instruction execution ? wrsr instruction completion ? write instruction completion ? write protect ( w ) is driven low write disable (wrdi) sequence s w c d q instruction 1 0 234567 high-z v ih v il v ih v il v ih v il v ih v il
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 17 of 29 read status register(rdsr): the read status register (rdsr) instruction allows the status register to be read. the status register may be read at any time, even while a write or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status register continuously, as shown in the following figure. read status register (rdsr) sequence s w c d q status register out 01234567 0 1 2 3 4 5 6 77 8 9 10 11 12 13 14 15 high-z v ih v il v ih v il v ih v il v ih v il the status and control bits of the status register are as follows: wip bit: the write in progress (wip) bit indicates whether the memory is busy with a write or write status register cycle. when set to 1, such a cycle is in progress. when reset to 0, no such cycles are in progress. wel bit: the write enable latch (wel) bit indicates the status of the internal write enable latch. when set to 1, the internal write enable latch is set. when set to 0, the internal write enable latch is reset and no write or write status register instructions are accepted. bp1, bp0 bits: the block protect (bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against write instructions. these bits are written with the write status register (wrsr) instruction. when one or both of the block protect (bp1, bp0) bits are set to 1, the relevant memory area (as defined in the status register format table) becomes protected against write (write) instructions. the block protect (bp1, bp0) bits can be written provided that the hardware protected mode has not been set.
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 18 of 29 write status register (wrsr): the write status register (wrsr) instruction allows new values to be written to the status register. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded and executed, the device sets the write enable latch(wel). the instruction sequence is shown in the following figure. the write status register (wrsr) instruction has no effect on b6, b5, b4, b1 and b0 of the status register. b6, b5 and b4 are always read as 0. chip select ( s ) must be driven high after the rising edge of serial clock (c) that latches in the eighth bit of the data byte, and before the next rising edge of serial clock (c). otherwise, the write status register (wrsr) instruction is not executed. as soon as chip select ( s ) is driven high, the self-timed write status register cycle (whose duration is t w ) is initiated. while the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed write status register cycle, and is 0 when it is completed. when the cycle is completed, write enable latch(wel) is reset. the write status register (wrsr) instruction allows the user to change the values of the block protect (bp1, bp0) bits, to define the size of the area that is to be treated as read-only, as defined in the status register format table. the contents of block protect (bp1, bp0) bits are frozen at their current values just before the start of the execution of the write status register (wrsr) instruction. the new, updated values take effect at the moment of completion of the execution of write status register (wrsr) instruction. write status register (wrsr) sequence s w c d q status register in msb 01234567 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 high-z v ih v il v ih v il v ih v il v ih v il
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 19 of 29 read from memory array (read): as shown in the following figure, to send this instruction to the device, chip select ( s ) is first driven low. the bits of the instruction byte and the address bytes are then shifted in, on serial data input (d). the addresses are loaded into an internal address register, and the byte of data at that address is shifted out, on serial data output (q). the most significant address (a8) should be sent as fifth bit in the instruction byte. if chip select ( s ) continues to be driven low, the internal address register is automatically incremented, and the byte of data at the new address is shifted out. when the highest address is reached, the address counter rolls over to zero, allowing the read cycle to be continued indefinitely. the whole memory can, therefore, be read with a single read instruction. the read cycle is terminated by driving chip select ( s ) high. the rising edge of the chip select ( s ) signal can occur at any time during the cycle. the addressed first byte can be any byte within any page. the instruction is not accepted, and is not executed, if a write cycle is currently in progress. read from memory array (read) sequence s w c d q 8-bit address data out 2 data out 1 01234567 a0 a1 a2 a3 a5 a6 a7 a8 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 high-z v ih v il v ih v il v ih v il v ih v il 0 1 2 3 4 5 6 77 instruction note: 1. depending on the memory size, as shown in the following table, the most significant address bits are don?t care. address range bits device HN58X2504I hn58x2502i address bits a8 to a0 a7 to a0 note: 1. a8 is don?t care on the hn58x2402.
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 20 of 29 write to memory array (write): as shown in the following figure, to send this instruction to the device, chip select ( s ) is first driven low. the bits of the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (d). the instruction is terminated by driving chip select ( s ) high at a byte boundary of the input data. in the case of the following figure, this occurs after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. the self-timed write cycle starts, and continues for a period t wc (as specified in ac characteristics). at the end of the cycle, the write in progress (wip) bit is reset to 0. if, though, chip select ( s ) continues to be driven low, as shown in the following figure, the next byte of the input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal write cycle. each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. if the number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the beginning of the page, and the previous data there are overwritten with the incoming data. (the page size of these device is 32 bytes). the instruction is not accepted, and is not executed, under the following conditions: ? if the write enable latch (wel) bit has not been set to 1 (by executing a write enable instruction just before) ? if a write cycle is already in progress ? if the addressed page is in the region protected by the block protect (bp1 and bp0) bits. ? if write protect ( w ) is low
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 21 of 29 byte write (write) sequence (1 byte) s w c d q 8-bit address data byte 1 01234567 0 1 2 3 a5 a6 a7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 high-z v ih v il v ih v il v ih v il v ih v il 4 5 6 7 a0 a1 a2 a3 instruction a8 note: 1. depending on the memory size, as shown in address range bits table, the most significant address bit is don?t care.
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 22 of 29 byte write (write) sequence (page) s w c d q 8-bit address data byte 1 01234567 0 1 2 3 a5 a6 a7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 high-z v ih v il v ih v il v ih v il v ih v il 4 5 6 7 a0 a1 a2 a3 instruction s w c d q data byte 3 data byte n 24 25 26 27 28 29 30 31 7 32 33 34 35 36 37 38 39 high-z v ih v il v ih v il v ih v il 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 data byte 2 a8 note: 1. depending on the memory size, as shown in address range bits table, the most significant address bit is don?t care.
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 23 of 29 data protect the block protect bits (bp1, bp0) define the area of memory that is protected against the execution of write cycle, as summarized in the following table. when write protect ( w ) is driven low, write to memory array (write) and write status register (wrsr) are disabled, and wel bit is reset. write protected block size status register bits array addresses protected bp1 bp0 protected blocks HN58X2504I hn58x2502i 0 0 none none none 0 1 upper quarter 180h ? 1ffh c0h ? ffh 1 0 upper half 100h ? 1ffh 80h ? ffh 1 1 whole memory 000h ? 1ffh 00h ? ffh
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 24 of 29 hold condition the hold ( hold ) signal is used to pause any serial communications with the device without resetting the clocking sequence. during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. to enter the hold condition, the device must be selected, with chip select ( s ) low. normally, the device is kept selected, for the whole duration of the hold condition. deselecting the device while it is in the hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. the hold condition starts when the hold ( hold ) signal is driven low at the same time as serial clock (c) already being low (as shown in the following figure). the hold condition ends when the hold ( hold ) signal is driven high at the same time as serial clock (c) already being low. the following figure also shows what happens if the rising and falling edges are not timed to coincide with serial clock (c) being low. hold condition activation c hold hold status hold status
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 25 of 29 notes data protection at v cc on/off when v cc is turned on or off, noise on s inputs generated by external circuits (cpu, etc) may act as a trigger and turn the eeprom to unintentional program mode. to prevent this unintentional programming, this eeprom have a power on reset function. be careful of the notices described below in order for the power on reset function to operate correctly. ? s should be fixed to v cc during v cc on/off. low to high or high to low transition during v cc on/off may cause the trigger for the unintentional programming. ? v cc should be turned on/off after the eeprom is placed in a standby state. ? v cc should be turned on from the ground level (v ss ) in order for the eeprom not to enter the unintentional programming mode. ? v cc turn on speed should be slower than 10 s/v. ? when wrsr or write instruction is executed before v cc turns off, v cc should be turned off after waiting write cycle time (t w ).
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 26 of 29 package dimensions hn58x2502fpi/hn58x2504fpi (fp-8db) package code jedec jeita mass (reference value) fp-8db ? ? 0.08 g *dimension including the plating thickness base material dimension 0 ? ?8 ? 1.27 8 5 1 4 0.10 0.25 m 1.73 max 3.90 *0.22 4.89 0.14 + 0.114 0.038 0.69 max 6.02 0.18 + 0.034 0.017 0.60 + 0.289 0.194 1.06 0.40 0.06 0.20 0.03 5.15 max *0.42 +0.063 0.064 as of january, 2003 unit: mm
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 27 of 29 hn58x2502ti/hn58x2504ti (ttp-8d) 0.50 0.10 0 ? 8 ? *0.17 0.05 6.40 0.20 0.10 1.10 max 0.13 m 0.65 14 85 4.40 3.00 3.30 max 0.805 max *0.22 +0.08 0.07 0.07 +0.03 0.04 0.20 0.06 0.15 0.04 1.0 package code jedec jeita mass (reference value) ttp-8d *dimension including the plating thickness base material dimension as of january, 2003 unit: mm
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 28 of 29 hn58x2502ni/hn58x2504ni (tnp-8da) + 0.08 0.07 + 0.055 0.045 0.22 *0.18 0.05 0.16 0.025 3.00 3.60 3.10 max 4.06 0.1 0.23 0.125 0.02 *0.145 0.675 max 14 85 0.80 max 0.65 0.08 m 0.10 package code jedec jeita mass (reference value) tnp-8da 0.022 g *dimension including the plating thickness base material dimension as of january, 2003 unit: mm
hn58x2502i/HN58X2504I rev.0.01, jul.29.2003, page 29 of 29 keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but ther e is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation p roduct best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporat ion or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, origin ating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reas ons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest produ ct information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracie s or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas te chnology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp oration assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used un der circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor wh en considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or u ndersea repeater use. 6. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lic ense from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com copyright ? 2003. renesas technology corporation, all rights reserved. printed in japan. colophon 0.0

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