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this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. june 2012 doc id 15234 rev 4 1/34 34 VNI8200XP octal high-side smart power solid state relay with serial/parallel selectable interface on chip datasheet ? preliminary data features output current: 0.7 a per channel serial/parallel selectable interface short-circuit protection 8-bit and 16-bit spi interface for ic command and control diagnostic channel overtemperature detection and protection thermal independence of separate channels drives all type of loads (resistive, capacitive, inductive load) loss of gnd protection power good diagnostic undervoltage shutdown with hysteresis overvoltage protection (v cc clamping) very low supply current common fault open drain output ic warning temperature detection channels output enable 100 ma high efficiency step-down switching regulator with integrated boot diode adjustable regulator output switching regulator disable 5 v and 3.3 v compatible i/os channel outputs status led driving 4 x 2 multiplexed array fast demagnetization of inductive loads esd protection designed to meet iec 61131-2, iec61000-4-4, and iec61000-4-5 applications programmable logic control industrial pc peripheral input/output numerical control machines type v demag (1) 1. per channel r ds(on) (1) i out (1) v cc VNI8200XP v cc -45 v 0.11 ? 0.7 a 45 v table 1. device summary part number package packing VNI8200XP powersso-36 tube VNI8200XPtr tape and reel powersso-36 www.st.com
contents VNI8200XP 2/34 doc id 15234 rev 4 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1 power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.4 logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.5 protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.6 step-down switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.7 led driving array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 functional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 spi/parallel selection mode (sel2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2 serial data in (sdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.3 serial data out (sdo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.4 serial data clock (clk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.5 slave select (ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.6 8/16-bit selection (sel1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.7 output enable (out_en) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.8 ic warning case temperature detection (twarn ) . . . . . . . . . . . . . . . . . . 16 6.9 fault indication (fault ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.10 power good (pg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.11 programmable watchdog counter reset (wd) . . . . . . . . . . . . . . . . . . . . . 18 7 spi operation (sel2 = h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.1 8-bit spi mode (sel1 = l) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VNI8200XP contents doc id 15234 rev 4 3/34 7.2 16-bit spi mode (sel1 = h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8 led driving array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9 step-down switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10 conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11 thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11.1 thermal behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12 interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 13 switching parameters test c onditions . . . . . . . . . . . . . . . . . . . . . . . . . 27 14 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
description VNI8200XP 4/34 doc id 15234 rev 4 1 description the VNI8200XP is a monolithic 8-channel driver featuring a very low supply current, with integrated spi interface and high efficiency 100 ma micropower step-down switching regulator peak current control loop mode. the ic, realized in stmicroelectronics? vipower? technology, is intended for driving any kind of load with one side connected to ground. active channel current limitation combined with thermal shutdown, independent for each channel, and automatic restart, protect the device against overload. additional embedded functions are: loss of gnd protection that automatically turns off the device outputs in case of ground disconnection, undervoltage shutdown with hysteresis, power good diagnostic for valid supply voltage range recognition, output enable function for immediate power outputs on/off, and programmable watchdog function for microcontroller safe operation; case overtemperature protection to control the ic case temperature. the device embeds a four-wire spi serial peripheral with selectable 8 or 16-bit operations; through a select pin the device can also operate with a parallel interface. both the 8-bit and 16-bit spi operations are compatible with daisy chain connection. the spi interface allows command of the output driver by enabling or disabling each channel featuring, in 16-bit format, a parity check control for communication robustness. it also allows the monitoring of the status of the ic signaling power good, overtemperature condition for each channel, ic pre-warning temperature detection. built-in thermal shutdown protects the chip from overtemperature and short-circuit. in overload condition, the channel turns off and on again automatically after the ic temperature decreases below a threshold fixed by a temperature hysteresis so that junction temperature is controlled. if this condition makes case temperature reaching case temperature limit, t csd , overloaded channels are turned off and restart, non- simultaneously, when case and junction temperature decrease below their own reset threshold. if the case of thermal reset, the channels loaded are not switched on until the junction temperature reset event. non-overloaded channels continue to operate normally. case temperature above t csd is reported through the twarn open drain pin. an internal circuit provides a not latched common fault indicator reporting if one of the following events occurs: channel ovt (overtemperature), parity check fail. the power good diagnostic warns the controller that the supply voltage is below a fixed threshold. the watchdog function is used to detect the occurrence of a software fault of the host controller. the watchdog circuitry generates an internal reset on expiry of the internal watchdog timer. the watchdog timer reset can be achieved by applying a negative pulse on the wd pin. the watchdog function can be disabled by the wd_en dedicated pin. this pin also allows the programming of a wide range of watchdog timings. an internal led matrix driver circuitry (4 rows, 2 columns) allows the detection of the status of the single outputs. an integrated step-down voltage regulator provides supply voltage to the internal led matrix driver and logic output buffers and can be used to supply the external optocouplers if the application requires isolation. the regulator is protected against short-circuit or overload conditions by means of pulse-by-pulse current limit with a peak current control loop.
VNI8200XP block diagram doc id 15234 rev 4 5/34 2 block diagram figure 1. block diagram $#6$$ 6cc #lamp $#$# #o nverter 30) ,ogic #lamp0owe r *un ction4e m p $etection 5ndervoltageand 0ower'ood ,%$ $rivng #ase 4e m p $etection #urrent,imiter &" 3%,). 7$?%.). /54?%.). 7$). 3$)). #,+). 33 ). 3$/). 3%, 6 2%' 2/7 2/7 2/7 2/7 #/, #/, &!5,4 '.$ /54 /54 /54 /54 /54 /54 /54 /54 0(!3% "//4 6 2%& 0' 6 ## 0ull down resistor 47!2. !-v
pin connection VNI8200XP 6/34 doc id 15234 rev 4 3 pin connection figure 2. pin connection (top view) table 2. pin description pin name type description 1 sel2 logic input spi/parallel selection mode 2 sel1/in1 logic input 8/16-bit spi selection mode/channel 1 input 3 wd_en/ in2 logic/analog input watchdog enable_setting/channel 2 input 4 out_en /in3 logic input output enable/channel 3 input 5 wd/in4 logic input watchdog input. the internal watchdog counter is cleared on the falling edges/channel 4 input. 6 sdi/in5 logic input serial data input/channel 5 input 7 clk/in6 logic input serial clock/channel 6 input 8ss /in7 logic input slave select/channel 7 input 9 sdo/in8 logic input/output serial data output/channel 8 input 10 vreg power supply spi/inputs/led supply voltage 11 col0 open source output led source output 12 col1 open source output led source output 13 dcvdd analog output internally generated dc-dc low voltage supply. (to be connected to external 10 nf capacitor). 14 vref analog output internally generated dc-dc voltage reference. (to be connected to external 10 nf capacitor). 3%, 3%,). 7$?%.). /54?%.). 7$). 3$)). #,+). 33). 62%' #/, #/, $# 6$$ 62%& 2/7 2/7 2/7 2/7 0' &!5,4 47 !2 . &" '.$ 0(!3% "//4 .# /54 /54 /54 /54 /54 /54 /54 /54 .# .# 3$/). 4!"6cc ".w
VNI8200XP pin connection doc id 15234 rev 4 7/34 pin name type description 15 row0 open drain output status channel 1-2 16 row1 open drain output status channel 3-4 17 row2 open drain output status channel 5-6 18 row3 open drain output status channel 7-8 19 pg open drain output power good diagnostic - active low 20 fault open drain output fault indication - active low 21 twarn open drain output ic case warning temperature detection - active low 22 fb analog input step-down feedback input. connecting the output voltage directly to this pin results in an output voltage of 3.3 v. an external resistor divider is required for higher output voltages. 23 gnd ground 24 phase power output step-down output 25 boot power output step-down bootstrap voltage. used to provide a drive voltage, higher than the supply voltage, to power the switch of the step-down regulator. 26 nc not connected 27 out8 power output channel 8 power output 28 out7 power output channel 7 power output 29 out6 power output channel 6 power output 30 out5 power output channel 5 power output 31 out4 power output channel 4 power output 32 out3 power output channel 3 power output 33 out2 power output channel 2 power output 34 out1 power output channel 1 power output 35 nc not connected 36 nc not connected tab tab power supply exposed tab internally connected to v cc table 2. pin description (continued)
maximum ratings VNI8200XP 8/34 doc id 15234 rev 4 4 maximum ratings table 3. absolute maximum ratings symbol parameter value unit v cc power supply voltage 45 v -v cc reverse supply voltage -0.3 v v reg logic supply voltage -0.3 to +6 v v fault v twarn v pg voltage range at pins twarn , fault , pg -0.3 to +6 v v boot bootstrap peak voltage v phase = v cc v cc +6 v v row voltage range at row pins -0.3 to +6 v v col voltage range at col pins -0.3 to +6 v v dig voltage level range at logic input pins -0.3 to +6 v i out output current (continuous) internally limited (1) a i r reverse output current (per channel) -5 a i gnd dc ground reverse current -250 ma i reg v reg input current -1/10 ma i fault i twarn, i pg current range at pins twarn , fault , pg -1 to +10 ma i in input current range -1 to +10 ma i row current range at row pins (row in on state) +20 ma current range at row pins (row in off state) -1 to +10 ma i col current range at col pins (col in on state) -10 ma current range at col pins (col in off state) -1 to +10 ma v esd electrostatic discharge (r = 1.5 k ? ; c = 100 pf) 2000 v e as single pulse avalanche energy per channel not simultaneously 300 mj p tot power dissipation at t c = 25 c internally limited (1) 1. protection functions are intended to avoid ic damage in fault conditions and are not intended for continuous operation. continuous and repetitive operat ion of protection functions may reduce the ic lifetime. w t j junction operating temperature internally limited c t stg storage temperature -55 to 150 c
VNI8200XP electrical characteristics doc id 15234 rev 4 9/34 4.1 thermal data 5 electrical characteristics 5.1 power section 10.5 v < v cc < 36 v; -40 c < t j < 125 c; unless otherwise specified. table 4. thermal data symbol parameter value unit r th(jc) thermal resistance junction-case (1) 1. per channel. max. 2 c/w r th(ja) thermal resistance junction-ambient (2) 2. when mounted using minimum recommended pad size on fr-4 board (for details refer to section 11 ). max. 52 c/w table 5. power section symbol parameter test conditions min. typ. max. unit v cc supply voltage 10.5 36 v v cc clamp clamp on v cc 45 50 52 v r ds(on) on state resistance i out = 0.5 a at t j = 25 c i out = 0.5 a 0.11 0.2 ? i s v cc supply current all channels in off state, dc- dc in off state, v reg =5 v, spi off (1) 1. ss signal high, no communication. 1ma all channels in on state, dc- dc in on state v reg =5 v, spi on (2) 2. ss signal low, communication on. tbd tbd ma i ds v reg supply current dc-dc off v reg = 5 v spi off wd_en=0 tbd ma dc-dc on v reg =5 v spi on wd_en=v reg tbd ma i lgnd output current at gnd disconnection all pins at 24 v except v out = 0 v 0.5 ma v out(off) off state output voltage v in = 0 v, iout = 0 a 3 v i out(off) off state output current v in = v out = 0 v 0 5 a f cp charge pump frequency channel in on state (3) 3. to cover en55022 class a and class b normatives. 1.45 mhz
electrical characteristics VNI8200XP 10/34 doc id 15234 rev 4 5.2 spi characteristics 10.5 v < v cc < 36 v; 2.7 v < v reg < 5 v; -40 VNI8200XP electrical characteristics doc id 15234 rev 4 11/34 5.4 logic inputs 10.5 v < v cc < 36 v; -40 c < t j < 125 c; unless otherwise specified. 5.5 protection and diagnostic 10.5 v < v cc < 36 v; -40 c < t j < 125 c; unless otherwise specified. table 8. logic inputs symbol parameter test conditions min. typ. max. unit v il input low level voltage 0.8 v v ih input high level voltage 2.20 v v i(hyst) input hysteresis voltage 0.15 v i in input current v in = 5 v 8 a table 9. protection and diagnostic symbol parameter test conditions min. typ. max. unit v pgh1 power good diagnostic on threshold 16.6 17.5 18.4 v v pgh2 power good diagnostic off threshold 15.6 16.5 17.4 v pghys power good diagnostic hysteresis 1 v usd undervoltage on protection 9.5 10.5 v undervoltage off protection 9v v usdhys undervoltage hysteresis 0.4 0.5 v v demag output voltage at turn- off i out = 0.5 a; l load 1 mh v cc -52 v cc -50 v cc -45 v v twarn twarn pin low-state output voltage i twarn = 3 ma (active condition) 0.6 v v fault fault pin low-state output voltage i fault = 3 ma (fault condition) 0.6 v v pg pg pin low-state output voltage i pg = 3 ma (active condition) v reg =3.3 v v cc =0 0.7 v i peak maximum dc output current 1.4 a i lim short-circuit current limitation per channel r load = 0 0.7 1.1 1.7 a hyst i lim tracking limits r load = 0 0.3 a
electrical characteristics VNI8200XP 12/34 doc id 15234 rev 4 5.6 step-down switching regulator 10.5 v < v cc < 36 v; -40 c < t j < 125 c ; unless otherwise specified. i lfault fault leakage current v pin = 5 v 2 a i twarn twarn leakage current i pg pg leakage current t tsd junction shutdown temperature 150 170 c t r junction reset temperature 150 c t hist junction thermal hysteresis 20 c t csd case shutdown temperature 115 130 145 c t cr case reset temperature 110 c t chyst case thermal hysteresis 20 c t wd watchdog hold time see figure 6 50 ns t wm watchdog time see ta bl e 1 3 and figure 6 t out_en out_en pin propagation delay (1) t d(off) ms t res out_en hold time 50 ns t wo watchdog timeout (2) t wm + t d(off) ms 1. time from reset active low and power out disable. 2. the time from t wm elapsed to power out disable. table 9. protection and diagnostic (continued) symbol parameter test conditions min. typ. max. unit table 10. step-down switching regulator symbol parameter test conditions min. typ. max. unit v dc_out regulated output voltage ireg from 0 to 100 ma vreg 3.3 v, figure 8. 3.135 3.3 3.465 v ireg from 0 to 100 ma vreg 5 v, figure 10. 5 v fb voltage feedback 3.135 3.3 3.465 v r dson mosfet on-resistance 1.5 ? i dc_out regulator output current 100 ma i peak maximum peak current 0.5 a
VNI8200XP electrical characteristics doc id 15234 rev 4 13/34 5.7 led driving array 10.5 v < v cc < 36 v; -40 c < t j < 125 c ; unless otherwise specified. i qop total operating quiescent current tbd ma i qst-by total standby quiescent current regulator standby tbd a i bootleak bootstrap reverse leakage current tbd a f s switching frequency 400 khz d max maximum duty cycle 80% % to n min minimum on-time tbd ns table 10. step-down switching regulator (continued) symbol parameter test conditions min. typ. max. unit table 11. led driving array symbol parameter test conditions min. typ. max. unit v col output source voltage at col pins output current 0 to 7 ma v reg -0.3 v reg -0.2 v v row open drain voltage at row pins output current 0 to 15 ma 0.2 0.3 v fsw row refresh frequency with duty=25% 780 hz
functional pin description VNI8200XP 14/34 doc id 15234 rev 4 6 functional pin description 6.1 spi/parallel selection mode (sel2) this pin allows the selection of the ic interfacing mode. the spi interface is selected if sel2 = h, while the parallel interface is selected if sel2 = l, according to ta bl e 1 2 : 6.2 serial data in (sdi) if sel2 = h, this pin is the input of the serial control frame. sdi is read on clk rising edges and, therefore, the microcontroller must change sdi state during the clk falling edges. after the ss falling edge, the sdi is equal to the most significant bit of the control frame ( figure 3 ). 6.3 serial data out (sdo) if sel2 = h, this pin is the output of the serial fault frame. sdo is updated on clk falling edges and, therefore, the microcontroller must read sdo state during the clk rising edges. the sdo pin is tri-stated when ss signal is high and it is equal to the most significant bit of the fault frame after the ss falling edge ( figure 3 ). table 12. pin description pin function sel2 (1) = h spi operation 1. sel2 has an internal weak pull-down. sel2 = l parallel operation sdo/in8 sdo serial data output in8 input to channel 8 ss /in7 ss slave select in7 input to channel 7 clk/in6 clk serial clock in6 input to channel 6 sdi/in5 sdi serial data input in5 input to channel 5 wd/in4 wd watchdog input in4 input to channel 4 out_en/in3 out_en ic output enable / disable in3 input to channel 3 wd_en/in2 wd_en watchdog enable / disable and timing preset in2 input to channel 2 sel1/in1 sel1 8/16-bit spi selection mode in1 input to channel 1
VNI8200XP functional pin description doc id 15234 rev 4 15/34 6.4 serial data clock (clk) if sel2 = h, the clk line is the input clock for serial data sampling. on clk rising edge the sdi input is sampled by the ic and the sdo output is sampled by the host microcontroller. on clk falling edge, both sdi and sdo lines are updated to the next bit of the frame, from the most to the less significant one (see figure 3 ). when the ss signal is high, slave not selected, the microcontroller should drive the clk low (the settings for the mcu spi port are cpha = 0 and cpol = 0). 6.5 slave select (ss ) if sel2 = h, the slave select (ss ) signal is used to enable the VNI8200XP serial communication shift register; data is flushed-in through the sdi pin and flushed-out from the sdo pin only when the ss pin is low. on the ss pin falling edge the shift register (containing the fault conditions) is frozen, so any change on the power switches status is latched until the next ss falling edge event and the sdo output is enabled. on the ss pin rising edge event the 8/16 bits present on the spi shift register are evaluated and the outputs are driven according to this frame. if more than 8/16 bits (depending on the spi settings) are flushed inside only the last 8/16 are evaluated; the others are flushed out from the sdo pin after fault condition bits; in this way a proper communication is possible also in a daisy chain configuration. figure 3. spi mode diagram 6.6 8/16-bit selection (sel1) if sel2 = h, sel1 is used to select between two possible spi configurations: the 8-bit spi mode (sel1 = l) and the 16-bit spi mode (sel1 = h). 8/16-bit spi operation is described below.
functional pin description VNI8200XP 16/34 doc id 15234 rev 4 6.7 output enable (out_en) if sel2 = h, the out_en pin provides a fast way to disable all the outputs simultaneously. when the out_en pin is driven low for at least t res , the outputs are disabled while fault conditions in the spi register are latched. to enable the outputs it is then necessary to raise the out_en pin and re-program the ic through the spi interface. as fault conditions are latched inside the ic and spi interface is working also while the out_en pin is driven low, it?s possible to use spi to detect if a fault condition occurred before the reset event. the device is ready to operate normally after a t su period. the out_en pin is the fastest way to disable all the outputs when a fault occurs. figure 4. output channel enable/disable behavior 6.8 ic warning case temperature detection (twarn ) the twarn pin is an active low open drain output. this pin is activated if the ic case temperature exceeds t csd . according to the pcb thermal design and r thjc value, this function allows a warning about a pcb overheating condition to be given. the twarn bit is also available through spi. this bit is not latched: the twarn pin is low only while the case overtemperature condition is active (t c > t csd ) and is released when this condition is removed (t c < t cr ). out_en vin( i) out(i) t t t t out_en am12 8 24v1
VNI8200XP functional pin description doc id 15234 rev 4 17/34 6.9 fault indication (fault ) the fault pin is an open drain active low fault indication pin. this pin is activated by one or more of the following conditions: channel overtemperature (ovt) this pin is activated when at least one of the channels is in junction overtemperature. unlike the spi fault detection bits, this signal is not latched: the fault pin is low only when the fault condition is active and is released if the input driving signal is off or after the ovt protection condition has been removed. this last event occurs if the channel temperature decreases below the threshold level and the case temperature has not exceeded tcsd or is below tcr. this means that the fault pin is low only while the junction overtemperature is active (t j >t tsd ) and is released after this condition has been removed (t j < t r and t c < t cr ). parity check fail when spi mode is used (sel2 = h), if a parity check fault of the incoming spi frame is detected or counted, clk rising edges are different by a multiple of 8, the fault pin is kept low. when counted clk rising edges are a multiple of 8 and parity check is valid, the fault pin is kept high. 6.10 power good (pg) the pg terminal is an open drain, that indicates the status of the supply voltage. when v cc supply voltage reaches the vsth1 threshold, pg goes into a high impedance state. it goes into a low impedance state when v cc falls below the vsth2 threshold. in 16-bit spi mode, a pg bit is also available. this bit is set high when the power good diagnostic is active, it is otherwise cleared. figure 5. power good diagnostic 6cc 0' 60'( 60'( !-v
functional pin description VNI8200XP 18/34 doc id 15234 rev 4 6.11 programmable watchdog counter reset (wd) if sel2 = h, the VNI8200XP embeds a watchdog counter that must be erased, with a negative pulse on the wd pin, before it expires. if the wd counter elapses, the VNI8200XP goes into an internal reset state where all the outputs are disabled; to restart normal operation a negative pulse must be applied at the wd pin. the watchdog enable/disable pin should be connected through an external divider to v reg . the watchdog time is fixed following ta b l e 1 3 : table 13. programmable watchdog time v wd_en t wm 0.25 v reg > v wd_en disable 0.25 v reg v wd_en < 0.5 v reg 40 10% ms 0.5 v reg v wd_en < 0.75 v reg 80 10% ms 0.75 v reg v wd_en = v reg 160 10% ms figure 6. watchdog reset wd t wd t wm t am11 8 02v1
VNI8200XP spi operation (sel2 = h) doc id 15234 rev 4 19/34 7 spi operation (sel2 = h) 7.1 8-bit spi mode (sel1 = l) if sel2 = h, the 8-bit spi mode is based on an 8-bit command frame sent from the microcontroller to the ic; each bit directly drives the corresponding output where lsb drives output 0 and msb drives output 7. each bit, set to ?1?, activates (closes) the corresponding output. at the same time, the ic transfers the channel fault conditions (ovt) to the microcontroller. these fault conditions are latched at the occurrence and cleared after each communication (each time the ss signal has a positive transition). each bit, set to ?1?, indicates an ovt condition for the corresponding channel. 7.2 16-bit spi mode (sel1 = h) the 16-bit spi mode is based on a 16-bit command frame sent from the microcontroller to the ic; the first 8 bits directly drive the output channels (each bit, set to ?1?, activates the corresponding output), the other 8 bits contain a 4-bit parity check code where the last bit (the inversion of the previous one) is used to detect a communication error condition (providing at least a transition in each frame): p0 = in0 in1 in2 in3 in4 in5 in6 in7 p1 = in1 in3 in5 in7 p2 = in0 in2 in4 in6 np0 = not p0 at the same time, the ic transfers to the microcontroller a 16-bit fault frame where the first 8 bits indicate a channel fault (ovt) condition (each bit, set to ?1?, indicates an ovt event), the following 4 bits provide general fault condition information. fb_ok: this bit is related to the dc-dc regulation: at the dc-dc turn-on, this bit is low and becomes high after fb rises above 90% of the nominal v fb voltage and a correct spi communication occurred. if the fb voltage falls below 80% of the nominal v fb voltage, this bit is zero; twarn (ic warning table 14. command 8-bit frame (master to slave) msb lsb in7 in6 in5 in4 in3 in2 in1 in0 table 15. fault 8-bit frame (slave to master) msb lsb f7 f6 f5 f4 f3 f2 f1 f0 table 16. command 16-bit frame (master to slave) msb lsb in7 in6 in5 in4 in3 in2 in1 in0 - - - - p2 p1 p0 np0
spi operation (sel2 = h) VNI8200XP 20/34 doc id 15234 rev 4 case temperature, see section 6.8 ), pc (parity check fail, the bit, set to ?1?, indicates a pc fail or the length is not a multiple of 8) and pg (power good, see section 6.10 ). the last 4 bits are used as parity check bits and communication error condition (see command 16 bit frame): p0 = f0 f1 f2 f3 f4 f5 f6 f7 p1 = pc fb_ok f1 f3 f5 f7 p2 = pg twarn f0 f2 f4 f6 np0 = not p0 channel indications are latched and cleared only after a communication. table 17. fault 16-bit frame slave to master msb lsb f7 f6 f5 f4 f3 f2 f1 f0 fb_ok twarn pc pg p2 p1 p0 np0
VNI8200XP led driving array doc id 15234 rev 4 21/34 8 led driving array figure 7. led driving array the following is an indication of how to choose the r ext resistors value. equation 1 note: i f(led) 7 ma. where (v col min.) and (v row max.) can be found in ta b l e 1 1 and v f(led) and i f(led) depend on the electrical characteristics of the leds. 2/7 2/7 2/7 2/7 #/, #/, 6 2%' 34!453 34!453 34!453 34!453 34!453 34!453 34!453 34!453 !-v r ext v colmin () v rowmax () v fled () ? ? i fled () ------------------------------------------------------------------------------------------- - =
step-down switching regulator VNI8200XP 22/34 doc id 15234 rev 4 9 step-down switching regulator the ic embeds a high efficiency 100 ma micropower step-down switching regulator. the regulator is protected against short-circuit or overload conditions. pulse-by-pulse current limit regulation is obtained in normal operation through a current loop control. a low esr output capacitor connected to the vreg pin helps to limit the regulated voltage ripple; a low esr (less than 10 m ? ) capacitor is preferable. the control loop pin fb allows 3.3 v to be regulated, connecting it directly to v reg , or 5 v connecting it through a voltage divider rl/rfbl. the dc-dc converter can be turned off by connecting the feedback pin to the dcvdd pin. in some applications it is possible to supply a 5 v or 3.3 v voltage externally or, in the case of two or more VNI8200XPs inside the same board, it's possible to configure the dc-dc converter on only one device and supply also the other ics.
VNI8200XP conventions doc id 15234 rev 4 23/34 10 conventions figure 8. typical circuit for switching regulation v dc-out = 3.3 v low%32mohm-,# # # n& 2 k 2 k , u (2)sm! # n& # u& 6reg 3%, 3%,) . 7$?%.). /54?% .). 7$). 3$)). #,+). 33) . 3$/). 62%' #/, #/, $#6$$ 62%& 2/7 2/7 2/7 2/7 0' &!5,4 47!2. &" '.$ 0(!3% "//4 .# /54 /54 /54 /54 /54 /54 /54 /54 .# .# 6.) # n & # n & )reg 4ab6cc !-v
conventions VNI8200XP 24/34 doc id 15234 rev 4 figure 9. typical circuit for switching regulation v dc-out = 5 v figure 10. spi directional logic convention low%32mohm -,# # 2 k 3% , 3%,). 7$?%.). /54?% .). 7$). 3$)). #,+). 33). 3$/). 62%' #/, #/, $#6$$ 62%& 2/7 2/7 2/7 2/7 0' &!5,4 47!2. &" '.$ 0(!3% "//4 .# /54 /54 /54 /54 /54 /54 /54 /54 .# .# 6.) # n& 2 k 2 k , u(2)sm! # n& # u& # n & # n & 6reg )reg 4ab6cc !-v 3$) 33 #,+ 3$/ 7$ /54?%. 7$?%. 3%, 3%, 0' &!5,4 47!2. /54 /54 /54 /54 /54 /54 /54 /54 '.$ 6reg 4!"6cc !-v
VNI8200XP thermal management doc id 15234 rev 4 25/34 11 thermal management the power dissipation in the ic is the main factor that sets the safe operating condition of the device in the application. therefore, it must be taken into account very carefully. heatsinking can be achieved using copper on the pcb with proper area and thickness. the following image ( figure 11 ) shows the junction-to-ambient thermal impedance values for the psso36 package. figure 11. psso36 thermal impedance vs. time for instance, three cases have been considered using a psso36 packaged with copper slug soldered on a 1.6 mm thickness fr4 board with dissipating footprint (copper thickness of 70 m): single layer pcb with just ic footprint dissipating area double layer pcb with footprint dissipating area on the top side and a 2 cm 2 dissipating layer on the bottom side through 15 via holes double layer pcb with footprint dissipating area on the top side and an 8 cm 2 dissipating layer on the bottom side through 15 via holes.
thermal management VNI8200XP 26/34 doc id 15234 rev 4 11.1 thermal behavior figure 12. thermal behavior note: 1 thermal shutdown. 2 junction hysteresis. 3 restore to idle condition. 4 case hysteresis. ./ 4 ji 4 tsd 6i n i ( /54 i /ff 34 !4 i /n, 4 c4 csd ./ 9%3 ./ 9%3 4 c4 cr 9%3 ./ 4 ji 4 jr 9%3 34 !4 i /ff( /54 i /n !-v 1 2 4 3
VNI8200XP interface timing diagram doc id 15234 rev 4 27/34 12 interface timing diagram figure 13. serial timing 13 switching parameters test conditions figure 14. dv/dt (on) and dv/dt (off) time diagram test conditions t f t r d6/. d6/&& 6out t !-v
switching parameters test conditions VNI8200XP 28/34 doc id 15234 rev 4 figure 15. t d(on) and t d(off) time diagram test conditions !-v ^^ 9 ? 9 ? 9 ? ~ke ? s}? ? ? ~k&&
VNI8200XP package mechanical data doc id 15234 rev 4 29/34 14 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. table 18. powersso-36 mechanical data symbol mm min. typ. max. a 2.15 2.47 a2 2.15 2.40 a1 0 0.075 b 0.18 0.36 c 0.23 0.32 d 10.10 10.50 e7.4 7.6 e0.5 e3 8.5 f2.3 g 0.075 g1 0.06 h 10.1 10.5 h 0.4 l 0.55 0.85 m4.3 n 10deg o1.2 q0.8 s2.9 t3.65 u1.0 x 4.1 4.7 y 4.9 5.5
package mechanical data VNI8200XP 30/34 doc id 15234 rev 4 figure 16. powersso-36 package dimensions figure 17. powersso-36 tube shipment (no suffix) note: all dimensions are in mm. table 19. powersso-36 tube shipment base q.ty 49 bulk q.ty 1225 tube length ( 0.5) 532 a 3.5 b 13.8 c ( 0.1) 0.6
VNI8200XP package mechanical data doc id 15234 rev 4 31/34 figure 18. powersso-36 reel shipment (suffix ?tr?) table 20. powersso-36 reel dimensions base q.ty 1000 bulk q.ty 1000 a (max.) 330 b (min.) 1.5 c ( 0.2) 13 f 20.2 g (2 0) 24.4 n (min.) 100 t (max.) 30.4
package mechanical data VNI8200XP 32/34 doc id 15234 rev 4 figure 19. powersso-36 tape dimensions note: according to the electronic industries association (eia) standard 481 rev. a, feb 1986. table 21. powersso-36 tape dimensions tape width w 24 tape hole spacing p0 ( 0.1) 4 component spacing p 12 hole diameter d ( 0.05) 1.55 hole diameter d1 (min.) 1.5 hole position f ( 0.1) 11.5 compartment depth k (max.) 2.85 hole spacing p1 ( 0.1) 2
VNI8200XP revision history doc id 15234 rev 4 33/34 15 revision history table 22. document revision history date revision changes 04-dec-2008 1 initial release 29-apr-2009 2 updated table 5 on page 9 19-jun-2012 3 updated: features , section 6.4 , section 6.7 , section 6.9 , section 6.10 , section 9 , ta bl e 2 , ta b l e 3 , ta bl e 5 , ta bl e 7 , table 8 , ta bl e 9 , ta bl e 1 0 , ta bl e 1 1 , table 13 , figure 1 , figure 2 . changed: figure 4 , figure 5 , figure 6 , figure 14 , figure 15 . content reworked to improve the readability. 27-jun-2012 4 changed: symbols in 16-bit frame section 7.2 .
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