View 82378ZB_5652637.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

e information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel?s terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. other brands and names are the property of their respective owners. ? intel corporation 1996 march 1996 order number: 290571-001 provides the bridge between the pci bus and isa bus 100% pci and isa compatible ? ? pci and isa master/slave interface ? ? directly drives 10 pci loads and 6 isa slots ? ? pci at 25 mhz and 33 mhz ? ? isa from 6 mhz to 8.33 mhz enhanced dma functions ? ? scatter/gather (s/g) (82378ZB) ? ? fast dma type a, b and f (82378ZB) ? ? compatible dma transfers ? ? 32-bit addressability(82378ZB) ? ? 27-bit addressability(82379ab) ? ? seven independently programmable channels ? ? functionality of two 82c37a dma controllers data buffers to improve performance ? ? 8-byte dma/isa master line buffer ? ? 32-bit posted memory write buffer to isa integrated 16-bit bios timer non-maskable interrupts (nmi) ? ? pci system err ors ? ? isa parity errors arbitration for isa devices ? ? isa masters ? ? dma and refresh four dedicated pci interrupts ? ? level sensitive ? ? mapped to any unused interrupt arbitration for pci devices ? ? six pci masters suppor ted ? ? fixed, rotating, or a combination utility bus (x-bus) peripheral support ? ? provides chip select decode ? ? controls lower x-bus data byte transceiver functionality of one 82c54 timer ? ? system timer ? ? refresh request ? ? speaker tone output functionality of two 82c59 interrupt controllers ? ? 14 interrupts supported ? ? edge/level selectable interrupts i/o apic (advanced programmable interrupt controller (82379ab) ? ? support for multi-processor systems system power management (intel smm support) ? ? programmable system management interrupt (smi) ? ? hardware events, software events, extsmi# ? ? programmable cpu clock control (stpclk#) ? ? fast-on/off mode 208-pin qfp package the 82378ZB system i/o (sio) and 82379ab system i/o apic (sio.a) components are pci-to-isa bus bridge devices. these devices integrate many of the common i/o functions found in today's isa-based pc systems ? a seven channel dma controller, two 82c59 interrupt controllers, an 8254 timer/counter, a bios timer, intel smm power management support, and logic for nmi generation. in addition, the sio and sio.a each support a total of six pci masters, and four pci interrupts. decode is provided for peripheral devices such as the flash bios, real time clock, keyboard/mouse controller, floppy controller, two serial ports, one parallel port, and ide hard disk drive. for both the sio and sio.a, each dma channel supports compatibility transfers. the sio also supports types a, b, and f transfers and scatter/gather. in addtion to the standard isa-compatible interrupt controller that is in both the sio and sio.a, the sio.a contains an advance programmable interrupt controller (io apic) for use in multi-processing systems. this document describes both the 82378ZB (sio) and 82379ab (sio.a) components. unshaded areas describe the 82378ZB. shaded areas, like this one, describe differences between the 82379ab and 82378ZB. 82378ZB system i/o (sio) and 82379ab system i/o apic (sio.a)
82378 zb (sio) and 82379ab (sio.a) e 2 req0#/siognt# dreq[7:5,3:0] data buffers pci decode isa decode pci bus interface isa bus interface pci arbiter interrupt timers/ counters d m a pciclk pcirst# ad[31:0] c/be#[3:0] frame# irdy# trdy# stop# lock# devsel# serr# par idsel memcs# req1# cpureq# gnt0#/sioreq# gnt1#/resume# cpugnt# memreq# memack# int nmi irq[15,14, 11:9,7:3,1] d a c k [ 7 : 5 , 3 : 0 ] # t c ( 8 2 3 7 9 a b ) refresh# sd[15:0] sa[19:0] la[23:17] iocs16# memcs16# sbhe# master# memr# memw# aen iochrdy iochk# sysclk bale ior# iow# smemr# smemw# zerows# rstdrv s p k r / t e s t o ubustr ubusoe# e c s a d d r [ 2 : 0 ] ecsen# dskchg alt_rst# alt_a20 ferr#/irq13 ignne# utility bus support logic osc flshreq# irq12/m irq8# test test bios timer spkr/testo req[3:2]# gnt[3:2]# pirq[3:0]# smi# stpclk# extsmi# init cpu interface i / o a p i c ( 8 2 3 7 9 a b o n l y ) apicclk a p i c d [ 1 : 0 ] e o p ( 8 2 3 7 8 z b ) sio_a_bk.drw note: i/o apic signals are only on the 82379ab. also, spkr/testo are only multiplexed on the 82379ab and are separate signals on the 82378ZB. the master# signal is only on the 82378ZB. 82378ZB sio and 82379ab sio.a component block diagram
e 82378 zb (sio) and 82379 (sio.a) 3 contents page 1.0. architectural overview ................................ ................................ ................................ .................... 9 2.0. signal description ................................ ................................ ................................ ............................... 12 2.1. pci bus interface signals ................................ ................................ ................................ ............. 13 2.2. pci arbiter signals ................................ ................................ ................................ ........................... 14 2.3. address decoder signal ................................ ................................ ................................ ............... 16 2.4. power management signals ................................ ................................ ................................ ........ 17 2.5. isa interface signals ................................ ................................ ................................ ...................... 17 2.6. dma signals ................................ ................................ ................................ ................................ .......... 19 2.7. timer signal ................................ ................................ ................................ ................................ ......... 20 2.8. interrupt controller signals ................................ ................................ ................................ .. 21 2.9. apic bus signals (82379ab only) ................................ ................................ ................................ .. 22 2.10. utility bus signals ................................ ................................ ................................ .......................... 22 2.11. test signals ................................ ................................ ................................ ................................ ....... 24 3.0. register description ................................ ................................ ................................ .......................... 25 3.1. sio configuration register description ................................ ................................ ............. 32 3.1.1. vid?vendor identification register ................................ ................................ ............... 32 3.1.2. did?device identification register ................................ ................................ ................. 33 3.1.3. com?command register ................................ ................................ ................................ ........ 33 3.1.4. ds?device status register ................................ ................................ ................................ . 34 3.1.5. rid?revision identification register ................................ ................................ ............. 34 3.1.6. pcicon?pci control register ................................ ................................ ............................ 35 3.1.7. pac?pci arbiter control register ................................ ................................ ................. 36 3.1.8. papc?pci arbiter priority control register ................................ ............................ 37 3.1.9. arbprix?pci arbiter priority control extension register ............................... 39 3.1.10. mcscon-memcs# control register ................................ ................................ ................. 39 3.1.11. mcsboh?memcs# bottom of hole register ................................ ............................... 40 3.1.12. mcstoh?memcs# top of hole register ................................ ................................ ........ 40 3.1.13. mcstom?memcs# top of memory register ................................ ................................ . 41 3.1.14. iadcon?isa address decoder control register ................................ ................... 41 3.1.15. iadrbe?isa address decoder rom block enable register ............................... 42 3.1.16. iadboh?isa address decoder bottom of hole register ................................ .... 42 3.1.17. iadtoh?isa address decoder top of hole register ................................ ............ 42 3.1.18. icrt?isa controller recovery timer register ................................ ..................... 43 3.1.19. icd?isa clock divisor register ................................ ................................ ....................... 44 3.1.20. ubcsa?utility bus chip select a register ................................ ................................ . 45 3.1.21. ubcsb?utility bus chip select b register ................................ ................................ . 46 3.1.22. mar1?memcs# attribute register #1 ................................ ................................ ............ 47
82378 zb (sio) and 82379ab (sio.a) e 4 3.1.23. mar2?memcs# attribute register #2 ................................ ................................ ............. 47 3.1.24. mar3?memcs# attribute register #3 ................................ ................................ ............. 48 3.1.25. pirq[3:0]#?pirq route control registers ................................ ................................ ... 48 3.1.26. pacc?pic/apic configuration control register (82379ab only) ........................ 49 3.1.27. apicbase?apic base address relocation (82379ab only) ................................ ....... 49 3.1.28. bios timer base address register ................................ ................................ .................. 50 3.1.29. smicntl?smi control register ................................ ................................ ........................ 50 3.1.30. smien?smi enable register ................................ ................................ ................................ 51 3.1.31. see?system event enable register ................................ ................................ .............. 51 3.1.32. ftmr?fast off timer register ................................ ................................ ......................... 52 3.1.33. smireq?smi request register ................................ ................................ .......................... 53 3.1.34. ctltmr?clock scale stpclk# low timer ................................ ................................ ..... 54 3.1.35. ctltmrh?clock scale stpclk# high timer ................................ ................................ . 54 3.2. dma register description ................................ ................................ ................................ ............. 55 3.2.1. dcom?dma command register ................................ ................................ ............................ 55 3.2.2. dcm?dma channel mode register ................................ ................................ .................... 55 3.2.3. dcem?dma channel extended mode register (82378ZB only) ................................ 56 3.2.4. dr?dma request register ................................ ................................ ................................ .... 59 3.2.5. mask register?write single mask bit ................................ ................................ ............. 59 3.2.6. mask register?write all mask bits ................................ ................................ ................. 60 3.2.7. ds?dma status register ................................ ................................ ................................ ....... 60 3.2.8. dma base and current address registers (8237 compatible segment) ......... 61 3.2.9. dma base and current byte/word count registers (8237 compatible segment) ................................ ................................ ................................ ................................ ................ 61 3.2.10. dma memory base low page and current low page registers ....................... 62 3.2.11. dma memory base high page and current high page registers ...................... 62 3.2.12. dma clear byte pointer register ................................ ................................ .................... 63 3.2.13. dmc?dma master clear register ................................ ................................ ................... 64 3.2.14. dcm?dma clear mask register ................................ ................................ ........................ 64 3.2.15. scatter/gather (s/g) command register (82378ZB only) ................................ ......... 64 3.2.16. scatter/gather (s/g) status register (82378ZB only) ................................ .............. 65 3.2.17. scatter/gather (s/g) descriptor table pointer register (82378ZB only) ..... 67 3.2.18. scatter/gather (s/g) interrupt status register (82378ZB only) ....................... 67 3.3. timer register description ................................ ................................ ................................ ......... 68 3.3.1. tcw?timer control word register ................................ ................................ ................ 68 3.3.2. interval timer status byte format register ................................ ............................. 70 3.3.3. counter access ports register ................................ ................................ ....................... 71 3.3.4. bios timer register ................................ ................................ ................................ ................... 71 3.4. interrupt controller register description ................................ ................................ .... 72 3.4.1. icw1?initialization command word 1 register ................................ ........................... 72 3.4.2. icw2?initialization command word 2 register ................................ ........................... 73 3.4.3. icw3?initialization command word 3 register ................................ ........................... 73
e 82378 zb (sio) and 82379 (sio.a) 5 3.4.4. icw3?initialization command word 3 register ................................ ........................... 73 3.4.5. icw4?initialization command word 4 register ................................ ........................... 74 3.4.6. ocw1?operational control word 1 register ................................ ........................... 74 3.4.7. ocw2?operational control word 2 register ................................ ........................... 75 3.4.8. ocw3?operational control word 3 register ................................ ........................... 76 3.5. control registers ................................ ................................ ................................ ........................... 77 3.5.1. nmisc?nmi status and control register ................................ ................................ ..... 77 3.5.2. nmi enable and real-time clock address register ................................ .................. 78 3.5.3. port 92 register ................................ ................................ ................................ ......................... 78 3.5.4. digital output register ................................ ................................ ................................ ......... 79 3.5.5. reset ubus irq1/irq12 register ................................ ................................ .......................... 79 3.5.6. coprocessor error register ................................ ................................ ............................ 80 3.5.7. elcr?edge/level control register ................................ ................................ ............... 80 3.6. power management registers ................................ ................................ ................................ ... 80 3.6.1. apmc?advanced power management control port ................................ .............. 81 3.6.2. apms?advanced power management status port ................................ .................. 81 3.7. apic registers (82379ab only) ................................ ................................ ................................ ...... 81 3.7.1. ioregsel?i/o register select register (82379ab only) ................................ ............ 82 3.7.2. iowin?i/o window register (82379ab only) ................................ ................................ ....... 82 3.7.3. apicid?i/o apic identification register (82379ab only) ................................ .............. 82 3.7.4. apicid?i/o apic version register (82379ab only) ................................ ........................... 83 3.7.5. apicarb?i/o apic arbitration register (82379ab only) ................................ ............... 83 3.7.6. ioredtbl[15:0]?i/o redirection table registers (82379ab only) ............................. 83 4.0. functional description ................................ ................................ ................................ .................... 86 4.1. memory and i/o address map ................................ ................................ ................................ ....... 86 4.1.1. memory address map (generating memcs#) ................................ ................................ . 86 4.1.2. bios memory space ................................ ................................ ................................ .................... 87 4.1.3. i/o accesses ................................ ................................ ................................ ................................ .. 87 4.1.4. subtractively decoded cycles to isa ................................ ................................ ............ 88 4.1.5. utility bus encoded chip selects ................................ ................................ ..................... 88 4.2. pci interface ................................ ................................ ................................ ................................ ....... 88 4.2.1. pci command set ................................ ................................ ................................ ......................... 88 4.2.2. transaction termination ................................ ................................ ................................ ....... 89 4.3. pci arbitration controller ................................ ................................ ................................ ........ 90 4.3.1. arbitration signal protocol ................................ ................................ .............................. 90 4.3.2. internal/external arbiter configuration ................................ ................................ ... 91 4.3.3. guaranteed access time mode ................................ ................................ ................................ ........ 92 4.3.3.1. dma latencies in gat mode only (82378ZB only) ................................ .................... 92 4.4. isa interface ................................ ................................ ................................ ................................ ....... 92 4.4.1. isa clock generation ................................ ................................ ................................ ............... 93 4.5. dma controller ................................ ................................ ................................ ................................ . 93
82378 zb (sio) and 82379ab (sio.a) e 6 4.5.1. dma timings ................................ ................................ ................................ ................................ .... 94 4.5.1.1. compatible timing (82378ZB and 82379ab) ................................ ................................ ... 95 4.5.1.2. type "a" timing (82378ZB) ................................ ................................ ................................ ..... 95 4.5.1.3. type "b" timing (82378ZB) ................................ ................................ ................................ ..... 95 4.5.1.4. type "f" timing (82378ZB) ................................ ................................ ................................ ..... 95 4.5.1.5. dreq and dack# latency control (82378ZB and 82379ab) ................................ .. 95 4.5.2. isa refresh cycles (82378ZB and 82379ab) ................................ ................................ ......... 95 4.5.3. scatter/gather (s/g) description (82378ZB) ................................ ................................ ... 95 4.6. data buffering ................................ ................................ ................................ ................................ ... 98 4.6.1. dma/isa master line buffer ................................ ................................ ................................ ... 98 4.6.2. pci master posted write buffer ................................ ................................ ........................ 98 4.7. sio timers ................................ ................................ ................................ ................................ ............... 98 4.7.1. interval timers ................................ ................................ ................................ ........................... 98 4.7.2. bios timer ................................ ................................ ................................ ................................ ........ 99 4.8. interrupt controller ................................ ................................ ................................ .................. 100 4.8.1. edge and level triggered modes ................................ ................................ .................... 101 4.8.2. non-maskable interrupt (nmi) ................................ ................................ ............................ 101 4.9. advanced programmable interrupt controller (apic) (82379ab only) ............... 102 4.9.1. physical characteristics of apic bus (82379ab only) ................................ .............. 105 4.9.2. arbitration for apic bus (82379ab only) ................................ ................................ .......... 105 4.9.3. intr and the pentium processor?s "through local mode" (82379ab only) .... 105 4.9.4. pulsing of apicd1 during cpu reset (82379ab only) ................................ ................... 107 4.9.5. sio.a asserting signals low during pcirst# (82379ab only) ................................ 111 4.10. utility bus peripheral support ................................ ................................ ............................. 111 4.11. power management ................................ ................................ ................................ ...................... 116 4.11.1. smm mode ................................ ................................ ................................ ................................ .... 117 4.11.2. smi sources ................................ ................................ ................................ ............................... 117 4.11.3. smi# and init interaction ................................ ................................ ................................ .... 118 4.11.4. clock control ................................ ................................ ................................ ......................... 119 4.11.5. dual-processor power management support (82379ab only) ........................... 120 4.11.5.1. smi# delivery mechanism ................................ ................................ ............................. 120 4.11.5.2. stpclk# tied to both sockets ................................ ................................ ................... 120 4.11.5.3. smi#/intr (apic mode) ................................ ................................ ................................ ....... 121 4.11.6. interrupt levels and system event generation in power managed systems (82378ZB only) ................................ ................................ ................................ .................... 121 4.12. design considerations (82378ZB/82379ab) ................................ ................................ ........... 121 4.12.1. good layout practice ................................ ................................ ................................ ..................... 121 4.12.2. asynchronously switching signals ................................ ................................ ............ 121 5.0. electrical characteristics ................................ ................................ ................................ ......... 122 5.1. maximum ratings ................................ ................................ ................................ .............................. 122 6.0. pin assignment ................................ ................................ ................................ ................................ ...... 123
e 82378 zb (sio) and 82379 (sio.a) 7 7.0. mechanical specifications ................................ ................................ ................................ ........... 127 7.1. package diagram ................................ ................................ ................................ ............................. 127 7.2. thermal specifications ................................ ................................ ................................ ............... 128 8.0. testability ................................ ................................ ................................ ................................ ............. 128 8.1. global tri-state ................................ ................................ ................................ .............................. 128 8.2. nand tree ................................ ................................ ................................ ................................ ............ 128 8.3. nand tree cell order ................................ ................................ ................................ ................... 129 8.4. nand tree diagram ................................ ................................ ................................ ......................... 137
82378 zb (sio) and 82379ab (sio.a) e 8
e 82378 zb (sio) and 82379 (sio.a) 9 1. 0. architectural overview the major functions of the sio and sio.a components are broken up into blocks as shown in the sio and sio.a component block diagrams. a description of each block is provided below. pci bus interface the pci bus interface provides the interface between the sio/sio.a and the pci bus. the sio/sio.a provides both a master and slave interface to the pci bus. as a pci master, the sio/sio.a runs cycles on behalf of dma, isa masters, and the internal data buffer management logic when buffer flushing is required. the sio/sio.a bursts a maximum of two dwords when reading from pci memory, and one dword when writing to pci memory. the sio/sio.a does not generate pci i/o cycles as a master. as a pci slave, the sio/sio.a accepts cycles initiated by pci masters targeted for the sio/sio.a internal register set or the isa bus. the sio/sio.a accepts a maximum of one data transaction before terminating the transaction. this supports the incremental latency mechanism as defined in the peripheral component interconnect (pci) specification. as a master, the sio/sio.a generates address and command signal (c/be#) parity for read and write cycles, and data parity for write cycles. as a slave, the sio/sio.a generates data parity for read cycles. parity checking is not supported. the sio/sio.a also provides support for system error reporting by generating a non- maskable-interrupt (nmi) when serr# is driven active. the sio/sio.a, as a resource, can be locked by any pci master. in the context of locked cycles, the entire sio/sio.a subsystem (including the isa bus) is considered a single resource. the sio/sio.a directly supports the pci interface running at either 25 mhz or 33 mhz. if a frequency of less than 33 mhz is required (not including 25 mhz), a sysclk divisor value (as indicated in the isa clock divisor register) must be selected that guarantees that the isa bus frequency does not violate the 6 mhz to 8.33 mhz sysclk range. pci arbiter the pci arbiter provides support for six pci masters; the host bridge, sio/sio.a, and four pci masters. the arbiter can be programmed for a purely rotating scheme, fixed, or a combination of the two. the arbiter can also be programmed to support bus parking. this gives the host bridge default access to the pci bus when no other device is requesting service. the arbiter can be disabled if an external arbiter is used. data buffers to isolate the slower isa bus from the pci bus, the sio/sio.a provides two types of data buffers. one dword- deep posted write buffer is provided for the posting of pci initiated memory write cycles to the isa bus. the second buffer is a bi-directional, 8-byte line buffer used for isa master and dma accesses to the pci bus. all dma and isa master read and write cycles go through the 8-byte line buffer. the data buffers also provide the data assembly or disassembly when needed for transactions between the pci and isa buses. buffering is programmable and can be enabled or disabled through software. isa bus interface the sio/sio.a incorporates a fully isa-bus compatible master and slave interface. the sio/sio.a directly drives six isa slots without external data or address buffering. the isa interface also provides byte swap logic, i/o recovery support, wait-state generation, and sysclk generation. the sio/sio.a supports isa bus frequencies from 6 to 8.33 mhz.
82378 zb (sio) and 82379ab (sio.a) e 10 as an isa master, the sio/sio.a generates cycles on behalf of dma, refresh, and pci master initiated cycles. the sio/sio.a supports compressed cycles when accessing isa slaves (i.e., zerows# asserted). as an isa slave, the sio/sio.a accepts isa master accesses targeted for the sio/sio.a internal register set or isa master memory cycles targeted for the pci bus. the sio/sio.a does not support isa master initiated i/o cycles targeted for the pci bus. the sio/sio.a also monitors isa master to isa slave cycles to generate smemr# or smemw#, and to support data byte swapping, if necessary. dma the dma controller in the sio/sio.a incorporates the functionality of two 82c37 dma controllers with seven independently programmable channels. each channel can be programmed for 8- or 16-bit dma device size. the dma controller is also responsible for generating isa refresh cycles. for the 82378ZB, isa-compatible or fast dma type "a", type "b", or type "f" timings are supported and 32-bit addressing is supported as an extension of the isa-compatible specification. the sio supports an enhanced feature called scatter/gather (s/g). this feature provides the capability of transferring multiple buffers between memory and i/o without cpu intervention. in s/g mode, the dma can read the memory address and word count from an array of buffer descriptors, located in system memory, called the s/g descriptor (sgd) table. this allows the dma controller to sustain dma transfers until all of the buffers in the sgd table are read. for the sio.a, the dma supports 8-/16-bit device size using isa-compatible timings and 27-bit addressing as an extension of the isa-compatible specification. scatter/gather is not supported. timer block the timer block contains three counters that are equivalent in function to those found in one 82c54 programmable interval timer. these three counters are combined to provide the system timer function, refresh request, and speaker tone. the three counters use the 14.31818 mhz osc input for a clock source. in addition to the three counters, the sio/sio.a provides a programmable 16-bit bios timer. this timer can be used by bios software to implement timing loops. the timer uses the isa system clock (sysclk) divided by 8 as a clock source. an 8:1 ratio between the sysclk and the bios timer clock is always maintained. the accuracy of the bios timer is 1 ms. utility bus (x-bus) logic the sio/sio.a provides four encoded chip selects that are decoded externally to provide chip selects for flash bios, real time clock, keyboard/mouse controller, floppy controller, two serial ports, one parallel port, and an ide hard disk drive. the sio/sio.a provides the control for the buffer that isolates the lower 8 bits of the utility bus from the lower 8 bits of the isa bus. in addition to providing the encoded chip selects and utility bus buffer control, the sio/sio.a also provides port 92 functions (alternate reset and alternate a20), coprocessor error reporting, the floppy dskchg function, and a mouse interrupt input. interrupt controller block the sio/sio.a provides an isa compatible interrupt controller that incorporates the functionality of two 82c59 interrupt controllers. the two interrupt controllers are cascaded so that 14 external and two internal interrupts are possible.
e 82378 zb (sio) and 82379 (sio.a) 11 advanced programmable interrupt controller (apic) (sio.a only) in addition to the standard isa-compatible interrupt controller described above, the sio.a incorporates the advanced programmable interrupt controller (apic). while the standard interrupt controller is intended for use in a uni-processor system, apic can be used in either a uni-processor or multi-processor system. apic provides multi-processor interrupt management and incorporates both static and dynamic symmetric interrupt distribution across all processors. in systems with multiple i/o subsystems, each subsystem can have its own set of interrupts. power management extensive power management capability permits a system to operate in a low power state without being powered down. once in the low power state (called 'fast-off' state), the computer appears to be off. for example, the system memory management (smm) code could turn off the crt, line printer, hard disk drive's spindle motor, and fans. in addition, the cpu's clock can be governed. to the user, the machine appears to be in the off state. however, the system is actually in an extremely low power state that still permits the cpu to function and maintain communication connections normally associated with today's desktops (e.g., lan, modem, or fax). programmable options provide power management flexibility. for example, various system events can be programmed to place the system in the low power state or break events can be programmed to wake the system up. test the test block provides the interface to the test circuitry within the sio/sio.a. the test input can be used to tri- state all of the sio/sio.a outputs.
82378 zb (sio) and 82379ab (sio.a) e 12 2. 0. signal descrip tion this section contains a detailed description of each signal. the signals are arranged in functional groups according to the interface. note that the '#' symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. when '#' is not present after the signal name, the signal is asserted when at the high voltage level. the terms assertion and negation are used extensively. this is done to avoid confusion when working with a mixture of 'active-low' and 'active-high' signals. the term assert , or assertion indicates that a signal is active, independent of whether that level is represented by a high or low voltage. the term negate , or negation indicates that a signal is inactive. the following notations are used to described the signal type. signal type description i input is a standard input-only signal. o totem pole output is a standard active driver. od open drain input/output. io input/output is a bidirectional, tri-state pin. s/t/s sustained tri-state is an active low tri-state signal owned and driven by one and only one agent at a time. the agent that drives a s/t/s pin low must drive it high for at least one clock before letting it float. a new agent can not start driving a s/t/s signal any sooner than one clock after the previous owner tri-states it. a pull-up sustains the inactive state until another agent drives it and is provided by the central resource. t/s/o tri-state output
e 82378 zb (sio) and 82379 (sio.a) 13 2.1. pci bus interface signals signal name type description pciclk i pci clock: pciclk provides timing for all transactions on the pci bus. all other pci signals are sampled on the rising edge of pciclk, and all timing parameters are defined with respect to this edge. frequencies supported by the sio/sio.a include 25 and 33 mhz. pcirst# i pci reset: pcirst# forces the sio/sio.a to a known state. ad[31:0], c/be[3:0]#, and par are always driven low by the sio/sio.a synchronously from the leading edge of pcirst#. the sio/sio.a always tri-states these signals from the trailing edge of pcirst#. if the internal arbiter is enabled (cpureq# sampled high on the trailing edge of pcirst#), the sio/sio.a will drive these signals low again (synchronously 2-5 pciclks later) until the bus is given to another master. if the internal arbiter is disabled (cpureq# sampled low on the trailing edge of pcirst#), these signals remain tri-stated until the sio/sio.a is required to drive them valid as a master or slave. frame#, irdy#, trdy#, stop#, devsel#, memreq#, flshreq#, cpugnt#, gnt0#/sioreq#, and gnt1#/resume# are tri-stated from the leading edge of pcirst#. frame#, irdy#, trdy#, stop#, and devsel# remain tri-stated until driven by the sio/sio.a as either a master or a slave. memreq#, flshreq#, cpugnt#, gnt0#/sioreq#, and gnt1#/resume# are tri-stated until driven by the sio/sio.a. after pcirst#, memreq# and flshreq# are driven inactive asynchronously from pcirst# inactive. cpugnt#, gnt0#/sioreq#, and gnt1#/resume# are driven based on the arbitration scheme and the asserted reqx#'s. all registers are set to their default values. pcirst# may be asynchronous to pciclk when asserted or negated. although asynchronous, negation must be a clean, bounce-free edge. note that pcirst# must be asserted for more than 1 s. ad[31:0] i/o pci address/data . the standard pci address and data lines. the address is driven with frame# assertion and data is driven or received in following clocks. c/be[3:0]# i/o bus command and byte enables: the command is driven with frame# assertion. byte enables corresponding to supplied or requested data are driven on following clocks. frame# i/o (s/t/s) c ycle frame: assertion indicates the address phase of a pci transfer. negation indicates that one more data transfer is desired by the cycle initiator. frame# is tri- stated from the leading edge of pcirst#. trdy# i/o (s/t/s) target ready: asserted when the target is ready for a data transfer. trdy# is tri-stated from the leading edge of pcirst#. irdy# i/o (s/t/s) initiator ready: asserted when the initiator is ready for a data transfer. irdy# is tri-stated from the leading edge of pcirst#. stop# i/o (s/t/s) stop: asserted by the target to request the master to stop the current transaction. stop# is tri-stated from the leading edge of pcirst#. lock# i lock: lock# indicates an atomic operation that may require multiple transactions to complete. lock# is always an input to the sio/sio.a. idsel i initialization device select: idsel is used as a chip select during configuration read and write transactions.
82378 zb (sio) and 82379ab (sio.a) e 14 signal name type description devsel# i/o (s/t/s) device select: the sio/sio.a asserts devsel# to claim a pci transaction through positive or subtractive decoding. devsel# is tri-stated from the leading edge of pcirst#. devsel# remains tri-stated until driven by the sio/sio.a as either a master or a slave. pirq[3:0]# i pci interrupt request: pirq# s are used to generate asynchronous interrupts to the cpu via the programmable interrupt controllers (82c59s) integrated in the sio/sio.a. these signals are defined as level sensitive and are asserted low. the pirqx# interrupts can be steered into any unused irq interrupt. the pirqx# route control register determines which irq interrupt each pci interrupt is steered into. these pins include a weak internal pull-up resistor. par o calculated parity signal: a single parity bit is provided over ad[31:0] and c/be[3:0]. par is always driven low by the 82379ab synchronously from the leading edge of pcirst#. serr# i system error: serr# can be pulsed active by any pci device that detects a system error condition. upon sampling serr# active, the sio/sio.a generates a non-maskable interrupt (nmi) to the cpu. 2.2. pci arbiter signals signal name type description cpureq# i cpu request: this signal provides the following functions: 1. if cpureq# is sampled high on the trailing edge of pcirst#, the internal arbiter is enabled. if cpureq# is sampled low on the trailing edge of pcirst#, the internal arbiter is disabled. this requires that the host bridge drive cpureq# high during pcirst#. 2. if the sio/sio.a internal arbiter is enabled, this pin is configured as cpureq#. an active low assertion indicates that the cpu initiator desires the use of the pci bus. if the internal arbiter is disabled, this pin is meaningless after reset. this pin has a weak internal pull-up resistor. req0#/ siognt# i request 0/sio grant: if the sio/sio.a internal arbiter is enabled, this pin is configured as req0#. an active low assertion indicates that initiator0 desires the use of the pci bus. if the internal arbiter is disabled, this pin is configured as siognt#. when asserted, siognt# indicates that the external pci arbiter has granted use of the bus to the sio/sio.a. this pin has a weak internal pull-up resistor. req1# i request 1: if the sio/sio.a internal arbiter is enabled through the arbiter configuration register, then this signal is configured as req1#. an active low assertion indicates that initiator1 desires the use of the pci bus. if the internal arbiter is disabled, the sio/sio.a ignores req1# after reset. this pin has a weak internal pull-up resistor.
e 82378 zb (sio) and 82379 (sio.a) 15 signal name type description cpugnt# t/s/o cpu grant: if the sio/sio.a internal arbiter is enabled, this pin is configured as cpugnt#. the sio/sio.a internal arbiter asserts cpugnt# to indicate that the cpu initiator has been granted the pci bus. if the internal arbiter is disabled, this signal is meaningless. cpugnt# is tri-stated from the leading edge of pcirst#. cpugnt# is tri-stated until driven by the sio/sio.a. cpugnt# is driven based on the arbitration scheme and the asserted reqx#s. gnt0#/ sioreq# t/s/o grant 0/sio request: if the sio/sio.a internal arbiter is enabled, this pin is configured as gnt0#. the sio/sio.a internal arbiter asserts gnt0# to indicate that initiator0 has been granted the pci bus. if the internal arbiter is disabled, this pin is configured as sioreq#. the sio/sio.a asserts sioreq# to request the pci bus. gnt0#/sioreq# is tri-stated from the leading edge of pcirst#. gnt0#/sioreq# is tri-stated until driven by the sio/sio.a. gnt0#/sioreq# is driven based on the arbitration scheme and the asserted reqx#'s. gnt1#/ resume# t/s/o grant 1/resume: if the sio's internal arbiter is enabled, this pin is configured as gnt1#. the sio/sio.a internal arbiter asserts gnt1# to indicate that initiator1 has been granted the pci bus. if the internal arbiter is disabled, this pin is configured as resume#. the sio/sio.a asserts resume# to indicate that the conditions causing the sio/sio.a to retry the cycle has passed. gnt1#/resume# is tri- stated from the leading edge of pcirst#. gnt1#/resume# is tri-stated until driven by the sio/sio.a. gnt1#/resume# is driven based on the arbitration scheme and the asserted reqx#'s. req2# i request 2: this pin is an active low signal that indicates that initiator2 desires the use of the pci bus. this signal has a weak internal pull-up resistor. req3# i request 3: this pin is an active low signal that indicates that initiator3 desires the use of the pci bus. this signal has a weak internal pull-up resistor. gnt2# t/s/o grant 2: this pin is configured as gnt2#. the sio/sio.a internal arbiter asserts gnt2# to indicate that initiator2 has been granted the pci bus. gnt2# is high upon reset. gnt3# t/s/o grant 3: this pin is configured as gnt3#. the sio/sio.a internal arbiter asserts gnt3# to indicate that initiator3 has been granted the pci bus. gnt3# is high upon reset.
82378 zb (sio) and 82379ab (sio.a) e 16 signal name type description memreq# t/s/o memory request: if the sio/sio.a is configured in guaranteed access time (gat) mode, memreq# will be asserted when an isa master or dma is requesting the isa bus (along with flshreq#) to indicate that the sio/sio.a requires ownership of the main memory. memreq# is tri-stated from the leading edge of pcirst#. memreq# remains tri-stated until driven by the sio/sio.a. after pcirst, memreq# is driven inactive asynchronously from pcirst# inactive. the sio/sio.a asserts flshreq# concurrently with asserting memreq#. flshreq# memreq# meaning 1 1 idle 0 1 flush buffers pointing towards pci to avoid isa deadlock 1 0 82378ZB. reserved 8237 9ab. gat enabled or disabled: for buffer coherency in apic systems, the buffers pointing to main memory must be flushed and disabled for the duration of assertion. 0 0 gat mode. guarantee pci bus immediate access to main memory (this may or may not require the pci-to-main memory buffers to be flushed first depending on the number of buffers). flshreq# t/s/o flush request: flshreq# is generated by the sio/sio.a to command all of the system's posted write buffers pointing towards the pci bus to be flushed. this is required before granting the isa bus to an isa master or the dma. flshreq# is tri-stated from the leading edge of pcirst#. flshreq# remains tri-stated until driven by the sio/sio.a. after pcirst, flshreq# is driven inactive asynchronously from pcirst# inactive. memack# i memory acknowledge: memack# is the response handshake that indicates to the sio/sio.a that the function requested over the memreq# and/or flshreq# signals has been completed. in gat mode (memreq# and flshreq# asserted), the main memory bus is dedicated to the pci bus and the system's posted write buffers pointing towards the pci bus have been flushed and are disabled. in non-gat mode (flshreq# asserted alone), this means the system's posted write buffers have been flushed and are disabled. in either case, the sio/sio.a can now grant the isa bus to the requester. 2.3. address decoder signal signal name type description memcs# o memory chip select . memcs# is a programmable address decode signal provided to a host cpu bridge. a cpu bridge can use memcs# to forward a pci cycle to main memory behind the bridge. memcs# is driven one pci clock after frame# is sampled active (address phase) and is valid for one clock cycle before going inactive. memcs# is high upon reset.
e 82378 zb (sio) and 82379 (sio.a) 17 2.4. power management signals signal name type description smi# o system management interrupt: smi# is asserted by the 82379ab in response to one of many enableable hardware or software events. this signal is driven low during a hard reset (pcirst# asserted) and driven high when pcirst# is negated. stpclk# o stop clock: stpclk# is asserted by the 82379ab in response to one of many enableable hardware or software events. stpclk# connects directly to the cpu. this signal is driven low during a hard reset (pcirst# asserted) and driven high when pcirst# is negated. extsmi# i external system management interrupt: extsmi# is a falling edge triggered input to the 82379ab indicating that an external device is requesting the system to enter smm mode. this pin includes a weak internal pull-up resistor. init i init: init is an input to the sio/sio.a indicating that the cpu is actually being soft reset. it is connected to the init pin of the cpu. this pin includes a weak internal pull-up resistor. 2.5. isa interface signals signal name type description aen o address enable: aen is asserted during dma cycles to prevent i/o slaves from misinterpreting dma cycles as valid i/o cycles. this signal is also driven high during refresh cycles. aen is driven low upon reset. bale o bus address latch enable: bale is an active high signal asserted by the sio/sio.a to indicate that the address (sa[19:0], la[23:17]), aen and sbhe# signal lines are valid. the la[23:17] address lines are latched on the trailing edge of bale. bale remains asserted throughout dma and isa master cycles. bale is driven low upon reset. sysclk o s ystem clock: s ysclk is an output of the sio/sio.a component. the frequencies supported are 6 to 8.33 mhz. iochrdy i/o i/o channel ready: resources on the isa bus assert iochrdy to indicate that additional time (wait states) is required to complete the cycle. iochrdy is tri- stated upon reset. iocs16# i 16-bit i/o chip select: this signal is driven by i/o devices on the isa bus to indicate that they support 16-bit i/o bus cycles. iochk# i i/o channel check: iochk# can be driven by any resource on the isa bus. when asserted, it indicates that a parity or an un-correctable error has occurred for a device or memory on the isa bus. a nmi will be generated to the cpu if the nmi generation is enabled. ior# i/o i/o read: ior# is the command to an isa i/o slave device that the slave may drive data on to the isa data bus (sd[15:0]). ior# is driven high upon reset. iow# i/o i/o write: iow# is the command to an isa i/o slave device that the slave may latch data from the isa data bus (sd[15:0]). iow# is driven high upon reset.
82378 zb (sio) and 82379ab (sio.a) e 18 signal name type description la[23:17] i/o unlatched address: these address lines allow accesses to physical memory on the isa bus up to 16 mbytes. the la[23:17] signals are at an unknown state upon reset. for the 82378ZB, these signals are undefined during dma type "a", "b", and "f" cycles. sa[19:0] i/o system address bus: these bi-directional address lines define the selection with the granularity of one byte within the one mbyte section of memory defined by the la[23:17] address lines. the address lines sa[19:17] that are coincident with la[19:17] are defined to have the same values as la[19:17] for all memory cycles. for i/o accesses, only sa[15:0] are used. sa[19:0] are outputs when the sio/sio.a owns the isa bus. sa[19:0] are inputs when an external isa master owns the isa bus. sa[19:0] are at an unknown state upon reset. for the 82378ZB, sa[19:0] are undefined during dma type "a", "b", or "f" cycles. sbhe# i/o system byte high enable: sbhe# indicates, when asserted, that a byte is being transferred on the upper byte (sd[15:8]) of the data bus. sbhe# is negated during refresh cycles. sbhe# is at an unknown state upon reset. memcs16# od memory chip select 16: memcs16# is a decode of la[23:17] without any qualification of the command signal lines. isa slaves that are 16-bit memory devices drive this signal low. the sio/sio.a drives this signal low during isa master to pci memory cycles. memcs16# is at an unknown state upon reset. master# (82378ZB only) i master: an isa bus master asserts master# to indicate that it has control of the isa bus. before the isa master can assert master#, it must first sample dack# active. once master# is asserted, the isa master has control of the isa bus until it negates master#. memr# i/o memory read: memr# is the command to a memory slave that it may drive data onto the isa data bus. memr# is an output when the sio/sio.a is a master on the isa bus. memr# is an input when an isa master, other than the sio/sio.a, owns the isa bus. this signal is also driven by the sio/sio.a during refresh cycles. for compatible timing mode dma cycles, the sio/sio.a, as a master, asserts memr# if the address is less than 16 mbytes. this signal is not generated for accesses to addresses greater than 16 mbytes. for the 82378ZB, memr# is not driven active during dma type "a", "b", or "f" cycles. memw# i/o memory write: memw# is the command to a memory slave that it may latch data from the isa data bus. memw# is an output when the sio/sio.a owns the isa bus. memw# is an input when an isa master, other than the sio/sio.a, owns the isa bus. for compatible timing mode dma cycles, the sio/sio.a, as a master, asserts memw# if the address is less than 16 mbytes. this signal is not generated for accesses to addresses greater than 16 mbytes. for the 82378ZB, memw# is not driven active during dma type "a", "b", or "f" cycles.
e 82378 zb (sio) and 82379 (sio.a) 19 signal name type description smemw# o system memory write: the sio/sio.a asserts smemw# to request a memory slave to accept data from the data lines. if the access is below the 1 mbyte range (00000000 - 000fffffh) during dma compatible, sio/sio.a master, or isa master cycles, the sio/sio.a asserts smemw#. smemw# is a delayed version of memw#. smemw# is driven high upon reset. smemr# o system memory read: the sio/sio.a asserts smemr# to request a memory slave to accept data from the data lines. if the access is below the 1 mbyte range (00000000 - 000fffffh) during dma compatible, sio/sio.a master, or isa master cycles, the sio/sio.a asserts smemr#. smemr# is a delay version of memr#. upon pcirst# this signal is low. smemr# is driven high upon reset. zerows# i zero wait states: an isa slave asserts zerows# after its address and command signals have been decoded to indicate that the current cycle can be shortened. a 16-bit isa memory cycle can be reduced to two sysclks. an 8-bit memory or i/o cycle can be reduced to three sysclks. zerows# has no effect during 16-bit i/o cycles. if iochrdy and zerows# are both asserted during the same clock, then zerows# is ignored and wait states are added as a function of iochrdy (i.e., iochrdy has precedence over zerows#). osc i oscillator: osc is the 14.31818 mhz isa clock signal. it is used by the internal 8254 timer, counters 0, 1, and 2. rstdrv o reset drive: the sio/sio.a asserts rstdrv to reset devices that reside on the isa bus. the sio/sio.a asserts this signal when pcirst# (pci reset) is asserted. in addition, the sio/sio.a can be programmed to assert rstdrv by writing to the isa clock divisor register. software should assert the rstdrv during configuration to reset the isa bus when changing the clock divisor. note that when rstdrv is generated via the isa clock divisor register, software must ensure that rstdrv is driven active for a minimum of 1 s. sd[15:0] i/o system data: sd[15:0] provide the 16-bit data path for devices residing on the isa bus. sd[15:8] correspond to the high order byte and sd[7:0] correspond to the low order byte. sd[15:0] are undefined during refresh. the sio/sio.a tri-states sd[15:0] during reset. 2.6. dma signals signal name type description dreq [3:0,7:5] i dma request: the dreq lines are used to request dma service from the sio/sio.a dma controller or for a 16-bit master to gain control of the isa expansion bus. the active level (high or low) is programmed via the dma command register (bit 6). the request must remain active until the appropriate dack signal is asserted. dack# [3:0,7:5] o dma acknowledge: the dack output lines indicate that a request for dma service has been granted by the sio/sio.a or that a 16-bit master has been granted the bus. the active level (high or low) is programmed via the dma command register (bit 7). these lines should be used to decode the dma slave device with the ior# or iow# line to indicate selection. upon pcirst#, these lines are set inactive (high).
82378 zb (sio) and 82379ab (sio.a) e 20 signal name type description eop (82378ZB) i/o end of process: eop is bi-directional, acting in one of two modes, and is directly connected to the tc line of the isa bus. dma slaves assert eop to the sio/sio.a to terminate dma cycles. the sio/sio.a asserts eop to dma slaves as a terminal count indicator. eop-in mode: for all transfer types during dma, the sio/sio.a samples eop. if it is sampled asserted, the transfer is terminated. tc-out mode: the sio asserts eop after a new address has been output, if the byte count expires with that transfer. the eop (tc) remains asserted until aen is negated, unless aen is negated during an autoinitialization. eop (tc) is negated before aen is negated during an autoinitialization. when all the dma channels are not in use, the eop signal is in output mode and negated (low). after pcirst#, eop is in output mode and inactive. tc (82379ab) o terminal count: the sio.a asserts tc after a new address has been output, if the byte count expires with that transfer. tc remains asserted until aen is negated, unless aen is negated during an autoinitialization. tc is negated before aen is negated during an autoinitialization. after pcirst#, eop is in output mode and inactive. refresh# i/o refresh: as an output, refresh# is used by the sio/sio.a to indicate when a refresh cycle is in progress. it should be used to enable the sa[15:0] address to the row address inputs of all banks of dynamic memory on the isa bus. thus, when memr# is asserted, the entire expansion bus dynamic memory is refreshed. memory slaves must not drive any data onto the bus during refresh. as an output, this signal is driven directly onto the isa bus. this signal is an output only when the sio/sio.a dma refresh is a master on the bus responding to an internally generated request for refresh. as an input, refresh# is driven by 16-bit isa bus masters to initiate refresh cycles. upon pcirst#, this signal is tri-stated. 2.7. timer signal signal name type description spkr (82378ZB) spkr/testo (82379ab) o speaker drive: the spkr signal, in the 82378ZB and 82379ab, is the output of counter 2 and has a 24 ma drive capability. upon reset, its output state is 0. for the 82379ab in test mode, this pin is the output pin used during nand tree testing.
e 82378 zb (sio) and 82379 (sio.a) 21 2.8. interrupt controller signals signal name type description irq[15,14,11: 9, 7:3,1] i interrupt request: the irq signals provide both system board components and isa bus i/o devices with a mechanism for asynchronously interrupting the cpu. the assertion mode of these inputs (edge or level triggered) is programmable via the elcr register. upon pcirst#, the irq lines are placed in edge-triggered mode. note: 1. for the 82378ZB, an active irq input must remain asserted until after the interrupt is acknowledged. if the input goes inactive before this time, a default irq7 occurs when the cpu acknowledges the interrupt. 2. for the 82379ab, a low to high transitio n on irq1 is latched by the 82379ab. the latch is cleared by a read of address 60h. 3. refer to the utility bus signal descriptions for irq12 and irq13 signal descriptions. irq8# i interrupt request eight signal: irq8# is an active low interrupt input. the assertion mode of these inputs (edge or level triggered) is programmable via the elcr register. upon pcirst#, the irq lines are placed in edge-triggered mode. note: 1. for the 82378ZB, irq8# must remain asserted until after the interrupt is acknowledged. if the input goes inactive before this time, a default irq7 will occur when the cpu acknowledges the interrupt. 2. for the 82379ab, this pin requires an external 8.2 k w pull-up resistor. int o cpu interrupt: int is driven by the sio/sio.a to signal the cpu that an interrupt request is pending and needs to be serviced. it is asynchronous with respect to sysclk or pciclk and is always an output. the interrupt controller must be programmed following a reset to ensure that int is at a known state. upon pcirst#, int is driven low. nmi o non-maskable interrupt: nmi is used to force a non-maskable interrupt to the cpu. the sio/sio.a generates an nmi when either serr# or iochk# is asserted, depending on how the nmi status and control register is programmed. the cpu detects an nmi when it detects a rising edge on nmi. after the nmi interrupt routine processes the interrupt, the nmi status bits in the nmi status and control register are cleared by software. the nmi interrupt routine must read this register to determine the source of the interrupt. the nmi is reset by setting the corresponding nmi source enable/disable bit in the nmi status and control register. to enable nmi interrupts, the two nmi enable/disable bits in the register must be set to 0, and the nmi mask bit in the nmi enable/disable and real-time clock address register must be set to 0. upon pcirst#, this signal is driven low.
82378 zb (sio) and 82379ab (sio.a) e 22 2.9. apic bus signals (82379ab only) pin name type description apicclk in apic bus clock: apicclk provides the timing reference for the apic bus. changes on apicd[1:0]# are synchronous to the rising edge of apicclk. apicd[1:0] od apic data: apicd1 and apicd0 are the apic data bus signals. interrupt messages are sent/received over this bus. apicd1 has a weak pull-down resistor. these signals require external pull-ups (330 w recommended) to the 3.3v rail. these signals are tri-stated during a hard reset. 2.10. utility bus signals signal name type description ubustr o utility data bus transmit/receive: ubustr is tied directly to the direction control of a 74f245 that buffers the utility data bus, ud[7:0]. ubustr is asserted for all i/o read cycles (regardless if a utility bus device has been decoded). ubustr is asserted for memory cycles only if bios space has been decoded. for pci and isa master-initiated read cycles, ubustr is asserted from the falling edge of either ior# or memr#, depending on the cycle type (driven from memr# only if bios space has been decoded). when the rising edge of ior# or memr# occurs, the sio/sio.a negates ubustr. for dma read cycles from the utility bus, ubustr is asserted when dackx# is asserted and negated when dackx# is negated. at all other times, ubustr is negated. upon pcirst#, this signal is driven low. ubusoe# o utility data bus output enable: ubusoe# is tied directly to the output enable of a 74f245 that buffers the utility data bus, ud[7:0], from the system data bus, sd[7:0]. ubusoe# is asserted anytime a sio/sio.a supported utility bus device is decoded, and the devices decode is enabled in the utility bus chip select enable registers. ubusoe# is asserted from the falling edge of the isa commands (ior#, iow#, memr#, or memw#) for pci and isa master-initiated cycles. ubusoe# is negated from the rising edge of the isa command signals for sio/sio.a-initiated cycles and the sa[16:0] and la[23:17] address for isa master- initiated cycles. for dma cycles, ubusoe# is asserted when dack2# is asserted and negated when dack2# negated. ubusoe# is not driven active under the following conditions: notes: 1. during an i/o access to the floppy controller, if dskchg is sampled low at reset. 2. if the digital output register is programmed to ignore dack2#. 3. during an i/o read access to floppy location 3f7h (primary) or 377h (secondary), if theide decode space is disabled (i.e., ide is not resident on the utility bus). 4. during any access to a utility bus peripheral in which its decode space has been disabled. upon a pcirst#, this signal is driven inactive (high). ecsaddr [2:0] o encoded chip selects: ecsaddr[2:0] are the encoded chip selects and/or control signals for the utility bus peripherals supported by the sio/sio.a. the binary code formed by the three signals indicates which utility bus device is selected. these signals tie to the address inputs of two external 74f138 decoder chips and are driven valid/invalid from the sa[16:0] and la[23:17] address lines. upon pcirst#, these signals are driven high.
e 82378 zb (sio) and 82379 (sio.a) 23 signal name type description ecsen# o encoded chip select enable: ecsen# is used to determine which of the two external 74f138 decoders is to be selected. ecsen# is driven low to select decoder 1 and driven high to select decoder 2. this signal is driven valid/invalid from the sa[16:0] and la[23:17] address lines (except for the generation of rtcale#, in which case, ecsen# is driven active based on iow# falling, and remains active for two sysclks). during a non-valid address or during an access not targeted for the utility bus, this signal is driven high. upon pcirst#, this signal is driven high. alt_rst# o alternate reset: alt_rst# is used to reset the cpu under program control. this signal is and'ed together externally with the reset signal (kbdrst#) from the keyboard controller to provide a software means of resetting the cpu. this provides a faster means of reset than is provided by the keyboard controller. writing a 1 to bit 0 in the port 92 register causes this signal to pulse low for approximately 4 sysclks. before another alt_rst# pulse can be generated, bit 0 must be set to 0. upon pcirst#, this signal is driven inactive high (bit 0 in the port 92 register is set to 0). alt_a20 o alternate a20: alt_a20 is used to force a20m# to the cpu low for support of real mode compatible software. this signal is externally or'ed with the a20gate signal from the keyboard controller and cpurst to control the a20m# input of the cpu. writing a 0 to bit 1 of the port 92 register forces alt_a20 low. alt_a20 low drives a20m# to the cpu low, if a20gate from the keyboard controller is also low. writing a 1 to bit 1 of the port 92 register force alt_a20 high. alt_a20 high drives a20m# to the cpu high, regardless of the state of a20gate from the keyboard controller. upon reset, this signal is driven low. dskchg i disk change: dskchg is tied directly to the dskchg signal of the floppy controller. this signal is inverted and driven on sd7 during i/o read cycles to floppy address locations 3f7h (primary) or 377h (secondary) as shown in the table below. note that the primary and secondary locations are programmed in the utility bus address decode enable/disable register "a". floppycs# idecsx# state of sd7 (output) state of ubusoe# decode decode enabled enabled tri-stated enabled enabled disabled driven via dskchg disabled disabled enabled tri-stated enabled (note) disabled disabled tri-stated disabled note: for this mode to be supported, extra logic is required to disable the u-bus transceiver for accesses to 3f7/377. this is necessary because of potential contention between the utility bus buffer and a floppy on the isa bus driving the system bus at the same time during shared i/o accesses. this signal is also used to determine if the floppy controller is present on the utility bus. it is sampled on the trailing edge of pcirst#, and if high, the floppy is present. for systems that do not support a floppy via the sio/sio.a, this pin should be strapped low. if sampled low, the sd7 function, ubusoe#, and ecsaddr[2:0] signals will not be enabled for dma or programmed i/o accesses to the floppy disk controller. this condition overrides the floppy decode enable bits in the utility bus chip select a.
82378 zb (sio) and 82379ab (sio.a) e 24 signal name type description ferr#/ irq13 i numeric coprocessor error/irq13: this signal has two separate functions, depending on bit 5 in the isa clock divisor register. this pin functions as a ferr# signal supporting coprocessor errors, if this function is enabled (bit 5=1), or as an external irq13, if the coprocessor error function is disabled (bit 5=0). if programmed to support coprocessor error reporting, this signal is tied to the coprocessor error signal on the cpu. if ferr# is asserted by the coprocessor inside the cpu, the sio/sio.a generates an internal irq13 to its interrupt controller unit. the sio/sio.a then asserts the int output to the cpu. also, in this mode, ferr# gates the ignne# signal to ensure that ignne# is not asserted to the cpu unless ferr# is active. when ferr# is asserted, the sio/sio.a asserts int to the cpu as an irq13. irq13 continues to be asserted until a write to f0h has been detected. if the coprocessor error reporting is disabled, ferr# can be used by the system as irq13. upon pcirst#, this signal provides the standard irq13 function. this signal should be pulled high with an external 8.2k w pull-up resistor if the irq13 mode is used or the pin is left floating. ignne# o ignore error: this signal is connected to the ignore error pin of the cpu. ignne# is only used if the sio/sio.a coprocessor error reporting function is enabled in the isa clock divisor register (bit 5=1). if ferr# is active, indicating a coprocessor error, a write to the coprocessor error register (f0h) causes the ignne# to be asserted. ignne# remains asserted until ferr# is negated. if ferr# is not asserted when the coprocessor error register is written, the ignne# is not asserted. ignne# is driven high upon a reset. irq12/m i interrupt request/mouse interrupt: in addition to providing the standard interrupt function as described in the pin description for irq[15,14, 11:9, 7:3, 1], this pin also provides a mouse interrupt function. bit 4 in the isa clock divisor register determines the functionality of irq12/m. when the mouse interrupt function is selected, a low-to-high transition on this signal is latched by the sio/sio.a and an int is generated to the cpu as irq12. an interrupt will continue to be generated until a pcirst# or an i/o read access to address 60h (falling edge of ior#) is detected. after a pcirst#, this pin provides the standard irq12 function. 2.11. test signals signal name type description test i test: the test signal is used to tri-state all of the sio/sio.a outputs. during normal operation, this input should be tied to ground. testo (82378ZB) spkr/testo (82379ab) o test output: for both the 82378ZB and 82379ab, this is the output pin used during nand tree testing. for the 82379ab, when not in test mode, this pin is the speaker output.
e 82378 zb (sio) and 82379 (sio.a) 25 3. 0. register description the sio/sio.a contains pci configuration registers and isa-compatible registers. in addition, the sio.a contains i/o apic registers. some of the sio/sio.a configuration and isa-compatible registers contain reserved bits. these bits are labeled "reserved". software must take care to deal correctly with bit-encoded fields that are reserved. on reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. on writes, software must ensure that the values of reserved bit positions are preserved. that is, the values of reserved bit positions must first be read, merged with the new values for other bit positions, and the data then written back. in addition to reserved bits within a register, the sio/sio.a contains address locations in the pci configuration space that are marked "reserved" (table 3 ). the sio/sio.a responds to accesses to these address locations by completing the pci cycle. however, reads of reserved address locations yield all zeroes and writes have no effect on the sio/sio.a. the sio/sio.a, upon receiving a hard reset (pcirst# signal), sets its internal registers to pre-determined default states. the default values are indicated in the individual register descriptions. configuration registers the configuration registers (table 3 ) are located in pci configuration space and are only accessible from the pci bus. addresses for configuration registers are offset values that appear on ad[7:2] and c/be#[3:0]. the configuration registers can be accessed as byte, word (16-bit), or dword (32-bit) quantities. all multi-byte numeric fields use "little-endian" ordering (i.e., lower addresses contain the least significant parts of the fields). isa-compatible registers the isa-compatible registers include dma registers, timer registers, interrupt controller registers, and non- maskable interrupt and utility bus support registers (table 6). all of these registers are accessible from the pci bus. in addition, some of the registers are accessible from the isa bus. except for the bios timer registers, the isa-compatible registers can only be accessed as byte quantities. if a pci master attempts a multi-byte access (i.e., more than one byte enable signal asserted), the sio/sio.a responds with a target-abort. the bios timer register can be accessed as byte, word, or dword quantities. in general, pci accesses to the isa-compatible registers will not be broadcast to the isa bus. however, pci accesses to addresses 70h, 60h, 92h, 3f2h, 372h, and f0h are exceptions. read and write accesses to these sio/sio.a locations are broadcast onto the isa bus. pci master accesses to sio/sio.a registers will be retried if the isa bus is owned by an isa master or the dma controller. accesses to the bios timer register are broadcast to the isa bus only if this register is disabled. if this register is enabled, the cycle is not broadcast to the isa bus. i/o apic registers (82379ab only) the apic registers are indirectly address through two 32-bit registers located in the cpu's memory space ? the i/o register select (ioregsel) and i/o window (iowin) registers (table 1 ). these registers can be relocated via the apic base address relocation register and are aligned on 128-bit boundaries. to access an i/o apic register, the ioregsel register is written with the address of the intended apic register. bits[7:0] of the ioregsel register provide the address offset (table 2 ). the iowin register then becomes a 32-bit window pointing to the register selected by the ioregsel register. note that, for each redirection table register, there are two offset addresses (e.g., address offset 10h selects ioredtbl0 bits[31:0] and 11h selects ioredtbl0 bits[63:32]).
82378 zb (sio) and 82379ab (sio.a) e 26 table 1 . memory address for accessing apic registers memory address mnemonic register name type fec0 xy00h ioregsel i/o register select r/w fec0 xy10h iowin i/o window r/w notes: xy are determined by the x and y fields in the apic base address relocation register. range for x=0-fh and the range for y=0,4,8,ch. table 2 . i/o apic registers address offset mnemonic register name type 00h ioapicid i/o apic id r/w 01h ioapicver i/o apic version ro 02h ioapicarb i/o apic arbitration id ro 10-2fh ioredtbl[0:15] redirection table (entries 0-15, 63 bits each) r/w note: address offset is determined by i/o register select bits[7:0]. table 3 . configuration registers configuration offset register register access bus access 00 - 01h vendor identification ro pci only 02 - 03h device identification ro pci only 04 - 05h command r/w pci only 06 - 07h device status r/w pci only 08h revision identification ro pci only 09 - 3fh reserved -- pci only 40h pci control r/w pci only 41h pci arbiter control r/w pci only 42h pci arbiter priority control r/w pci only 43h pci arbiter priority control extension register r/w pci only 44h memcs# control r/w pci only 45h memcs# bottom of hole r/w pci only 46h memcs# top of hole r/w pci only 47h memcs# top of memory r/w pci only 48h isa address decoder control r/w pci only
e 82378 zb (sio) and 82379 (sio.a) 27 configuration offset register register access bus access 49h isa address decoder rom block enable r/w pci only 4ah isa address decoder bottom of hole r/w pci only 4bh isa address decoder top of hole r/w pci only 4ch isa controller recovery timer r/w pci only 4dh isa clock divisor r/w pci only 4eh utility bus chip select enable a r/w pci only 4fh utility bus chip select enable b r/w pci only 50 - 53h reserved -- pci only 54h memcs# attribute register #1 r/w pci only 55h memcs# attribute register #2 r/w pci only 56h memcs# attribute register #3 r/w pci only 57h reserved (82379ab) -- pci only 57h s/g relocation base address (82378ZB) r/w pci only 58 - 5fh reserved -- pci only 60h pirq0# route control r/w pci only 61h pirq1# route control r/w pci only 62h pirq2# route control r/w pci only 63h pirq3# route control r/w pci only 64 - 6fh reserved -- pci only 70h reserved (82378ZB) -- pci only 70h pic/apic configuration control (82379ab) wo pci only 71h reserved (82378ZB) -- pci only 71h apic base address relocation (82379ab) wo pci only 72 - 7fh reserved -- pci only 80 - 81h bios timer base address r/w pci only 82 - 9fh reserved -- pci only a0h smi control (smicntl) r/w pci only a1h reserved -- pci only a2h - a3h smi enable (smien) r/w pci only a4h - a7h system event enable (see) r/w pci only
82378 zb (sio) and 82379ab (sio.a) e 28 configuration offset register register access bus access a8h fast-off timer (ftmr) r/w pci only a9h reserved -- pci only aah - abh smi request (smireq) r/w pci only ach clock throttle stpclk# low timer (ctltmrl) r/w pci only adh reserved -- pci only aeh clock throttle stpclk# high timer (ctltmrh) r/w pci only af - ffh reserved -- pci only table 4 . isa-compatible registers address address type name block fedc ba98 7654 3210 0000h 0000 0000 000x 0000 r/w dma1 ch0 base and current address dma 0001h 0000 0000 000x 0001 r/w dma1 ch0 base and current count dma 0002h 0000 0000 000x 0010 r/w dma1 ch1 base and current address dma 0003h 0000 0000 000x 0011 r/w dma1 ch1 base and current count dma 0004h 0000 0000 000x 0100 r/w dma1 ch2 base and current address dma 0005h 0000 0000 000x 0101 r/w dma1 ch2 base and current count dma 0006h 0000 0000 000x 0110 r/w dma1 ch3 base and current address dma 0007h 0000 0000 000x 0111 r/w dma1 ch3 base and current count dma 0008h 0000 0000 000x 1000 r/w dma1 status(r) command(w) register dma 0009h 0000 0000 000x 1001 wo dma1 write request register dma 000ah 0000 0000 000x 1010 wo dma1 write single mask bit dma 000bh 0000 0000 000x 1011 wo dma1 write mode register dma 000ch 0000 0000 000x 1100 wo dma1 clear byte pointer dma 000dh 0000 0000 000x 1101 wo dma1 master clear dma 000eh 0000 0000 000x 1110 wo dma1 clear mask register dma 000fh 0000 0000 000x 1111 r/w dma1 read/write all mask register bits dma 0020h 0000 0000 001x xx00 r/w int 1 control register pic 0021h 0000 0000 001x xx01 r/w int 1 mask register pic 0040h 0000 0000 010x 0000 r/w timer counter 1 - counter 0 count tc 0041h 0000 0000 010x 0001 r/w timer counter 1 - counter 1 count tc
e 82378 zb (sio) and 82379 (sio.a) 29 address address type name block fedc ba98 7654 3210 0042h 0000 0000 010x 0010 r/w timer counter 1 - counter 2 count tc 0043h 0000 0000 010x 0011 wo timer counter 1 command mode register tc 0060h 2 0000 0000 0110 0000 ro reset ubus irq12 control 0061h 0000 0000 0110 0xx1 r/w nmi status and control control 0070h 2 0000 0000 0111 0xx0 wo cmos ram address and nmi mask register control 0078 - 007bh 3,4,5 0000 0000 0111 10xx r/w bios timer tc 0080h 1 0000 0000 100x 0000 r/w dma page register (reserved) dma 0081h 0000 0000 100x 0001 r/w dma channel 2 page register dma 0082h 0000 0000 1000 0010 r/w dma channel 3 page register dma 0083h 0000 0000 100x 0011 r/w dma channel 1 page register dma 0084h 1 0000 0000 100x 0100 r/w dma page register (reserved) dma 0085h 1 0000 0000 100x 0101 r/w dma page register (reserved) dma 0086h 1 0000 0000 100x 0110 r/w dma page register (reserved) dma 0087h 0000 0000 100x 0111 r/w dma channel 0 page register dma 0088h 1 0000 0000 100x 0100 r/w dma page register (reserved) dma 0089h 0000 0000 100x 1001 r/w dma channel 6 page register dma 008ah 0000 0000 100x 1010 r/w dma channel 7 page register dma 008bh 0000 0000 100x 1011 r/w dma channel 5 page register dma 008ch 1 0000 0000 100x 1100 r/w dma page register (reserved) dma 008dh 1 0000 0000 100x 1101 r/w dma page register (reserved) dma 008eh 1 0000 0000 100x 1110 r/w dma page register (reserved) dma 008fh 0000 0000 100x 1111 r/w dma low page register refresh dma 0090h 6 0000 0000 100x 0000 r/w dma page register (reserved) dma 0092h 2 0000 0000 1001 0010 r/w system control port control 0094h 6 0000 0000 100x 0100 r/w dma page register (reserved) dma 0095h 6 0000 0000 100x 0101 r/w dma page register (reserved) dma 0096h 6 0000 0000 100x 0110 r/w dma page register (reserved) dma 0098h 6 0000 0000 100x 1000 r/w dma page register (reserved) dma 009ch 6 0000 0000 100x 1100 r/w dma page register (reserved) dma
82378 zb (sio) and 82379ab (sio.a) e 30 address address type name block fedc ba98 7654 3210 009dh 6 0000 0000 100x 1101 r/w dma page register (reserved) dma 009eh 6 0000 0000 100x 1110 r/w dma page register (reserved) dma 009fh 0000 0000 100x 1111 r/w dma low page register refresh dma 00a0h 0000 0000 101x xx00 r/w int 2 control register pic 00a1h 0000 0000 101x xx01 r/w int 2 mask register pic 00b2h 0000 0000 1011 0010 r/w advanced power management control port pm 00b3h 0000 0000 1011 0011 r/w advanced power management status port pm 00c0h 0000 0000 1100 000x r/w dma2 ch0 base and current address dma 00c2h 0000 0000 1100 001x r/w dma2 ch0 base and current count dma 00c4h 0000 0000 1100 010x r/w dma2 ch1 base and current address dma 00c6h 0000 0000 1100 011x r/w dma2 ch1 base and current count dma 00c8h 0000 0000 1100 100x r/w dma2 ch2 base and current address dma 00cah 0000 0000 1100 101x r/w dma2 ch2 base and current count dma 00cch 0000 0000 1100 110x r/w dma2 ch3 base and current address dma 00ceh 0000 0000 1100 111x r/w dma2 ch3 base and current count dma 00d0h 0000 0000 1101 000x r/w dma2 status(r) command(w) register dma 00d2h 0000 0000 1101 001x wo dma2 write request register dma 00d4h 0000 0000 1101 010x wo dma2 write single mask bit dma 00d6h 0000 0000 1101 011x wo dma2 write mode register dma 00d8h 0000 0000 1101 100x wo dma2 clear byte pointer dma 00dah 0000 0000 1101 101x wo dma2 master clear dma 00dch 0000 0000 1101 110x wo dma2 clear mask register dma 00deh 0000 0000 1101 111x r/w dma2 read/write all mask register bits dma 00f0h 2 0000 0000 1111 0000 wo coprocessor error control 0372h 2 0000 0011 0111 0010 wo secondary floppy disk digital output reg. control 03f2h 2 0000 0011 1111 0001 wo primary floppy disk digital output reg. control 040ah 3 0000 0100 0000 1010 ro s/g interrupt status (82378ZB only ) dma 040bh 0000 0100 0000 1011 wo dma1 extended mode (82378ZB only ) dma 0410h 3,4 0000 0100 0001 0000 wo ch0 s/g command (82378ZB only ) dma 0411h 3,4 0000 0100 0001 0001 wo ch1 s/g command (82378ZB only ) dma
e 82378 zb (sio) and 82379 (sio.a) 31 address address type name block fedc ba98 7654 3210 0412h 3,4 0000 0100 0001 0010 wo ch2 s/g command (82378ZB only ) dma 0413h 3,4 0000 0100 0001 0011 wo ch3 s/g command (82378ZB only ) dma 0415h 3,4 0000 0100 0001 0101 wo ch5 s/g command (82378ZB only ) dma 0416h 3,4 0000 0100 0001 0110 wo ch6 s/g command (82378ZB only ) dma 0417h 3,4 0000 0100 0001 0111 wo ch7 s/g command (82378ZB only ) dma 0418h 3,4 0000 0100 0001 1000 ro ch0 s/g status (82378ZB only ) dma 0419h 3,4 0000 0100 0001 1001 ro ch1 s/g status (82378ZB only ) dma 041ah 3,4 0000 0100 0001 1010 ro ch2 s/g status (82378ZB only ) dma 041bh 3,4 0000 0100 0001 1011 ro ch3 s/g status (82378ZB only ) dma 041dh 3,4 0000 0100 0001 1101 ro ch5 s/g status (82378ZB only ) dma 041eh 3,4 0000 0100 0001 1110 ro ch6 s/g status (82378ZB only ) dma 041fh 3,4 0000 0100 0001 1111 ro ch7 s/g status (82378ZB only ) dma 0420h 3,4 0000 0100 0010 00xx r/w ch0 s/g descriptor table pointer (82378ZB only ) dma 0424h 3,4 0000 0100 0010 01xx r/w ch1 s/g descriptor table pointer (82378ZB only ) dma 0428h 3,4 0000 0100 0010 10xx r/w ch2 s/g descriptor table pointer (82378ZB only ) dma 042ch 3,4 0000 0100 0010 11xx r/w ch3 s/g descriptor table pointer (82378ZB only ) dma 0434h 3,4 0000 0100 0011 01xx r/w ch5 s/g descriptor table pointer (82378ZB only ) dma 0438h 3,4 0000 0100 0011 10xx r/w ch6 s/g descriptor table pointer (82378ZB only ) dma 043ch 3,4 0000 0100 0011 11xx r/w ch7 s/g descriptor table pointer (82378ZB only ) dma 0481h 0000 0100 1000 0001 r/w dma ch2 high page r egister dma 0482h 0000 0100 1000 0010 r/w dma ch3 high page r egister dma 0483h 0000 0100 1000 0011 r/w dma ch1 high page r egister dma 0487h 0000 0100 1000 0111 r/w dma ch0 high page r egister dma 0489h 0000 0100 1000 1001 r/w dma ch6 high page r egister dma 048ah 0000 0100 1000 1010 r/w dma ch7 high page r egister dma 048bh 0000 0100 1000 1011 r/w dma ch5 high page r egister dma
82378 zb (sio) and 82379ab (sio.a) e 32 address address type name block fedc ba98 7654 3210 04d0 0000 0100 1101 0000 r/w int cntrl-1 edge level control register control 04d1 0000 0100 1101 0001 r/w int cntrl-2 edge level control register control 04d6h 0000 0100 1101 0010 wo dma2 extended mode r egister (82378ZB only) dma notes: 1. pci write cycles to these address locations flow through to the isa bus. pci read cycles to these address locations do not flow through to the isa bus. 2. pci read and write cycles to these address locations flow through to the isa bus. 3. the i/o address of t his register is relocatable. the value shown in this table is the default address location. 4. this register can be accessed as a byte, word, or dword quantity. 5. if this register location is enabled, pci accesses to the bios timer register do not flow through to the isa bus. if disabled, accesses to this address location flow through to the isa bus. 6. when the dmaac bit in the pci control register is '0', the sio/sio.a aliases i/o accesses in the 80h-8fh range to the 90h-9fh range. write accesses to these address locations flow through to the isa bus. read cycles to these address locations do not flow through to the isa bus. when dmaac=1, the sio/sio.a will only respond to the 80h-8fh range and read and write accesses to these addresses in the 90h-9fh range will be forwarded from the pci bus to the isa bus (i/o port 92h is always a distinct register in the 90 ? 9fh range and is always fully decoded, regardless of the setting of the dmaac bit). 3.1. sio configuration register description this section describes the sio/sio.a configuration registers. these registers include the mandatory header registers (located in the first 64 bytes of configuration space) and the sio/sio.a specific registers (located from configuration offset 40 - 56h). 3.1.1. vid ? vendor identification register address offset: 00 ? 01h default value: 8086h attribute: read only the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 vendor identification number: this is a 16-bit value assigned to intel.
e 82378 zb (sio) and 82379 (sio.a) 33 3.1.2. did ? device identification register address offset: 02 ? 03h default value: 0484h attribute: read only the did register contains the device identification number. this register, along with the vendor id, uniquely identifies the sio/sio.a. writes to this register have no effect. bit description 15:0 device identification number: this is a 16-bit value assigned to the sio/sio.a. 3.1.3. com ? command register address offset: 04 ? 05h default value: 0007h attribute: read/write bit description 15:5 reserved: read as 0. 4 pmwe (postable memory write enable): enable postable memory write, memory write and invalidate, and memory read pre-fetch commands. the sio/sio.a does not support these commands as a master or slave so this bit is not implemented. this bit will always be read as a 0. 3 sce (special cycle enable): 1=enable (the sio/sio.a will recognize pci special cycles); 0=disable (the sio/sio.a will ignore all pci special cycles). this bit must be enabled if the stpclk feature is being used. 2 bme (bus master enable): since the sio/sio.a always requests the pci bus on behalf of isa masters, dma, or line buffer pci requests, this bit is hardwired to a 1 and will always be read as a 1. 1 mse (memory space enable): enables sio/sio.a to accept a pci-originated memory cycle. since the sio/sio.a always responds to pci-originated memory cycles (and isa-bound cycles) by asserting devsel#, this bit is hardwired to a 1 and will always be read as a 1. 0 iose (i/o space enable): enable sio/sio.a to accept a pci-originated i/o cycle. since the sio/sio.a always responds to a master i/o cycle, this bit is hardwired to a 1 and will always be read as a 1.
82378 zb (sio) and 82379ab (sio.a) e 34 3.1.4. ds ? device status register address offset: 06 ? 07h default value: 0200h attribute: read/write dsr is a 16-bit status register that reports the occurrence of a pci master-abort by the sio/sio.a or a pci target-abort when the sio/sio.a is a master. the register also indicates the sio/sio.a devsel# signal timing that is hardwired in the sio/sio.a. bit description 15 reserved. read as 0. 14 serrs (serr# status) ? not implemented: this bit is set by the pci devices that assert the serr# signal. since serr# is only an input to the sio/sio.a, this bit is not implemented and will always be read as 0. 13 ma (master-abort status) ? r/w: when the sio/sio.a, as a master, generates a master-abort, ma is set to a 1. software sets ma to 0 by writing a 1 to this bit location. 12 rta (received target-abort status) ? r/w: when the sio/sio.a is a master on the pci bus and receives a target-abort, this bit is set to a 1. software sets rta to 0 by writing a 1 to this bit location. 11 sta (signaled target-abort status) ? ro: this bit is set to a 1 by the sio/sio.a when it generates a target-abort. 10:9 devt (sio devsel# timing status) ? ro: this 2-bit field defines the timing for devsel# assertion. these read only bits indicate the sio/sio.a devsel# timing when performing a positive decode. since the sio/sio.a always generates devsel# with medium timing, devt=01. this devsel# timing does not include configuration cycles. 8:0 reserved: read as 0's. 3.1.5. rid ? revision identification register address offset: 08h default value: xxh (dependent on part revision) attribute: read only this register contains the revision number for the sio/sio.a. this number indicates the stepping number of the component. additionally, the upper nibble of the value is reserved. bios should mask the upper nibble when reading this register. bit description 7:4 reserved 3:0 revision identification number: this is a 4-bit value that indicates the revision identification number for the sio/sio.a. 82378ZB 3h: 82378ZB a0-stepping 82379ab 88h: 82379ab a0 stepping
e 82378 zb (sio) and 82379 (sio.a) 35 3.1.6. pcicon ? pci control register address offset: 40h default value: 20h attribute: read/write this 8-bit register controls the line buffer operation, the sio/sio.a pci posted write buffer enabling, and the devsel# signal sampling point. the pcicon register also controls how the sio/sio.a responds to inta cycles on the pci bus and if the reserved dma page registers are aliased from 80h-8fh to 90h-9fh. bit description 7 reserved: read as 0. 6 dmaac (dma reserved page register aliasing control): this bit controls whether the sio/sio.a aliases i/o accesses in the 80h-8fh to the 90h-9fh range. when dmaac=0, the sio/sio.a aliases i/o accesses in the 80h-8fh to the 90h-9fh range (ad4 is not used for decoding the dma reserved page registers). when dmaac=1, the sio/sio.a only respond to the 80h-8fh range (ad4 is used for decoding the dma reserved page registers). read and write accesses to the 90h-9fh range will be forwarded from the pci bus to the isa bus. note i/o port 92h is always a distinct register in the 90h-9fh range and is always fully decoded, regardless of the setting of this bit. 5 iae (interrupt acknowledge enable): when iae=0, the sio/sio.a ignores inta cycles generated on the pci bus. however, when disabled, the sio/sio.a still responds to accesses to the 8259's register set and allows poll mode functions. when iae=1, the sio/sio.a responds to inta cycles in the normal fashion. 4:3 sdsp (subtractive decoding sample point): the sdsp field determines the devsel# sample point, after which an inactive devsel# results in the sio/sio.a forwarding the unclaimed pci cycle to the isa bus (subtractive decoding). this setting should match the slowest device in the system. bit[4:3] operation bit[4:3] operation 00 slow sample point 10 fast sample point 01 typical sample point 11 reserved 2 ppbe (pci posted write buffer enable): when ppbe=0 (default), the pci posted write buffer is disabled. when ppbe=1, the pci posted write buffer is enabled. 1 ilbc (isa master line buffer configuration): when ilbc=0 (default), the line buffer is in single transaction mode. when ilbc=1, the line buffer is in 8-byte mode. this bit applies only to isa master transfers. 0 dlbc (dma line buffer configuration): when dlbc=0 (default), the line buffer is in single transaction mode. when dlbc=1, the line buffer is in 8-byte mode. this bit applies only to dma transfers.
82378 zb (sio) and 82379ab (sio.a) e 36 3.1.7. pac ? pci arbiter control register address offset: 41h default value: 00h attribute: read/write this 8-bit register controls the operation of the pci arbiter. the pac register enables/disables the guaranteed access time mode, controls bus lock cycles, enables/disables cpu bus parking, and controls the master retry timer. bit description 7:5 reserved: read as 0's. 4:3 mrt (master retry timer): this 2-bit field determines the number of pciclks after the first retry that a pci initiator's bus request will be unmasked. bit[4:3] operation 00 timer disabled, retries never masked. 01 retries unmasked after 16 pciclk's. 10 retries unmasked after 32 pciclk's. 11 retries unmasked after 64 pciclk's. 2 bp (bus park): set to a 1 the sio/sio.a will park cpureq# on the pci bus when it detects the pci bus idle. if bus park is disabled, the sio/sio.a takes responsibility for driving ad, c/be# and par upon detection of bus idle state if the internal arbiter is enabled. 1 bl (bus lock): 1=bus lock (the arbiter considers the entire pci bus locked upon initiation of any locked transaction.); 0=resource lock (a locked agent is considered a locked resource and other agents may continue normal pci transactions.) 0 gat (guaranteed access time): this bit enables/disables the guaranteed access time mode. when gat=1, the sio/sio.a is configured for guaranteed access time mode. this mode is available in order to guarantee the 2.5 s chrdy time-out specification for the isa bus. when the sio/sio.a is an initiator on behalf of an isa master, the pci and memory busses are arbitrated for in serial and must be owned before the isa master is given ownership of the isa bus. when gat=0, the guaranteed access time mode is disabled. when guaranteed access time mode is disabled, the isa master is first granted the isa bus and then the sio/sio.a arbitrates for the pci bus.
e 82378 zb (sio) and 82379 (sio.a) 37 3.1.8. papc ? pci arbiter priority control register address offset: 42h default value: 04h attribute: read/write this register controls the pci arbiter priority scheme. the arbiter supports six masters arranged through four switching banks. this permits the six masters to be arranged in a purely rotating priority scheme, one of 24 fixed priority schemes, or a hybrid combination of the fixed and rotating priority schemes. if both fixed and rotate modes are enabled for the same bank, the bank will be in rotate mode. for example, if both bits 0 and 4 are set to a 1, bank 0 will be in rotate mode. for each bit, 1=enable and 0=disable. bit description bit description 7 bank 3 rotate control 3 bank 2 fixed priority mode select b 6 bank 2 rotate control 2 bank 2 fixed priority mode select a 5 bank 1 rotate control 1 bank 1 fixed priority mode select 4 bank 0 rotate control 0 bank 0 fixed priority mode select 00 01 10 bank 2 fixed control bank 2 (a,b) rotate control bank 2 bank 3 0 1 req1# req2# 0 1 cpureq# req3# fixed control bank 1 rotate control bank 1 bank 1 fixed control bank 0 rotate control bank 0 bank 0 0 1 sioreq# req0# fixed control bank 3 rotate control bank 3 057101 note: sioreq#/siognt# are sio/sio.a internal signals. figure 1 . arbiter configuration diagram
82378 zb (sio) and 82379ab (sio.a) e 38 fixed priority mode the fixed bank control bits select which requester is the highest priority device within that particular bank. table 5 . fixed mode bank control bits bank priority mode 3 2b 2a 1 0 highest lowest 00 0 0 0 0 0 sioreq# req0# req2# req3# cpureq# req1# 01 0 0 0 0 1 req0# sioreq# req2# req3# cpureq# req1# 02 0 0 0 1 0 sioreq# req0# req2# req3# req1# cpureq# 03 0 0 0 1 1 req0# sioreq# req2# req3# req1# cpureq# 04 0 0 1 0 0 cpureq# req1# sioreq# req0# req2# req3# 05 0 0 1 0 1 cpureq# req1# req0# sioreq# req2# req3# 06 0 0 1 1 0 req1# cpureq# sioreq# req0# req2# req3# 07 0 0 1 1 1 req1# cpureq# req0# sioreq# req2# req3# 08 0 1 0 0 0 req2# req3# cpureq# req1# sioreq# req0# 09 0 1 0 0 1 req2# req3# cpureq# req1# req0# sioreq# 0a 0 1 0 1 0 req2# req3# req1# cpureq# sioreq# req0# 0b 0 1 0 1 1 req2# req3# req1# cpureq# req0# sioreq# 0c-0f 0 1 1 x x reserved 10 1 0 0 0 0 sioreq# req0# req3# req2# cpureq# req1# 11 1 0 0 0 1 req0# sioreq# req3# req2# cpureq# req1# 12 1 0 0 1 0 sioreq# req0# req3# req2# req1# cpureq# 13 1 0 0 1 1 req0# sioreq# req3# req2# req1# cpureq# 14 1 0 1 0 0 cpureq# req1# sioreq# req0# req3# req2# 15 1 0 1 0 1 cpureq# req1# req0# sioreq# req3# req2# 16 1 0 1 1 0 req1# cpureq# sioreq# req0# req3# req2# 17 1 0 1 1 1 req1# cpureq# req0# sioreq# req3# req2# 18 1 1 0 0 0 req3# req2# cpureq# req1# sioreq# req0# 19 1 1 0 0 1 req3# req2# cpureq# req1# req0# sioreq# 1a 1 1 0 1 0 req3# req2# req1# cpureq# sioreq# req0# 1b 1 0 1 1 req3# req2# req1# cpureq# req0# sioreq# 1c-1f 1 1 1 x x reserved
e 82378 zb (sio) and 82379 (sio.a) 39 rotating priority mode when any bank rotate control bit is set to a 1, that particular bank rotates between the two requesting inputs. any or all banks can be set in rotate mode. if, within a rotating bank, the highest priority input does not have an active request, then the lower priority input will be granted the bus. however, this does not change the roration scheme. when the bank toggles, the previously lowest priority input will become the highest priority input. because of this, the maximum latency a device may encounter would be two complete rotations. 3.1.9. arbprix ? pci arbiter priority control extension register address offset: 43h default value: 00h attribute: read/write this register provides the fixed priority mode select for bank 3 of the arbiter. the arbprix register fields are shown. bit description 7:1 reserved: read as 0. 0 bank 3 fixed priority mode select: 0=req2# higher priority; 1=req3# higher priority. 3.1.10. mcscon-memcs# control register address offset: 44h default value: 00h attribute: read/write bits[2:0] of this register enable memcs# blocks. pci addresses within the enabled blocks result in the generation of memcs#. note that the 0 - 512-kbyte segment does not have re and we bits. the 0 - 512-kbyte segment can only be turned off with the memcs# master enable bit (bit 4). note also, that when the re and we bits are both 0 for a particular segment, the pci master can not access the segment. bit description 7:5 reserved: read as 0's. 4 memcs# master enable ? r/w: when the memcs# master enable bit is set to a 1, the sio/sio.a asserts memcs# for all accesses to the defined memcs# region (that have been programmed in this register and the mar1, mar2, and mar3 registers). also, when this bit is a 1, the positive decoding functions enabled by having the isa clock divisor register bit 6=1 and the utility bus chip select register "a" bit 6=1 are ignored. subtractive decoding is provided for these memory areas, instead. when the memcs# master enable bit is set to a 0, the entire memcs# function is disabled. when this bit is 0, memcs# will never be asserted. 3 write enable for 0f0000h ? 0fffffh (upper 64 kbyte bios): 1=enable; 0=disable. 2 read enable for 0f0000h ? 0fffffh (upper 64 kbyte bios): 1=enable; 0=disable. 1 write enable for 080000h ? 09ffffh (512 ? 640 kbyte): 1=enable; 0=disable. 0 read enable for 080000h ? 09ffffh (512 ? 640 kbyte): 1=enable; 0=disable.
82378 zb (sio) and 82379ab (sio.a) e 40 3.1.11. mcsboh ? memcs# bottom of hole register address offset: 45h default value: 10h attribute: read/write this register defines the bottom of the memcs# hole. memcs# is not generated for accesses to addresses within the hole defined by this register and the mcstoh register. the hole is defined by the following equation: toh 3 address 3 boh. toh is the top of the memcs# hole defined by the mcstoh register and boh is the bottom of the memcs# hole defined by this register. for example, to program the boh at 1 mbyte, the value of 10h should be written to this register. to program the boh at 2 mbytes + 64 kbytes this register should be programmed to 21h. to program the boh at 8 mbytes, this register should be programmed to 80h. when the toh < boh the hole is effectively disabled. it is the responsibility of the programmer to guarantee that the boh is at or above 1 mbyte. ad[31:24] must be 0's for the hole, meaning the hole is restricted to be under the 16-mbyte boundary. the default value for the boh and toh effectively disables the hole. bit description 7:0 bottom of memory hole: bits[7:0] correspond to address lines ad[23:16], respectively. 3.1.12. mcstoh ? memcs# top of hole register address offset: 46h default value: 0fh attribute: read/write this register defines the top of the memcs# hole. memcs# is not generated for accesses to addresses within the hole defined by this register and the mcsboh register. the hole is defined by the following equation: toh 3 address 3 boh. toh is the top of the memcs# hole defined by this register and boh is the bottom of the memcs# hole defined by the mcsboh register. for example, to program the toh at 1 mbyte + 64 kbytes, this register should be programmed to 10h. to program the toh at 2 mbytes + 128 kbytes, this register should be programmed to 21h. to program the toh at 12 mbytes, this register should be programmed to bfh. when the toh < boh the hole is effectively disabled. it is the responsibility of the programmer to guarantee that the toh is above 1 mbyte. ad[31:24] must be 0's for the hole, meaning the hole is restricted to be under the 16 mbyte boundary. the default value for the boh and toh effectively disables the hole. bit description 7:0 top of memory hole: bits[7:0] correspond to address lines ad[23:16], respectively.
e 82378 zb (sio) and 82379 (sio.a) 41 3.1.13. mcstom ? memcs# top of memory register address offset: 47h default value: 00h attribute: read/write this register determines memcs# top of memory boundary. the top of memory boundary ranges up to 512 mbytes, in 2-mbyte increments. this register is typically set to the top of main memory. accesses 3 2 mbytes and top of memory boundary results in the assertion of the memcs# signal (unless the address resides in the hole programmed by the mcsboh and mcstoh registers). a value of 00h disables this 2 mbyte-to-top memory region. a value of 00h assigns the top of memory to include 2 mbyte - 1. a value of ffh assigns the top of memory to include 512 mbytes - 1. bit description 7:0 top of main memory: bits[7:0] correspond to address lines ad[28:21], respectively. 3.1.14. iadcon ? isa address decoder control register address offset: 48h default value: 01h attribute: read/write this register enables the forwarding of isa or dma memory cycles to the pci bus. in addition, this register sets the top of the "1 mbyte to top of main memory" region. bit description 7:4 isa memory cycle forwarding to pci: the top can be assigned in 1 mbyte increments from 1 mbyte up to 16 mbytes. isa master or dma accesses within this region are forwarded to pci unless they are within the hole. bits[7:4] top of memory bits[7:4] top of memory 0000 1 mbyte 1000 9 mbytes 0001 2 mbytes 1001 10 mbytes 0010 3 mbytes 1010 11 mbytes 0011 4 mbytes 1011 12 mbytes 0100 5 mbytes 1100 13 mbytes 0101 6 mbytes 1101 14 mbytes 0110 7 mbytes 1 110 15 mbytes 0111 8 mbytes 1111 16 mbytes 3:0 isa and dma memory cycle to pci bus enables: the memory block is enabled by writing a 1 to the corresponding bit position. setting the bit to 0 disables the corresponding block. isa or dma memory cycles to the enabled blocks result in the isa cycle being forwarded to the pci bus. the bioscs# enable bit (bit 6 in the ubcsa register) for the 896k-960k region overrides the function of bit 3 of this register. if the bioscs# bit is set to a 1, the isa or dma memory cycle is always contained to isa, regardless of the setting of bit 3 in this register. if the bioscs# bit is disabled, the cycle is forwarded to the pci bus if bit 3 in this register is enabled. bit memory block bit memory block 0 0 - 512-kbyte memory 2 640 - 768-kbyte vga memory 1 512 - 640-kbyte memory 3 896 - 960-kbyte low bios
82378 zb (sio) and 82379ab (sio.a) e 42 3.1.15. iadrbe ? isa address decoder rom block enable register address offset: 49h default value: 00h attribute: read/write isa addresses within the enabled ranges result in the isa memory cycle being forwarded to the pci bus. if the memory block is disabled, the isa cycle is not forwarded to the pci bus. for each bit, 1=enable and 0=disable. bit description bit description 7 880-896k memory enable 3 816-832k memory enable 6 864-880k memory enable 2 800-816k memory enable 5 848-864k memory enable 1 784-800k memory enable 4 832-848k memory enable 0 768-784k memory enable 3.1.16. iadboh ? isa address decoder bottom of hole register address offset: 4ah default value: 10h attribute: read/write this register defines the bottom of the isa address decoder hole. the hole is defined by the following equation: toh 3 address 3 boh, where boh is the bottom of the hole address programmed into this register and toh is the top of the hole address programmed into the iadtoh register. isa master or dma addresses falling within the hole will not be forwarded to the pci bus. the hole can be sized in 64-kbyte increments and placed anywhere between 1 mbyte and 16 mbytes on any 64-kbyte boundary. when toh < boh, the hole is effectively disabled. the default value for the boh and toh disables the hole. for example, to program the boh at 1 mbyte, this register should be set to 10h. to program the boh at 2 mbytes, this register should be set to 20h. to program the boh at 8 mbytes, this register should be set to 80h. bit description 7:0 isa bottom of memory hole address: bits[7:0] correspond to address lines a[23:16], respectively. 3.1.17. iadtoh ? isa address decoder top of hole register address offset: 4bh default value: 0fh attribute: read/write this register defines the top of the isa address decoder hole. the hole is defined by the following equation: toh 3 address 3 boh, where boh is the bottom of the hole address programmed into the ladboh register and toh is the top of the hole address programmed into this register. isa master or dma addresses within the hole will not be forwarded to the pci bus. the hole can be sized in 64-kbyte increments and placed anywhere between 1 mbyte and 16 mbytes on any 64-kbyte boundary. when toh < boh, the hole is disabled. the default value for the boh and toh disables the hole. for example, to program the toh at 1 mbyte + 64 kbytes, this register should be set to 10h. to program the toh at 2 mbytes + 128 kbytes, this register should be set to 21h. to program the toh at 12 mbytes, this register should be set to bfh.
e 82378 zb (sio) and 82379 (sio.a) 43 bit description 7:0 isa top of memory hole address: bits[7:0] correspond to address lines a[23:16], respectively. 3.1.18. icrt ? isa controller recovery timer register address offset: 4ch default value: 56h attribute: read/write the i/o recovery mechanism in the sio/sio.a is used to add additional recovery delay between pci originated 8-bit and 16-bit i/o cycles to the isa bus. the sio/sio.a automatically forces a minimum delay of five sysclks between back-to-back 8- and 16-bit i/o cycles to the isa bus. the delay is measured from the rising edge of the i/o command (ior# or iow#) to the falling edge of the next bale. if a delay of greater than five sysclks is required, the isa i/o recovery time register can be programmed to increase the delay in increments of sysclks. note that no additional delay is inserted for back-to-back i/o "sub cycles" generated as a result of byte assembly or disassembly. this register defaults to 8- and 16-bit recovery enabled with two clocks added to the standard i/o recovery. bit description 7 reserved: read as 0. 6 8-bit i/o recovery enable: 1=enable delay programmed via bits[5:3]; 0=disable delay. 5:3 8-bit i/o recovery times: this 3-bit field defines the recovery times for 8-bit i/o. programmable delays between back-to-back 8-bit pci cycles to isa i/o slaves is shown in terms of isa clock cycles (sysclk) added to the five minimum. the selected delay programmed into this field is enabled/disabled via bit 6 of this register. bit[5:3] sysclk total bit[5:3] sysclk total added sysclks added sysc lks 001 +1 6 101 +5 10 010 +2 7 110 +6 11 011 +3 8 111 +7 12 100 +4 9 000 +8 13 2 16-bit i/o recovery enable: 1=enable delay programmed via bits[1:0]; 0=disable delay. 1:0 16-bit i/o recovery times: this 2-bit field defines the recovery time for 16-bit i/o. programmable delays between back-to-back 16-bit pci cycles to isa i/o slaves is shown in terms of isa clock cycles (sysclk) added to the five minimum. the selected delay programmed into this field is enabled/disabled via bit 2 of this register. bit[5:3] sysclk total bit[5:3] sysclk total added sysclks added sysclks 01 +1 6 11 +3 8 10 +2 7 00 +4 9
82378 zb (sio) and 82379ab (sio.a) e 44 3.1.19. icd ? isa clock divisor register address offset: 4dh default value: 40h attribute: read/write this register selects the integer value used to divide the pci clock (pciclk) to generate the isa clock (sysclk). in addition, this register provides an isa reset bit to software control rstdrv, a bit to enable/disable the mouse function, a bit to enable/disable the coprocessor error support, and a bit to disable the positive decode for the upper 64 kbytes of bios at the top of 1 mbyte (f0000 ? fffffh) and aliased regions. bit description 7 reserved: read as 0. 6 positive decode of upper 64 kbyte bios enable: this bit enables (bit 6=1) and disables (bit 6=0) the positive decode of the upper 64 kbytes of bios area at the top of 1 mbyte (f0000 ? fffffh) and the aliased regions at the top of 4 gbytes (ffff0000 ? ffffffffh) and 4 gbytes-1 mbyte (ffef0000 ? ffefffffh). when bit 6=1, these address regions are positively decoded, unless bit 4 in the memcs# control register is set to a 1 in which case these regions are subtractively decoded. when bit 6=0, these address regions are subtractively decoded. the encoded chip selects for bioscs# and the ubusoe# signal will always be generated when these locations are accessed, regardless of the state of this bit. 5 coprocessor error enable: this bit is used to enable and disable the coprocessor error support. when enabled (bit 5=1), the ferr# input, when driven active, triggers an irq13 to the sio/sio.a interrupt controller. ferr# is also used to gate the ignne# output. when disabled (bit 5=0), the ferr# signal can be used as irq13 and the coprocessor support is disabled. 4 irq12/m mouse function enable: when this bit is set to 1, irq12/m provides the mouse function. when this bit is set to 0, irq12/m provides the standard irq12 interrupt function. 3 rstdrv enable: this bit is used to enable rstdrv on the isa bus. when this bit is set to 1, rstdrv is asserted and remains asserted until this bit is set to a 0. when set to 0, normal operation of rstdrv is provided. this bit should be used during configuration to reset the isa bus when changing the clock divisor. note that the software must ensure that rstdrv is asserted for a minimum of 1 s. 2:0 pciclk-to-isa sysclk divisor: these bits are used to select the integer that is used to divide the pciclk down to generate the isa sysclk. upon reset, these bits are set to 000 (divisor of 4 selected). for pci frequencies less than 33 mhz (not including 25 mhz), a clock divisor value must be selected that ensures that the isa bus frequency does not violate the 6 mhz to 8.33 mhz sysclk specification. bit[2:0] divisor sysclk bit[2:0] divisor sysclk 000 4 (33 mhz) 8.33 mhz 100 reserved 001 3 (25 mhz) 8.33 mhz 101 reserved 010 reserved 110 reserved 011 reserved 111 reserved
e 82378 zb (sio) and 82379 (sio.a) 45 3.1.20. ubcsa ? utility bus chip select a register address offset: 4eh default value: 07h attribute: read/write this register enables/disables accesses to the rtc, keyboard controller, floppy disk controller, ide, and bios locations e0000 ? effffh and fff80000 ? fffdffffh. disabling any of these bits prevents the encoded chip select bits (ecsaddr[2:0]) and utility bus transceiver control signal (ubusoe#) for that device from being generated. this register is also used to select which address range (primary or secondary) will be decoded for the resident floppy controller and ide. this ensures that there is no contention with the utility bus transceiver driving the system data bus during read accesses to these devices. bit description 7 extended bios enable: when bit 7=1 (enabled), pci accesses to locations fff80000 ? fffdffffh result in the generation of the encoded signals (ecsaddr[2:0]) for bios. when enabled, pci master accesses to this area are positively decoded and ubusoe# is generated. when this bit is disabled (bit 7=0), the sio/sio.a does not generate the encoded (ecsaddr[2:0]) signals or ubusoe#. 6 lower bios enable: when bit 6=1 (enabled), pci or isa accesses to the lower 64 kbyte bios block (e0000 ? effffh) at the top of 1 mbyte, or the aliases at the top of 4 gbyte and 4 gbyte - 1 mbyte results in the generation of the encoded (ecsaddr[2:0]) signals for bios. when enabled, pci master accesses to this area are positively decoded to the isa bus, unless bit 4 in the memcs# control register is set to a 1 in which case these regions are subtractively decoded. also, when enabled, isa master or dma master accesses to this region are not forwarded to the pci bus. when this bit is disabled (bit 6=0), the sio/sio.a does not generate the encoded (ecsaddr[2:0]) signals. also, when this bit is disabled, isa master or dma accesses to this region are forwarded to pci, if bit 3 in the iadcon register is set to 1. 4 ide decode enable: bit 4 enables/disables ide locations 1f0 ? 1f7h (primary) or 170 ? 177h (secondary) and 3f6h, 3f7h (primary) or 376h, 377h (secondary). when bit 4=1, the ide encoded chip select signals and the utility bus transceiver signal (ubusoe# ) are generated for these addresses. when bit 4=0, these signals are not generated for these addresses. 5,3:2 floppy disk address locations enable: bits 2 and 3 are used to enable or disable the floppy locations as indicated below. a pcirst# sets bit 2 to 1 and bit 3 to 0. bit 5 is used to select between the primary and secondary address range used by the floppy controller and the ide. only primary or only secondary can be programmed at any one time. a pcirst# sets this bit to 0 (primary). the following table shows how these bits are used to select the floppy controller: address bit 5 bit 3 bit 2 dskchg ecsaddr[2:0] floppycs# x x x x 0 1 1 1 1 3f0h, 3f1h 0 1 x 1 1 0 0 0 3f2 ? 3f7h 0 x 1 1 1 0 0 0 (note) 370h, 371h 1 1 x 1 1 0 0 0 372 ? 37fh 1 x 1 1 1 0 0 0 (note) note if ide decode is enabled (bit 4=1), all accesses to locations 03f6h and 03f7h (primary) or 0376h and 0377h (secondary) result in the ecsaddr[2:0] signals generating a decode for idecs1# (floppycs# is not generated). an external and gate can be used to tie idecs1# and floppycs# together to insure that the floppy is enabled for these accesses. if ide decode is disabled (bit 4=0), and the decode for the floppy is enabled, then the encoded chip selects for the floppy locations are generated.
82378 zb (sio) and 82379ab (sio.a) e 46 bit description 1 keyboard controller address location enable: 1=enable. 0=disable. when disabled, the keyboard controller encoded chip select signals (ecsaddr[2:0]) and the utility bus transceiver signal (ubusoe#) are not generated for the address locations below. for the 82378ZB, the enabled address locations are 60h, 62h, 64h, and 66h. for the 82379ab, the enabled address locations are 60h, and 64h. 0 rtc address location enable: enables (1) or disables (0) the rtc address locations 70 ? 77h. when this bit is set to 0, the rtc encoded chip select signals (ecsaddr[2:0]), rtcale#, rtccs#, and ubusoe# signals are not generated for these addresses. 3.1.21. ubcsb ? utility bus chip select b register address offset: 4fh default value: 4fh attribute: read/wr ite this register is used to enable/disable accesses to the serial ports and parallel port locations supported by the sio/sio.a. when disabled, the ecsaddr(2:0) encoded chip select bits and utility bus transceiver control signal (ubusoe#), for that device, are not generated. this register is also used to disable accesses to port 92 and enable or disable configuration ram decode. bit description 7 configuration ram decode enable: this bit is used to enable (bit 7=1) or disable (bit 7=0) i/o write accesses to location 0c00h and i/o read/write accesses to locations 0800 ? 08ffh. when enabled, the encoded chip select signals for generating an external configuration page chip select (cpagecs#) are generated for accesses to 0c00h. the encoded chip select signals for generating an external configuration memory chip select (cfigmemcs#) are generated for accesses to 0800 ? 08ffh. when bit 7=0, configuration ram decode is disabled and the cpagecs# and cfigmemcs# are not generated for the corresponding accesses. 6 port 92 enable: 1=enable; 0=disable. 5:4 parallel port enable: these bits are used to select the parallel port address range: (lpt1, lpt2, lpt3, or disable). when a pcirst# occurs, this field is set to 00 (lpt1). bit[5:4] function bit[5:4] function 00 3bc ? 3bfh (lpt1) 10 278 ? 27fh (lpt3) 01 378 ? 37fh (lpt2) 11 disabled 3:2 serial port b enable: these bits are used to assign serial port b address range: (com1, com2, or disable). if either com1 or com2 address ranges are selected, the encoded chip select signals [ecsaddr(2:0)] for port b will be generated. a pcirst# sets bit[3:2] to 11 (port b disabled). note that, if serial port a and b are programmed for the same i/o address, the encoded chip select signals, ecsaddr(2:0), for port b are disabled. bit[3:2] function bit[3:2] function 00 3f8 ? 3ffh (com1) 10 reserved 01 2f8 ? 2ffh (com2) 11 port b disabled
e 82378 zb (sio) and 82379 (sio.a) 47 bit description 1:0 serial port a enable: these bits are used to assign serial port a address range (com1, com2, or disable). if either com1 or com2 address ranges are selected, the encoded chip select signals (ecsaddr[2:0]) for port a will be generated. a pcirst# sets bits[1:0] to 11 (port a disabled). note that, if serial port a and b are programmed for the same i/o address, the encoded chip select signals, ecsaddr[2:0], for port b are disabled. bit[1:0] function bit[1:0] function 00 3f8 ? 3ffh (com1) 10 reserved 01 2f8 ? 2ffh (com2) 11 port a disabled 3.1.22. mar1 ? memcs# attribute register #1 address offset: 54h default value: 00h attribute: read/write re ? read enable . when re=1 (bit 6, 4, 2, 0), the sio/sio.a generates memcs# for pci master, dma, or isa master memory read accesses to the corresponding segment. when re=0, the sio/sio.a does not generate memcs# for pci master memory read accesses to the corresponding segment. when re=we=0 (or bit 4=0 in the memcs# control register - disabled), the pci master, dma, or isa master can not access the segment. we ? write enable . when we=1 (bit 7, 5, 3, 1), the sio/sio.a generates memcs# for pci master, dma, or isa master memory write accesses to the corresponding segment. when we=0, the sio/sio.a does not generate memcs# for pci master memory write accesses to the corresponding segment. when the re=we bits=0 (or bit 4=0 in the memcs# control register - disabled), the pci master, dma, or isa master can not access the segment. bit description bit description 7 0cc000 ? 0cffffh exp. rom: we 3 0c4000 ? 0c7fffh exp. rom: we 6 0cc000 ? 0cffffh exp. rom: re 2 0c4000 ? 0c7fffh exp. rom: re 5 0c8000 ? 0cbfffh exp. rom: we 1 0c0000 ? 0c3fffh exp. rom: we 4 0c8000 ? 0cbfffh exp. rom: re 0 0c0000 ? 0c3fffh exp. rom: re 3.1.23. mar2 ? memcs# attribute register #2 address offset: 55h default value: 00h attribute: read/write re ? read enable . when re=1 (bit 6, 4, 2, 0), the sio/sio.a generates memcs# for pci master, dma, or isa master memory read accesses to the corresponding segment. when re=0, the sio/sio.a does not generate memcs# for pci master memory read accesses to the corresponding segment. when re= we=0 (or bit 4=0 in the memcs# control register - disabled), the pci master, dma, or isa master can not access the segment. we ? write enable . when we=1 (bit 7, 5, 3, 1), the sio/sio.a generates memcs# for pci master, dma, or isa master memory write accesses to the corresponding segment. when we=0, the sio/sio.a does not generate memcs# for pci master memory write accesses to the corresponding segment. when re=we=0 (or bit 4=0 in the memcs# control register - disabled), the pci master, dma, or isa master can?t access the segment.
82378 zb (sio) and 82379ab (sio.a) e 48 bit description bit description 7 0dc000 ? 0dffffh exp. rom : we 3 0d4000 ? 0d7fffh exp. rom : we 6 0dc000 ? 0dffffh exp. rom : re 2 0d4000 ? 0d7fffh exp. rom : re 5 0d8000 ? 0dbfffh exp. rom : we 1 0d0000 ? 0d3fffh exp. rom : we 4 0d8000 ? 0dbfffh exp. rom : re 0 0d0000 ? 0d3fffh exp. rom : re 3.1.24. mar3 ? memcs# attribute register #3 address offset: 56h default value: 00h attribute: read/write re ? read enable . when re=1 (bit 6, 4, 2, 0), the sio/sio.a generates memcs# for pci master, dma, isa master memory read accesses to the corresponding segment. when re=0, the sio/sio.a does not generate memcs# for pci master memory read accesses to the corresponding segment. when the re=we=0 (or bit 4=0 in the memcs# control register - disabled), the pci master can not access the segment. we ? write enable . when we=1 (bit 7, 5, 3, 1), the sio/sio.a generates memcs# for pci master, dma, isa master memory write accesses to the corresponding segment. when we=0, the sio/sio.a does not generate memcs# for pci master memory write accesses to the corresponding segment. when re=we=0 (or bit 4=0 in the memcs# control register - disabled), the pci master can not access the segment. bit description bit description 7 0ec000 ? 0effffh lower 64-kbyte bios: we 3 0e4000 ? 0e7fffh lower 64-kbyte bios: we 6 0ec000 ? 0effffh lower 64-kbyte bios: re 2 0e4000 ? 0e7fffh lower 64-kbyte bios: re 5 0e8000 ? 0ebfffh lower 64-kbyte bios: we 1 0e0000 ? 0e3fffh lower 64-kbyte bios: we 4 0e8000 ? 0ebfffh lower 64-kbyte bios: re 0 0e0000 ? 0e3fffh lower 64-kbyte bios: re 3.1.25. pirq[3:0]# ? pirq route control registers address offset: 60h, 61h, 62h, 63h default value: 80h attribute: read/write these four registers control the routing of pci interrupts (pirq[0:3]#) to the pc compatible interrupts. each pci interrupt can be independently routed to 1 of 11 compatible interrupts. note that two or more pci interrupts (pirq[3:0]#) can be steered into the same irq signal (the interrupts are level sensitive and can be shared). in addition, each irq to which a pci interrupt is steered into must have its interrupt set to level sensitive in the edge\level control register. bit description 7 routing of interrupts: when enabled, this bit routes the pci interrupt signal to the pc compatible interrupt signal specified in bits[3:0]. at reset, this bit is disabled (set to 1).
e 82378 zb (sio) and 82379 (sio.a) 49 bit description 6:4 reserved: read as 0's. 3:0 irqx# routing bits: these bits specify which irq signal to generate. bits[3:0] irqx# bits[3:0] irqx# bits[3:0] irqx# 0000 reserved 0110 irq6 1100 irq12 0001 reserved 0111 ir q7 1101 reserved 0010 reserved 1000 reserved 1110 irq14 0011 irq3 1001 irq9 1111 irq15 0100 irq4 1010 irq10 0101 irq5 1011 irq11 3.1.26. pacc ? pic/apic configuration control register (82379ab only) address offset: 70h default value: 00h attribute: write only the pac register controls the operation of the int signal in apic/pic configuration and the routing of the system management interrupt (smi). bit description 7:2 reserved 1 smi routing control (smirc): 1=smi routed via the apic; 0=smi routed via the smi# signal. when smrc=1, int can not be routed through the apic, since it is sharing the apic interrupt input with smi. 0 int routing control (intrc): when apic is enabled (in mixed or pure apic mode), this bit allows the 82379ab's external int signal to be masked (forces int to the inactive state but does not tri-states the signal). thus, the cpu's int pin can be used (by providing a simple -gate) for the apic local interrupt (lintrx). however, int must not be masked via this bit when apic is disabled and int is the only mechanism to signal the 8259 recognized interrupts to the cpu. when intrc=1, int is disabled (apic must be enabled). when intrc=0, int is enabled. 3.1.27. apicbase ? apic base address relocation (82379ab only) address offset: 71h default value: 00h attribute: write only the apicbase register provides the modifier for the apic base address. apic is mapped in the cpu memory space at the locations fec0_xy00h and fec0_xy10h (x=0-fh, y=0,4,8,ch). the value of 'y' is defined by bits [1:0] and value of 'x' is defined by bits [5:2]. thus, the relocation register provides a 1 kbyte address granularity (i.e., potentially up to 64 i/o apics can be uniformly addresses in the memory space). the default value of 00h provides apic unit mapping at the addresses fec00000h and fec00010h. bit description 7:6 reserved 5:2 x-base address: bits[5:2] are compared to host address bits a[15:12], respectively. 1:0 y-base address: bits[1:0] are compared to host address bits a[11:10], respectively.
82378 zb (sio) and 82379ab (sio.a) e 50 3.1.28. bios timer base address register address offset: 80 ? 81h default value: 0078h attribute: read/write this register determines the base address for the bios timer register located in the i/o space. the base address can be set at dword boundary anywhere in the 64 kbyte i/o space. this register also provides the bios timer access enable/disable control bit. bit description 15:2 bios timer base address: bits[15:2] correspond to pci address lines a[15:2], respectively. 1 reserved. read as 0. 0 bios timer access enable: when bit 0=1, access to the bios timer is enabled. when bit 0=0, access to the bios timer is disabled. the default value is 0 (disabled). 3.1.29. smicntl ? smi control register address offset: a0h default value: 08h attribute: read/write the smicntl register provides fast-off timer control, stpclk# enable/disable, and cpu clock scaling. this register also enables/disables the system management interrupt (smi). bit description 7 reserved: must be 0 when writing this register. 6 82378ZB: reserved. 82379ab: cwsgntdi ? r/w: when this bit is set to a 0, the 82379ab requires a stop grant bus cycle before negating the stpclk# signal. when this bit is set to a 1, the 82379ab does not wait for stop grant before negating stpclk#. 5:4 reserved 3 fast-off timer freeze (ctmrfrz) ? r/w: 1 = fast-off timer stops counting (prevents time-outs from occurring while executing smm code); 0=fast-off timer counts. 2 stpclk# scaling enable (cstpclksc) ? r/w: this bit enables/disables control of the stpclk# high/low times by the clock scaling timers. when bit 2=1, the stpclk# signal scaling control is enabled. when enabled (and bit 1=1, enabling the stpclk# signal), the high and low times for the stpclk# signal are controlled by the clock scaling stpclk# high timer and clock scaling stpclk# low timer registers, respectively. when bit 2=0 (default), the scaling control of the stpclk# signal is disabled. 1 stpclk# signal enable (cstpclke) ? r/w: this bit permits software to place the cpu into a low power state. when bit 1=1, the stpclk# signal is enabled and a read from the apmc register causes stpclk# to be asserted. when bit 1=0 (default), the stpclk# signal is disabled and is negated (high). software can set this bit to 0 by writing a 0 to it or by any write to the apmc register.
e 82378 zb (sio) and 82379 (sio.a) 51 bit description 0 smi# gate (csmigate) ? r/w: when bit 0=1, the smi# signal is enabled and a system management interrupt condition causes the smi# signal to be asserted. when bit 0=0 (default), the smi# signal is masked and negated. this bit only affects the smi# signal and does not affect the detection/recording of smi events (i.e., this bit does not affect the smi status bits in the smireq register). thus, smi conditions can be pending when this bit is set to 1. if an smi is pending when this bit is set to 1, the smi# signal is asserted. 3.1.30. smien ? smi enable register address offset: a2 - a3h default value: 0000h attribute: read/write this register enables the generation of smi (asserting the smi# signal) for the associated hardware events (bits[5:0]), and software events (bit 7). when a hardware event is enabled, the occurrence of a corresponding event results in the assertion of smi#, if enabled via the smicntl register. the smi# is asserted independent of the current power state (power-on or fast-off). the default for all sources in this register is disabled. bit de scription 15:8 reserved. 7 apmc write smi enable: 1=enable; 0=disable 6 extsmi# smi enable: 1=enable; 0=disable 5 fast-off timer smi enable: 1=enable; 0=disable 4 irq12 smi enable (ps/2 mouse interrupt): 1=enable; 0=disable 3 irq8 smi enable (rtc alarm interrupt): 1=enable; 0=disable 2 irq4 smi enable ( c om2/com4 interrupt or mouse): 1=enable; 0=disable 1 irq3 smi enable (com1/com3 interrupt or mouse): 1=enable; 0=disable 0 irq1 smi enable (keyboard interrupt): 1=enable; 0=disable 3.1.31. see ? system event enable register address offsset: a4 - a7h default value: 00000000h attribute: read/write this register enables hardware events as system events or break events for power management control. for i/o locations that can cause a system event via bits[27:24], refer to the power management section. system events : activity by these events can keep the system from powering down. when a system event is enabled, the corresponding hardware event activity prevents a fast-off powerdown condition. anytime the corresponding hardware event occurs (signal is asserted or an access within the defined range), the fast-off timer is re-loaded with its initial count. break events : these events can awaken a powered down system. when a break event is enabled, the corresponding hardware event activity powers up the system by negating stpclk#. note that stpclk# is not
82378 zb (sio) and 82379ab (sio.a) e 52 negated until the stop grant special cycle has been generated by the cpu. thus, from the time that stpclk# is asserted until the stop grant cycle is returned, the occurrence of subsequent break events are latched in the sio/sio.a. note init is always enabled as a break event. however, init only causes a break event after a stop grant special cycle has been received. if init is asserted while stpclk# is active and then negated before the stop grant cycle is received, init does not cause a break event. bit description 31 fast-off smi enable (fsmien): 1=enable; 0=disable. system and break events. 30 82378ZB: reserved. 82379ab: fast-off interrupt enable (fintren). 1=enable; 0=disable. break event only. 29 fast-off nmi enable (fnmien): 1=enable; 0=disable. system and break events. 28 reserved. 27 82378ZB: reserved. 82379ab: fast-off com enable (fcomen): 1=enable; 0=disable. system events only. 26 82378ZB: reserved. 82379ab: fast-off lpf enable (flpten): 1=enable; 0=disable. system events only. 25 82378ZB: reserved. 82379ab: fast-off drive enable (fdrven): 1=enable; 0=disable. system events only. 24 82378ZB: reserved. 82379ab: fast-off dma enable (fdmaen): 1=enable; 0=disable. system events only. 23:16 reserved. 15:3 fast-off irq[15:3] enable (firq[15:3]en): 1=enable; 0=disable. system and break events. 2 reserved. 1:0 fast-off irq[1:0] enable (firq[1:0]en): 1=enable; 0=disable. system and break events. 3.1.32. ftmr ? fast off timer register address offset: a8h default value: 0fh attribute: read/write the fast-off timer is used to indicate (through an smi) that the system has been idle for a pre-programmed period of time. the fast-off timer consists of a count-down timer and the value programmed into this register is loaded into the fast-off timer when an enabled system event occurs. when the timer expires, an smi special cycle is generated. when the fast-off timer is enabled (bit 3=0 in the smicntl register), the timer counts down from the value loaded into this register. the count time interval is one minute. when the fast-off timer reaches 00h, an smi is generated and the timer is re-load with the value programmed into this register. if an enabled system event occurs before the fast-off timer reaches 00h, the fast-off timer is re-loaded with the value in this register.
e 82378 zb (sio) and 82379 (sio.a) 53 note before writing to the ftmr register, the fast-off timer must be stopped via bit 3 of the smicntl register. in addition, this register should not be programmed to 00h. bit description 7:0 fast-off timer value: bits[7:0] contain the starting count value. a read from the ftmr register returns the value last written. 3.1.33. smireq ? smi request register address offset: aa - abh default value: 00h attribute: read/write the smireq register contains status bits indicating the cause of an smi. when an enabled event causes an smi, the sio/sio.a automatically sets the corresponding event's status bit to 1. note that, if software attempts to set a status bit to 0 at the same time that the sio/sio.a is setting it to 1, the bit is set to 1. if the smi event is still active when the corresponding smireq bit is set to 0, the sio/sio.a does not set the status bit back to a 1 (i.e., there is only one status indication per active smi event). when an irqx signal is asserted, the corresponding rirqx bit is set to a 1. if the irqx signal is still active when software sets the rirqx bit to 0, rirqx is not set back to a 1. the irqx may be negated before software sets the rirqx bit to 0. if the rirqx bit is set to 0 at the same time a new irqx is activated, rirqx remains at 1. this indicates to the smi handler that a new smi event has been detected. note 1. the smireq bits are set, cleared, or read independently of each other and independently of the csmigate bit in the smicntl register. 2. if an irqx is set in level mode and shared by two devices, the irq should not be enabled as an smi# event. the sio/sio.a smireq bits are essentially set with an edge. when the second irq occurs on a shared irq, there is no second edge and the smi# will not be generated for the second irq. bit description 15:8 reserved 7 apm smi status (rapmc): the sio/sio.a sets this bit to 1 to indicate that a write to the apm control register caused an smi. software sets this bit to a 0 by writing a 0 to it. 6 extsmi# smi status (rext): the sio/sio.a sets this bit to 1 to indicate that extsmi# caused an smi. software sets this bit to a 0 by writing a 0 to it. 5 fast-off timer expired status (rfot): the sio/sio.a sets this bit to 1 to indicate that the fast-off timer expired and caused an smi. software sets this bit to a 0 by writing a 0 to it. when the fast-off timer expires, the sio/sio.a sets this bit to a 1. note that the timer re-starts counting one the next clock after it expires. 4 irq12 request smi status (rirq12): the sio/sio.a sets this bit to 1 to indicate that irq12 caused an smi. software sets this bit to a 0 by writing a 0 to it. 3 irq8# request smi status: the sio/sio.a sets this bit to 1 to indicate that irq8# caused an smi. software sets this bit to a 0 by writing a 0 to it.
82378 zb (sio) and 82379ab (sio.a) e 54 bit description 2 irq4 request smi status: the sio/sio.a sets this bit to 1 to indicate that irq4 caused an smi. software sets this bit to a 0 by writing a 0 to it. 1 irq3 request smi status: the sio/sio.a sets this bit to 1 to indicate that irq3 caused an smi. software sets this bit to a 0 by writing a 0 to it. 0 irq1 request smi status: the sio/sio.a sets this bit to 1 to indicate that irq1 caused an smi. software sets this bit to a 0 by writing a 0 to it. 3.1.34. ctltmr ? clock scale stpclk# low timer address offset: ach default value: 00h attribute: read/write the value in this register defines the duration of the stpclk# asserted period when bit 2 in the smicntl register is set to 1. the value in this register is loaded into the stpclk# timer when stpclk# is asserted. however, the timer does not start until the stop grant bus cycle is received. the stpclk# timer counts using a 32 s clock. bit description 7:0 clock scaling stpclk# low timer value: bits[7:0] define the duration of the stpclk# asserted period during clock throttling. 3.1.35. ctltmrh ? clock scale stpclk# high timer address offset: aeh default value: 00h attribute: read/write the value in this register defines the duration of the stpclk# negated period when bit 2 in the smicntl register is set to 1. the value in this register is loaded into the stpclk# timer when stpclk# is negated. the stpclk# timer counts using a 32 s clock. bit description 7:0 clock scaling stpclk# high timer value: bits[7:0] define the duration of the stpclk# negated period during clock throttling.
e 82378 zb (sio) and 82379 (sio.a) 55 3.2. dma register description the sio/sio.a contains dma circuitry that incorporates the functionality of two 82c37 dma controllers (dma1 and dma2). the dma registers control the operation of the dma controllers and are all accessible from the pci bus via pci i/o space. in addition, some of the registers are accessed from the isa bus via isa i/o space. table 4 , at the beginning of section 4.0. lists the bus access for each register. this section describes the dma registers. unless otherwise stated, a pcirst# sets each register to its default value. 3.2.1. dcom ? dma command register address offset: channels 0 - 3 ? 08h; channels 4 - 7 ? 0d0h default value: 00h attribute: write only this 8-bit register controls the configuration of the dma. it is programmed by the microprocessor in the program condition and is cleared by pcirst# or a master clear instruction. note that disabling channels 4-7 also disables channels 0-3, since channels 0-3 are cascaded onto channel 4. bit description 7 dack# assert level (dack#[3:0], [7:5]): 1=active high; 0=active low. 6 dreq sense assert level (dreq[3:0], [7:5]): 1=active low; 0=active high. 5 reserved: must be 0. 4 dma group arbitration priority: 1=rotating priority; 0=fixed priority. 3 reserved: must be 0. 2 dma channel group enable: 1=disable; 0=enable. 1:0 reserved: must be 0. 3.2.2. dcm ? dma channel mode register address offset: channels 0 - 3 ? 0bh; channels 4 - 7 ? 0d6h default value: bits[7:2]=0, bits[1:0]=undefined attribute: write only each channel has a dma channel mode register. the channel mode registers provide control over dma transfer type, transfer mode, address increment/decrement, and autoinitialization. bit description 7:6 dma transfer mode: each dma channel can be programmed in one of four modes. channel 4 defaults to cascade mode and cannot be programmed for any mode other than cascade mode. bits[7:6] transfer mode bits[7:6] transfer mode 00 demand mode 10 block mode 01 single mode 11 cascade mode 5 address increment/decrement select: 0=increment; 1=decrement. 4 autoinitialize enable: 1=enable; 0=disable.
82378 zb (sio) and 82379ab (sio.a) e 56 bit description 3:2 dma transfer type: when bits[7:6]=11, the transfer type bits are irrelevant. bits[3:2] tr ansfer type bits[3:2] transfer type 00 verify transfer 10 read transfer 01 write transfer 11 illegal 1:0 dma channel select: bits[1:0] select the dma channel mode register written by bits[7:2]. bits[1:0] channel bits[1:0] channel 00 0 (4) 10 2 (6) 01 1 (5) 11 3 (7) 3.2.3. dcem ? dma channel extended mode register (82378ZB only) address offset: channels 0-3 - 040bh channels 4-7 - 04d6h default value: bits[1:0]=undefined, bits[3:2]=00 for dma1, bits[3:2]=01 for dma2, bits[7:4]=0 attribute: write only for the sio, each channel has a dma channel extended mode register. the register is used to program the dma device data size, timing mode, eop input/output selection, and stop register selection. bits [1:0] select the appropriate channel extend mode register and are not stored. only bits[7:2] are stored in the register. four timing modes are available: isa-compatible, "a", "b", and "f". timings "a", "b", and "f" are extended timing modes and can only be run to main memory. dma cycles to isa expansion bus memory defaults to compatible timing if the channel is programmed in an extended timing mode. the default bit values for each dma group are selected upon pcirst#. a master clear or any other programming sequence will not set the default register settings. the default programmed values for dma1 channels 0-3 are 8-bit i/o count by bytes, compatible timing, and eop output. the default values for dma2 channels 4-7 are 16-bit i/o count by words with shifted address, compatible timing, and eop output. bit description 7 reserved. must be 0. 6 eop input/output selection: bit 6 selects whether the eop signal is to be used as an output during dma transfers on this channel or an input. eop is typically used as an output, as was available on the pc/at. the input function was added to support data communication and other devices that would like to trigger an autoinitialize when a collision or some other event occurs. the direction of eop is switched when dack is changed (when a different channel is granted the bus). there may be some overlap of the sio driving the eop signal along with the dma slave. however, during this overlap, both devices drive the signal to a low level (inactive). for example, assume channel 2 is about to go inactive (dack negating) and channel 1 is about to go active. in addition, assume that channel 2 is programmed for "eop out" and channel 1 is programmed for "eop in". when channel 2's dack is negated and channel 1's dack is asserted, the sio may be driving eop to a low value on behalf of channel 2. at the same time the device connected to channel 1 is driving eop in to the sio, also at an inactive level. this overlap only lasts until the sio eop output buffer is tri-stated, and does not effect the dma operation. upon pcirst#, bit 6 is set to 0 - eop output selected.
e 82378 zb (sio) and 82379 (sio.a) 57 bit description 5:4 dma cycle timing mode. the sio supports four dma transfer timings: isa-compatible, type "a", "b", and "f". each timing and its corresponding code are described below. upon pcirst#, compatible timing is selected and the value of these bits is "00". the cycle timings noted below are for a sysclk (8.33 mhz, maximum sysclk frequency). dma cycles to isa expansion bus memory defaults to compatible timing if the channel is programmed in one of the performance timing modes (type "a", "b", or "f"). bits[5:4]=00: compatible timing compatible timing is provided for dma slave devices that, due to some design limitation, cannot support one of the faster timings. compatible timing runs at 9 sysclks (1080 ns/single cycle) and 8 sysclks (960 ns/cycle) during the repeated portion of a block or demand mode transfer. bits[5:4]=01: type "a" timing type "a" timing is provided to allow shorter cycles to main memory (via the pci bus). type "a" timing runs at 6 sysclks (720 ns/cycle) during the repeated portion of a block or demand mode transfer. type "a" timing varies from compatible timing primarily in shortening the memory operation to the minimum allowed main memory. the i/o portion of the cycle (data setup on write, i/o read access time) is the same as with compatible cycles. the actual active command time is shorter. however, it is expected that the dma devices that provide the data access time or write data setup time should not require excess ior# or iow# command active time. because of this, most isa dma devices should be able to use type "a" timing. bits[5:4]=10: type "b" timing type "b" timing is provided for 8/16-bit isa dma devices that can accept faster i/o timing. type "b" only works with fast main memory. type "b" timing runs at 5 sysclks (600 ns/cycle) during the repeated portion of a block or demand mode transfer. type "b" timing requires faster dma slave devices than compatible timing. in type "b" timing the cycles are shortened so that the data setup time on i/o write cycles is shortened and the i/o read access time is required to be faster. bits[5:4]=11: type "f" timing type "f" timing provides high performance dma transfer capability. type "f" timing runs at 3 sysclks (360 ns/single cycle) during the repeated portion of a block or demand mode transfer, resulting in a maximum data transfer rate of 8.33 mbytes/second.
82378 zb (sio) and 82379ab (sio.a) e 58 bit description 3:2 addressing mode. the sio supports both 8 and 16 bit dma device data sizes. three data size options are programmable with bits[3:2]. both the 8-bit i/o, "count by bytes" mode and the 16-bit i/o, "count by words" (address shifted) mode are isa compatible. the 16-bit i/o, "count by bytes" mode is offered as an extension of the isa compatible modes. bits[3:2]=10 is reserved. byte assembly/disassembly is performed by the isa control unit. each of the data transfer size modes is discussed below. bits[3:2]=00: 8-bit i/o, "count by bytes" mode in 8-bit i/o, "count by bytes" mode, the current address register can be programmed to any address. the current byte/word count register is programmed with the "number of bytes minus 1" to transfer. bits[3:2]=01: 16-bit i/o, "count by words" (address shifted) mode in "count by words" mode (address shifted), the current address register can be programmed to any even address, but must be programmed with the address value shifted right by one bit. the low page and high page registers are not shifted during dma transfers. thus, the least significant bit of the low page register is ignored when the address is driven out onto the bus. the current byte/word count register is programmed with the number of words minus 1 to be transferred. bits[3:2]=10: reserved bits[3:2]=11: 16-bit i/o, "count by bytes" mode in 16-bit "count by bytes" mode, the current address register can be programmed to any byte address. for most dma devices, however, it should be programmed only to even addresses. if the address is programmed to an odd address, the dma controller does a partial word transfer during the first and last transfer, if necessary. the bus controller does the byte/word assembly necessary to write any size memory device. in this mode, the current address register is incremented or decremented by two and the byte count is decremented by the number of bytes transferred during each bus cycle. the current byte/word count register is programmed with the "number of bytes minus 1" to be transferred. this mode is offered as an extension of the two isa compatible modes discussed above. this mode should only be programmed for 16-bit isa dma slaves. 1:0 dma channel select. bits[1:0] select the particular channel that will have its dma channel extend mode register programmed with bits[7:2]. bits [1:0] channel 00 0 (4) 01 1 (5) 10 2 (6) 11 3 (7)
e 82378 zb (sio) and 82379 (sio.a) 59 3.2.4. dr ? dma request register address offset: channe ls 0 - 3 ? 09h; channels 4 - 7 ? 0d2h default value: bits[1:0]=undefined, bits[7:2]=0 attribute: write only each channel has a request bit in one of the two dma request registers. the request register is used by software to initiate a dma request. the dma responds to the software request as though dreq[x] is asserted. these requests are non-maskable and subject to prioritization by the priority encoder network. the entire register is set to 0 upon pcirst# or a master clear. it is not affected upon a rstdrv output. to make a software request, the channel must be in block mode. the request register status for dma1 and dma2 is output on bits[7:4] of a status register read to the appropriate port. bit description 7:3 reserved: must be 0. 2 dma channel service request: 0=resets the individual software dma channel request bit. 1=sets the request bit. generation of a tc also sets this bit to 0. 1:0 dma channel select: bits[1:0] select the dma channel mode register to program with bit 2. bits[1:0] channel bits[1:0 ] channel 00 0 10 2 (6) 01 1 (5) 11 3 (7) 3.2.5. mask register ? write single mask bit address offset: channels 0 - 3 ? 0ah; channels 4 - 7 ? 0d4h default value: bits[1:0]=undefined, bit 2=1, bits[7:3]=0 attribute: write only each dma channel has a mask bit that enables/disables an incoming dma channel service request dreq[x]. two mask registers store the current mask status for dma1 and dma2. setting the mask bit disables the incoming dreq[x] for that channel. clearing the mask bit enables the incoming dreq[x]. a channel's mask bit is automatically set when the current byte/word count register reaches terminal count (unless the channel is programmed for autoinitialization). each mask bit may also be set or cleared under software control. the entire register is also set by a pcirst# or a master clear. setting the entire register disables all dma requests until a clear mask register instruction allows them to occur. this instruction format is similar to the format used with the dma request register. masking dma channel 4 (dma controller 2, channel 0) automatically masks dma channels [3:0] bit description 7:3 reserved: must be 0. 2 channel mask select: when bit 2 is set to a 1, dreq is disabled for the selected channel. when bit 2 is set to a 0, dreq is enabled for the selected channel. 1:0 dma channel select: bits[1:0] select the dma channel mode register for bit 2. bits[1:0] channel bits[1:0] channel 00 0 (4) 10 2 (6) 01 1 (5) 11 3 (7)
82378 zb (sio) and 82379ab (sio.a) e 60 3.2.6. mask register ? write all mask bits address offset: channels 0 - 3 ? 0fh; channels 4 - 7 ? 0deh default value: bit[3:0]=1, bit[7:4]=0 attribute: read/write a channel's mask bit is automatically set to 1 when the current byte/word count register reaches terminal count (unless the channel is programmed for autoinitialization). bits[3:0] are set to 1 by a pcirst# or a master clear. setting bits[3:0] to 1 disables all dma requests until a clear mask register instruction enables the requests. note that, masking dma channel 4 (dma controller 2, channel 0) will automatically mask dma channels [3:0]. in addition, masking dma controller 2 with a write to port 0deh will also mask dreq assertions from dma controller 1. bit description 7:4 reserved: must be 0. 3:0 channel mask bits: 1=disable the corresponding dreq(s); 0=enable the corresponding dreq(s). bit channel bit channel 0 0 (4) 2 2 (6) 1 1 (5) 3 3 (7) 3.2.7. ds ? dma status register address offset: channels 0 - 3 ? 08h; channels 4 - 7 ? 0d0h default value: 00h attribute: read only each dma controller has a read-only dma status register indicating which channels have reached terminal count and which channels have a pending dma request. bit description 7:4 channel request status: when a valid dma request is pending for a channel (on its dreq signal line), the corresponding bit is set to 1. when a dma request is not pending for a particular channel, the corresponding bit is set to 0. the source of the dreq may be hardware, a timed-out block transfer, or a software request. note that channel 4 does not have dreq or dack lines, so the response for a read of dma2 status for channel 4 is irrelevant. bit channel bit channel 4 0 6 2 (6) 5 1 (5) 7 3 (7) 3:0 channel terminal count status: 1=tc reached; 0=tc is not reached. bit channel bit channel 0 0 2 2 (6) 1 1 (5) 3 3 (7)
e 82378 zb (sio) and 82379 (sio.a) 61 3.2.8. dma base and current address registers (8237 compatible segment) address offset: dma channel 0 ? 000h; dma channel 4 ? 0c0h dma channel 1 ? 002h; dma channel 5 ? 0c4h dma channel 2 ? 004h; dma channel 6 ? 0c8h dma channel 3 ? 006h; dm a channel 7 ? 0cch default value: all bits undefined attribute: read/write each channel has a 16-bit current address register. for the 82378ZB, this register contains the value of the 16 least significant bits of the full 32-bit address used during dma transfers. for the 82379ab, this register contains the value of the 16 least significant bits of the full 27-bit address used during dma transfers. the address is automatically incremented or decremented after each transfer and the intermediate values of the address are stored in the current address register during the transfer. this register is written to or read from by the pci bus or isa bus master in successive 8-bit bytes. the programmer must issue the "clear byte pointer flip-flop" command to reset the internal byte pointer and correctly align the write prior to programming the current address register. autoinitialize takes place only after a tc or eop. for the 82378ZB in s/g mode, these registers store the lowest 16 bits of the current memory address. during an s/g transfer, the dma will load a reserve buffer into the base memory address register. bit description 15:0 base and current address [15:0]. these bits represent address bits[15:0] used when foming the address for dma transfers. upon pcirst# or master clear, the value of these bits is 0000h. 3.2.9. dma base and current byte/word count registers (8237 compatible segment) address offset: dma channel 0 ? 001h dma channel 4 ? 0c2h dma channel 1 ? 003h dma channel 5 ? 0c6h dma channel 2 ? 005h dma cha nnel 6 ? 0cah dma channel 3 ? 007h dma channel 7 ? 0ceh default value: all bits undefined attribute: read/write this register determines the number of transfers to be performed. the actual number of transfers is one more than the number programmed in the current byte/word count register. the byte/word count is decremented after each transfer. when the value in the register goes from zero to 0ffffh, a tc is generated. following the end of a dma service the register may also be re-initialized by an autoinitialization back to its original value. autoinitialize can only occur when a tc occurs. if it is not autoinitialized, this register has a count of ffffh after tc. for transfers to/from an 8-bit i/o, the byte/word count indicates the number of bytes to be transferred. for transfers to/from a 16-bit i/o, with shifted address, the byte/word count indicates the number of 16-bit words to be transferred. when the extended mode register is programmed for transfers to/from a 16-bit i/o, the byte/word count indicates the number of bytes to be transferred. the number of bytes does not need to be a multiple of two or four in this case.
82378 zb (sio) and 82379ab (sio.a) e 62 for the 82378ab in s/g mode, these registers store the 16 bits of the current byte/word count. during s/g transfer, the dma will load a reserve buffer into the base byte/word count register. bit description 15:0 base and current byte/word count: these bits represent the 16 byte/word count bits used when counting down a dma transfer. upon pcirst# or master clear, the value of these bits is 0000h. 3.2.10. dma memory base low page and current low page registers address offset: dma channel 0 ? 087h; dma channel 5 ? 08bh dma channel 1 ? 083h; dma channel 6 ? 089h dma channel 2 ? 081h; dma channel 7 ? 08ah dma channel 3 ? 082h; default value: all bits undefined the dma memory low page register contains the eight second most-significant bits of the address (32-bit address for the 82378ZB and 27-bit address for the 82379ab). the register works in conjunction with the dma controller's high page register and current address register to define the complete address for the dma channel. this register may be re-initialized by an autoinitialize back to its original value. autoinitialize takes place only after a tc or eop. for the 82378ZB in s/g, these registers store the 8 bits from the third byte of the current memory address. during a scater-gather transfer, the dma will load a reserve buffer into the base memory address register. bit description 7:0 dma low page and base low page [23:16]. these bits represent the eight second most significant address bits when forming the full address for a dma transfer. upon pcirst# or master clear, the value of these bits is 00h. 3.2.11. dma memory base high page and current high page registers address offset: dma channel 0 ? 0487h; dma channel 5 ? 048bh dma channel 1 ? 0483h; dma channel 6 ? 0489h dma channel 2 ? 0481h; dma channel 7 ? 048ah dma channel 3 ? 0482h; default value: all bits undefined this register works in conjunction with the dma controller's current low page register and current address register to define the complete address for the dma channels and corresponds to the current address register for each channel. this register may be autoinitialized back to its original value. autoinitialize takes place only after a tc or eop. for the 82378ZB, this register contains the eight most significant bits of the 32-bit address. for the 82379ab, this register contains the three most significant bits of the 27-bit address. this register is set to 0 during the programming of both the current low page register and the current address register. thus, if this register is not programmed after the other address and low page registers are programmed, then its value is 00h. in this case, the dma channel operates the same as an 82c37 (from an addressing standpoint). this is the address compatibility mode. if the high 8 bits (3-bits for the 82379ab) of the address are programmed after the other addresses, then the channel modifies its operation to increment (or decrement) the entire 32-bit (27-bit for the 82379ab) address. this is unlike the 82c37 "page" register in the original pcs which could only increment to a 64 kbyte boundary
e 82378 zb (sio) and 82379 (sio.a) 63 for 8-bit channels or 128 kbyte boundary for 16-bit channels. this is extended address mode. in this mode, the isa bus controller generates the signals memr# and memw# only for addresses below 16 mbytes. for the 82378ZB in s/g, these registers store the 8 bits from the highest byte of the current memory address. during a s/g transfer, the dma will load a reserve buffer into the base memory address register. 82378ZB: bit description 7:0 dma high page and base high page [31:24]. these bits represent the eight most-significant address bits when forming the full 32-bit address for a dma transfer. upon pcirst# or master clear, the value of these bits is 00h. 82379ab: bit description 7:3 reserved. 2:0 dma high page and base high page [26:24]. these bits represent the three most-significant address bits when forming the full 27-bit address for a dma transfer. upon pcirst# or master clear, the value of these bits is 00h. 3.2.12. dma clear byte pointer register address offset: channels 0 - 3 ? 00ch; channels 4 - 7 ? 0d8h default value: all bits undefined attribute: write only writing to this register executes the clear byte pointer command. this command is executed prior to writing or reading new address or word count information to the dma. this command initializes the byte pointer flip-flop to a known state so that subsequent accesses to register contents will address upper and lower bytes in the correct sequence. the master clear command clears the internal latch used to address the upper or lower byte of the 16-bit address and word count register. the host cpu may read or write a 16-bit dma controller register by performing two consecutive accesses to the i/o port. the clear byte pointer command precedes the first access. the first i/o write to a register port loads the least significant byte, and the second access automatically accesses the most significant byte. bit description 7:0 clear byte pointer: no specific pattern. command enabled with a write to the i/o port address.
82378 zb (sio) and 82379ab (sio.a) e 64 3.2.13. dmc ? dma master clear register address offset: channel 0 - 3 ? 00dh; channel 4 - 7 ? 0dah default value: all bits undefined attribute: write only this software instruction has the same effect as the hardware reset. the command, status, request, and internal first/last flip-flop registers are cleared and the mask register is set. the dma controller enters the idle cycle. bit description 7:0 master clear: no specific pattern. command enabled with a write to the i/o port address. 3.2.14. dcm ? dma clear mask register address offset: channel 0 - 3 ? 00eh; channel 4 - 7 ? 0dch default value: all bits undefined attribute: write only this command clears the mask bits of all four channels, enabling them to accept dma requests. i/o port 0eh is used for channels 0-3 and i/o port 0dch is used for channels 4-7. bit description 7:0 clear mask register: no specific pattern. command enabled with a write to the i/o port address. 3.2.15. scatter/gather (s/g) command register (82378ZB only) address offset: channels 0 default address ? 0410h; channels 5 default address ? 0415h channels 1 default address ? 0411h; channels 6 default address ? 0416h channels 2 default address ? 0412h; channels 7 default address ? 0417h channels 3 default address ? 0413h; default value: 00h attribute: write only, relocatable the s/g command register controls operation of the descriptor table aspect of scatter/gather transfers. this register can be used to start and stop a scatter/gather transfer. the register can also be used to select between irq13 and eop to be asserted following a terminal count. the current scatter/gather transfer status can be read in the scatter/gather channel's corresponding s/g status register. after a pcirst# or master clear, irq13 is disabled and eop is enabled.
e 82378 zb (sio) and 82379 (sio.a) 65 bit description 7 irq13/eop select. bit 7, if enabled via bit 6 of this register, selects whether eop or irq13 is asserted at termination caused by a last buffer expiring. the last buffer can be either the last buffer in the list or the last buffer loaded in the dma while it is suspended. if bit 7=1 (and bit 6=1), eop is asserted when the last buffer is completed. if bit 7=0 (and bit 6=1), irq13 is asserted when the last buffer is completed. eop can be used to alert an expansion bus i/o device that a scatter/gather termination condition was reached. the i/o device, in turn, can assert its own interrupt request line to invoke a dedicated interrupt handling routine. irq13 should be used when the cpu needs to be notified directly. following pcirst#, or master clear, the value stored for this bit is 1, and eop is selected. bit 6 must be set to a 1 to enable this bit during a s/g command register write. when bit 6 is a 0 during the write, bit 7 will not have any effect on the current eop/irq13 selection. 6 irq13/eop programming enable. enabling irq13/eop programming allows initialization or modification of the s/g termination handling bits. when bit 6=0, bit 7 does not affect the state of irq13 or eop assertion. when bit 6=1, bit 7 determines the termination handling following a terminal count. 5:2 reserved. must be 0. 1:0 scatter/gather (s/g) commands. this 2-bit field is used to start and stop scatter/gather. bits[1:0]=00: no s/g operation no s/g command operation is performed. bits[7:6] may still be used to program irq13/eop selection. bits[1:0]=01: start s/g command the start command initiates the scatter/gather process. immediately after the start command is issued (setting bits[1:0] to 01), a request is issued to fetch the initial buffer from the descriptor table to fill the base register set in preparation for performing a transfer. the buffer prefetch request has the same priority with respect to other channels as the dreq it is associated with. within the channel, dreq is higher in priority than a prefetch request. the start command assumes the base and current registers are both empty and will request a prefetch automatically. note that this command also sets the s/g status register to s/g active, base empty, current empty, not terminated, and next null indicator to 0. the eop/irq13 bit will still reflect the last value programmed bits[1:0]=10: stop s/g command the stop command halts a s/g transfer immediately. when a stop command is given, the terminate bit in the s/g status register and the dma channel mask bit are both set. bits[1:0]=11: reserved 3.2.16. scatter/gather (s/g) status register (82378ZB only) address offset: channels 0 default address ? 0418h; channels 5 default address ? 041dh channels 1 default address ? 0419h; channels 6 default address ? 041eh channels 2 default address ? 041ah; channels 7 default address ? 041fh channels 3 default address ? 041bh; default value: 00h attribute: read only, relocatable
82378 zb (sio) and 82379ab (sio.a) e 66 the s/g status register contains information on the scatter/gather transfer status. this register provides dynamic status information on s/g transfer activity, the current and base buffer state, s/g transfer termination, and the end of the list indicator. an active bit is set to "1" after the s/g start command is issued. the active bit will be "0" before the initial start command, following a terminal count, and after a s/g stop command is issued. the current register and base register status bits indicate whether the corresponding register has a buffer loaded. it is possible for the base register status to be set while the current register status is cleared. when the current register transfer is complete, the base register will not be moved into the current register until the start of the next data transfer. thus, the current register state is empty (cleared), while the base register state is full (set). the terminate bit is set active after a stop command, after tc for the last buffer in the list, and both base and current registers have expired. the eop and irq13 bits indicate which end of process indicator will be used to alert the system of an s/g process termination. the eol status bit is set if the dma controller has loaded the last buffer of the link list. following pcirst#, or master clear, each bit in this register is reset to "0". bit description 7 next link null indicator. if the next scatter/gather descriptor fetched from memory during a fetch operation has the eol value set to 1, the current value of the next link register is not overwritten. instead, bit 7 of the channel's s/g status register is set to a 1. if the fetch returns a eol value set to 0, this bit is set to 0. this status bit is written after every fetch operation. following pcirst#, or master clear, this bit is set to 0. this bit is also cleared by an s/g start command write to the s/g command register. 6 reserved. 5 issue irq13/eop on last buffer. when bit 5=0, eop was either defaulted to at reset or selected through the s/g command register as the s/g process termination indicator. eop is issued when a terminal count occurs or following the stop command. when bit 5=1, an irq13 is issued to alert the cpu of this same status. 4 reserved. 3 scatter/gather base register status. when bit 3=0, the base register is empty. when bit 3=1, the base register has a buffer link loaded. note that the base register state may be set while the current register state is cleared. this condition occurs when the current register expires following a transfer. the base register will not be moved into the current register until the start of the next dma transfer. 2 scatter/gather current register status. when bit 2=0, the current register is empty. when bit 2=1, the current register has a buffer link loaded and is considered full. following pcirst#, bit 2 is set to 0. 1 reserved. 0 scatter/gather active. the s/g active bit indicates the current s/g transfer status. bit 0 is set to a 1 after an s/g start command is issued. bit 0 is set to 0 before the start command is issued. bit 0 is 0 after terminal count on the last buffer on the channel is reached. bit 0 is also 0 after an s/g stop command has been issued. following a pcirst# or master clear, this bit is 0.
e 82378 zb (sio) and 82379 (sio.a) 67 3.2.17. scatter/gather (s/g) descriptor table pointer register (82378ZB only) address offset: channel 0 default address ? 0420 - 0423h; channel 5 default address ? 0434 - 0437h channel 1 default address ? 0424 - 0424h; channel 6 default address ? 0438 - 043bh channel 2 default address ? 0428 - 042bh; channel 7 default address ? 043c - 043fh channel 3 default address ? 042c - 042ch; default value: all bits undefined attribute: read/write, relocatable the s/g descriptor table pointer register contains the 32-bit pointer address to the first scatter/gather descriptor entry in the descriptor table in memory. before the start of a s/g transfer, this register should be programmed to point to the first descriptor in the s/g descriptor table. following a s/g start command, the sio reads the first sgd entry. subsequently, at the end of the each buffer block transfer, the contents of the sgd table pointer registers are incremented by 8 until the end of the sgd table is reached. the s/g descriptor table pointer registers can be programmed with a single 32-bit pci write. following a prefetch to the address pointed to by the channel's s/g descriptor table pointer register, the new memory address is loaded into the base address register, the new byte count is loaded into the base byte count register, and the newly fetched next scatter/gather descriptor replaces the current next scatter/gather value. the end of the s/g descriptor table is indicated by an end of table field having a msb equal to 1. when this value is read during a scatter/gather descriptor fetch, the current scatter/gather descriptor value is not replaced. instead, bit 7 of the channel's status register is set to a 1, when the eol is read from memory. bit description 31:0 descriptor table pointer address. the s/g descriptor table pointer register contains a 32-bit pointer address to the main memory location where the software maintains the scatter gather descriptors for the linked-list buffers. bits[31:0] correspond to a[31:0] on the pci. 3.2.18. scatter/gather (s/g) interrupt status register (82378ZB only) address offset: 040ah default value: 00h attribute: read only, relocatable size: 8 bits the s/g interrupt status register is a read only register and is used to indicate the source (channel) of a dma s/g interrupt on irq13. the dma controller drives irq13 active after reaching terminal count during a s/g transfer. it does not drive irq13 active during the initial programming sequence that loads the base registers. bit description 7 channel 7 interrupt status. when this bit is set to a 1, channel 7 has an interrupt due to a s/g transfer; otherwise this bit is set to a 0. 6 channel 6 interrupt status. when this bit is set to a 1, channel 6 has an interrupt due to a s/g transfer; otherwise this bit is set to a 0. 5 channel 5 interrupt status. when this bit is set to a 1, channel 5 has an interrupt due to a s/g transfer; otherwise this bit is set to a 0. 4 reserved. read as 0.
82378 zb (sio) and 82379ab (sio.a) e 68 bit description 3 channel 3 interrupt status. when this bit is set to a 1, channel 3 has an interrupt due to a s/g transfer; otherwise this bit is set to a 0. 2 channel 2 interrupt status. when this bit is set to a 1, channel 2 has an interrupt due to a s/g transfer; otherwise this bit is set to a 0. 1 channel 1 interrupt status. when this bit is set to a 1, channel 1 has an interrupt due to a s/g transfer; otherwise this bit is set to a 0. 0 channel 0 interrupt status. when this bit is set to a 1, channel 0 has an interrupt due to a s/g transfer; otherwise this bit is set to a 0. 3.3. timer register description the sio/sio.a contains three counters that are equivalent to those found in the 82c54 programmable interval timer. the timer registers control these counters and can be accessed from either the isa bus via isa i/o space or the pci bus via pci i/o space. this section describes the counter/timer registers on the sio/sio.a. 3.3.1. tcw ? timer control word register address offset: 043h default value: all bits undefined attribute: write only the timer control word register specifies the counter selection, the operating mode, the counter byte programming order and size of the count value, and whether the counter counts down in a 16-bit or binary-coded decimal (bcd) format. after writing the control word, a new count can be written at any time. the new value will take effect according to the programmed mode. following pcirst#, the control words for each register are undefined. each timer must be programmed to bring it into a known state. however, each counter out signal is set to 0 following pcirst#. the spkr output, interrupt controller input irq0 (internal), bit 5 of port 061h, and the internally generated refresh request are each set to 0 following pcirst#. bit description 7:6 counter select: bit[7:6] function bit[7:6] function 00 counter 0 select 10 counter 2 select 01 counter 1 select 11 read back command 5:4 read/write select: bits[5:4] are the read/write control bits. the counter latch command is selected when bits[5:4] are both 0. the read/write options include r/w least significant byte, r/w most significant byte, or r/w the lsb and then the msb. the actual counter programming is done through the counter i/o port (040h, 041h, and 042h for counters 0, 1, and 2, respectively). bit[5:4] function bit[5:4] function 00 counter latch command 10 r/w most significant byte 01 r/w least significant byte 11 r/w lsb then msb
e 82378 zb (sio) and 82379 (sio.a) 69 bit description 3:1 counter mode selection: bits[3:1] select one of six possible operating modes: bit[3:1] mode function 000 0 out signal on end of count (=0) 001 1 hard ware retriggerable one-shot x10 2 rate generator (divide by n counter) x11 3 square wave output 100 4 software triggered strobe 101 5 hardware triggered strobe 0 binary/bcd countdown select: 0=binary countdown. the largest possible binary count is 2 16 . 1=binary coded decimal (bcd) count is used. the largest bcd count allowed is 10 4 . read back command the read back command is used to determine the count value, programmed mode, and current states of the out pin and null count flag of the selected counter or counters. the read back command is written to the timer control word register which latches the current states of the above mentioned variables. the value of the counter and its status may then be read by i/o access to the counter address. note that the timer counter register bit definitions are different during the read back command than for a normal timer counter register write. bit description 7:6 read back command: when bits[7:6] are both 1, the read back command is selected during a write to the timer control word register. following the read back command, i/o reads from the selected counter's i/o addresses produce the current latch status, the current latched count, or both if bits 4 and 5 are both 0. 5 latch count of selected counters: when bit 5=1, the current count value of the selected counters will be latched. when bit 4=0, the status will not be latched. 4 latch status of selected counters: when bit 4=1, the status of the selected counters will be latched. when bit 4=0, the status will not be latched. 3 counter 2 select: when bit 3=1, counter 2 is selected for the latch command selected with bits 4 and 5. when bit 3=0, status and/or count will not be latched. 2 counter 1 select: when bit 2=1, counter 1 is selected for the latch command selected with bits 4 and 5. when bit 2=0, status and/or count will not be latched. 1 counter 0 select: when bit 1=1, counter 0 is selected for the latch command selected with bits 4 and 5. when bit 1=0, status and/or count will not be latched. 0 reserved: must be 0. counter latch command the counter latch command latches the current count value at the time the command is received. this command is used to insure that the count read from the counter is accurate (particularly when reading a two- byte count). the count value is then read from each counter's count register (via the counter ports access ports register). one, two or all three counters may be latched with one counter latch command. if a counter is latched once and then later latched again before the count is read, the second counter latch command is ignored. the count read will be the count at the time the first counter latch command was issued.
82378 zb (sio) and 82379ab (sio.a) e 70 the count must be read according to the programmed format. specifically, if the counter is programmed for two byte counts, two bytes must be read. the two bytes do not have to be read one right after the other (read, write, or programming operations for other counters may be inserted between the reads). note 1. if a counter is programmed to read/wr ite two-byte counts, a program must not transfer control between reading the first and second byte to another routine that also reads from that same counter. otherwise, an incorrect count will be read. finish reading the latched two-byte count before transferring control to another routine. 2. the timer counter register bit definitions are different during the counter latch command than for a normal timer counter register write. bit description 7:6 counter selection: bits 6 and 7 are used to select the counter for latching. bit[7:6] function bit[7:6] function 00 latch counter 0 select 10 latch counter 2 select 01 latch counter 1 select 11 read back command select 5:4 counter latch command: when bits[5:4]=00, the counter latch command is selected during a write to the timer control word register. following the counter latch command, i/o reads from the selected counter's i/o addresses produce the current latched count. 3:0 reserved. must be 0. 3.3.2. interval timer status byte format register address offset: counter 0 ? 040h; counter 1 ? 041h; counter 2 ? 042h default value: bits[6:0]=x, bit 7=0 attribute: read only each counter's status byte can be read following an interval timer read back command. if latch status is chosen (bit 4=0, read back command) as a read back option for a given counter, the next read from the counter's counter access ports register returns the status byte. bit description 7 counter out pin state: 1=pin is 1; 0=pin is 0. 6 count register status: this bit indicates when the last count written to the count register (cr) has been loaded into the counting element (ce). 0=count has been transferred from cr to ce and is available for reading. 1=count has not been transferred from cr to ce and is not yet available for reading. 5:4 read/write selection status: bits[5:4] reflect the read/write selection made through bits[5:4] of the control register. the binary codes returned during the status read match the codes used to program the counter read/write selection. bit[5:4] fun ction bit[5:4] function 00 counter latch command 10 r/w most significant byte 01 r/w least significant byte 11 r/w lsb then msb
e 82378 zb (sio) and 82379 (sio.a) 71 bit description 3:1 mode selection status: bits[3:1] return the counter mode programming. bit[3:1] mode selected bit[3:1] mode selected 000 0 x11 3 001 1 100 4 x10 2 101 5 0 countdown type status: 0=binary countdown; 1=binary coded decimal (bcd) countdown. 3.3.3. counter access ports register address offset: counter 0 ? 040h; counter 1 ? 041h; counter 2 ? 042h default value: all bits undefined attribute: read/write each of these i/o ports is used for writing count values to the count registers; reading the current count value from the counter by either an i/o read, after a counter-latch command, or after a read back command; and reading the status byte following a read back command. bit description 7:0 counter port bit[x]: each counter i/o port address is used to program the 16-bit count register. the order of programming, either lsb only, msb only, or lsb then msb, is defined with the interval counter control register at i/o port address 043h. the counter i/o port is also used to read the current count from the count register, and return the status of the counter programming following a read back command. 3.3.4. bios timer register register location: default=78 ? 7bh (dword aligned) default value: 0000xxxxh attribute: read/write, programmable a write to the bios timer initiates a counting sequence. the timer can be initiated by writing either a 16-bit data portion or the entire 32-bit register (the upper 16 bits are don't cares). bits[15:0] can be written with the initial count value to start the timer or read to check the current count value. it is the programmer's responsiblity to ensure that all 16 bits are written at the same time. after data is written into the bios timer, the timer starts decrementing until it reaches zero. it will "freeze" at zero until the new count value is written. the bios timer consists of a single 32-bit register mapped in the i/o space on the location determined by the value written into the bios timer base address register. bit 0 of the bios timer base address register enables/disables accesses to the bios timer and must be 1 to enable access to the bios timer register. when the bios timer is enabled, pci accesses to the bios timer register do not flow through to the isa bus. if the bios timer is disabled, accesses to the addresses assigned to the bios timer register flow through to the isa bus. note, however, that the counter continues to count normally. bit description 31:16 reserved. read as 0. 15:0 timer count value
82378 zb (sio) and 82379ab (sio.a) e 72 3.4. interrupt controller register description the sio/sio.a contains an isa compatible interrupt controller that incorporates the functionality of two 82c59 interrupt controllers. the interrupt registers control the operation of the interrupt controller and can be accessed from the pci bus via pci i/o space. in addition, some of the registers can be accessed from the isa bus via isa i/o space. 3.4.1. icw1 ? initia lization command word 1 register register location: int cntrl-1 ? 020h; int cntrl-2 ? 0a0h default value: all bits undefined attribute: write only a write to initialization command word 1 starts the interrupt controller initialization sequence. addresses 020h and 0a0h are referred to as the base addresses of cntrl-1 and cntrl-2, respectively. an i/o write to the cntrl-1 or cntrl-2 base address with bit 4 equal to 1 is interpreted as icw1. for sio/sio.a-based isa systems, three i/o writes to "base address + 1" must follow the icw1. the first write to "base address + 1" performs icw2, the second write performs icw3, and the third write performs icw4. icw1 starts the initialization sequence during which the following automatically occur: a. the edge sense circuit is reset. this means that following initialization, an interrupt request (irq) input must make a low-to-high transition to generate an interrupt. b. the interrupt mask register is cleared. c. irq7 input is assigned priority 7. d. the slave mode address is set to 7. e. special mask mode is cleared and status read is set to irr. f. if ic4 was set to 0, then all functions selected by icw4 are set to 0. however, icw4 must be programmed in the sio/sio.a implementation of this interrupt controller, and ic4 must be set to a 1. bit description 7:5 icw/ocw select: these bits should be 000 when programming the sio/sio.a. 4 icw/ocw select: bit 4 must be a 1 to select icw1. after the fixed initialization sequence to icw1, icw2, icw3, and icw4, the controller base address is used to write to ocw2 and ocw3. bit 4 is a 0 on writes to these registers. a 1 on this bit at any time will force the interrupt controller to interpret the write as an icw1. the controller will then expect to see icw2, icw3, and icw4. 3 ltim (edge/level bank select): this bit is ignored by the sio/sio.aand is read as a 1. 2 adi ? wo: ignored for the sio/sio.a. 1 sngl (single or cascade): this bit must be programmed to a 0 to indicate that two interrupt controllers are operating in cascade mode on the sio/sio.a. 0 ic4 (icw4 write required): this bit must be set to a 1.
e 82378 zb (sio) and 82379 (sio.a) 73 3.4.2. icw2 ? initialization command word 2 register address offset: int cntrl-1 ? 021h; int cntrl-2 ? 0a1h default value: all bits undefined attribute: write only icw2 is used to initialize the interrupt controller with the five most significant bits of the interrupt vector address. bit description 7:3 interrupt vector base address: bits[7:3] define the base address in the interrupt vector table for the interrupt routines associated with each interrupt request level input. 2:0 interrupt request level: when writing icw2, these bits should all be 0. 3.4.3. icw3 ? initialization command word 3 register address offset: int cntrl-1 ? 021h default value: all bits undefined attribute: write only the meaning of icw3 differs between cntrl-1 and cntrl-2. on cntrl-1, the master controller, icw3 indicates which cntrl-1 irq line physically connects the int output of cntrl-2 to cntrl-1. icw3 must be programmed to 04h, indicating the cascade of the cntrl-2 int output to the irq[2] input of cntrl-1. an interrupt request on irq2 causes cntrl-1 to enable cntrl-2 to present the interrupt vector address during the second interrupt acknowledge cycle. bit description 7:3 not used: these bits must be programmed to 0. 2 cascaded interrupt controller irq connection: bit 2 must always be programmed to a 1 selecting cascade mode. 1:0 not used: these bits must be programmed to 00. 3.4.4. icw3 ? initialization command word 3 regi ster address offset: int cntrl-2 ? 0a1h default value: all bits undefined attribute: write only on cntrl-2 (the slave controller), icw3 is the slave identification code broadcast by cntrl-1 from the trailing edge of the first inta# pulse to the trailing edge of the second inta# pulse. bit description 7:3 reserved. must be 0. 2:0 slave identification code: the slave identification code must be programmed to 010b during the initialization sequence. the code stored in icw3 is compared to the incoming slave identification code broadcast by the master controller during interrupt acknowledge cycles.
82378 zb (sio) and 82379ab (sio.a) e 74 3.4.5. icw4 ? initialization command word 4 register address offset: int cntrl-1 ? 021h; int cntrl-2 ? 0a1h default value: 01h attribute: write only size: 8 bits both sio/sio.a interrupt controllers must have icw4 programmed as part of their initialization sequence. bit description 7:5 reserved. must be 0. 4 special fully nested mode (sfnm): bit 4, sfnm, should normally be disabled by writing a 0 to this bit. if sfnm=1, the special fully nested mode is programmed. 3 buffered mode (buf): must be programmed to 0 selecting non-buffered mode. 2 master/slave in buffered mode: bit 2 should always be programmed to 0. bit not used. 1 automatic end of interrupt (aeoi): this bit should normally be programmed to 0. this is the normal end of interrupt. if this bit is 1, the automatic end of interrupt mode is programmed. 0 microprocessor mode: the microprocessor mode bit must be programmed to 1 indicating an 80x86- based system. 3.4.6. ocw1 ? operational control word 1 register address offset: int cntrl-1 ? 021hi; nt cntrl-2 ? 0a1h default value: 00h attribute: read/write ocw1 sets and clears the mask bits in the interrupt mask register (imr). each interrupt request line may be selectively masked or unmasked any time after initialization. a single byte is written to this register. each bit position in the byte represents the same-numbered channel: bit 0=irq[0], bit 1=irq[1] and so on. setting the bit to a 1 sets the mask, and clearing the bit to a 0 clears the mask. note that masking irq[2] on cntrl-1 will also mask all of controller 2's interrupt requests (irq8-irq15). reading ocw1 returns the controller's mask register status. the imr stores the bits which mask the interrupt lines to be masked. the imr operates on the irr. masking of a higher priority input will not affect the interrupt request lines of lower priority. unlike status reads of the isr and irr, for reading the imr, no ocw3 is needed. the output data bus will contain the imr whenever i/o read is active and the i/o port address is 021h or 0a1h (ocw1). all writes to ocw1 must occur following the icw1-icw4 initialization sequence, since the same i/o ports are used for ocw1, icw2, icw3 and icw4. bit description 7:0 interrupt request mask (mask [7:0]): when a 1 is written to any bit in this register, the corresponding irqx line is masked. for example, if bit 4 is set to a 1, then irq4 will be masked. interrupt requests on irq4 will not set channel 4's interrupt request register (irr) bit as long is the channel is masked. when a 0 is written to any bit in this register, the corresponding irqx mask bit is cleared, and interrupt requests will again be accepted by the controller. note that masking irq2 on cntrl-1 will also mask the interrupt requests from cntrl-2, which is physically cascaded to irq2.
e 82378 zb (sio) and 82379 (sio.a) 75 3.4.7. ocw2 ? operational control word 2 register address offset: int cntrl-1 ? 020h; int cntrl-2 ? 0a0h default value: bit[4:0]=undefined, bit[7:5]=001 attribute: write only ocw2 controls both the rotate mode and the end of interrupt mode, and combinations of the two. the three high order bits in an ocw2 write represent the encoded command. the three low order bits are used to select individual interrupt channels during three of the seven commands. the three low order bits (labeled l2, l1 and l0) are used when bit 6 is set to a 1 during the command. following a pcirst# and icw initialization, the controller enters the fully nested mode of operation. non-specific eoi without rotation is the default. both rotation mode and specific eoi mode are disabled following initialization. bit description 7:5 rotate and eoi codes: r, sl, eoi: these three bits control the rotate and end of interrupt modes and combinations of the two. a chart of these combinations is listed above under the bit definition. bits[7:5] function 001 non-specific eoi command 011 specific eoi command 101 rotate on non-specific eoi command 100 rotate in auto eoi mode (set) 000 rotate in auto eoi mode (clear) 111 *rotate on specific eoi command 110 *set priority command 010 no operation * l0 ? l2 are used 4:3 ocw2 select: when selecting ocw2, bits 3 and 4 must both be 0. if bit 4 is a 1, the interrupt controller interprets the write to this port as an icw1. therefore, always ensure that these bits are both 0 when writing an ocw2. 2:0 interrupt level select (l2, l1, l0): l2, l1, and l0 determine the interrupt level acted upon when the sl bit is active (bit 6). when the sl bit is inactive these bits do not have a defined function; programming l2, l1 and l0 to 0 is sufficient in this case. bit[2:0] interrupt level bit[2:0] interrupt level 000 irq 0(8) 100 irq 4(12) 001 irq 1(9) 101 irq 5(13) 010 irq 2(10) 110 irq 6(14) 011 irq 3(11) 111 irq 7(15)
82378 zb (sio) and 82379ab (sio.a) e 76 3.4.8. ocw3 ? operational control word 3 register address offset: int cntrl-1 ? 020h; int cntrl-2 ? 0a0h default value: bit[6,0]=0, bit[7,4:2]=undefined, bit[5,1]=1 attribute: read/write ocw3 serves three important functions: enable special mask mode, poll mode control, and irr/isr register read control. bit description 7 reserved: must be 0. 6 smm (special mask mode): if esmm=1 and smm=1 the interrupt controller enters special mask mode. if esmm=1 and smm=0, the interrupt controller is in normal mask mode. when esmm=0, smm has no effect. 5 esmm (enable special mask mode): 1=enable smm bit; 0=disable smm bit. 4:3 ocw3 select: must be programmed to 01 selecting ocw3. 2 poll mode command: 0=disable poll command. when bit 2=1, the next i/o read to the interrupt controller is treated as an interrupt acknowledge cycle representing the highest priority level requesting service. 1:0 register read command: bits[1:0] provide control for reading the in-service register (isr) and the interrupt request register (irr). when bit 1=0, bit 0 will not affect the register read selection. when bit 1=1, bit 0 selects the register status returned following an ocw3 read. if bit 0=0, the irr will be read. if bit 0=1, the isr will be read. following icw initialization, the default ocw3 port address read will be "read irr". to retain the current selection (read isr or read irr), always write a 0 to bit 1 when programming this register. the selected register can be read repeatedly without reprogramming ocw3. to select a new status register, ocw3 must be reprogrammed prior to attempting the read. bit[1:0] function bit[1:0] function 00 no action 10 read irq register 01 no action 11 read is register
e 82378 zb (sio) and 82379 (sio.a) 77 3.5. control registers this section contains nmi registers, a real-time clock register, port 92 register, and the digital output register. 3.5.1. nmisc ? nmi status and control register address offset: 061h default value: 00h attribute: read/write this register is used to check the status of different system components, control the output of the speaker counter (counter 2), and gate the counter output that drives the spkr signal. bit description 7 serr# status ? ro: 1=serr# pulsed. 0=no serr#. bit 7 is set if a system board agent (pci devices or main memory) detects a system board error and pulses the pci serr# line. this interrupt is enabled by setting bit 2 to 0. to reset the interrupt, set bit 2 to 0 and then set it to 1. when writing to port 061h, bit 6 must be a 0. 6 iochk# nmi source status ? ro: bit 6 is set if an expansion board asserts iochk# on the isa/sio bus. this interrupt is enabled by setting bit 3 to 0. to reset the interrupt, set bit 3 to 0 and then set it to 1. when writing to port 061h, bit 6 must be a 0. 5 timer counter 2 out status ? ro: the counter 2 out signal state is reflected in bit 5. the value on this bit following a read is the current state of the counter 2 out signal. counter 2 must be programmed following a pcirst# for this bit to have a determinate value. when writing to port 061h, bit 5 must be a 0. 4 refresh cycle toggle ? ro: the refresh cycle toggle signal toggles from either 0 to 1 or 1 to 0 following every refresh cycle. this read-only bit is a 0 following pcirst#. when writing to port 061h, bit 4 must be a 0. 3 iochk# nmi enable ? r/w: 1=clear and disable; 0=enable iochk# nmi's. 2 pci serr# enable ? r/w: 1=clear and disable. 0=enable. 1 speaker data enable ? r/w: 1=spkr output is 0; 1=spkr output is the counter 2 out value. 0 timer counter 2 enable ? r/w: 0=disable; 1=enable
82378 zb (sio) and 82379ab (sio.a) e 78 3.5.2. nmi enable and real-time clock address register address offset: 070h default value: bit[6:0]=undefined, bit 7=1 attribute: write only the mask register for the nmi interrupt is at i/o address 070h shown below. the most significant bit enables or disables all nmi sources including iochk# and the nmi port. write an 80h to port 70h to mask the nmi signal. this port is shared with the real-time clock. the real-time-clock uses the lower six bits of this port to address memory locations. writing to port 70h sets both the enable/disable bit and the memory address pointer. do not modify the contents of this register without considering the effects on the state of the other bits. reads and writes to this register address flow through to the isa bus. bit description 7 nmi enable: 1=disable; 0=enable. 6:0 real time clock address: used by the real time clock on the base i/o component to address memory locations. not used for nmi enabling/disabling. 3.5.3. port 92 register address offset: 92h default value: 24h attribute: read/write this register is used to support the alternate reset (alt_rst#) and alternate a20 (alt_a20) functions. this register is only accessible if bit 6 in the utility bus chip select b register is set to a 1. reads and writes to this register location flow through to the isa bus. bit description 7:6 reserved: read as 0s. 5 reserved: read as 1. 4:3 reserved: read as 0s. 2 reserved: read as 1. 1 alt_a20 signal control ? r/w: 0=alt_a20 signal negated (low). 1=alt_a20 signal asserted (high). 0 alternate system reset ? r/w: this read/write bit provides an alternate system reset function. this function provides an alternate means to reset the system cpu to effect a mode switch from protected virtual address mode to the real address mode. this provides a faster means of reset than is provided by the keyboard controller. this bit is set to a 0 by a system reset. writing a 1 to this bit will cause the alt_rst# signal to pulse active (low) for approximately 4 sysclk's. before another alt_rst# pulse can be generated, this bit must be written back to a 0.
e 82378 zb (sio) and 82379 (sio.a) 79 3.5.4. digital output register address offset: 03f2h (primary), 0372h (secondary) default value: bit[7:4,2:0]=undefined, bit 3=0 attribute: write only this register is used to prevent ubusoe# from responding to dack2# during a dma read access to a floppy controller on the isa bus. if a second floppy (residing on the isa bus) is using dack2# in conjunction with a floppy on the utility bus, this prevents the floppy on the utility bus and the utility bus transceiver from responding to an access targeted for the floppy on the isa bus. this register is also located in the floppy controller device. reads and writes to this register location flow through to the isa bus. bit description 7:4 not used: these bits exist in the floppy controller. 3 dma enable: when this bit is a 1, the assertion of dack# will result in ubusoe# being asserted. if this bit is 0, dack2# has no effect on ubusoe#. this port bit also exists on the floppy controller. this bit defaults to disable (0). 2:0 not used: these bits exist in the floppy controller. 3.5.5. reset ubus irq1/irq12 register address offset: 60h default value: n/a attribute: read only this address location (60h) is used to clear the mouse and keyboard interrupt functions to the cpu. reads to this address are monitored by the sio/sio.a. when the mouse interrupt function is enabled (bit 4 of the isa clock divisor register is 1), the mouse interrupt function is provided on the irq12/m input signal. in this mode, a mouse interrupt generates an interrupt through irq12/m to the host cpu. a read of 60h releases irq12. if bit 4=0 in the isa clock divisor register, a read of address 60h has no effect on irq12/m. reads and writes to this register flow through to the isa bus. for additional information, see the irq12/m description in signal description section. a read of 60h always releases irq1, regardless of the setting of bit 4 in the isa clock divisor register. bit description 7:0 reset irq1/irq12: no specific pattern. a read of address 60h executes the command.
82378 zb (sio) and 82379ab (sio.a) e 80 3.5.6. coprocessor error register address offset: f0h default value: n/a attribute: write only this address location (f0h) is used when the sio/sio.a is programmed for coprocessor error reporting (bit 5 of the isa clock divisor register is 1). writes to this address are monitored by the sio/sio.a. in this mode, the sio/sio.a generates an interrupt (int) to the cpu when it receives an error signal (ferr# asserted) from the cpu's coprocessor. writing address f0h, when ferr# is asserted, causes the sio/sio.a to assert ignne# and negate irq13. ignne# remains asserted until ferr# is negated. if ferr# is not asserted, writing to address f0h does not effect ignne#. reads and writes to this register flow through to the isa bus. for additional information, see the ignne# description in the signal description section bit description 7:0 reset irq12: no specific pattern. a write to address f0h executes the command. 3.5.7. elcr ? edge/level control register address offset: int cntrl-1 ? 04d0h; int cntrl-2 ? 04d1h default value: 00h attribute: read/write the edge/level control register is used to set the interrupts to be triggered by either the signal edge or the logic level. int0, int1, int2, int8, int13 must be set to edge sensitive. after a reset, all the int signals are set to edge sensitive. each irq that a pci interrupt is steered into (see the pirq route control register) must have it's interrupt set to level sensitive. bit 7:0 edge/level select: 0=edge sensitive interrupt; 1=level sensitive. bit port 04d0h port 04d1h 0 int0* int8* 1 int1* int9 2 int2* int10 3 int3 int11 4 int4 int12 5 int5 int13* 6 int6 int14 7 int7 int15 * must be 0 when written. 3.6. power management registers this section describes the two power management registers (apms and apmc) that are located in normal i/o space. these registers are accessed via the cpu or pci bus with 8 bit accesses. note that the rest of the power management registers are part of the sio/sio.a configuration registers.
e 82378 zb (sio) and 82379 (sio.a) 81 3.6.1. apmc ? advanced power management control port i/o address: 0b2h default value: 00h attribute: read/write this register passes data (apm commands) between the os and the smi handler. in addition, writes can generate an smi and reads can cause stpclk# to be asserted. the sio/sio.a operation is not affected by the data in this register. bit description 7:0 apm control port (apmc): writes to this register store data in the apmc register and reads return the last data written. in addition, writes generate an smi, if bit 7 of the smien register and bit 0 of the smicntl register are both is set to 1. reads cause the stpclk# signal to be asserted, if bit 1 of the smicntl register is set to 1. reads do not generate an smi. 3.6.2. apms ? advanced power management status port i/o address: 0b3h default value: 00h attribute: read/write this register passes status information between the os and the smi handler. the sio/sio.a operation is not affected by the data in this register. bit description 7:0 apm status port (apms): writes store data in this register and reads return the last data written. 3.7. apic registers (82379ab only) this section describes the registers used to program the advanced programmable interrupt controller. the i/o apic registers are accessed by an indirect addressing scheme using two registers (ioregsel and iowin) that are located in the cpu's memory space (memory address specified by the apicbase register). to reference an i/o apic register, a dword memory write loads the ioregsel register with a 32 bit value that specifies the apic register. the iowin register then becomes a four byte window pointing to the apic register specified by bits [7:0] of the ioregsel register. the register address table is at the beginning of the register section. all apic registers are accessed using 32-bit loads and stores. this implies that to modify a field (e.g., bit, byte) in any register, the whole 32-bit register must be read, the field modified, and the 32 bits written back. in addition, registers that are described as 64 bits wide are accessed as multiple independent 32-bit registers.
82378 zb (sio) and 82379ab (sio.a) e 82 3.7.1. ioregsel ? i/o register select regis ter (82379ab only) memory address: fec0 xy00h (xy=see apicbase register) default value: 00h attribute: read/write this register selects an i/o apic unit register. the contents of the selected 32-bit register can be manipulated via the i/o window register. bit description 31:8 reserved 7:0 apic register address: bits[7:0] specify the apic register to be read/written via the iowin register. 3.7.2. iowin ? i/o window register (82379ab only) memory address: fec0 xy10h (xy=see apicbase register) default value: 00h attribute: read/write this register is mapped onto the i/o unit's register selected by the ioregsel register. readability/writability by software is determined by the i/o apic register that is currently selected. bit description 31:0 apic register data: memory references to this register are mapped to the apic register specified by the contents of the ioregsel register. 3.7.3. apicid ? i/o apic identification register (82379ab only) address offset: 00h default value: 00000000h attribute: read/write this register contains the unit's 4-bit apic id. the id serves as a physical name of the i/o apic unit. all apic units using the apic bus should have a unique apic id. the apic bus arbitration id for the i/o unit is also writtten during a write to the apicid register (same data is loaded into both). this register must be programmed with the correct id value before using the i/o apic unit for message transmission. bit description 31:28 reserved 27:24 i/o apic identification: this 4 bit field contains the i/o apic identification. 23:0 reserved
e 82378 zb (sio) and 82379 (sio.a) 83 3.7.4. apicid ? i/o apic version register (82379ab only) address offset: 01h default value: 000f0011h attribute: read only the i/o apic version register identifies the apic hardware version. software can use this to provide compatibility between different apic implementations and their versions. in addition, this register provides the maximum number of entries in the i/o redirection table. bit description 31:24 reserved 23:16 maximum redirection entry: this field contains the entry number (0 being the lowest entry) of the highest entry in the i/o redirection table. the value is equal to the number of interrupt input pins minus one of this i/o apic. the range of values is 0 through 239. for the 82379ab, this value is 0fh. 15:8 reserved 7:0 apic version: this 8 bit field identifies the implementation version. the version number for the 82379ab is 11h. 3.7.5. apicarb ? i/o apic arbitration register (82379ab only) address offset: 02h default value: 00000000h attribute: read only the apicarb register contains the bus arbitration priority for the i/o apic. this register is loaded when the i/o apic id register is written. bit description 31:28 reserved 27:24 i/o apic arbitration identification: this 4 bit field contains the i/o apic arbitration priority identification. 23:0 reserved 3.7.6. ioredtbl[15:0] ? i/o redirection table registers (82379ab only) address offset: 10-11h (ioredtbl0) 1c-1dh (ioredtbl6) 26-27h (ioredtbl1 1) 12-13h (ioredtbl1) 1e-1fh (ioredtbl7) 28-29h (ioredtbl12) 14-15h (ioredtbl2) 20-21h (ioredtbl8) 2a-2bh (ioredtbl13) 16-17h (ioredtbl3) 22-23h (ioredtbl9) 2c-2dh (ioredtbl14) 18-19h (ioredtbl4) 24-25h (ioredtbl10) 2e-2fh (ioredtbl15) 1a-1bh (ioredtbl5) default value: xx000000 00010xxxh attribute: read/write each of the 16 i/o redirection table entry registers is a dedicated entry for each interrupt input pin. unlike irq pins of the 8259a, the notion of interrupt priority is completely unrelated to the position of the physical interrupt input pin on the apic. instead, software determines the vector (and therefore the priority) for each corresponding interrupt input pin. for each interrupt pin, the operating system can also specify the signal polarity (low active or
82378 zb (sio) and 82379ab (sio.a) e 84 high active), whether the interrupt is signaled as edges or levels, as well as the destination and delivery mode of the interrupt. the information in the redirection table is used to translate the corresponding interrupt pin information into an inter-apic message. for a signal on an edge-sensitive interrupt input pin to be recognized as a valid edge (and not a glitch), the input level on the pin must remain asserted until the i/o apic unit broadcasts the corresponding message over the apic bus and the message has been accepted by the destination(s) specified in the destination field. only then will the source apic be able to recognize a new edge on that interrupt input pin. that new edge only results in a new invocation of the handler if its acceptance by the destination apic causes the interrupt request register bit to go from 0 to 1. (in other words, if the interrupt wasn't already pending at the destination.) bit description 63:56 destination field ? r/w: if the destination mode of this entry is physical mode (bit 11=0), bits[59:56] contain an apic id. if logical mode is selected (bit 11=1), the destination field potentially defines a set of processors. bits[63:56] of the destination field specify the logical destination address. 55:17 reserved 16 interrupt mask ? r/w: when this bit is 1, the interrupt signal is masked. edge-sensitive interrupts signaled on a masked interrupt pin are ignored (i.e., not delivered or held pending). level-asserts or negates occurring on a masked level-sensitive pin are also ignored and have no side effects. changing the mask bit from unmasked to masked after the interrupt is accepted by a local apic has no effect on that interrupt. this behavior is identical to the case where the device withdraws the interrupt before that interrupt is posted to the processor. it is software's responsibility to handle the case where the mask bit is set after the interrupt message has been accepted by a local apic unit but before the interrupt is dispensed to the processor. when this bit is 0, the interrupt is not masked. an edge or level on an interrupt pin that is not masked results in the delivery of the interrupt to the destination. 15 trigger mode ? r/w: the trigger mode field indicates the type of signal on the interrupt pin that triggers an interrupt. this bit is set to 1 for level sensitive and 0 for edge sensitive. 14 remote irr ? ro: this bit is used for level triggered interrupts. its meaning is undefined for edge triggered interrupts. for level triggered interrupts, this bit is set to 1 when local apic(s) accept the level interrupt sent by the i/o apic. the remote irr bit is set to 0 when an eoi message with a matching interrupt vector is received from a local apic. 13 interrupt input pin polarity (intpol) ? r/w: this bit specifies the polarity of the interrupt signal. a 0 selects high active and a 1 selects low active. 12 delivery status (delivs) ? ro: the delivery status bit contains the current status of the delivery of this interrupt. delivery status is read-only and writes to this bit (as part of a 32 bit word) do not affect this bit. when bit 12=0 (idle), there is currently no activity for this interrupt. when bit 12=1 (send pending), the interrupt has been injected. however, its delivery is temporarily held up due to the apic bus being busy or the inability of the receiving apic unit to accept that interrupt at that time. 11 destination mode (destmod) ? r/w: this field determines the interpretation of the destination field. when destmod=0 (physical mode), a destination apic is identified by its id. bits 56 through 59 of the destination field specify the 4-bit apic id. when destmod=1 (logical mode), destinations are identified by matching on the logical destination under the control of the destination format register and logical destination register in each local apic. bits 56 through 63 (8 msb) of the destination field specify the 8 bit apic id.
e 82378 zb (sio) and 82379 (sio.a) 85 bit description 10:8 delivery mode (delmod) ? r/w: the delivery mode is a 3-bit field that specifies how the apics listed in the destination field should act upon reception of this signal. note that certain delivery modes only operate as intended when used in conjunction with a specific trigger mode. these restrictions are indicated in the following table for each delivery mode. bits mode de scription [10:8] 000 fixed deliver the signal on the int signal of all processor cores listed in the destination. trigger mode for "fixed" delivery mode can be edge or level. 001 lowest priority deliver the signal on the int signal of the processor core that is executing at the lowest priority among all the processors listed in the specified destination. trigger mode for "lowest priority". delivery mode can be edge or level. 010 smi system management interrupt. a del ivery mode equal to smi requires an edge trigger mode. the vector information is ignored but must be programmed to all zeroes for future compatibility. 011 reserved 100 nmi deliver the signal on the nmi signal of all processor cores listed in the destination. vector information is ignored. nmi must be programmed as edge-triggered for proper operation. 101 init deliver the signal to all processor cores listed in the destination by asserting the init signal. all addressed local apics will assume their init state. init must be programmed as edge-triggered for proper operation. 110 reserved 111 extint deliver the signal to the int signal of all processor cores listed in the destination as an interrupt that originated in an externally connected (8259a-compatible) interrupt controller. the inta cycle that corresponds to this extint delivery is routed to the external controller that is expected to supply the vector. a delivery mode of "extint" requires an edge trigger mode. 7:0 interrupt vector (intvec) ? r/w : the vector field is an 8-bit field containing the interrupt vector for this interrupt. vector values range from 10 ? feh.
82378 zb (sio) and 82379ab (sio.a) e 86 4. 0. functional description this section describes the sio/sio.a functions and hardware interfaces including memory and i/o address mapping, pci interface, isa interface, system arbitration, dma, interrupt controller, advanced interrupt controller, timer/counters, power management, and the utility bus. 4.1. memory and i/o a ddress map the sio/sio.a interfaces to the pci and isa buses. positive decode is provided for certain pci master memory and i/o accesses. the sio/sio.a also provides positive decode for certain dma and isa master memory and i/o accesses. 4.1.1. memory address map (generating memcs#) pci master access the sio/sio.a decodes accesses to main memory and generates a memory chip select (asserts memcs#), if enabled. various memory regions listed below can be enabled/disabled by programming the mcscon, mcsboh, mcstoh, mcstom, mar1, mar2, and mar3 registers. accesses within these enabled regions generate a memcs# signal that can be used by the host bridge to know when to forward pci cycles to main memory. 0 ? 512 kbytes memory (can only be disabled if memcs# is completely disabled) 512 ? 640 kbytes memory (1 mbyte-64 kbytes) to 1 mbyte memory (bios area) 768 ? 918 kbytes in 16-kbyte se ctions (total of 8 sections) 918 ? 983 kbytes in 16-kbyte sections (total of 4 sections) 1 mbyte-to-programmable boundary on 2-mbyte increments from 2 ? 512 mbytes programmable memory hole in 64-kbyte increments between from 1 ? 16 mbytes the sio/sio.a generates memcs# from the pci address. memcs# is generated from the clock edge after frame# is sampled active. memcs# will only go active for one pci clock period. the sio/sio.a does not take any other action as a result of this decode other than generating memcs#. it is the responsibility of the device using the memcs# signal to generate devsel#, trdy# and any other cycle response. the device using memcs# will always generate devsel# on the next clock. this fact can be used to avoid an extra clock delay in the subtractive decoder described in the next section. isa/dma access isa master or dma accesses that are positively decoded are forwarded to the pci bus. various memory regions listed below can be enabled/disabled by programming the iadcon, iadboh, iadtoh, and iadrbe registers. a memory address above 16 mbytes will be forwarded to the pci bus automatically. this is possible only during dma cycles in which the dma has been programmed for addressing above 16 mbytes. 0 ? 512 kbytes 512 ? 640 kbytes 640 ? 768 kbytes (video buffer) 768 ? 896 kbytes in eight 16-kbyte sections (expansion rom) 896 ? 960 kbytes (lower bios area)
e 82378 zb (sio) and 82379 (sio.a) 87 1-to-x mbytes (up to 16 mbytes) within which a hole can be opened. accesses to the hole are not forwarded to pci. the top of the region can be programmed on 64 kbyte boundaries up to 16 mbytes. the hole can be between 64 kbytes and 8 mbytes in size in 64-kbyte increments located on any 64-kbyte boundary. greater than 16 mbytes are forw arded to pci 4.1.2. bios memory space pci master access the sio/sio.a supports 512 kbytes of bios space. this includes the normal 128-kbyte space plus an additional 384-kbyte bios space (known as the enlarged bios area). the 128-kbyte bios memory space is located at 000e0000 ? 000fffffh (top of 1 mbyte), and is aliased at fffe0000 ? ffffffffh (top of 4 gbytes) and ffee0000 ? ffefffffh (top of 4 gbytes-1 mbyte). this 128-kbyte block is split into two 64 -kbyte blocks. the top 64 kbytes is always enabled while the bottom 64 kbytes can be enabled or disabled (the aliases automatically match). when the lower 64-kbyte bios space (000e0000 ? 000effffh) is enabled, accesses to this space generate a bios chip select (asserts bioscs#). access to the upper 64 kbytes is controlled by bit 6 in the isa clock divisor register and bit 4 in the memcs# control register. when pci master accesses to the 128-kbyte bios space at 4 gbytes - 1 mbyte are forwarded to the isa bus, the la20 line is driven to a 1 to avoid aliasing at the 15-mbyte area. the 4 gbytes - 1 mbyte bios region accounts for the condition when a20m# is asserted and an alt-ctrl-del reset is generated. the cpu's reset vector will access 4 gbyte - 1 mbyte. when this gets forwarded to isa, ad[32:24] are truncated and the access is aliased to 16 mbytes - 1 mbyte = 15 mbyte space. if isa memory is present at 15 mbytes, there will be contention. forcing la20 high aliases this region to 16 mbytes. the alias here is permissible since this is the 80286 reset vector location. the additional 384-kbyte region (fff80000 ? fffdffffh) can only be accessed by pci masters. when enabled via the ubcsa register, memory accesses within this region are forwarded to the isa bus and encoded bioscs# generated. when forwarded to the isa bus, the pci ad[23:20] signals will be propagated to the isa la[23:20] lines as all 1s which will result in aliasing this 512-kbyte region at the top of the 16-mbyte space. to avoid contention, isa add-in memory must not be present in this space. all pci accesses to enabled bios space are forwarded to the isa bus. note that pci burst reads from the bios space invoke "disconnect target termination", in order to meet the pci incremental latency guidelines. isa/dma access isa masters can only access bios in the 000e0000 ? 000fffffh region. isa originated accesses to the enabled 64-kbyte sections of the bios space (000e0000h ? 000fffffh) generate the encoded bioscs# signal. isa originated cycles arel not forwarded to the pci bus. encoded bioscs# is combinatorially generated from the isa sa and la address bus. encoded bioscs# is disabled during refresh and dma cycles. 4.1.3. i/o accesses for pci master accesses, the sio/sio.a positively decodes i/o addresses for registers contained within the sio/sio.a (exceptions: 60h, 70h, 92h, 3f2h, 372h, and f0h). the sio/sio.a also provides positive decode for isa masters to most of the isa-compatible registers. refer to the register description section for details on accessing the sio/sio.a internal registers. note that for the sio.a, the apic registers are memory mapped and accesses to these registers are also described in the register description section.
82378 zb (sio) and 82379ab (sio.a) e 88 4.1.4. subtractively decoded cycles to isa the addresses that reside on the isa bus could be highly fragmented. for this reason, subtractive decoding is used to forward pci cycles to the isa bus. an inactive devsel# will cause the sio/sio.a to forward the pci cycle to the isa bus. the devsel# sample point can be configured for three different settings ? fast, typical, or slow. note that when unclaimed cycles are forwarded to the isa bus, the sio/sio.a asserts devsel#. since an active memcs# will always result in an active devsel# at the "slow" sample point, memcs# is used as an early indication of devsel#. in this case, if the device using memcs# is the only "slow" agent in the system, the sample point can be moved in to the "typical" edge. unclaimed pci cycles with memory addresses above 16m and i/o addresses above 64k are not forwarded to the isa bus. to avoid the possibility of aliasing, the sio/sio.a does not respond with devsel# (bios accesses are an exception to this). 4.1.5. utility bus encoded chip selects the sio/sio.a generates encoded chip selects for certain functions that are located on the utility bus (formerly x-bus). the encoded chip selects are generated combinatorially from the isa sa[15:0] address bus. chip selects can be enabled or disabled via configuration registers. in general, the chip select addresses do not reside in the sio/sio.a itself. write only addresses 70h, 372h, 3f2h are exceptions since particular bits from these registers reside in the sio/sio.a. for isa master cycles, the sio/sio.a responds to writes to address 70h, 372h, and 3f2h by generating iochrdy and writing to the appropriate bits. note that the sio/sio.a monitors read accesses to address 60h to support the mouse function. in this case, iochrdy is not generated. 4.2. pci interface 4.2.1. pci command set bus commands indicate to the slave the type of transaction the master is requesting. bus commands are encoded on the c/be[3:0]# lines during the address phase of a pci cycle. table 6 . pci commands c/be[3:0]# command type as slave supported as slave supported as master 0000 interrupt acknowledge yes no 0001 special cycle 4 no/yes no 0010 i/o read yes no 0011 i/o write yes no 0100 reserved 3 no no 0101 reserved 3 no no 0110 memory read yes yes 0111 memory write yes yes 1000 reserved 3 no no
e 82378 zb (sio) and 82379 (sio.a) 89 c/be[3:0]# command type as slave supported as slave supported as master 1001 reserved 3 no no 1010 configuration read yes no 1011 configuration write yes no 1100 memory read multiple no 2 no 1101 reserved 3 no no 1110 memory read line no 2 no 1111 memory write and invalidate no 1 no notes: 1. treated as memory write. 2. treated as memory read. 3. reserved cycles are considered invalid by the sio/sio.a and are to be competely ignored. all internal address decoding is ignored and devsel# is never to be asserted. 4. special cycles are considered invalid by the 82378ib and are completely ignored. the 82378 zb responds to a stop grant special cycle. note during pci reads of the isa bus the pci ad signals can change asynchrounously. the system design should be careful to avoid any cross coupled noise that may be generated from the pci ad signals onto the pci control signals. otherwise, system failures may occur. 4.2.2. transaction termination the sio/sio.a supports both master-initiated termination as well as target-initiated termination. two forms of master-initiated termination are supported ? normal te rmination of a completed transaction and abnormal termation due to no slave response to the transaction (abort). the sio/sio.a also supports three forms of target-initiated termination ? disconnect, retry, and abort. note the sio/sio.a always terminates burst cycles with a disconnect protocol. except for accesses to the internal bios timer register, the sio/sio.a issues a target-abort when the internal sio/sio.a registers are the target of a pci master i/o cycle and more than one byte enable is active. the following lists the sio/sio.a response as a master to a target-termination: 1. for a target-abort, the sio/sio.a will not retry the cycle. if an isa master or the dma is waiting for the pci cycle to complete (chrdy negated), the target-abort condition will cause the sio/sio.a to assert chrdy and end the cycle on the isa bus. if the isa master or dma device was reading from pci memory, the sio/sio.a will drive all 1's on the data lines of the isa bus. the received target-abort status bit in the pci status register will be set indicating that the sio/sio.a experienced a target-abort condition. 2. if the sio/sio.a is retried as a master on the pci bus, it will remove it's request for 2 pci clocks before asserting it again to retry the cycle. 3. if the sio/sio.a is disconnected as a master on the pci bus, it will respond very much as if it had been retried. the difference between retry and disconnect is that the sio/sio.a did not see any data phase for the retry.
82378 zb (sio) and 82379ab (sio.a) e 90 4.3. pci arbitration controller the sio/sio.a contains a pci bus arbiter that supports six pci masters; the host bridge, sio/sio.a, and two other masters. the sio/sio.a req#/gnt# lines are internal. the integrated arbiter can be disabled by asserting cpureq# during pcirst#. when disabled, the sio/sio.a req#, gnt#, and resume# signals become visible for an external arbiter. the internal arbiter is enabled upon power-up. the internal arbiter contains several features that contribute to system efficiency: use of a resume# signal to re-enable a backed-off initiator in order to minimize pci bus thrashing when the sio/sio.a generates a retry. a programmable timer to re-enable retried initiators after a programmable number of pciclks. the cpu (host bridge) can be optionally parked on the pci bus. a programmable pci bus lock or pci resource lock function. the pci arbiter is also responsible for control of the guaranteed access time (gat) mode signals. 4.3.1. arbitration signal protocol the internal arbiter follows the pci arbitration method as outlined in the peripheral component interconnect (pci) specification . the pci arbitration priority scheme is programmable through the pci arbiter priority control and arbiter priority control extension register. see the register description section for further discussions on arbitration priority. note 1. the sio /sio.a as a master does not generate fast back-to-back accesses. 2. as a target, the sio/sio.a does support back-to-back transactions. for back-to-back cycles, the sio/sio.a treats positively decoded accesses and subtractively decoded accesses as different targets. therefore, masters can only run fast back-to-back cycles to positively decoded addresses or to subtractively decoded addresses. 3. before an isa master or the dma can be granted the pci bus, it is necessary that all pci system posted write buffers be flushed (including the sio/sio.a posted write buffer). also, since the isa originated cycle could access memory on the host bridge, it's possible that the isa master or the dma could be held in wait states (via iochrdy) waiting for the host bridge arbitration for longer than the 2.5 s isa specification. the sio/sio.a has an optional mode called the guaranteed access time mode (gat) that ensures that this timing specification is not violated. 4. an external arbiter in gat mode will require special lo gic in the arbiter. retry thrashing resolve when a pci initiator's access is retried, the initiator releases the pci bus for a minimum of two pci clocks and will then normally request the pci bus again. to avoid thrashing the bus with retry after retry, the pci arbiter provides req# masking. the req# masking mechanism differentiates between sio/sio.a target retries and all other retries. for initiators which were retried by the sio/sio.a as a target, the masked req# is flagged to be cleared upon resume# active. all other retries trigger the master retry timer, if enabled. when the timer expires, the mask is cleared. the conditions under which the sio/sio.a forces a retry to a pci master and will mask the req# are: 1. any required buffer management
e 82378 zb (sio) and 82379 (sio.a) 91 2. isa bus occupied by isa master or dma 3. the pci to isa posted write buffer is full 4. the sio/sio.a is locked as a resource and lock# is asserted during the address process. the resume# signal is pulsed whenever the sio/sio.a has retried a pci cycle for one of the above reasons and that condition has passed. when resume# is asserted, the sio/sio.a will unmask the req#'s that are masked and flagged to be cleared by resume#. if the internal arbiter is enabled, resume# is an internal signal. the resume# signal becomes visible as an output when the internal arbiter is disabled. this allows an external arbiter to optionally avoid retry thrashing associated with the sio/sio.a as a target. the resume# signal is asserted for one pci clock. bus parking the sio/sio.a provides pci bus parking (enabled via the arbiter control register). parking is only allowed for the device which is tied to cpureq# (typically the system cpu). when bus parking is enabled, cpugnt# is asserted when no other agent is currently using or requesting the bus. when cpugnt# is asserted due to bus parking enabled and the pci bus idle, the cpu (or the parked agent) must ensure that ad[31:0], c/be[3:0], and (one pciclk later) par are driven. if bus parking is disabled, the sio/sio.a takes responsibility for driving the bus when it is idle. bus lock mode as an option, the sio/sio.a arbiter can be configured to run in bus lock mode or resource lock mode. the bus lock mode is used to lock the entire pci bus. this may improve performance in some systems that frequently run quick read-modify-write cycles. bus lock mode emulates the lock environment found in today's pc by restricting bus ownership when the pci bus is locked. with bus lock enabled, the arbiter recognizes a lock# being driven by any initiator and does not allow any other pci initiator to be granted the pci bus until lock# and frame# are both negated indicating the master released lock. when bus lock is disabled, the default resource lock mechanism is implemented (normal resource lock) and a higher priority pci initiator could intervene between the read and write cycles and run non-exclusive accesses to any unlocked resource. 4.3.2. internal/external arbiter configuration the sio/sio.a arbiter is enabled if cpureq# is sampled high on the trailing edge of pcirst#. when enabled, the arbiter is set in fixed priority mode 4 with cpu bus parking turned off. fixed mode 4 guarantees that the cpu will be able to run accesses to the bios in order to configure the system, regardless of the state of the other req#'s. note that the host bridge should drive cpureq# high during the trailing edge of pcirst#. when the arbiter is enabled, the sio/sio.a acts as the central resource responsible for driving the ad[31:0], c/be[3:0]#, and par signals when no one is granted the pci bus and the bus is idle. the sio/sio.a is always responsible for driving ad[31:0], c/be[3:0]#, and par when it is granted the bus and as appropriate when it is the master of a transaction. after reset, if the arbiter is enabled, cpugnt#, gnt0#, gnt1#, and the internal siognt# will be driven based on the arbitration scheme and the asserted req#'s. if an external arbiter is present in the system, the cpureq# signal should be tied low. when cpureq# is sampled low on the trailing edge of pcirst#, the internal arbiter is disabled. when the internal arbiter is disabled, the sio/sio.a does not drive ad[31:0], c/be[3:0]#, and par as the central resource. in this case, the sio/sio.a is only responsible for driving ad[31:0], c/be[3:0]#, and par when it is granted the bus. if the sio/sio.a arbiter is disabled, gnt0# becomes sioreq#, gnt1# becomes resume#, and req0# becomes siognt#. this exposes the normally embedded sio/sio.a arbitration signals. note that usage of an external arbiter in gat mode will require special logic in the arbiter.
82378 zb (sio) and 82379ab (sio.a) e 92 4.3.3. guaranteed access time mode guaranteed access time (gat) mode is enabled/disabled via the pci arbiter control register. when this mode is enabled, the memreq# and memack# signals are used to guarantee that the isa 2.5 s iochrdy specification is not violated. when an isa master or dma slave requests the isa bus (dreq# active), the isa bus, the pci bus, and the memory bus must be arbitrated for and all three must be owned before the isa master or dma slave is granted the isa bus. after receiving the dreq# signal from the isa master or dma slave, memreq# and flshreq# are asserted (flshreq# is driven active, regardless of gat mode being enabled or disabled). memreq# is a request for direct access to main memory. memreq# and flshreq# will be asserted as long as the isa master or the dma owns the isa bus. when memack# is received by the sio/sio.a (all posted write buffers are flushed and the memory bus is dedicated to the pci interface), it will request the pci bus. when it is granted the pci bus, it asserts the dack signal releasing the isa bus to the requesting master or the dma. the use of memreq#, flshreq#, and memack# does not guarantee functionality with isa masters that don't acknowledge iochrdy. these signals just guarantee the iochrdy inactive specification. note that usage of an external arbiter in gat mode will require special logic in the arbiter. 4.3.3.1. dma latencies in gat mode only (82378ZB only) in gat mode, the system may have dreq# to dack# latencies of up to 53 msec. two recommendations for reducing long latencies are: 1. bios implementation: use non-gat mode. systems may not meet the 2.1 m s iochrdy specification in non-gat mode if a write back cycle is required. however, intel has found no issues with non-gat mode in compatibility testing. because non-gat mode allows concurrency on all three buses in the system, (host, pci and isa buses) non-gat mode is the preferred and higher performance mode of operation for a pci system. 2. bios and hardware implementation: use non-gat mode and connect the flushreq# pin from the 82378ZB to the flushreq# and memreq# pins of the host bridge (neptune, saturn or mercury). memreq# on the 82378ZB is unconnected. this avoids the dreq# to dack# latency and still meets the isa 2.1 us iochrdy specification. 4.4. isa interface the sio/sio.a incorporates a fully isa bus compatible master and slave interface. the sio/sio.a directly drives six isa slots without external data or address buffers. the isa interface also provides byte swap logic, i/o recovery support, wait-state generation, and sysclk generation. the isa interface supports the following types of cycles: pci-initiated i/o and memory cycles to the isa bus. for the 82379ab, dma compatible cycles between pci memory and isa i/o and between isa i/o and isa memory. for the 82378ZB, dma compatible cycles between pci memory and isa i/o and between isa i/o and isa memory, dma type "a", type "b", and type "f" cycles between pci memory and isa i/o. isa refresh cycles initiated by either the sio/sio.a or an external isa master. isa master-initiated memory cycles to the pci bus and isa master-initiated i/o cycles to the internal sio/sio.a registers.
e 82378 zb (sio) and 82379 (sio.a) 93 an isa master can access pci memory, but not i/o devices residing on the pci bus. if the sio/sio.a is programmed for gat mode, the sio/sio.a arbiter will not grant the isa bus before gaining ownership of both the pci bus and system memory. however, if the sio/sio.a is not programmed in this mode, the sio/sio.a does not need to arbitrate for the pci bus before granting the isa bus to the isa master. all cycles forwarded to a pci resource will run as 16-bit extended cycles (i.e., iochrdy will be held inactive until the cycle is completed). because the isa bus size is different from the pci bus size, the data steering logic inside the sio/sio.a is responsible for steering the data to the correct byte lanes on both buses, and assembling/disassemblying the data as necessary. 4.4.1. isa clock generation the sio/sio.a generates the isa system clock (sysclk). sysclk is a divided down version of the pciclk (see table 9). the clock divisor value is programmed through the isa clock divisor register. table 7 . sysclk generation from pciclk pciclk (mhz) divisor (programmable) sysclk (mhz) 25 3 8.33 33 4 (default) 8.33 note: for pci frequencies less than 33 mhz (not including 25 mhz), a clock divisor value must be selected that ensures that the isa bus frequency does not violate the 6 mhz to 8.33 mhz sysclk specification. note when the isa clock divisor is programmed for pciclk/3 (i.e., offset 4dh, bits 2:0 are set to 001), the dma line should be disabled. for proper operation, disable the dma line buffers by setting bit 0 of the pci control register (offset 40h) to 0 when pciclk/3 is selected. note that the isa master line buffer enable (bit 1) can remain enabled. 4.5. dma controller the 82378ZB/82379ab dma circuitry incorporates the functionality of two 82c37 dma controllers with seven independently programmable channels (channels 0 - 3 and channels 5 - 7). dma channel 4 is used to cascade the two controllers and will default to cascade mode in the dma channel mode (dcm) register. in addition to accepting requests from dma slaves, the dma controller also responds to requests that are initiated by software. software may initiate a dma service request by setting any bit in the dma channel request register to a 1. the dma controller for channels 0-3 is referred to as "dma-1" and the controller for channels 4 - 7 is referred to as "dma-2".
82378 zb (sio) and 82379ab (sio.a) e 94 c h a n n e l 0 c h a n n e l 1 c h a n n e l 3 c h a n n e l 2 d m a - 1 c h a n n e l 4 c h a n n e l 5 c h a n n e l 7 c h a n n e l 6 d m a - 2 057102 figure 2 . internal dma controller for the 82378ZB, the dma supports programmable 8 and 16-bit device sizes per channel using isa-compatible, type "a", type "b", or type "f" transfer timing. each dma channel defaults to the compatible settings for dma device size: channels [3:0] default to 8-bit, count-by-bytes transfers, and channels [7:5] default to 16-bit, count- by-words (address shifted) transfers. the sio provides the timing control and data size translation necessary for the dma transfer between the pci and the isa bus. isa-compatible is the default transfer timing. full 32-bit addressing is supported as an extension of the isa-compatible specification. for the 82379ab, the dma supports 8/16-bit device size using isa-compatible timings. each dma channel is hardwired to the compatible settings for dma device size ? channels [3:0] are hardwired to 8-bit, count-by-bytes transfers and channels [7:5] are hardwired to 16-bit, count-by-words (address shifted) transfers. the 82379ab provides the timing control and data size translation necessary for the dma transfer between the pci and the isa bus. full 27-bit addressing is supported as an extension of the isa-compatible specification for both the 82378ZB and 82379ab, a dma device (i/o device) is always on the isa bus, but the memory referenced is located on either an isa bus device or in main memory. for compatible timing mode, the sio/sio.a drives the memr# or memw# strobes if the address is less than 16 mbytes (00000000 - 00ffffffh). note that the 82379ab always generates isa-compatible dma memory cycles. the memr# and memw# memory strobes are generated, regardless of whether the cycle is decoded for pci or isa memory. the smemr# and smemw# is generated if the address is less than 1 mbyte (00000000 - 000fffffh). to avoid aliasing problems when the address is greater than 16 mbytes (1000000 ? 7ffffffh), the memr# or memw# strobe is not generated. for the 82378ZB, if the memory is decoded to be on the isa bus, the dma cycle runs as a compatible cycle. if the memory is decoded to be on the pci bus, the cycle can run as compatible, "a", "b", or "f" type. the isa controller does not drive a valid address for type "a", "b", and "f" dma transfers on the isa bus. for type "a", "b", and "f" timing mode dma cycles, the sio only generates the memr# or memw# strobe when the address is decoded for isa memory. when this occurs, the cycle converts to compatible mode timing. for both the 82378ZB and 82379ab, the channels can be programmed for any of four transfer modes ? single, block, demand, or cascade. each of the three active transfer modes (single, block, and demand), can perform three different types of transfers (read, write, or verify). note that memory-to-memory transfers are not supported by the 82379ab. the dma supports fixed and rotating channel priorities. the dma controller also features refresh address generation, and auto-initialization following a dma termination. 4.5.1. dma timings isa-compatible timing is provided for dma slave devices. for the 82378ZB, three additional timings are provided for i/o slaves capable of running at faster speeds. these timings are referred to as type "a", type "b", and type "f".
e 82378 zb (sio) and 82379 (sio.a) 95 4.5.1.1. compatible timing (82378ZB and 82379ab) compatible timing runs at 8 sysclks during the repeated portion of a block or demand mode transfer. 4.5.1.2. type "a" timing (82378ZB) type "a" timing is provided to allow shorter cycles to pci memory. type "a" timing runs at 6 sysclks (720 ns/cycle) during the repeated portion of a block or demand mode transfer. this timing assumes an 8.33 mhz sysclk. type "a" timing varies from compatible timing primarily in shortening the memory operation to the minimum allowed by system memory. the i/o portion of the cycle (data setup on write, i/o read access time) is the same as with compatible cycles. the actual active command time is shorter, but it is expected that the dma devices which provide the data access time or write data setup time should not require excess ior# or iow# command active time. because of this, most isa dma devices should be able to use type "a" timing. 4.5.1.3. type "b" timing (82378ZB) type "b" timing is provided for 8/16-bit isa dma devices which can accept faster i/o timing. type "b" only works with pci memory. type "b" timing runs at 5 sysclks (600 ns/cycle) during the repeated portion of a block or demand mode transfer. this timing assumes an 8.33 mhz sysclk. type "b" timing requires faster dma slave devices than compatible timing in that the cycles are shortened so that the data setup time on i/o write cycles is shortened and the i/o read access time is required to be faster. some of the current isa devices should be able to support type "b" timing, but these will probably be more recent designs using relatively fast technology. 4.5.1.4. type "f" timing (82378ZB) type "f" timing provides high performance dma transfer capability. these transfers are mainly for fast i/o devices (i.e., ide devices). type "f" timing runs at 3 sysclks (360 ns/cycle) during the repeated portion of a block or demand mode transfer. 4.5.1.5. dreq and dack# latency control (82378ZB and 82379ab) the sio/sio.a dma arbiter maintains a minimum dreq to dack# latency on dma channels programmed to operate in compatible timing mode. this is to support older devices such as the 8272a. the dreqs are delayed by eight sysclks prior to being seen by the arbiter logic. software requests will not have this minimum request to dack# latency. 4.5.2. isa refresh cycles (82378ZB and 82379ab) refresh cycles are generated by two sources: the refresh controller inside the sio/sio.a component or by isa bus masters other than the sio/sio.a. the isa bus controller will enable the address lines sa[15:0] so that when memr# goes active, the entire isa system memory is refreshed at one time. memory slaves on the isa bus must not drive any data onto the data bus during the refresh cycle. 4.5.3. scatter/gather (s/g) description (82378ZB) scatter/gather (s/g) provides the capability of transferring multiple buffers between memory and i/o without cpu intervention. in s/g, the dma can read the memory address and word count from an array of buffer descriptors, located in system memory (isa or pci), called the s/g descriptor (sgd) table. this allows the dma controller to sustain dma transfers until all of the buffers in the sgd table are transferred.
82378 zb (sio) and 82379ab (sio.a) e 96 the s/g command and status registers are used to control the operational aspect of s/g transfers. the sgd table pointer register holds the address of the next buffer descriptor in the sgd table. the next buffer descriptor is fetched from the sgd table by a dma read transfer. dack# will not be asserted for this transfer because the io device is the sio itself. the sio will fetch the next buffer descriptor from either pci memory or isa memory, depending on where the sgd table is located. if the sgd table is located in pci memory, the memory read will use the line buffer to temporarily store the pci read before loading it into the dma s/g registers. the line buffer mode (8-byte or single transaction) for the s/g fetch operation will be the same as what is set for all dma operations. if set in 8-byte mode, the sgd table fetches will be pci burst memory reads. the sgd table pci cycle fetches are subject to all types of pci cycle termination (retry, disconnect, target- abort, master-abort). the fetched sgd table data is subject to normal line buffer coherency management and invalidation. eop will be asserted at the end of the complete link transfer. to initiate a typical dma s/g transfer between memory and an i/o device, the following steps are required: 1. software prepares a sgd table in system memory. each sgd is 8 bytes long and consists of an address pointer to the starting address and the transfer count of the memory buffer to be transferred. in any given sgd table, two consecutive sgds are offset by 8 bytes and are aligned on a 4-byte boundary. each s/g descriptor for the linked list contains the following information: a. memory address (buffer start) 4 bytes b. transfer size (buffer size) 2 bytes c. end of link list 1 bit ( msb) m e m o r y a d d r e s s t r a n s f e r s i z e d w o r d 0 d w o r d 1 b y t e 3 b y t e 2 b y t e 1 b y t e 0 x x x 0 h a d d r e s s x x x 3 h x x x 4 h x x x 7 h e o l r s v d r s v d 057103 figure 3 . sgd format 2. initialize the dma channel mode and dma channel extended mode registers with transfer specific information like 8/16-bit i/o device, transfer mode, transfer type, etc. 3. software provides the starting address of the sgd table by loading the sgd table pointer register. 4. engage the s/g function by writing a start command to the s/g command register. 5. the mask register should be cleared as the last step of programming the dma register set. this is to prevent the dma from starting a transfer with a partially loaded command description. 6. once the register set is loaded and the channel is unmasked, the dma will generate an internal request to fetch the first buffer from the sgd table. after the above steps are finished, the dma will then respond to dreq or software requests. the first transfer from the first buffer moves the memory address and word count from the base register set to the current register set. as long as s/g is active and the base register set is not loaded and the last buffer has not been fetched, the channel will generate a request to fetch a reserve buffer into the base register set. the reserve buffer is loaded to minimize latency problems going from one buffer to another. fetching a reserve buffer has a lower priority than completing dma transfers for the channel.
e 82378 zb (sio) and 82379 (sio.a) 97 the dma controller will terminate a s/g cycle by detecting an end of list (eol) bit in the sgd table. after the eol bit is detected, the channel transfers the buffers in the base and current register sets, if they are loaded. at terminal count the channel asserts eop or irq13, depending on its programming and set the terminate bit in the s/g status register. if the channel asserted irq13, then the appropriate bit is set in the s/g interrupt status register. the active bit in the s/g status register will be reset and the channel's mask bit will be set. m e m o r y a d d r e s s t r a n s f e r s i z e s g d t a b l e m e m o r y b u f f e r s buffer a buffer b buffer c s g d a s g d b s g d c 0 0 1 s g d t a b l e p t r . r e g i s t e r p t r . p t r . + 8 h p t r . + 1 0 h t r a n s f e r s i z e t r a n s f e r s i z e m e m o r y a d d r e s s m e m o r y a d d r e s s 057104 figure 4 . link list example
82378 zb (sio) and 82379ab (sio.a) e 98 4.6. data buffering the sio/sio.a contains data buffers to isolate the pci bus from the isa bus. the buffering is described from two perspectives: pci master accesses to the isa bus (posted write buffer) and dma/isa master accesses to the pci bus (line buffer). temporarily buffering the data requires buffer management logic to ensure that the data buffers remain coherent. 4.6.1. dma/isa master line buffer an 8-byte line buffer is used to isolate the isa bus's slower i/o devices from the pci bus. the line buffer is bi- directional and is used by isa masters and the dma controller to assemble and disassemble data. only memory data written to or read from the pci bus by an isa master or dma is assembled/disassembled using this 8-byte line buffer. i/o cycles do not use the buffer. bits 0 and 1 of the pci control register set the buffer to operate in either single transaction mode (bit=0) or 8-byte mode (bit=1). note that isa masters and dma controllers can have their buffer modes configured separately. in single transaction mode, the buffer will store only one transaction. for dma/isa master writes, this single transaction buffer looks like a posted write buffer. as soon as the isa cycle is complete, a pci cycle is scheduled. subsequent dma/isa master writes are held off in wait-states until the buffer is empty. for dma/isa master reads, only the data requested is read over the pci bus. for instance, if the dma channel is programmed in 16-bit mode, 16 bits of data will be read from pci. as soon as the requested data is valid on the pci bus, it is latched into the line buffer and the isa cycle is then completed, as timing allows. single transaction mode will guarantee strong read and write ordering through the buffers. in 8-byte mode, for write data assembly, the line buffer acts as two individual 4 byte buffers working in ping pong fashion. for read data disassembly, the line buffer acts as one 8-byte buffer. 4.6.2. pci master posted write buffer pci master memory write cycles destined to isa memory are buffered in a 32-bit posted write buffer. the pci memory write and memory write and invalidate commands are all treated as a memory write and can be posted, subject to the posted write buffer status. the posted write buffer has an address associated with it. a pci master memory write can be posted any time the posted write buffer is empty and write posting is enabled (bit 2 of the pci control configuration register is set to a 1). also, the isa bus must not be occupied. if the posted write buffer contains data, the pci master write cycle is retried. if the posted write buffer is disabled, the sio/sio.a response to a pci master memory write is dependent on the state of the isa bus. if the isa bus is available and the posted write buffer is disabled, the cycle will immediately be forwarded to the isa bus (trdy# will not be asserted until the isa cycle has completed). if the isa bus is busy and the posted write buffer is disabled, the cycle is retried. memory read and i/o read and i/o write cycles do not use the 32-bit posted write buffer. 4.7. sio timers 4.7.1. interval timers the sio/sio.a contains three counters that are equivalent to those found in the 82c54 programmable interval timer. the three counters are contained in one sio/sio.a timer unit, referred to as timer-1. each counter output provides a key system function. counter 0 is connected to interrupt controller irq0 and provides a system timer interrupt for a time-of-day, diskette time-out, or other system timing functions. counter 1 generates a refresh request signal and counter 2 generates the tone for the speaker. note that the 14.31818 mhz counters use osc for a clock source.
e 82378 zb (sio) and 82379 (sio.a) 99 counter 0, system timer: this counter functions as the system timer by controlling the state of irq0 and is typically programmed for mode 3 operation. the counter produces a square wave with a period equal to the product of the counter period (838 ns) and the initial count value. the counter loads the initial count value one counter period after software writes the count value to the counter i/o address. the counter initially asserts irq0 and decrements the count value by two each counter period. the counter negates irq0 when the count value reaches 0. it then reloads the initial count value and again decrements the initial count value by two each counter period. the counter then asserts irq0 when the count value reaches 0, reloads the initial count value, and repeats the cycle, alternately asserting and negating irq0. counter 1, refresh request signal: this counter provides the refresh request signal and is typically programmed for mode 2 operation. the counter negates refresh request for one counter period (833 ns) during each count cycle. the initial count value is loaded one counter period after being written to the counter i/o address. the counter initially asserts refresh request, and negates it for 1 counter period when the count value reaches 1. the counter then asserts refresh request and continues counting from the initial count value. counter 2, speaker tone: this counter provides the speaker tone and is typically programmed for mode 3 operation. the counter provides a speaker frequency equal to the counter clock frequency (1.193 mhz) divided by the initial count value. the speaker must be enabled by a write to port 061h (see register description section). note 1. in the pc-at architecture, the three interval timers in the 82c54 perform the following functions ? timer 1 is the system timer, timer 2 provides the refresh request, and timer 3 is used for the speaker tone. the interval timer in the sio/sio.a, are intended to be used for these functions. other operations are not supported and may produce unintended operations. in other than these operations, the timer may be in a state where a counter can be read at the same time it?s count is changing and an incorrect value is latched. the readback and latch commands are also affected. 2. hardware re-triggerable one-shot mode (timer mode 1) for timer 2. this mode uses a rising edge on the timer gate input to start the timer. the timer gate input can be toggled by writing to i/o port 61h. because the gate pin is asserted relative to pciclk, the setup and hold time requirements of the gate pin relative to the 82c54 osc clock can be violated. because gate is edge triggered in timer mode 1, the 82c54 does not recognize the rising edge and the timer does not begin counting. in the pc-at architecture, timer 2 is the only timer that has its gate input connected to an i/o port. all the other gate inputs are tied high. this condition was uncovered during 82c54 diagnostic testing. no application failures have been reported due to this issue. 4.7.2. bios timer the sio/sio.a provides a system bios timer that decrements at each edge of its 1.04 mhz clock (derived by dividing the 8.33 mhz sysclk by 8). since the state of the counter is undefined at power-up, it must be programmed before it can be used. accesses to the bios timer are enabled and disabled through the bios timer base address register. the timer continues to count even if accesses are disabled. a bios timer register is provided to start the timer counter by writing an initial clock value. the bios timer register can be accessed as a single 16-bit i/o port or as a 32-bit port with the upper 16-bits being "don't care" (reserved). it is up to the software to access the i/o register in the most convenient way. the i/o address of the bios timer register is software relocatable. the i/o address is determined by the value programmed into the bios timer base address register. the bios timer clock has a value of 1.04 mhz using an 8.33 mhz sysclk input (an 8-to-1 ratio will always exist between sysclk and the timer clock). this allows the counting of time intervals from 0 to approximately 65 ms. because of the pci clock rate, it is possible to start the counter and read the value back in less than 1 s. the expected value of the expired interval is 0, but depending on the state of the internal clock divisor, the bios timer might indicate that 1 ms has expired. therefore, accuracy of the counter is 1 s.
82378 zb (sio) and 82379ab (sio.a) e 100 a write operation to the bios timer register will initiate the counting sequence. the timer can be initiated by writing either the 16-bit data portion or the whole 32-bit register (upper 16 bits are "don't care"). after initialization, the bios timer will start decrementing until it reaches zero. then it will stop decrementing (and hold a zero value) until initialized again. after the timer is initialized, the current value can be read at any time and the timer can be reprogrammed (new initial value written), even before it reaches zero. all write and read operations to the bios timer register should include all 16 counter bits. separate accesses to the individual bytes of the counter must be avoided since this can cause unexpected results (wrong count intervals). 4.8. interrupt controller the sio/sio.a provides an isa-compatible interrupt controller which incorporates the functionality of two 82c59 interrupt controllers. the two controllers are cascaded so that 14 external and two internal interrupts are possible. the master interrupt controller provides irq[7:0] and the slave interrupt controller provides irq[15:8] (see figure 5 ). the two internal interrupts are used for internal functions only and are not available to the user. irq2 is used to cascade the two controllers together and irq0 is used as a system timer interrupt and is tied to interval timer 1, counter 0. the remaining 14 interrupt lines (irq1, irq[15:3]) are available for external system interrupts. edge or level sense selection is programmable on a by-controller basis. the interrupt controller consists of two separate 82c59 cores. interrupt controller 1 (cntrl-1) and interrupt controller 2 (cntrl-2) are initialized separately and can be programmed to operate in different modes. the default settings are: 80x86 mode, edge sensitive (irq0-15) detection, normal eoi, non-buffered mode, special fully nested mode disabled, and cascade mode. cntrl-1 is connected as the master interrupt controller and cntrl-2 is connected as the slave interrupt controller. note that irq13 is generated internally (as part of the coprocessor error support) by the sio/sio.a when bit 5 in the isa clock divisor register is set to a 1. when this bit is set to a 0, then the ferr#/irq13 signal is used as an external irq13 signal and has the same functionality as the normal irq13 signal. irq12/m is generated internally (as part of the mouse support) by the sio/sio.a when bit 4 in the isa clock divisor register is set to a 1. when set to a 0, the standard irq12 function is provided. int (to cpu) 82c59 core controller 1 (master) timer 1 counter 0 irq1 irq3 irq4 irq5 irq6 irq7 0 1 2 3 4 5 6 7 82c59 core controller 2 (slave) irq9 irq11 irq12/mouse ferr# irq14 irq15 0# 1 2 3 4 5 6 7 intr irq8# irq10 057105 figure 5 . block diagram of the interrupt controller
e 82378 zb (sio) and 82379 (sio.a) 101 4.8.1. edge and level triggered modes there are two elcr registers, one for each 82c59 bank. they are located at i/o ports 04d0h (for the master bank, irq[7:3,1:0]#) and 04d1h (for the slave bank, irq[15:8])#. they allow the edge and level sense selection to be made on an interrupt by interrupt basis instead of on a complete bank. interrupts reserved for isa use must be programmed for edge sensitivity (to ensure isa compatibility). that is, irq (0,1,2,8#,13) must be programmed for edge sensitive operation. the ltim bit (edge/level bank select, offsets 20h, a0h) is disabled in the sio/sio.a. the default programming is equivalent to programming the ltim bit (icw1 bit 3) to a 0. if an elcr bit is equal to 0, an interrupt request will be recognized by a low to high transition on the corresponding irq input. the irq input can remain high without generating another interrupt. if an elcr bit is equal to 1, an interrupt request will be recognized by a "low" level on the corresponding irq input, and there is no need for an edge detection. for level triggered interrupt mode, the interrupt request signal must be removed before the eoi command is issued or the cpu interrupt must be disabled. this is necessary to prevent a second interrupt from occurring. in both the edge and level triggered modes the irq inputs must remain active until after the falling edge of the first inta#. if the irq input goes inactive before this time a default irq7 will occur when the cpu acknowledges the interrupt. this can be a useful safeguard for detecting interrupts caused by spurious noise glitches on the irq inputs. to implement this feature the irq7 routine is used for "clean up" simply executing a return instruction, thus ignoring the interrupt. if irq7 is needed for other purposes a default irq7 can still be detected by reading the isr. a normal irq7 interrupt will set the corresponding isr bit, a default irq7 won't. if a default irq7 routine occurs during a normal irq7 routine, however, the isr will remain set. in this case, it is necessary to keep track of whether or not the irq7 routine was previously entered. if another irq7 occurs, it is a default. 4.8.2. non-maskable interrupt (nmi) an nmi is an interrupt requiring immediate attention and has priority over the normal interrupt lines (irqx). the sio/sio.a indicates error conditions by generating a non-maskable interrupt. nmi interrupts are caused by: 1. system errors on the pci bus. serr# is driven low by a pci resource when this error occurs. 2. parity errors on the add-in memory boards on the isa expansion bus. iochk# is driven lo w when this error occurs. the nmi logic incorporates two different 8-bit registers ? the nmi status and control register and the nmi enable and real-time clock address register. these registers are described in the register description section. all nmi sources can be enabled or disabled by setting port 070h bit 7 to a 0 or 1. this disable function does not clear the nmi detect flip-flops. this means, if nmi is disabled then enabled via port 070h, then an nmi will occur when port 070h is re-enabled if one of the nmi detect flip-flops had been previously set. to ensure that all nmi requests are serviced, the nmi service routine software needs to incorporate a few very specific requirements. these requirements are due to the edge detect circuitry of the host microprocessor, 80386 or 80486. the software flow would need to be the following: 1. nmi is detected by the processor on the rising edge of the nmi input. 2. the processor will read the status stored in port 061h to determine what sources caused the nmi. the processor may then set to 0 the register bits controlling the sources that it has determined to be active. between the time the processor reads the nmi sources and sets them to a 0, an nmi may have been generated by another source. the level of nmi will then remain active. this new nmi source will not be recognized by the processor because there was no edge on nmi.
82378 zb (sio) and 82379ab (sio.a) e 102 3. the processor must then disable all nmi's by setting bit 7 of port 070h to a 1 and then enable all nmi's by setting bit 7 of port 070h to a 0. this will cause the nmi output to transition low then high if there are any pending nmi sources. the cpu's nmi input logic will then register a new nmi. 4.9. advanced programmable interrupt controller (apic) (82379ab only) in addition to the standard isa compatible interrupt controller described in the previous section, the 82379ab incorporates the advanced programmable interrupt controller (apic). while the standard interrupt controller is intended for use in a uni-processor system, apic can be used in either a uni-processor or multi-processor system. apic provides multi-processor interrupt management and incorporates both static and dynamic symmetric interrupt distribution across all processors. in systems with multiple i/o subsystems, each subsystem can have its own set of interrupts. in a uni-processor system, apic's dedicated interrupt bus can reduce interrupt latency over the standard interrupt controller (i.e., the latency associated with the propagation of the interrupt acknowledge cycle across multiple busses using the standard interrupt controller approach). interrupts can be controlled by the standard isa compatible interrupt controller unit, the i/o apic unit, or mixed mode where both the standard and i/o apic are used. the selection of which controller responds to an interrupt is determined by how the interrupt controllers are programmed. note that it is the programmer's responsibility to make sure that the same interrupt input signal is not handled by both interrupt controllers. at the system level, apic consists of two parts (figure 6 ) ? one residing in the i/o subsystem ( i/o apic ) and the other in the cpu ( local apic ). the 82379ab contains an i/o apic unit. the local apic and the i/o apic communicate over a dedicated apic bus. the 82379ab's i/o apic bus interface consists of two bi-directional data signals (apicd[1:0]) and a clock input (apicclk). note any designs should strive to make the apicclk as clean as possible at the input of any cpu. further details can be found in the latest "pentium processor at icomp index 735\90 (or 816\100) mhz stepping information" document, errata 8ap. this document also provides routing and topology guidelines. the cpu's local apic unit contains the necessary intelligence to determine whether or not its processor should accept interrupts broadcast on the apic bus. the local unit also provides local pending of interrupts, nesting and masking of interrupts, and handles all interactions with its local processor (e.g., the intr/inta/eoi protocol). the local unit further provides inter-processor interrupts and a timer, to its local processor. the register level interface of a processor to its local apic is identical for every processor.
e 82378 zb (sio) and 82379 (sio.a) 103 sio.a processor local apic register access int, nmi init, smi processor local apic apic bus i/o apic 057106 figure 6 . apic system structure the 82379ab i/o apic unit consists of a set of interrupt input signals, a 16-entry interrupt redirection table, programmable registers, and a message unit for sending and receiving apic messages over the apic bus (figure 7 ). i/o devices inject interrupts into the system by asserting one of the interrupt lines to the i/o apic (figure 8 ). the i/o apic selects the corresponding entry in the redirection table and uses the information in that entry to format an interrupt request message. each entry in the redirection table can be individually programmed to indicate edge/level sensitive interrupt signals, the interrupt vector and priority, the destination processor, and how the processor is selected (statically or dynamically). the information in the table is used to transmit a message to other apic units (via the apic bus). the 82379ab i/o apic contains a set of programmable registers. two of the registers (i/o register select and i/o window registers) are located in the cpu's memory space and are used to indirectly access the other apic registers as described in the register description section. the version register provides the implementation version of the i/o apic. the i/o apic id register is programmed with an id value that serves as a physical name of the i/o apic. this id is loaded into the arb id register when the i/o apic id register is written and is used during bus arbitration. note 1. when the 82379ab i/o apic receives an interrupt request, the 82379ab flushes its buffers and requests all system buffers pointing to pci to be flushed (via the flshreq#/memreq# signals). the apic does not send the interrupt message over the apic bus until the 82379ab receives confirmation (via the memack# signal) that all buffers have been flushed and temporarily disabled. 2. the interrupt number or the vector does not imply a particular priority for being sent. the i/o apic continually polls the 16 interrupts in a rotating fashion, one at a time. the pending interrupt polled first is the one sent.
82378 zb (sio) and 82379ab (sio.a) e 104 version register i/o window register i/o reg. select register i/o apic id register arb id register dest. mode vector dest. mode vector 0 15 interrupts apic bus data/address send/receive redirection table 0 63 31 0 057107 figure 7 . i/o apic register block diagram int (to cpu) i/o apic timer 1 counter 0 internal 8259 output irq1 irq3 irq4 irq5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 irq6 irq7 irq8# irq9 irq10 irq11 irq12/m ferr#/irq13 irq15 irq14 057108 figure 8 . i/o apic interrupt mapping
e 82378 zb (sio) and 82379 (sio.a) 105 4.9.1. physical characteristics of apic bus (82 379ab only) the apic bus is a 3-wire synchronous bus connecting all apics (all i/o units and all local units). two of these wires are used for data transmission, and one wire is a clock. for bus arbitration, the apic uses only one of the data wires. the bus is logically a wire-or and electrically an open-drain connection providing for both message transmission and arbitration for lowest priority. all the values mentioned in the protocol description are logical values (i.e., "bus driven" is logical 1 and "bus not driven" is logical 0). the electrical values are 0 for logical one and 1 for logical zero. 4.9.2. arbitration for apic bus (82379ab only) the apic uses one wire arbitration to win the bus ownership. a rotating priority scheme is used for arbitration. the winner of the arbitration becomes the lowest priority agent and assumes an arbitration id of 0. all other agents, except the agent whose arbitration id is 15, increment their arbitration ids by one. the agent whose id was 15 takes the winner's arbitration id and increments it by one. arbitration ids are changed (incremented or assumed) only for messages that are transmitted successfully. for lowest priority messages, the arbitration id is updated before the final status cycle, which ultimately decides if the message is successful. a message is transmitted successfully if no cs error or acceptance error is reported for that message. an apic agent can acquire the bus using two different priority schemes; normal, or eoi (end of interrupt). eoi has the highest priority. eoi priority is used to send eoi messages for level interrupts from local apic to the i/o apic. when an agent requests the bus with eoi priority, all others requesting the bus with normal priorities back off. a bus arbitration cycle starts by the agent driving a start cycle (bit 1=eoi, bit 0=1) on the apic bus (table 7 ). bit 1=1 indicates "eoi" priority and bit 1=0 indicates normal priority. bit 0 should be 1. in cycles 2 through 5, the agent drives the arbitration id on bit 1 of the bus. high-order id bits are driven first with successive cycles proceeding to the low bits of the id. all arbitration losers in a given cycle drop off the bus, using every subsequent cycle as a tie breaker for the previous cycle. when all arbitration cycles are completed, there will be only one agent left driving the bus table 7 . tt_apicbusarbbus arbitration cycles cycle bit 1 bit 0 1 eoi 1 0 1 = normal, 1 1 = eoi 2 arbid3 0 arbitration id bits 3 through 0 3 arbid2 0 4 arbid1 0 5 arbid0 0 4.9.3. intr and the pentium processor?s "through local mode" (82379ab only) the b-1 thru b-5 steppings of the pentium a processor at icomp index 735\90 (or 815\100) have a stepping publication information (10ap) when using the local apic in through local mode (virtual wire). the pentium stepping information provides software solutions that permit the customer to use the local apic in through local mode. this section provides hardware solutions. if a processor has its local apic setup in through local mode (virtual wire), the 82379ab can potentially negate and then reassert int before the interrupt acknowledge cycle for the first interrupt completes. when this occurs,
82378 zb (sio) and 82379ab (sio.a) e 106 the cpu ignores the second interrupt and the system eventually ? hangs ? because no further interrupts are serviced. the pcmc can wait 106 host clocks during an interrupt acknowledge cycle between frame# assertion on the pci bus and brdy# being asserted on the host bus. since the sio.a can reassert int as soon as 18 host clocks after receiving frame# of the interrupt acknowledge cycle, there is a ? window ? of 88 host clocks where int can be reasserted by the sio.a. one solution uses an external circuit where lock# and m/io# from the processor blocks the assertion of int until the interrupt acknowledge cycle has completed. loading and timing on the lock# and m/io must be considered for this solution as they are host bus signals. the following is the logic equation used for int: int_out = ((int * int_out + (int*m/io#) + (int*lock#)) another solution delays the assertion of int by 88 hostclocks (1320 ns). an rc circuit on the output of the required external buffer on the int signal can also accomplish this delay. any solution that prevents int from being asserted for 106 host clocks after frame# goes low at the start of an interrupt acknowledge cycle will work. as an example, another way to implement the delay is to block the re- assertion of int for 14 bclks after int goes low. the logic uses int going low as the start of the ? block clock ? as this transition signals the beginning of the blocking period. int can, therefore, be directly passed through the circuit with no appreciable delay at all other times. 14 bclks was chosen for the following reasons : frame# to brdy# = 106 host clocks frame# to int low (sio) = 2 pciclks (4 host clocks) block needed from int low to brdy# = 104 host clocks = 13 bclks (chosen to minimize flip flops) = 13 + 1 (needed due to asynchronous lock s) = 14 bclks q d q r q t q r i n t ( f r o m s i o ) p c i r s t # bclk i n t ( f r o m c p u ) q t q r q t q r q t q r 057109 figure 9 . intr - through local mode hardware solution
e 82378 zb (sio) and 82379 (sio.a) 107 4.9.4. pulsing of apicd1 during cpu reset (82379ab only) for dual-processing (dp) isa systems using the pentium a processor at icomp index 735\90 (or 815\100) and the a-1 stepping of the 82434nx pcmc host bridge an anomily can occur when the ioapic data line is pulsed during cpu reset. (single processor designs are not affected. also, pentium pro processor systems are not affected.) to avoid this issue, use one of the following workarounds: the cpus apic data lines (apicd[0,1]), have secondary functions when cpu reset (cpurst) is active. apicd1 is the apicen (apic enable) pin and apicd0 is the dpen# (dual processor enable) pin. the local apics are enabled if apicen is sampled active high on the falling edge of cpurst. also, during reset, the second cpu drives dpen# active low to indicate to the boot processor that it is present. on the a-1 stepping of the 82434nx pcmc, there is approximately a 1-ms delay (specifically 66,672 external host clocks) between the negation of pcirst# and the negation of cpurst following a cold system boot (i.e., the pwrok input of the pcmc transitions from low to high). during this 1-ms window, the i/o apic in the sio.a, which is no longer in reset, begins to monitor the apic bus for valid messages. apicen (apicd1 = logic 1) and dpen# (apicd0 = logic 0) remain asserted during this period. the i/o apic interprets the states of these two bits as the beginning of a normal apic message and continues to sample the apic data lines. the i/o apic responds, per the apic protocol, by driving apicd1(apicen) low once every 20 apicclks, indicating a checksum error has been detected on the current message. under these circumstances, this is proper operation for the sio.a. from the time that pcirst# negates until the time that cpurst negates, the i/o apic periodically pulses apicd1 low for one out of every 20 apicclks. if the pulse on apicd1 (apicen) aligns with the falling edge of cpu reset (cpurst), the local apics will not be enabled; this prevents proper dp or dp-ready functionality (figure 10 }. cpurst pcirst# apicd1 apicclk 66,672 hz 057110 figure 10 . reset/apic data signl timing (not to scale) hardware solution #1: calculate the window for the apicd1 pulse relative to cpurst for a given host clock (hclk) and apic clock (apicclk) frequency. the following example demonstrates that by using a 60.0 mhz hclk and a 15.0 mhz apicclk (0.01% accuracy for both) the apicd1 pulse will be outside the sampling window of cpurst. with these equations, equally acceptable windows can be found for other values of hclk and apicclk.
82378 zb (sio) and 82379ab (sio.a) e 108 note that with the above frequency accuracies, a 15.0 mhz apicclk with a 50-mhz or 66-mhz hclk may not always function correctly under worst-case clock variations in a dp isa environment. also, a 16.0-mhz apicclk may not function correction with 50mhz, 60mhz or 66mhz under worst-case clock variations. sample calculation: two key variables in the system first must be identified: 1. the accuracy of the host clock oscillator input to the pcmc (hclkosc) additional inaccuracy in hclk or pci clock (pclk) is not induced by the internal pcmc plls. 2. the accuracy of the apic clock oscillator. the following example assumes a 60-mhz host clock (hclk) frequency with an oscillator accuracy of 0.01% and a 15.0-mhz apic clock (apicclk) frequency with an accuracy of 0.01%. step 1 : determine the nominal clock frequency for hclk, pclk and apicclk. also, determine the accuracy for hclk and apicclk. since pclk is hclk/2, no additional inaccuracy is incurred. signal frequency accuracy hclk 60 mhz 0.01% apicclk 15 mhz 0.01% step 2 : calculate the maximum and minimum window from pcirst# and cpurst. one less hclk (66,671) was used to account for the uncertainty between hclk and pclk for the minimum case. this provides the minimum time window between the i/o apic responding to the apic messages and the falling edge of cpurst. convert these two extremes to absolute time (seconds). w hen converting the maximum hclk window to real time be sure to use the max hclk period possible due to clock tolerances. similarly, use the minimum hclk period for the min hclk window. equation #1: (hclk cycles) * max hclk period = max hclk window (66,672) * (1.66683335e-08) = 1.111311 msec (hclk cycles) * min hclk period = min hclk window (66,671) * (1.66650002e-08) = 1.111072 msec apicd1 pulse window (s) max hclk window 1.111311e-03 min hclk window 1.111072e-03 step 3 : determine the equivalent n umber of apicclks contained in the maximum and minimum pulse windows calculated above. account for the accuracy of the apicclk source. also, since apicclk and hclk are completely asynchronous to each other, one apicclk should be subtracted from the minimum window to account for any hclk/apicclk misalignment. equation #2: (max apicd1 pulse window) * (max apicclk frequency) = max apicclks 1.111311e-03 * 15.0015 mhz = 16,671.33 apicclks
e 82378 zb (sio) and 82379 (sio.a) 109 (min apicd1 pulse window) * (min apicclk frequency) - 1 = min apicclk s 1.111072e-03 * 14.9985 mhz - 1 = 16,663.42 apicclks apicclk frequency max window (apicclks) min window (apicclks) 15.0 mhz + 0.01% 16671.33 15.0 mhz - 0.01% 16663.42 step 4 : select the maximum and minimum number of apicclks contained within the pulse window. the two cases are underlined in the step 3 calculation above. for each case, divide the number of apicclks by 20 to determine the minimum and maximum number of apicd1 pulses driven by the i/o apic during this window. apicd1 is pulled to a logic 1 via the strong, external pullup resistor for 19 apicclks before pulsing low via the i/o apic for 1 apicclk. signal max apicd1 pulses min apicd1 pulses apicd1 (apicen) pulses 833.56 833.17 step 5 : the fractional portion of each pulse calculation above provides the time (in apicclks) between the final apicd1 pulse and the falling edge of cpurst. to calculate the apicen setup time for the maximum pulse condition (833.56 pulses), multiply the fractional portion of the pulse calculation (0.56) by 20 and then divide by the maximum apicclk frequency. this results in the actual setup time between the end of the last apicd1 pulse and the falling edge of cpurst. subtracting this setup time from [(19 divided by the maximum apicclk frequency)] results in the apicen hold time from the falling edge of cpurst. to calculate the setup and hold times for apicen for the minimum pulse condition (833.56), the minimum apicclk frequency is used. equation #3 - maximum apicd1 pulse condition [(fractional number of max apicd1 pulses) * 20]/(max apicclk frequency) = apicen setup time [(0.56) * 20]/(15.0015 mhz) = 747 ns [19/(max apicclk frequency)] - apicen setup time = apicen hold time equation #3 - minimum apicd1 pulse condition [(fractional number of min apicd1 pulses) * 20]/(min apicclk frequency) = apicen setup time [(0.17) * 20]/(14.9985 mhz) = 227 ns [19/(min apicclk frequency)] - apicen setup time = apicen hold time [19/(14.9985 mhz)] - 975 ns = 1040 ns step 6 : if the whole number portion of the pulses cal culated in step 4 is identical in the minimum and maximum cases, then the minimum setup and hold time margins for apicen easily fall out. therefore, in this example, for this combination of oscillator frequencies and accuracies, worst-case apicen setup and hold times clearly meet the minimum cpu setup and hold specifications of 2 hclks. apicen will be properly sampled by the cpus under all circumstances. if the whole number portions are not equal for the minimum and maximum cases, then the accuracy of the hclk and apicclk frequencies is not sufficient to keep the apicd1 pulse from aliasing, i.e., shifting through the entire 20 apicclk window under worst-case conditions.
82378 zb (sio) and 82379ab (sio.a) e 110 hardware solution #2 generate apicclk by dividing the pclk by two. in this case, there will not be an anomaly of apicd1 pulsing low during the negation of cpurst, as long as pclk is generated by dividing hclk by two and apicclk is generated by dividing pclk by two. this is only viable for designs using the 82379ab. for eisa designs using the 82374eb(sb) esc, this solution is invalid. the esc begins pulsing the apicd1 pin later in time, causing the apicd1 pulse to align with the falling edge of cpurst for dp eisa systems. hardware solution #3. add logic to ensure that pcirst# remains asserted low until pwrok is valid and then once pwrok is valid, let pcirst# become the logical inverse of cpurst. this ensures that the i/o apic and both cpus exit reset simultaneously preventing the i/o apic from responding to phantom apic messages. possible implementations: a. connect a buffered version of cpurst to an inverter and then connect the output of this inverter to the input of a three-state buffer. pwrok# is used as the active low enable to the three-state buffer. the output of this three-state buffer is used as the pcirst# signal for the entire system. note that the pcmc pcirst# output pin (pin 147) should be disconnected from the system. it is important to use a buffered version of cpurst and preferably one that already exists in the system due to the critical ac timing of this signal. a weak pulldown resistor (8.2k, for instance) should be added to the pcirst# net to ensure it is low while pwrok is low. p w o r k c p u r s t p c i r s t # 057111 figure 11 . pcirst# soln 3a logic b. connect a buffered version of cpurst to an inverter and then connect the output of this inverter to one input of a two-input and gate. pwrok is the second input to the and gate. the output of the and gate becomes pcirst# for the entire system. again, the pcmc pcirst# output pin (pin 147) should be disconnected from the system. pcirst# cpurst pwrok 057112 figure 12 . pcirst# soln 3b logic
e 82378 zb (sio) and 82379 (sio.a) 111 4.9.5. sio.a asserting signals low during pcirst# (82379ab only) the sio.a drives smi#, alt_a20, int, nmi, ignne#, alt_rst#, and stpclk# low while pcirst# is asserted low, and does not drive them high until after pci reset is released. an anomaly can exist with these seven signals remaining low during and immediately after pcirst# is negated. the three instances in which this can cause a problem are : during a targeted pci reset, and in a 82450gx/kx-p6 system, both during power-up and when binit# is asserted on the pentium pro processor bus. targeted pci resets systems that support targeted pci resets (resetting the pci bus via software control without resetting the microprocessor) may have a problem with some of the seven signals being asserted low during the targeted pci reset. since the microprocessor can not know when a pcirst is occurring, this fix must be incorporated in order to reset the pci bus via the register. this will affect all designs using the sio.a. the reset mask blocking circuit shown above will block signal a from being seen by the cpu during the pci reset. the second flip flop is necessary to avoid a glitch on the z output to the cpu which can happen if signal a is asserted simultaneously with pcirst#. the blocking circuitry for all of the signals should be incorporated into a pld. this will ease loading on pciclk and pcirst#. signals alt_rst#, ignne#, alt20, stpclk#, and smi# should have blocking circuitry. q d q r q d q r p c i c l k a z p c i r s t 057113 figure 13 . reset mask blocking logic using sio.a 4.10. utility bus peripheral support the utility bus is a secondary bus buffered from the isa bus used to interface with peripheral devices that do not require a high speed interface. the buffer control for the lower 8 data signals is provided by the sio/sio.a via two control signals; ubusoe# and ubustr. figure 14 shows a block diagram of the external logic required as part of the decode and utility bus buffer control. the sio/sio.a provides the address decode and three encoded chip selects to support floppy controller, keyboard controller, real time clock, ide drive, 2 serial ports (com1 and com2), 1 parallel port (lpt1, 2, or 3), bios memory, and configuration memory (8 kbyte i/o mapped). the sio/sio.a also supports floppy dskchg function, port 92 function (alternate a20 and alternate reset), and coprocessor logic (ferr# and ignne# function)
82378 zb (sio) and 82379ab (sio.a) e 112 the binary code formed by the three encoded chip selects determines which utility bus device is selected. the sio/sio.a also provides an encoded chip select enable signal (ecsen#) that is used to select between the two external decoders. a zero selects decoder 1 and a one selects decoder 2. the table below shows the address decode for each of the utility bus devices. table 8 . encoded chip select summary table ecs2 ecs1 ecs0 ecsen# address decoded external chip select note cycle type decoder 1 0 0 0 0 70h, 72h, 74, 76h rtcale# i/o w 0 0 1 0 71h, 73h, 75h, 77h rtccs# i/o r/w 0 1 0 0 60h, 62h, 64h, and 66h (82378ZB) 60h and 64h (82379ab) keybrdcs# i/o r/w 0 1 1 0 000e0000 ? 000fffffh fffe0000 ? ffffffffh fff80000 ? fffdffffh bioscs# 1 mem r/w 1 0 0 0 3f0h-3f7h (primary) 370h-377h (secondary) floppycs# 2 i/o r/w 1 0 1 0 1f0 ? 1f7h (primary) 170 ? 177h (secondary) idecs0# 2 i/o r/w 1 1 0 0 3f6 ? 3f7h (primary) 376 ? 377h (secondary) idecs1# 2 i/o r/w 1 1 1 0 reserved decoder 2 0 0 0 1 reserved 0 0 1 1 0c00h cpagecs# 3 i/o r/w 0 1 0 1 0800 ? 08ffh cfigmemcs# 3 i/o r/w 0 1 1 1 3f8 ? 3ffh (com1) -or- 2f8 ? 2ffh (com2) comacs# 4 i/o r/w 1 0 0 1 3f8 ? 3ffh (com1) -or- 2f8 ? 2ffh (com2) combcs# 4 i/o r/w 1 0 1 1 3bc ? 3bfh (lpt1) 378 ? 37fh (lpt2) 278 ? 27fh (lpt3) lptcs# 5 i/o r/w 1 1 0 1 reserved 1 1 1 1 idle state
e 82378 zb (sio) and 82379 (sio.a) 113 notes: 1. the encoded chip select signals for bioscs# will always be generated for accesses to the upper 64 kbytes at the top of 1 mbyte (f0000 ? fffffh) and its aliases at the top of the 4 gbytes and 4 gbytes - 1 mbyte. access to the lower 64 kbytes (e0000 ? effffh) and its aliases at the top of 4 gbytes and 4 gbytes ? 1 mbyte can be enabled or disabled through the sio/sio.a. an additional 384 kbytes of bios memory at the top of 4 gbytes (fffd0000 ? fffdffffh) can be enabled for bios use. 2. the primary and secondary locations are programmable through the sio/sio.a. only one location range can be enabled at any one time. the floppy and ide share the same enable and disable bit (i.e., if the floppy is set for primary, the ide is also set for primary). 3. these signals can be used to select additional configuration ram. 4. com1 and com2 address ranges can be programmed for either port a (comacs#) or port b (combcs#). 5. only one address range (lpt1, lpt2, or lpt3) can be programmed at any one time. port 92h function the sio/sio.a integrates the port 92h register. this register provides the alternate reset (altrst) and alternate a20 (alt_a20) functions. figure 14 shows how these functions are tied into the system. dskchg function dskchg is tied directly to the dskchg signal of the floppy controller. this signal is inverted and driven onto system data line 7 (sd7) during i/o read cycles to floppy address locations 3f7h (primary) or 377 (secondary) as indicated by table 9 . table 9 . dskchg summary table floppycs# decode idecsx# decode state of sd7 (output) state of ubusoe# enabled enabled tri-stated enabled enabled disabled driven via dskchg disabled disabled enabled tri-stated enabled 1 disabled disabled tri-stated disabled note: 1. this mode requires external logic to disable the u-bus transceiver for access to 3f7h/377h. this is necessary due to potential contention between the utility bus buffer and a floppy on the isa bus driving the system bus at the same time during shared i/o accesses. coprocessor error support if bit 5 in the isa clock divisor register is set to a one, the sio/sio.a will support coprocessor error reporting through the ferr#/irq13 signal. ferr# is tied directly to the coprocessor error signal of the cpu. if ferr# is driven active in this mode (coprocessor error detected by the cpu), an internal irq13 is generated and the int output from the sio/sio.a is driven active. when a write to i/o location f0h is detected, the sio/sio.a negates irq13 and drives ignne# active. ignne# remains active until ferr# is driven inactive. note that ignne# is not generated unless ferr# is active.
82378 zb (sio) and 82379ab (sio.a) e 114 sd0-7 ubustr ubusoe# sd0-7 f245 t/r# oe# ud0-7 irq12/m ecsaddr0 ecsaddr1 ecsaddr2 ecsen# dskchg alt_rst# alt_a20 ignne# ferr#/irq13 a20gate f32 cpurst a20m# alt_a20 alt_rst# kbdrst# f08 sreset# dirq12 a20gate kbdrst# 0 1 2 0 1 2 3 4 5 6 7 f 1 3 8 en en0# en1# ecsen# keybrdcs# 8x42 keybrd xmemr# bioscs# floppycs# idecs1# f08 82077cs# floppy 82077 dskchg xior# rtccs# xiow# rtcrd# rtcwr# rtcale rtc ubustr ubusoe# i d e c o n n 245 oe# f32 iocs16# idecs0# idecs1# sd8-15 ferr# ignne# f32 xiow# cpagecs# udxx[0:4] conf. memory lpageaddr[0:4] xiow# xior# we# oe# cfigmemcs# note: not used if conf. mem. in flash device comacs# combcs# lptcs# vcc bios (flash) wr# oe# cc# 374 clk f32 f32 xmemw# f32 f32 s i o f32 1 0 1 2 0 1 2 3 4 5 6 7 f 1 3 8 en en0# en1# 2 xior reserved b a a b t/r# dack6# f08 note: dack6# supports ide dma note: applicable when icd bit 4 = 0 xiow# f08 dack6# not used rtcale# f32 note: applicable when icd bit 5 = 1 7
e 82378 zb (sio) and 82379 (sio.a) 115 utility bus accesses by the sio/sio.a, by an isa master, and by the dma are shown in figure 15 and figure 16 . ubusoe# and ubustr are driven differently for dma cycles as shown in figure 16 . u-bus access cycle (sio as master) u-bus access, 8-bit i/o, rtcale cycle u-bus access cycle (isa master) bale sa [16:0], la[23:17],sbhe# ior#,iow# sd[7:0] r sd[7:0] w ecsaddr[2:0] ecsen# ubusoe# ubustr ubusoe# ubustr ecsen# rtcale rtcale# 057115 figure 15 . utility bus access (sio/sio.a and isa master) dack2# ubusoe# ubustr dack0,1,3,5,6,7# ubusoe# ubustr 057116 figure 16 . utility bus access (dma)
82378 zb (sio) and 82379ab (sio.a) e 116 4.11. power management the sio/sio.a has extensive power management capability permitting a system to operate in a low power state without being powered down. in a typical desktop personal computer there are two states ? power-on and power-off. leaving a system powered on when not in use wastes power. the sio/sio.a provides a fast-on/off feature that creates a third state called fast-off (figure 17 ). when in the fast-off state, the system consumes less power than the power-on state. the sio/sio.a power management architecture is based on three functions ? system management mode (smm), clock control, and advanced power management (apm). software (called smm code) controls the transitions between the power-on state and the fast-off state. the sio/sio.a invokes this software by generating an smi to the cpu (asserting the smi# signal). a variety of programmable events are provided that can generate an smi. the smm code places the system in either the power-on state or the fast-off state. a fast-on event is an event that instructs the computer (via an smi to the cpu) to enter the power-on state in anticipation of system activity by the user. fast-on events are programmable and include moving the mouse, pressing a key on the keyboard, an external hardware event, an incoming call to a system fax/modem, a rtc alarm, or the operating system. fast off power switch turned on fast off event (timer expires, extsmi#, rtc alarm, apm call) power switch turned off fast on event (mouse, keyboard, comport activity, extsmi#, rtc alarm, apm call) power switch turned off power on power off 057117 figure 17 . fast-on/off flow
e 82378 zb (sio) and 82379 (sio.a) 117 4.11.1. smm mode smm mode is invoked by asserting the smi# signal to the cpu. the sio/sio.a provides a variety of programmable events that can generate an smi. when the cpu receives an smi, it enters smm mode and executes smm code out of smram. the smm code places the system in either the power-on state or the fast- off state. in the power-on state, the computer system operates normally. in this state one of the four programmable events listed below can trigger an smi. 1. a global idle timer called the fast-off timer expires (an indication that the end user has not used the computer for a programmed period of time). 2. the extsmi# pin is asserted. 3. an rtc alarm interrupt is detected. 4. the operating system issues an apm call. 4.11.2. smi sources the smi# signal can be asserted by hardware interrupt events, the fast-off timer, an external smi event (extsmi#), and software events (via the apmc and apms registers). enable/disable bits (in the smien register) permit each event to be individually masked from generating an smi. in addition, the smi# signal can be globally enabled/disabled in the smicntl register. status of the individual events causing an smi is provided in the smireq register. for detailed information on the smi control/status registers, refer to register description section. hardware interrupt events hardware events (irq[12,8#,4,3,1] and the fast-off timer) are enabled/disabled from generating an smi in the smien register. when enabled, the occurrence of the corresponding hardware event generates an smi (asserts the smi# signal), regardless of the current power state of the system. fast-off timer the fast-off timer is used to indicate (through an smi) that the system has been idle for a programmed period of time. the timer counts down from a programmed start value and when the count reaches 00h, can generate an smi. the timer decrement rate is 1 count every minute and is re-loaded each time a system event occurs. this counter should not be programmed to 00h. system events are programmable events that can keep the system in the power-on state when there is system activity. these events are indicated by the assertion of irq[15:9,8#,7:3,1:0], nmi, or smi signals. system events also include certain peripheral i/o address accesses (table 10 ). the system event prevents the system from entering the fast-off state by re-loading the fast-off timer. in addition to system events, break events cause the system to transition from a fast-off state to the power-on state. system events (and break events) are enabled/disabled in the see register. when enabled and the associated hardware event occurs (signal is asserted or an access within the defined range), the fast-off timer is re-loaded with its initial count.
82378 zb (sio) and 82379ab (sio.a) e 118 table 10 . decode for system events to trigger fast-off timer re-load address range device 170-17fh, 1f0-1ffh ide/floppy 278-27fh printer 2e8-2efh, 2f8-2ffh com 320-32fh ide/floppy 378-37fh printer 3bc-3bfh printer 370-377h, 3f0-3f7h ide/floppy 3e8-3efh, 3f8-3ffh com 0-0fh dma registers 1 80-8fh dma registers 1 c0-deh dma registers 1 400-43fh, 481-4ffh dma registers 1 note: 1. access to positively decoded dma registers (and aliases) creates a system event. extsmi# the extsmi# input pin provides the system designer the capability to invoke smm with external hardware. for example, the extsmi# input could be connected to a "green button" permitting the user to enter the fast-off state by depressing a button. the extsmi# generation of an smi is enabled/disabled in the smien register. software events software events (accessing the apmx registers) indicate that the os is passing power management information to the smi handler. there are two advanced power management (apm) registers ? apm control (apmc) and apm status (apms) registers. these registers permit software to generate an smi; by writing to the apmc register. for example, the apmc can be used to pass an apm command between apm os and bios and the apms register could be used to pass data between the os and the smi handler. the two apm registers are located in normal i/o space. the sio/sio.a subtractively decodes pci accesses to these registers and forwards the accesses to the isa bus. the apm registers are not accessible by isa masters. note that the remaining power management registers are located in pci configuration space. 4.11.3. smi# and init interaction the smi# input to the cpu is an edge sensitive signal. when an s-series processor is reset (init asserted), the processor resets the smi# edge detect logic. after init is negated, it takes two clocks before the edge detect circuit can catch an edge. the sio/sio.a only asserts smi# when init is negated. if the sio/sio.a asserts smi# and then the init signal is sampled asserted, the sio/sio.a negates smi#.
e 82378 zb (sio) and 82379 (sio.a) 119 4.11.4. clock control the cpu can be put in a low power state by asserting the stpclk# signal. stpclk# is an interrupt to the cpu. however, for this type of interrupt, the cpu does not generate an interrupt acknowledge cycle. once the stpclk# interrupt is executed, the cpu enters the stop grant state. in this state, the cpu's internal clocks are disabled and instruction execution is stopped. the stop grant state is exited when the stpclk# signal is negated. software can assert stpclk#, if enabled via the smicntl register, by a read of the apmc register. note that stpclk# can also be periodically asserted by using clock scaling as described below. the sio/sio.a automatically negates stpclk# when a break event occurs (if enabled in the see register) and the cpu stop grant special cycle has been received. software can negate stpclk# by disabling stpclk# in the smicntl register or by a write to the apmc register. note 1. init is always enabled as a break event. otherwise, init acts exactly as other break events: if stpclk# is negated when init is asserted, the stpclk high timer is reloaded. if ini t is asserted when stpclk# is asserted but before the stop grant bus cycle, stpclk# negation waits until after the stop grant bus cycle. this happens after the cpu is reset when it samples stpclk# still asserted. if init is asserted when stpclk# is asserted and after the stop grant bus cycle, stpclk# is negated immediately. this guarantees that stpclk# will be negated after the cpu is reset. 2. while the stpclk# signal is asserted, the external interrupts (nmi, smi# and in t) may be asserted to the cpu. if intr is asserted, it will remain asserted until the cpu inta cycle is detected. if smi# (or nmi) is asserted, it remains asserted until the smi (or nmi) handler clears the sio/sio.a csmigate (or sets the sio/sio.a nmimask bit). thus, smi#, nmi and intr can be applied to the cpu independent of the stpclk# signal state. note that when smi#, nmi, and irqx are enabled as break events, the occurrence of the break event negates stpclk#. clock scaling (emulating clock division) clock scaling permits the sio/sio.a to periodically place the cpu in a low power state. this emulates clock division. when clock scaling is enabled, the cpu runs at full frequency for a pre-defined time period and then is stopped for a pre-defined time period. the run/stop time interval ratio emulates the clock division effect from a power/performance point of view. however, clock scaling is more effective than dividing the cpu frequency. for example, if the cpu is in the stop-grant state and a break event occurs, the cpu clock returns to full frequency. in addition, there is no recovery time latency to start the clock. two programmable 8-bit clock scale timer control registers set the stpclk# high (negate) and low (assert) times ? the ctltmrh and ctltmrl registers. the timer is clocked by a 32 sec internal clock. this allows a programmable timer interval for both the stpclk# high and low times of 0 - 8 sec. when enabled via the smicntl register, the stpclk# timer operates as follows: when stpclk# is negated, the timer is loaded with the value in the ctltmrh register and starts counting down. when the timer reaches 00h, stpclk# is asserted. since the timer is re-loaded with the contents of the ctltmrh register every time stpclk# is negated (for break events or clock throttling), the stpclk# minimum inactive time is guaranteed. when stpclk# is asserted, the timer is loaded with the value in the ctltmrl register. if wait for stop clock special cycle is enabled (smicntl register), the sio/sio.a does not start the timer until the stop grant special cycle is received. when the timer reaches 00h, stpclk# is negated. note that for the
82378 zb (sio) and 82379ab (sio.a) e 120 82379ab, if the wait for stop grant special cycle function is disabled, the sio.a does not wait for the stop grant special cycle before starting the timer. note, also, that a break event also negates stpclk#. this feature is not programmable in the 82378ZB. note if stpclk# is negated and a break event occurs, the stpclk# timer is loaded with the value in the ctltmrh register. 4.11.5. dual-processor power management support (82379ab only) figure 18 depicts the power management support for dual-processor (dp) or p54ct upgrade processor configura tion. the input signals of smi#, stpclk#, and nmi of both oem and upgrade sockets are tied together. p54c stpclk# smi# nmi local apic p54cm/ct stpclk# smi# nmi local apic i/o apic 8259a sio.a apic bus local interrupts local interrupts system i/o interrupts 057118 figure 18 . sio.a dual processor system configuration 4.11.5.1. smi# delivery mechanism for uni or ct upgrade processor system configuration, smi# can either be delivered through the sio.a smi# signal or i/o apic. for the p54c/cm dual-processor configuration, smi# should be deliver through i/o apic only. ideally, the os will put the cm processor in autohalt after the cm processor received a fast-off smi#. the cm processor will wake up if any non-masked system events occur. 4.11.5.2. stpclk# tied to both sockets to support a glueless upgrade socket, it is necessary to tie stpclk# to both sockets. for p54c/ct processor configuration, the p54ct processor will disable p54c and the toggling of stpclk# has no effect to p54c. for a p54c/cm dp configuration, the toggling of stpclk# effects both processors (unless the processor is in autohalt state). both processors respond with a stpgnt special bus cycle after recognizing stpclk# low. both of the stpgnt special bus cycles are passed onto pci by the pcmc as pci stpgnt special cycles. when bit 6=0 in the smicntl register, the sio.a recognizes the first stpgnt# assertion and negates stpclk# upon the stop clock timer expiration or a stop break event.
e 82378 zb (sio) and 82379 (sio.a) 121 4.11.5.3. smi#/intr (apic mode) when the apic is used for interrupt delivery, additional considerations exist regarding ordering. if local interrupts (lint0/1) are used in apic mode, then the system can not guarantee an ordering between the local interrupts and any related smi# events. in dp mode, interrupts can generally be directed to a specific processor, which may not be the same processor that the smi# is directed. the irq blocking logic in the sio.a still operates with apic delivery mode. thus, if an irq is enabled to cause an smi# event, it will be blocked until the csmigate is cleared, regardless of where the irq or smi is to be directed by the apic. 4.11.6. interrupt levels and system event generation in power managed systems (82378ZB only) the 82378ZB (sio) can use the 14 irq input pins (irq[15,9,8,7:3,1]) to generate hardware system events in pci systems that support power management mode by programming the system event enable register bits [15:0], corresponding to the selected interrupt. detection of these events causes the fast-off timer to be re- loaded with its initial count value and negate the stpclk# pin. the sio samples the enabled interrupts as level sensitive, active high signals, for system event determination. most motherboard devices or isa add-in cards using an interrupt drive the interrupt low when the interrupt is inactive, and only drive the interrupt high when it needs to generate an interrupt to the cpu. these devices work properly with the 82378ZB level sensitive logic. pc-at system design considerations devices or isa add-in cards that float their interrupt line (i.e., a device that doe not drive its interrupt low when inactive) may not be able to use the power management capabilities of the 82378ZB. thus, it is recommended that these devices not be used with the 82378ZB. 4.12. design considerations (82378ZB/82379ab) 4.12.1. good layout practice incorrect board layout practices have shown that care must be taken to minimize ground bounce that could generate noise glitches above the threshold on the following signals ? eop, bale, nmi, int, devsel#, rstdrv, and dack[7:0]. care should be taken not to route these signals long distances and to ensure that they are terminated properly. an additional good layout practice is to pull any affected signals to ground with a capacitor (120 pf) at each receiver. for devsel#, a 50 pf capacitor should be sufficient. 4.12.2. asynchronously switchin g signals good design practice should ensure that asynchronously switching signals should not be routed along synchronous signals to minimize crosstalk. on the sio/sio.a, the following signals switch asynchronously ? ecsaddr[2:0], ecsen#, mem16#, memcs#, ubusoe#, ubustr. the irq lines are susceptible to cross coupled switching noise from these asynchronous signals. it is recommended that the irq signals not be routed along these asynchronously switching signals. if an irq signal is routed along these signals, capacitors should be used (100 pf) to decouple the switching from the irq input.
82378 zb (sio) and 82379ab (sio.a) e 122 5. 0. electrical characteristics 5.1. maximum ratings case temperature under bias -65 c to 110 c. storage temperature -65 c to 150 c. supply voltages with respect to ground -0.5v to v cc + 0.5v voltage on any pin -0.5v to v cc + 0.5v warning stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may affect reliability.
e 82378 zb (sio) and 82379 (sio.a) 123 6. 0. pin assignment the sio and sio.a packages are 208-pin quad flatpacks (qfp). the package signals are shown in figure 19 and listed in table 12. the following notations are used to describe pin types. pin 20 21 73 195 206 s i g n a l t c a p i c d 1 t e s t / s p k r a p i c c l k a p i c d 0 82379ab 8 2 3 7 8 z b / 8 2 3 7 9 a b
82378 zb (sio) and 82379ab (sio.a) e 124 table 11 . alphabetical pin assignment (82379ab) pin name pin # type ad00 159 i/o ad01 155 i/o ad02 154 i/o ad03 153 i/o ad04 152 i/o ad05 151 i/o ad06 150 i/o ad07 149 i/o ad08 148 i/o ad09 146 i/o ad10 143 i/o ad11 142 i/o ad12 141 i/o ad13 140 i/o ad14 139 i/o ad15 138 i/o ad16 123 i/o ad17 122 i/o ad18 121 i/o ad19 120 i/o ad20 119 i/o ad21 118 i/o ad22 115 i/o ad23 114 i/o ad24 112 i/o ad25 111 i/o ad26 110 i/o ad27 109 i/o ad28 108 i/o ad29 107 i/o pin name pin # type ad30 106 i/o ad31 102 i/o aen 193 o alt_a20 85 o alt_rst# 76 o apicclk (82379ab) 195 i apicd0 (82379ab) 206 od apicd1 (82379ab) 21 od bale 23 o c/be0# 147 i/o c/be1# 137 i/o c/be2# 124 i/o c/be3# 113 i/o cpugnt# 95 t/s/o cpureq# 96 i dack0# 45 o dack1# 48 o dack2# 18 o dack3# 49 o dack5# 50 o dack6# 59 o dack7# 63 o devsel# 128 i/o (s/t/s) dreq0 47 i dreq1 56 i dreq2 57 i dreq3 58 i pin name pin # type dreq5 51 i dreq6 61 i dreq7 65 i dskchg 161 i ecsaddr0 175 o ecsaddr1 174 o ecsaddr2 173 o ecsen# 170 o eop (82378ZB) 20 i/o extsmi# 171 i ferr#/ irq13 71 i flshreq# 89 t/s/o frame# 125 i/o (s/t/s) gnt0#/ sioreq# 92 t/s/o gnt1#/ resume# 94 t/s/o gnt2# 91 t/s/o gnt3# 99 t/s/o idsel 101 i ignne# 72 o init 136 i int 75 o iochk# 176 i iochrdy 191 i/o iocs16# 33 i ior# 200 i/o iow# 198 i/o irdy# 126 i/o (s/t/s)
e 82378 zb (sio) and 82379 (sio.a) 125 pin name pin # type irq1 168 i irq10 35 i irq11 37 i irq12/m 39 i irq14 43 i irq15 41 i irq3 16 i irq4 14 i irq5 11 i irq6 9 i irq7 7 i irq8# 172 i irq9 184 i la17 46 i/o la18 44 i/o la19 42 i/o la20 40 i/o la21 38 i/o la22 36 i/o la23 34 i/o lock# 133 i (s/t/s) master# (82378ZB) 206 i memack# 88 i memcs# 86 o memcs16# 31 i/o (o/d) memr# 203 i/o memreq# 87 t/s/o memw# 204 i/o nmi 74 o pin name pin # type osc 80 i par 135 o pciclk 90 i pcirst# 163 i pirq0# 81 i pirq1# 82 i pirq2# 83 i pirq3# 84 i refresh# 4 i/o req0#/ siognt# 93 i req1# 98 i req2# 97 i req3# 100 i rstdrv 177 o sa00 30 i/o sa01 29 i/o sa02 28 i/o sa03 24 i/o sa04 22 i/o sa05 19 i/o sa06 17 i/o sa07 15 i/o sa08 13 i/o sa09 10 i/o sa10 8 i/o sa11 6 i/o sa12 5 i/o sa13 3 i/o sa14 207 i/o sa15 205 i/o pin name pin # type sa16 202 i/o sa17 201 i/o sa18 199 i/o sa19 197 i/o sbhe# 32 i/o sd00 190 i/o sd01 189 i/o sd02 187 i/o sd03 186 i/o sd04 185 i/o sd05 180 i/o sd06 179 i/o sd07 178 i/o sd08 55 i/o sd09 60 i/o sd10 62 i/o sd11 64 i/o sd12 67 i/o sd13 68 i/o sd14 69 i/o sd15 70 i/o serr# 134 i smemr# 196 o smemw# 192 o smi# 160 o spkr (82378ZB) 73 o spkr/testo (82379ab) 73 i/o stop# 132 i/o (s/t/s) stpclk# 167 o
82378 zb (sio) and 82379ab (sio.a) e 126 pin name pin # type sysclk 166 o tc (82379ab) 20 o test 169 i testo (82378ZB) 21 o trdy# 127 i/o (s/t/s) ubusoe# 164 o ubustr 165 o v dd 1 v v dd 79 v v dd 104 v v dd 105 v v dd 116 v v dd 131 v pin name pin # type v dd 144 v v dd 156 v v dd 157 v v dd 181 v v dd (82378ZB) v dd 25 v v dd 52 v v dd 53 v v dd 208 v v ss 2 v v ss 12 v v ss 26 v v ss 27 v v ss 54 v v ss 66 v pin name pin # type v ss 77 v v ss 78 v v ss 103 v v ss 117 v v ss 129 v v ss 130 v v ss 145 v v ss 158 v v ss 162 v v ss 182 v v ss 183 v v ss 194 v zerows# 188 i
e 82378 zb (sio) and 82379 (sio.a) 127 7. 0. mechanical s pecifications 7.1. package diagram 0 . 5 0 0 . 5 0 0 . 1 0 0 . 2 3 0 . 0 5 u n i t s : m m 1 5 2 5 3 1 0 4 1 0 5 156 1 5 7 2 0 8 0 m i n 5 m a x 0 . 3 0 5 0 . 0 5 5 0 . 0 7 6 m a x * n o t e * h e i g h t m e a s u r e m e n t s s a m e a s w i d t h m e a s u r e m e n t s 0 . 1 0 m a x t o l e r a n c e w i n d o w f o r l e a d s k e w f r o m t h e o r e t i c a l t r u e p o s i t i o n 3 0 . 6 0 0 . 2 0 2 8 . 0 0 . 1 0 2 5 . 3 5 ( r e f ) 3 . 4 0 0 . 1 0 3 . 8 6 m a x 057120 figure 20 . 208-pin quad flat pack (qfp) package dimensions
82378 zb (sio) and 82379ab (sio.a) e 128 7.2. thermal specifications table 12 . 82378 qfp package thermal characteristics thermal resistance - c/watt air flow rate (ft./min) parameter 0 200 400 q junction to case 6.6 6.6 6.6 q case to ambient 36.6 27.4 24 8. 0. testability the test and testo pins are used to test the sio/sio.a. during normal operations, the test pin must be grounded. the test output testo may be left as a no-connect (nc). 8.1. global tri-state the test pin and irq3 are used to provide a high-impedance tri-state test mode. when the following input combination occurs, all outputs and bi-directional pins are tri-stated, with the exception of testo: test = '1' irq3 = '1' the sio/sio.a must be reset after the bi-directional and output pins have been tri-stated in this manner. 8.2. nand tree a nand tree is provided primarily for vil/vih testing. the nand tree is also useful for ate at board level testing. the nand tree allows the tester to test the solder connections for each individual signal pin. the test pin, along with irq5 or irq6, activates the nand tree. all bi-directional pins, and certain pure output pins using bi-directional buffers for performance reasons, are tri-stated when the following input combinations occur: test = '1' irq5 = '1' - or - test = '1' irq6 = '0' the output pulse train is observed at the testo test output. pure output pins are not included directly in the nand tree. as noted in section 8.3, each output can be expected to toggle after the corresponding node noted next to the pin name toggles from a "1" to a "0".
e 82378 zb (sio) and 82379 (sio.a) 129 the sequence of the ate test is as follows: 1. drive test and irq5 high or test high and irq6 low. 2. drive each input and bi-directional pin noted in section 8.3 high. 3. startin g with the pin farthest from testo (sa8 on the 82378ZB and smi# on the 82379ab), individually drive each pin low. expect testo to toggle with each pin. expect each pure output noted in section 8.3 to toggle after each corresponding input pin has been driven low. 4. turn off tester drivers before driving test low. 5. reset the sio/sio.a prior to proceeding with further testing. 8.3. nand tree cell order table 13 . nand tree cell order for 82378ZB tree output# pin # pin name notes 14 irq4 reserved 21 testo test mode output 1 11 irq5 cell closest to testo 2 10 sa9 3 9 irq6 4 8 sa10 5 7 irq7 6 6 sa11 7 5 sa12 8 4 refresh# 9 3 sa13 10 207 sa14 11 206 master# 12 205 sa15 13 204 memw# 14 203 memr# 15 202 sa16 16 201 sa17 17 200 ior# 18 199 sa18 19 198 iow# 20 197 sa19
82378 zb (sio) and 82379ab (sio.a) e 130 tree output# pin # pin name notes 21 196 smemr# 22 193 aen 23 192 smemw# 24 191 iochrdy 25 190 sd0 26 189 sd1 27 188 zerows# 28 187 sd2 29 186 sd3 30 185 sd4 31 184 irq9 32 180 sd5 33 179 sd6 34 178 sd7 35 177 rstdrv 36 176 iochk# 175 ecsaddr0 nand tree output of tree cell 28 174 ecsaddr1 nand tree output of tree cell 29 173 ecsaddr2 nand tree output of tree cell 30 37 172 irq8# 38 171 extsmi# 170 ecsen# nand tree output of tree cell 32 169 test pi => vcc, test must be '1' 39 168 irq1 167 stpclk# 40 166 sysclk 165 ubustr nand tree output of tree cell 33 164 ubusoe# nand tree output of tree cell 34 41 163 pcirst# 42 161 dskchg 160 smi#
e 82378 zb (sio) and 82379 (sio.a) 131 tree output# pin # pin name notes 43 159 ad0 44 155 ad1 45 154 ad2 46 153 ad3 47 152 ad4 48 151 ad5 49 150 ad6 50 149 ad7 51 148 ad8 52 147 c/be0# 53 146 ad9 54 143 ad10 55 142 ad11 56 141 ad12 57 140 ad13 58 139 ad14 59 138 ad15 60 137 c/be1# 61 136 init 62 135 par 63 134 serr# 64 133 lock# 65 132 stop# 66 128 devsel# 67 127 trdy# 68 126 irdy# 69 125 frame# 70 124 c/be2# 71 123 ad16 72 122 ad17 73 121 ad18
82378 zb (sio) and 82379ab (sio.a) e 132 tree output# pin # pin name notes 74 120 ad19 75 119 ad20 76 118 ad21 77 115 ad22 78 114 ad23 79 113 c/be3# 80 112 ad24 81 111 ad25 82 110 ad26 83 109 ad27 84 108 ad28 85 107 ad29 86 106 ad30 87 102 ad31 88 101 idsel 89 100 req3# 90 98 req1# 91 97 req2# 92 96 cpureq# 95 cpugnt# nand tree output of tree cell 93 94 gnt1# nand tree output of tree cell 95 93 93 req0# 92 gnt0# nand tree output of tree cell 100 94 90 pciclk 89 flshreq# nand tree output of tree cell 102 95 88 memack# 87 memreq# nand tree output of tree cell 103 86 memcs# nand tree output of tree cell 104 85 alt_a20 nand tree output of tree cell 105 96 84 pirq[3]# 97 83 pirq[2]#
e 82378 zb (sio) and 82379 (sio.a) 133 tree output# pin # pin name notes 98 82 pirq[1]# 99 81 pirq[0]# 100 80 osc 76 alt_rst# nand tree output of tree cell 23 75 int nand tree output of tree cell 24 74 nmi nand tree output of tree cell 25 101 73 spkr 72 ignne# nand tree output of tree cell 26 102 71 ferr# 103 70 sd15 104 69 sd14 105 68 sd13 106 67 sd12 107 65 dreq7 108 64 sd11 109 63 dack7# 110 62 sd10 111 61 dreq6 112 60 sd9 113 59 dack6# 114 58 dreq3 115 57 dreq2 116 56 dreq1 117 55 sd8 118 51 dreq5 119 50 dack5# 120 49 dack3# 121 48 dack1# 122 47 dreq0 123 46 la17 124 45 dack0#
82378 zb (sio) and 82379ab (sio.a) e 134 tree output# pin # pin name notes 125 44 la18 126 43 irq14 127 42 la19 128 41 irq15 129 40 la20 130 39 irq12/m 131 38 la21 132 37 irq11 133 36 la22 134 35 irq10 135 34 la23 136 33 iocs16# 137 32 sbhe# 138 31 memcs16# 139 30 sa0 140 29 sa1 141 28 sa2 142 24 sa3 143 23 bale 144 22 sa4 145 20 eop 146 19 sa5 147 18 dack2# 148 17 sa6 149 16 irq3 output signals will transition from high-impedance state to driving state after this pin is driven low. 150 15 sa7 151 13 sa8 cell furthest from testo start of nand tree
e 82378 zb (sio) and 82379 (sio.a) 135 table 14 . nand tree cell order for 82379ab order pin # pin name 1 160 smi# 2 91 gnt2# 3 99 gnt3# 4 195 apicclk 5 21 apicd1 6 13 sa8 7 15 sa7 8 16 irq3 9 17 sa6 10 18 dack2# 11 19 sa5 12 20 tc 13 22 sa4 14 23 bale 15 24 sa3 16 28 sa2 17 29 sa1 18 30 sa0 19 31 memcs16# 20 32 sbhe# 21 33 iocs16# 22 34 la23 23 35 irq10 24 36 la22 25 37 irq11 26 38 la21 27 39 irq12/m 28 40 la20 29 41 irq15 30 42 la19 31 43 irq14 32 44 la18 33 45 dack0# 34 46 la17 table 14 . nand tree cell order for 82379ab order pin # pin name 35 47 dreq0 36 48 dack1# 37 49 dack3# 38 50 dack5# 39 51 dreq5 40 55 sd8 41 56 dreq1 42 57 dreq2 43 58 dreq3 44 59 dack6# 45 60 sd9 46 61 dreq6 47 62 sd10 48 63 dack7# 49 64 sd11 50 65 dreq7 51 67 sd12 52 68 sd13 53 69 sd14 54 70 sd15 55 71 ferr# 56 72 ignne# 57 74 nmi 58 75 int 59 76 alt_rst# 60 80 osc 61 81 pirq0# 62 82 pirq1 63 83 pirq2 64 84 pirq3# 65 85 alt_a20 66 86 memcs# 67 87 memreq# 68 88 memack# table 14 . nand tree cell order for 82379ab order pin # pin name 69 89 flshreq# 70 90 pciclk 71 92 gnt0 72 93 req0# 73 94 gnt1# 74 95 cpugnt# 75 96 cpureq# 76 97 req2# 77 98 req1# 78 100 req3# 79 101 idsel 80 102 ad31 81 106 ad30 82 107 ad29 83 108 ad28 84 109 ad27 85 110 ad26 86 111 ad25 87 112 ad24 88 113 c/be3# 89 114 ad23 90 115 ad22 91 118 ad21 92 119 ad20 93 120 ad19 94 121 ad18 95 122 ad17 96 123 ad16 97 124 c/be2# 98 125 frame# 99 126 irdy# 100 127 trdy# 101 128 devsel# 102 132 stop#
82378 zb (sio) and 82379ab (sio.a) e 136 table 14 . nand tree cell order for 82379ab order pin # pin name 103 133 lock# 104 134 serr# 105 135 par 106 136 init 107 137 c/be1# 108 138 ad15 109 139 ad14 110 140 ad13 111 141 ad12 112 142 ad11 113 143 ad10 114 146 ad9 115 147 c/be0# 116 148 ad8 117 149 ad7 118 150 ad6 119 131 ad5 120 152 ad4 121 153 ad3 122 154 ad2 123 155 ad1 124 159 ad0 125 161 dskchg 126 163 pcirst# table 14 . nand tree cell order for 82379ab order pin # pin name 127 164 ubusoe# 128 165 ubustr 129 166 sysclk 130 167 stpclk# 131 168 irq1 132 170 ecsen# 133 171 extsmi# 134 172 irq8# 135 173 ecsaddr2 136 174 ecsaddr1 137 175 ecsaddr0 138 176 iochk# 139 177 rstdrv 140 178 sd7 141 179 sd6 142 180 sd5 143 184 irq9 144 185 sd4 145 186 sd3 146 187 sd2 147 188 zerows# 148 189 sd1 149 190 sd0 150 191 iochrdy table 14 . nand tree cell order for 82379ab order pin # pin name 151 192 smemw# 152 193 aen 153 196 smemr# 154 197 sa19 155 198 iow# 156 199 sa18 157 200 ior# 158 201 sa17 159 202 sa16 160 203 memr# 161 204 memw# 162 205 sa15 163 206 apicd0 164 207 sa14 165 3 sa13 166 4 refresh# 167 5 sa12 168 6 sa11 169 7 irq7 170 8 sa10 171 9 irq6 172 10 sa9 173 11 irq5
e 82378 zb (sio) and 82379ab (sio.a) 137 8.4. nand tree diagram figures 21 and 22 shows the nand tree diagrams. note that the pulse generator shown is only used for testing the irq4 signal. it is enabled when irq4 is pulsed high. v c c s a 8 c e l l 1 5 1 s a 7 c e l l 1 5 0 z e r o w s # c e l l 2 7 s d 1 s d 0 c e l l 2 6 c e l l 2 5 i g n n e # n m i s a 9 i r q 5 c e l l 2 c e l l 1 t e s t o i r q 3 c e l l 1 4 9 057121 figure 21 . nand tree diagram for 82378ZB vcc sa8 cell 150 sa7 cell 149 sd10 cell 110 dack7# sd11 cell 109 cell 108 ignne# nmi sa9 irq5 cell 2 cell 1 testo irq3 cell 148 057122 figure 22 . nand tree diagram for the 82379ab

▲Up To Search▲

Price & Availability of 82378ZB

	To Download 82378ZB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .