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1 100v, 2a peak, half-bridge driver with tri-level pwm input and adjustable dead-time ISL78420 the ISL78420 is a 100v, high frequency, half-bridge mosfet driver with a tri-level pwm input. this part is a derivative of the hip2121 half-bridge driver. the non-automotive version of the ISL78420 is the hip2124. this driver is designed to work in conjunction with the isl78220 , ?6-phase interleaved boost pwm controller with light load efficiency enhancement?. equally, it can be used in most applications where a half-bridge driver is used. this driver has a programmable dead-time to ensure break-before-make operation between the high-side and low-side drivers. a resistor is used to adjust the dead-time up to 220ns. the tri-level input allows the pwm input to also function as a disable input. when the pwm input is a logic high, the high-side bridge fet is turned on and the low-side fet is off. when the input is a logic low, the low-side bridge fet is turned on and the high-side fet is turned off. when the input voltage is midrange, both the high and low-side bridge fets are turned off. the enable pin (en), when low, drives both outputs to a low state. this input is used when the controller does not utilize a tri-state output. all logic inputs are v dd tolerant. two package options are provided. the 10 ld 4x4 dfn package has standard pinouts. the 9 ld 4x4 dfn package omits pin 2 to comply with 100v conductor spacing per ipc-2221. features ? programmable break-before-make dead-time prevents shoot-through and is adjustable up to 220ns ? bootstrap supply maximum voltage to 114vdc ? wide supply voltage range (8v to 14v) ? supply undervoltage protection ?on-chip 1 bootstrap diode ? unique tri-level pwm input logic enables phase shedding when using multi-phase pwm controllers (e.g. isl78220/225) ? 9 ld tdfn ?b? package compliant with 100v conductor spacing guidelines per ipc-2221 ? aec-q100 qualified applications ? automotive applications ? multi-phase boost (isl78220/225) ?half-bridge dc/dc converter ? class-d amplifiers ? forward converter with active clamp related literature ? fn7668 hip2120, hip2121 ?100v, 2a peak, high frequency half-bridge drivers with adjustable dead time control and pwm input? ? fn8363 hip2124, ?100v, 2a peak, half bridge driver with tri-level input and adjustable dead time? (non-automotive) ? fn7688 isl78220, ?6-phase interleaved boost pwm controller with light load efficiency enhancement? ? fn7909 isl78225, ?4-phase interleaved boost pwm controller with light load efficiency enhancement? figure 1. typical application figure 2. dead-time vs timing resistor vdd hb ho hs lo vss pwm en 100v max rdt feedback with isolation pwm controller secondary circuits ISL78420 epad half bridge r dt (k ) 81624324856 40 64 80 dead-time (ns) 200 160 140 120 100 80 60 40 20 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. september 24, 2012 fn8296.1
ISL78420 2 fn8296.1 september 24, 2012 block diagram pin configurations ISL78420artaz (10 ld 4x4 tdfn) top view ISL78420artbz (9 ld 4x4 tdfn) top view level shift under voltage under voltage epad delay ISL78420 vdd pwm rdt en hb ho hs lo vss delay + - + - 5v 5v 100k 100k 210k epad 1 2 3 4 5 10 9 8 7 6 vdd hb ho hs nc lo vss pwm en rdt epad 1 3 4 5 10 9 8 7 6 vdd hb ho hs lo vss pwm en rdt pin descriptions 10 ld 9 ld symbol description 1 1 vdd positive supply voltage for lower gate driver. decouple this pin to ground with a 4.7f or larger ceramic capacitor to vss 2 3 hb high-side bootstrap supply voltage referenced to hs. connect bootstrap capaci tor to this pin and hs. 3 4 ho high-side output connected to gate of high-side fet. 4 5 hs high-side source connect to source of high-side fet. connect bootstrap capacitor to this pin and hb. 8 8 pwm pwm input. for pwm = 5v, ho = 1, lo = 0. for pwm = 0v, ho = 0, lo = 1. for pwm = 2.5v, ho = lo = 0. 7 7 en output enable, when low, ho = lo = 0 9 9 vss negative voltage supply, connected to ground. 10 10 lo low-side output. connect to gate of low-side fet. 5 - nc no connect. this pin is isolated from all other pins. may optionally be connected to vss. note that on the 9 ld package, there is no pin present at the location normally occupied by pin 2. 6 6 rdt a resistor connected between this pin and vss adds dead time by adding delay time to the falling and rising edges of the pwm input. - - epad the epad is electrically isolated. it is recommended that the epad be connected to the vss plane for heat removal.
ISL78420 3 fn8296.1 september 24, 2012 ordering information part number (notes 1, 2, 3) part marking input temp. range (c) package (pb-free) pkg. dwg. # ISL78420art a z 78420 az 5v tri-level -40 +125 10 ld 4x4 tdfn l10.4x4 ISL78420art b z (note 4) 78420 bz 5v tri-level -40 +125 9 ld 4x4 tdfn l9.4x4 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or ex ceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL78420 . for more information on msl please see tech brief tb363 . and tb477 . 4. ?b? package option has alternate pin assignments for compliance with 100v conductor spacing guidelines per ipc-2221. note tha t pin 2 is omitted for additional spacing between pins 1 and 3.
ISL78420 4 fn8296.1 september 24, 2012 absolute maximum ratings (note 6) thermal information supply voltage, v dd , v hb - v hs (notes 5) . . . . . . . . . . . . . . . . . -0.3v to 18v pwm and en input voltage . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd + 0.3v voltage on lo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd + 0.3v voltage on ho . . . . . . . . . . . . . . . . . . . . . . . . . . . . vhs - 0.3v to vhb + 0.3v voltage on hs (continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to 110v voltage on hb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118v average current in v dd to hb diode . . . . . . . . . . . . . . . . . . . . . . . . . 100ma maximum recommended operating conditions (note 6) supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8v to 14v voltage on hs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to 100v voltage on hs . . . . . . . . . . . . . . . . . . . . . .(repetitive transient) -5v to 105v voltage on hb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v hs + 8v to v hs + 14v and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dd - 1v to v dd + 100v hs slew rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50v/ns temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c thermal resistance (typical) ja (c/w) jc (c/w) 10 ld tdfn (notes 7, 8) . . . . . . . . . . . . . . . 42 4 9 ld tdfn (notes 7, 8) . . . . . . . . . . . . . . . . 42 4 max power dissipation at +25c in free air 10 ld tdfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0w 9 ld tdfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1w storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-55c to +150c pb-free reflow profile (*) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb487 *peak temperature during solder reflow . . . . . . . . . . . . . . +235c max esd ratings human body model class 2 (tested pe r jesd22-a114e) . . . . . . . . 3000v machine model class b (tested per jesd22-a115-a) . . . . . . . . . . . . 300v charged device model class iv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500v latch up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . 100ma caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. the ISL78420 is capable of derated operation at supply voltages exceeding 14v. figure 17 shows the high-side voltage derating curve for this mode of operation. 6. all voltages referenced to v ss unless otherwise specified. 7. ja is measured in free air with the componen t mounted on a high effective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379 . 8. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v dd = v hb = 12v, v ss = v hs = 0v, r dt = 0 k , pwm = 0v, no load on lo or ho, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +125c. parameters symbol test conditions t a = +25c t a = -40c to +125c units min typ max min (note 9) max (note 9) supply currents v dd quiescent current i dd8k r dt = 8k - 650 950 - 1000 a i dd80k r dt = 80k - 1.0 2.1 - 2.2 ma v dd operating current i ddo8k f = 500khz, r dt = 8k - 2.5 3 - 3 ma i ddo80k f = 500khz, r dt = 80k - 3.4 4 - 4 ma total hb quiescent current i hb li = hi = 0v - 65 115 - 150 a total hb operating current i hbo f = 500khz - 2.0 2.5 - 3 ma hb to v ss current, quiescent i hbs li = hi = 0v; v hb = v hs = 114v - 0.05 1.5 - 10 a hb to v ss current, operating i hbso f = 500khz; v hb = v hs = 114v - 1.2 1.5 - 1.6 ma tri-level pwm input high level threshold v pwmh -3.64.0 - 4.3 v high middle level threshold v midh 3.0 3.4 - 2.9 - v low middle level threshold v midl -1.62.1 - 2.2 v low level threshold v pwml 0.8 1.1 - 0.7 - v pwm mid level pull-up resistors r mid -160- - - k
ISL78420 5 fn8296.1 september 24, 2012 en input low level input threshold v enl 1.4 1.8 - 1.2 -v high level input threshold v enh -1.82.2 - 2.4 v en pull-up resistance r pu -210- 100 320 k undervoltage protection v dd rising threshold v ddr 6.8 7.3 7.8 6.5 8.1 v v dd threshold hysteresis v ddh -0.6- - - v hb rising threshold v hbr 6.2 6.9 7.5 5.9 7.8 v hb threshold hysteresis v hbh -0.6- - - v bootstrap diode low current forward voltage v dl i vdd-hb = 100ma - 0.6 0.7 - 0.8 v high current forward voltage v dh i vdd-hb = 100ma - 0.7 0.9 - 1 v dynamic resistance r d i vdd-hb = 100ma - 0.8 1 - 1.5 lo gate driver low level output voltage v oll i lo = 100ma - 0.25 0.4 - 0.5 v high level output voltage v ohl i lo = -100ma, v ohl = v dd - v lo - 0.25 0.4 - 0.5 v peak pull-up current i ohl v lo = 0v - 2 - - - a peak pull-down current i oll v lo = 12v - 2 - - - a ho gate driver low level output voltage v olh i ho = 100ma - 0.25 0.4 - 0.5 v high level output voltage v ohh i ho = -100ma, v ohh = v hb - v ho - 0.25 0.4 - 0.5 v peak pull-up current i ohh v ho = 0v - 2 - - - a peak pull-down current i olh v ho = 12v - 2 - - - a electrical specifications v dd = v hb = 12v, v ss = v hs = 0v, r dt = 0 k , pwm = 0v, no load on lo or ho, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +125c. (continued) parameters symbol test conditions t a = +25c t a = -40c to +125c units min typ max min (note 9) max (note 9) switching specifications v dd = v hb = 12v, v ss = v hs = 0v, r dt = 0k , no load on lo or ho, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +125c. parameters symbol test conditions t j = +25c t j = -40c to +125c units min type max min (note 9) max (note 9) ho turn-off propagation delay pwm falling to ho falling t plho -3250 - 60 ns lo turn-off propagation delay pwm rising to lo falling t pllo -3250 - 60 ns minimum dead-time delay (note 10) ho falling to lo rising t dthlmin r dt = 80k, pwm 1 to 0 15 35 50 10 60 ns minimum dead-time delay (note 10) lo falling to ho rising t dtlhmin r dt = 80k pwm 0 to 1 15 25 50 10 60 ns maximum dead-time delay (note 10) ho falling to lo rising t dthlmax r dt = 8k, pwm 1 to 0 150 220 300 - - ns
ISL78420 6 fn8296.1 september 24, 2012 timing diagram maximum dead-time delay (note 10) lo falling to ho rising t dtlhmax r dt = 8k, pwm 0 to 1 150 220 300 - - ns either output rise/fall time (10% to 90%/90% to 10%) t rc, t fc c l = 1nf - 10 - - - ns bootstrap diode turn-on or turn-off time t bs -10- - - ns notes: 9. parameters with min and/or max limits are 100% tested at +25c , unless otherwise specified. te mperature limits are establishe d by characterization and are not production tested. 10. dead-time is defined as the period of time between the lo falling and ho rising or between ho falling and lo rising. switching specifications v dd = v hb = 12v, v ss = v hs = 0v, r dt = 0k , no load on lo or ho, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +125c. (continued) parameters symbol test conditions t j = +25c t j = -40c to +125c units min type max min (note 9) max (note 9) pwm ho lo en v pwmh v midl v midh v pwml t dtlh t pllo t phho t dthl pwm ho lo en rise and fall transitions of the pwm inputs are exaggerated to clearly illustrate the low, mid, and high threshold levels.
ISL78420 7 fn8296.1 september 24, 2012 typical performance curves figure 3. i dd operating current vs frequency, r dt = 8k figure 4. i dd operating current vs frequency, r dt = 80k figure 5. i hb operating current vs frequency, r dt = 8k figure 6. i hbs operating current vs frequency r dt = 80k figure 7. high level output voltage vs temperature figure 8. low level output voltage vs temperature 0.1 1.0 10.0 frequency (hz) i ddo (ma) t = +25c t = +125c t = +150c 10k 100k 1m t = -40c 10k 100k 1m 0.1 1.0 10.0 frequency (hz) i ddo (ma) t = +25c t = -40c t = +125c t = +150c frequency (hz) i hbo (ma) 0.01 1.0 10.0 t = +25c t = +125c t = +150c 10k 100k 1m 0.1 t = -40c frequency (hz) i hbso (ma) 0.01 1.0 10.0 t = +25c t = -40c t = +125c t = +150c 10k 100k 1m 0.1 -50 0 50 100 150 50 100 150 200 250 300 temperature (c) v ohl , v ohh (mv) v dd = v hb = 12v v dd = v hb = 14v v dd = v hb = 8v -50 0 50 100 150 50 100 150 200 v oll , v olh (mv) temperature (c) v dd = v hb = 12v v dd = v hb = 14v v dd = v hb = 8v
ISL78420 8 fn8296.1 september 24, 2012 figure 9. undervoltage lockout threshold vs temperature figure 10. undervoltage lockout hysteresis vs temperature figure 11. propagation delays vs temperature figure 12. delay matching vs temperature figure 13. peak pull-up current vs output voltage figure 14. peak pull-down current vs output voltage typical performance curves (continued) v ddr , v hbr (v) -50 0 50 100 150 6.7 temperature (c) v hbr v ddr 6.5 6.3 6.1 5.9 5.7 5.5 5.3 v ddh , v hbh (v) -50 0 50 100 150 0.70 temperature (c) v hbh v ddh 0.65 0.60 0.55 0.50 0.45 0.40 25 30 35 40 45 50 55 t lplh , t lphl , t hplh , t hphl (ns) -50 0 50 100 150 temperature (c) t lphl t hphl t lplh t hplh 25 30 35 40 45 50 55 t lplh , t lphl , t hplh , t hphl (ns) -50 0 50 100 150 temperature (c) t hplh t lplh t hphl t lphl 0 4 8 10 12 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v lo , v ho (v) i ohl , i ohh (a) 26 0481012 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v lo , v ho (v) i ohl , i ohh (a) 26 1.0 0.5
ISL78420 9 fn8296.1 september 24, 2012 functional description functional overview when connected to a half bridge, the output of the bridge on the hs node follows the pwm input. in other words, when the pwm input is high, the high-side bridge fet is turned on and the low-side fet is off. when the pwm input is low, the low-side bridge fet is turned on and the high-side is turned off. the enable pin (en), when low, drives both outputs to a low state. a unique feature of the ISL78420 is the tri-level logic of the pwm input. the logic thresholds of the pwm input is divided into 3 levels. a logic low ensures that the output of the low-side bridge fet is on and the high-side fet is off. a logic high ensures that the high-side bridge fet is on an d the low-side fet is off. when the logic input is midrange (2.5v), both the high and low side fets are off. this driver is designed to work in conjunction with the isl78220 , ?6-phase interleaved boost pwm controller with light load efficiency enhancement?. when the pwm input transitions high or low, it is necessary to ensure that both bridge fets ar e not on at the same time to prevent shoot-through currents (break before make). the internal programmable timers delay the ri sing edge of either output resulting with both outputs being off before either of the bridge fets are driven on. an 8k resistor connected between r dt and vss results in a nominal dead time of 220ns. an 80k results with a minimum nominal dead time of 25ns. resistors values less than 8k and greater than 80k are not recommended. while the voltage of the input signal to the pwm is within the boundaries of the mid-level logic, the outputs are in a dead time state because both outputs are of f. the actual delay time, as programed by the r dt value, begins when the high or low logic levels are transitioned. the period while the input logic in the mid-level range, is consequently added to the programmed dead time period. this may be a cons ideration when selecting the r dt value. the high-side driver bias is established by the boot capacitor connected between hb and hs. the charge on the boot capacitor is provided by the internal boot diode that is connected to vdd. the current path to charge the boot capacitor occurs when the low-side bridge fet is on. this charge current is limited in amplitude by the inherent resistance of the boot diode and by the drain-source voltage of the low-si de fet. assuming that the on time of the low-side fet is sufficiently long to fully charge the boot capacitor, the boot voltage will charge very close to vdd (less the boot diode drop and the on-voltage of the low-side bridge fet). when the pwm input transitions high, the high-side bridge fet is driven on after the dead time. because the hs node is connected figure 15. quiescent current vs voltage figure 16. bootstrap diode i-v characteristics figure 17. v hs voltage vs v dd voltage typical performance curves (continued) 0 5 10 15 20 0 10 20 30 40 50 60 70 80 90 100 110 120 v dd , v hb (v) i dd , i hb (a) i hb i dd 0.3 0.4 0.5 0.6 0.7 0.8 1 . 10 -3 0.01 0.10 1.00 forward voltage (v) forward current (a) 1 . 10 -4 1 . 10 -5 1 . 10 -6 12 13 14 15 16 0 20 40 60 80 100 120 v hs to v ss voltage (v) v dd to v ss voltage (v)
ISL78420 10 fn8296.1 september 24, 2012 to the source of the high-side fet, the hs node will rise almost to the level of the bridge voltage (less the conduction voltage across the bridge fet). because the boot capacitor voltage is referenced to the source voltage of the hi gh-side fet, the hb node is v dd volts above the hs node and the boot diode is reversed biased. because the high-side driver circuit is referenced to the hs node, the ho output is now approximately vhb + vbridge above ground. during the low to high transiti on of the hs node, the boot capacitor sources the necessary gate charge to fully enhance the high-side bridge fet gate. after the gate is fully charged, the boot capacitor no longer sources the charge to the gate but continues to provide bias current to the high-side driver. it is clear that the charge of the boot capacitor must be substantially larger than the required charge of the high -side fet and high-side driver otherwise the boot voltage will sag excessively. if the boot capacitor value is too small for the required maximum of on-time of the high-side fet, the high -side uv lockout may engage resulting with an unexpected operation. application information selecting the boot capacitor value the boot capacitor value is chosen not only to supply the internal bias current of the high-side driver but also, and more significantly, to provide the gate charge of the driven fet without causing the boot voltage to sag excessively. in practice, the boot capacitor should have a total charge that is approximately 20x the gate charge of the driven power fet for a 5% drop in voltage after the charge has been transfer red from the boot capacitor to the gate capacitance. the following parameters are required to calculate the value of the boot capacitor for a specific amount of voltage droop. in this example, the values used are arbitrary. they should be changed to comply with the actual application. the following equations calculate the total charge required for the period. these equations assume that all of the parameters are constant during the period du ration. the error is insignificant if the ripple is small. if the gate to source resistor is removed (r gs is usually not needed or recommended), then: c boot = 0.33f v dd = 10v v dd can be any value between 7 and 14vdc v hb = v dd - 0.6v = v ho high side driver bias voltage (v dd - boot diode voltage) referenced to v hs period = 1ms this is the longest expected switching period i hb = 100a worst case high side driver current when xho = high (this value is specified for v dd = 12v but the error is not significant) r gs = 100k gate-source resistor (usually not needed) ripple= 5% desired ripple voltage on the boot cap (larger ripple is not recommended) i gate_leak = 100na from the fet vendor?s datasheet qgate80v = 64nc from figure 18 figure 18. typical gate charge of a power fet 12 10 8 6 4 2 0 10 20 30 40 50 60 70 80 qg total gate charge (nc) vgs, gate-to-source voltage (v) 0 v ds = 80v v ds = 50v v ds = 20v i d = 33a (eq. 1) q c q gate80v = period + i hb v ho r gs i gate_leak + () ? + c boot q c ripple ? vdd () ? = c boot 0.52 f =
ISL78420 11 fn8296.1 september 24, 2012 typical application circuit figure 19 is an example of how the ISL78420 can be configured for an active clamp forward powe r supply application. note that the pwm signal from the controlle r must be inverted for this active clamp forward topology. depending on the application, th e switching speed of the bridge fets can be reduced by adding series connected resistors between the xho outputs and the fet gates. gate-source resistors are recommended on the low-side fets to prevent unexpected turn-on of the bridge should the bridge voltage be applied before vdd. gate-source resistors on the high-side fets are not usually required if low- side gate-source resistors are used. if relatively low value gate-source resistors are used on the high-side fets, be aware that a larger value for the boot capacitor may be required. transients on hs node an important operating condition that is frequently overlooked by designers is the negative transient on the xhs pins that occurs when the high-side bridge fet turns off. the absolute maximum transient allowed on the xhs pin is -6v but it is wise to minimize the amplitude to lower levels. this transient is the result of the parasitic inductance of the low-side drain-source conductor on the pcb. even the parasitic inductance of the low-side fet contributes to this transient. when the high-side bridge fet turns off (see figure 20), because of the inductive characteristics the load, the current that was flowing in the high-side fet (blue) must rapidly commutate to flow through the low-side fet (red). the amplitude of the negative transient impressed on the xhs node is (di/dt x l) where l is the total parasitic inductance of the low-side fet drain-source path and di/dt is the rate at which the high-side fet is turned off. with the increasing power levels of power supplies and motors, clamping this tran sient become more and more significant for the proper operation of the ISL78420. there are several ways of reducing the amplitude of this transient. if the bridge fets are turned off more slowly to reduce di/dt, the amplitude will be redu ced but at the expense of more switching losses in the fets. carefu l pcb design will also reduce the value of the parasitic inductance. however, these two solutions by themselves may not be sufficient. figure 20 illustrates a simple me thod for clamping the negative transient. a fast pn junction, 1a diode is connected between xhs and vss as shown. it is important that this diode be placed as close as possible to the xhs and vss pins to minimize the parasitic inductance of this current path. because this clamping diode is essentially in parallel with the body diode of the low-side fet, a small value resistor is necessary to limit current when the body diode of the low-side bridge fet is conducting during the dead time. the resistor in series with hs, can be used instead of the gate resistor of the high-side fet. please note that a similar transien t with a positive polarity occurs when the low-side fet turns off. this is less frequently a problem because xhs node is floating up toward the bridge bias voltage. the absolute max voltage rating for the xhs node does need to be observed when the positive transient occurs. ISL78420 hi driver lo driver logic ho lo hs pwm en rdt vss vdd hb 8v to 15v 100v max pwm controller pwm * figure 19. typical active clamp forward application vss hs lo ho inductive load + - + - hb figure 20. parasitic inductance causes transients on hs node
ISL78420 12 fn8296.1 september 24, 2012 power dissipation the dissipation of the ISL78420 is dominated by the gate charge required by the driven bridge fets and the switching frequency. the internal bias and boot diode also contribute to the total dissipation but these losses are us ually insignificant compared to the gate charge losses. the calculation of the power dissi pation of the ISL78420 is very simple. gate power (for the ho and lo outputs) where q gate is the charge of the driven bridge fet at vdd, and freq is the switching frequency. boot diode dissipation where 0.6v is the diode conduction voltage bias current where i bias is the internal bias curr ent of the ISL78420 at the switching frequency total power dissipation p total = p gate + p diode + p bias operating temperatures t j = p total x ja + t amb where t j is the junction temperature at the operating air temperature, t amb , in the vicinity of the part. t j = p total x jc + t pcb where t j is the junction temperat ure with the operating temperature of the pcb, t pcb , as measured where the epad is soldered. pc board layout the ac performance of the is l78420 depends significantly on the design of the pc board. the following layout design guidelines are recommended to achieve optimum performance from the ISL78420: ? understand well how power currents flow. the high amplitude di/dt currents of the bridge fets will induce significant voltage transients on the associated traces. ? keep power loops as short as possible by paralleling the source and return traces. ? use planes where practical; they?re usually more effective than parallel traces. ? planes can also be non-grounded nodes. ? avoid paralleling high di/dt traces with low level signal lines. high di/dt will induce currents in the low level signal lines. ? when practical, minimize impedances in low level signal circuits; the noise, magnetically induced on a 10k resistor, is 10x larger than the noise on a 1k resistor. ? be aware of magnetic fields em anating from transformers and inductors. core gaps in these st ructures are especially bad for emitting flux. ? if you must have traces close to magnetic devices, align the traces so that they are parallel to the flux lines. ? the use of low inductance components such as chip resistors and chip capacitors is recommended. ? use decoupling capacitors to reduce the influence of parasitic inductors. to be effective, these capacitors must also have the shortest possible lead lengths. if vias are used, connect several paralleled vias to reduce the inductance of the vias. ? it may be necessary to add resi stance to dampen resonating parasitic circuits. in pcb designs with long leads on the lo and ho outputs, it may be necessary to add series gate resistors on the bridge fets to dampen the oscillations. ? keep high dv/dt nodes away from low level circuits. guard banding can be used to shunt away dv/dt injected currents from sensitive circuits. this is especially true for the pwm control circuits. ? avoid having a signal ground pl ane under a high dv/dt circuit. this will inject high di/dt currents into the signal ground paths. ? do power dissipation and voltage drop calculations of the power traces. most pcb/cad prog rams have built in tools for calculation of trace resistance. ? large power components (power fets, electrolytic capacitors, power resistors, etc.) will have internal parasitic inductance, which cannot be eliminated. this must be accounted for in the pcb layout and circuit design. ? if you simulate your circuits, consider including parasitic components. (eq. 3) p gate 4q gate freq vdd = (eq. 4) i diode_avg q gate freq = (eq. 5) p diode i diode_avg 0.6v = (eq. 6) p bias i bias vdd =
ISL78420 13 fn8296.1 september 24, 2012 epad design considerations the thermal pad of the ISL78420 is electrically isolated. it?s primary function is to provide heat sinking for the ic. it is recommended to tie the epad to v ss (gnd). figure 21 is an example of how to use vias to remove heat from the ic substrate. depending on the amount of power dissipated by the ISL78420, it may be necessary, to connect the epad to one or more ground plane layers. a via array, within the area of the epad, will conduct heat from the epad to the ground plane on the bottom layer. if inner pcb layers are available, it is also be desirable to connect these additional layers with the plated-through vias. the number of vias and the size of the gnd planes required for adequate heatsinking is determined by the power dissipated by the ISL78420, the air flow, and th e maximum temperature of the air around the ic. it is important that the vias have a low thermal resistance for efficient heat transfer. do not use ?thermal relief? patterns to connect the vias. figure 21. recomended pcb heatsink vdd epad gnd plane component layer hb ho hs lo vss pwm en epad gnd plane bottom layer vdd hb ho hs hb ho hs ls this plane is connected to hs and is under all high side driver circuits rdt nc nc
ISL78420 14 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8296.1 september 24, 2012 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, re lated documentation and related parts, plea se see the respective product information page. also, please check the product information page to ensure that you have the most updated datasheet: ISL78420 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change september 24, 2012 fn8296.1 initial release
ISL78420 15 fn8296.1 september 24, 2012 package outline drawing l9.4x4 9 lead thin dual flat no-lead plastic package rev 1, 1/10 typical recommended land pattern detail "x" side view top view bottom view located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be e-pad is offset from center. dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 4.00 2.20 0.15 (3.80) (4x) (9x 0.30) (6x 0.8) 0 .75 base plane c seating plane 0.08 c 0.10 c 9 x 0.30 see detail "x" 0.10 4 ca mb index area 6 pin 1 4.00 a b pin #1 index area bsc 3.2 ref 6x 0.80 6 (9 x 0.60) 0 . 00 min. 0 . 05 max. c 0 . 2 ref 9x 0 . 40 0.100 3.00 (2.20) (3.00) 0.05 m c 5 4 9 1 1.2 ref 4 (1.2)
ISL78420 16 fn8296.1 september 24, 2012 package outline drawing l10.4x4 10 lead thin dual flat no-lead plastic package rev 1, 1/08 typical recommended land pattern detail "x" side view top view bottom view located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 4.00 2.60 0.15 ( 3.80) (4x) ( 10x 0 . 30 ) ( 8x 0 . 8 ) 0 .75 base plane c seating plane 0.08 c 0.10 c 10 x 0.30 see detail "x" 0.10 4 ca mb index area 6 pin 1 4.00 a b pin #1 index area bsc 3.2 ref 8x 0.80 6 ( 10 x 0.60 ) 0 . 00 min. 0 . 05 max. c 0 . 2 ref 10x 0 . 40 3.00 ( 2.60) ( 3.00 ) 0.05 m c 6 5 10 1

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