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CXD3606R timing generator for frame readout ccd image sensor description the CXD3606R is a timing generator ic which generates the timing pulses for performing frame readout using the icx412 ccd image sensor. features base oscillation frequency 45mhz electronic shutter function supports draft (sextuple speed) / af (auto focus) drive horizontal driver for ccd image sensor vertical driver for ccd image sensor applications digital still cameras structure silicon gate cmos ic applicable ccd image sensors icx412 (type 1/1.8, 3240k pixels) pin configuration absolute maximum ratings supply voltage v dd v ss ?0.3 to +7.0 v v l ?0.0 to v ss v v h v l ?0.3 to +26.0 v input voltage v i v ss ?0.3 to v dd + 0.3 v output voltage v o1 v ss ?0.3 to v dd + 0.3 v v o2 v l ?0.3 to v ss + 0.3 v v o3 v l ?0.3 to v h + 0.3 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage v dd b 3.0 to 5.25 v v dd a, v dd c, v dd d 3.0 to 3.6 v v m 0.0 v v h 14.5 to 15.5 v v l ?.0 to ?.0 v operating temperature topr ?0 to +75 ? ?1 e01216-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 48 pin lqfp (plastic) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 h2 v dd 3 v dd 4 xshp xshd xrs pblk clpdm v ss 4 obclp adclk v ss 5 cko cki osco osci v dd 5 mcko ssi sck sen vd hd v ss 6 h1 v ss 3 v ss 2 rg v dd 2 ssgsl v dd 1 wen id/exp sncsl rst v ss 1 test2 sub v3b vl v3a v1b vh v1a v4 v2 vm test1 ? groups of pins enclosed in the figure indicate sections for which power supply separation is possible.
2 CXD3606R block diagram 35 34 39 44 43 41 5 4 22 20 19 28 27 26 25 30 v1b v2 v3a v1a wen id/exp v ss 5 obclp clpdm pblk vd hd 7 29 1 v ss 1 36 v ss 6 v dd 5 v dd 1 mcko cko cki osco osci pulse generator 2 37 48 test2 test1 rst 45 38 42 47 40 46 vl vm vh sub v4 v3b 31 32 33 sen sck ssi register v driver 6 ssgsl 3 sncsl 1/2 10 9 8 v ss 2 rg v dd 2 21 18 17 16 15 v ss 4 xrs xshd xshp v dd 4 23 adclk 11 13 12 14 v ss 3 h2 h1 v dd 3 selector selector latch ssg 24
3 CXD3606R pin description gnd internal system reset input. high: normal operation, low: reset control normally apply reset during power-on. schmitt trigger input/protective diode on power supply side control input used to switch sync system. high: cki sync, low: mcko sync with pull-down resistor vertical direction line identification pulse output/exposure time identification pulse output. switching possible using the serial interface data. (default: id) memory write timing pulse output internal ssg enable. high: internal ssg valid, low: external sync valid. with pull-down resistor 3.3v power supply. (power supply for common logic block) 3.3v power supply. (power supply for rg) ccd reset gate pulse output gnd gnd ccd horizontal register clock output ccd horizontal register clock output 3.3 to 5.0v power supply. (power supply for h1/h2) 3.3v power supply. (power supply for cds) ccd precharge level sample-and-hold pulse output ccd data level sample-and-hold pulse output sample-and-hold pulse output for analog/digital conversion phase alignment pulse output for horizontal and vertical blanking period pulse cleaning ccd dummy signal clamp pulse output gnd ccd optical black signal clamp pulse output the horizontal/vertical ob pattern can be changed using the serial interface data. clock output for analog/digital conversion ic logical phase adjustment possible using the serial interface data gnd inverter output inverter input inverter output for oscillation. when not used, leave open or connect a capacitor. inverter input for oscillation. when not used, fix low. 3.3v power supply. (power supply for common logic block) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 v ss 1 rst sncsl id/exp wen ssgsl v dd 1 v dd 2 rg v ss 2 v ss 3 h1 h2 v dd 3 v dd 4 xshp xshd xrs pblk clpdm v ss 4 obclp adclk v ss 5 cko cki osco osci v dd 5 i i o o i o o o o o o o o o o o i o i pin no. symbol i/o description
4 CXD3606R 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 system clock output for signal processing ic serial interface data input for internal mode settings. schmitt trigger input/protective diode on power supply side serial interface clock input for internal mode settings. schmitt trigger input/protective diode on power supply side serial interface strobe input for internal mode settings. schmitt trigger input/protective diode on power supply side vertical sync signal input/output horizontal sync signal input/output gnd ic test pin 1; normally fixed to gnd. with pull-down resistor gnd (gnd for vertical driver) ccd vertical register clock output ccd vertical register clock output ccd vertical register clock output 15.0v power supply. (power supply for vertical driver) ccd vertical register clock output ccd vertical register clock output 7.5v power supply. (power supply for vertical driver) ccd vertical register clock output ccd electronic shutter pulse output ic test pin 2; normally fixed gnd. with pull-down registor mcko ssi sck sen vd hd v ss 6 test1 vm v2 v4 v1a vh v1b v3a vl v3b sub test2 o i i i i/o i/o i o o o o o o o i pin no. symbol i/o description
5 CXD3606R electrical characteristics dc characteristics (within the recommended operating conditions) v dd 2 v dd 3 v dd 4 v dd 1, v dd 5 rst, ssi, sck, sen test1, test2, sncsl, ssgsl vd, hd h1, h2 rg xshp, xshd, xrs, pblk, obclp, clpdm, adclk cko mcko id/exp, wen v1a, v1b, v3a, v3b, v2, v4 sub v dd a v dd b v dd c v dd d v t+ v t v ih1 v il1 v ih2 v il2 v oh1 v ol1 v oh2 v ol2 v oh3 v ol3 v oh4 v ol4 v oh5 v ol5 v oh6 v ol6 v oh7 v ol7 i ol i om1 i om2 i oh i osl i osh 3.0 3.0 3.0 3.0 0.8v dd d 0.7v dd d 0.8v dd d v dd d 0.8 v dd b 0.8 v dd a 0.8 v dd c 0.8 v dd d 0.8 v dd d 0.8 v dd d 0.8 10.0 5.0 5.4 3.3 3.3 3.3 3.3 3.6 5.25 3.6 3.6 0.2v dd d 0.2v dd d 0.2v dd d 0.4 0.4 0.4 0.4 0.4 0.4 0.4 5.0 7.2 4.0 v v v v v v v v v v v v v v v v v v v v v v v v ma ma ma ma ma ma feed current where i oh = 1.2 ma pull-in current where i ol = 2.4ma feed current where i oh = 22.0ma pull-in current where i ol = 14.4ma feed current where i oh = 3.3ma pull-in current where i ol = 2.4ma feed current where i oh = 3.3ma pull-in current where i ol = 2.4ma feed current where i oh = 6.9ma pull-in current where i ol = 4.8ma feed current where i oh = 3.3ma pull-in current where i ol = 2.4ma feed current where i oh = 2.4ma pull-in current where i ol = 4.8ma v1a/b, v2, v3a/b, v4 = 8.25v v1a/b, v2, v3a/b, v4 = 0.25v v1a/b, v3a/b = 0.25v v1a/b, v3a/b = 14.75v sub = 8.25v sub = 14.75v supply voltage 1 supply voltage 2 supply voltage 3 supply voltage 4 input voltage 1 ? 1 input voltage 2 ? 2 input/output voltage output voltage 1 output voltage 2 output voltage 3 output voltage 4 output voltage 5 output voltage 6 output current 1 output current 2 item pins symbol conditions min. typ. max. unit ? 1 these input pins are schmitt trigger inputs, and have a protective diode on the power supply side in the ic. therefore, they do not support 5v input. ? 2 this input pin is with pull-down registor in the ic. note) the above table indicates the condition for 3.3v drive.
6 CXD3606R inverter i/o characteristics for oscillation (within the recommended operating conditions) item logical vth input voltage output voltage feedback resistor oscillation frequency pins osci osci osco osci, osco osci, osco symbol lvth v ih v il v oh v ol rfb f conditions feed current where i oh = 3.6ma pull-in current where i ol = 2.4ma v in = v dd d or v ss min. 0.7v dd d v dd d 0.8 500k 20 typ. v dd d/2 2m max. 0.3v dd d 0.4 5m 50 unit v v v v v ? mhz item logical vth input voltage input amplitude pins cki symbol lvth v ih v il v in conditions fmax 50mhz sine wave min. 0.7v dd d 0.3 typ. v dd d/2 max. 0.3v dd d unit v v v vp-p item rise time fall time output noise voltage symbol ttlm ttmh ttlh ttml tthm tthl vclh vcll vcmh vcml conditions vl to vm vm to vh vl to vh vm to vl vh to vm vh to vl min. 200 200 30 200 200 30 typ. 350 350 60 350 350 60 max. 500 500 90 500 500 90 1.0 1.0 1.0 1.0 unit ns ns ns ns ns ns v v v v inverter input characteristics for base oscillation clock duty adjustment (within the recommended operating conditions) note) input voltage is the input voltage characteristics for direct input from an external source. input amplitude is the input amplitude characteristics in the case of input through a capacitor. switching characteristics (vh = 15.0v, vm = gnd, vl = 7.5v) notes) 1) the mos structure of this ic has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. 2) for noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1f or more) between each power supply pin (vh, vl) and gnd. 3) to protect the ccd image sensor, clamp the sub pin output at vh before input to the ccd image sensor.
7 CXD3606R switching waveforms v1a (v1b, v3a, v3b) v2 (v4) sub ttmh tthm vh vm vl vm vl vh vl 90% 10% 90% 10% ttlm ttlm 90% 10% 90% 10% ttlh tthl 90% 90% 10% 10% ttml 90% 10% ttml 90% 10% waveform noise vcmh vcml vm vl vclh vcll
8 CXD3606R measurement circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 vd cki c6 c6 c6 c6 c6 c6 c6 c6 c6 c5 c5 c4 c3 CXD3606R serial interface data hd +3.3v 7.5v +15.0v c2 c2 c2 c2 c2 r1 r1 r1 r2 r1 r1 r1 c2 c2 c2 c2 c2 c2 c2 c2 c2 c1 c1 c1 c1 c1 c1 c2 c1 3300pf c2 560pf c3 820pf c4 8pf c5 215pf c6 10pf r1 30 ? r2 10 ?
9 CXD3606R ac characteristics ac characteristics between the serial interface clocks ssi 0.2v dd d 0.2v dd d 0.8v dd d ts2 th1 ts1 ts3 0.8v dd d 0.8v dd d sck sen sen 0.2v dd d symbol t s1 t h1 t s2 t s3 definition ssi setup time, activated by the rising edge of sck ssi hold time, activated by the rising edge of sck sck setup time, activated by the rising edge of sen sen setup time, activated by the rising edge of sck min. typ. max. 20 20 20 20 unit ns ns ns ns serial interface clock internal loading characteristics (1) (within the recommended operating conditions) th1 enlarged view example: during frame mode 0.2v dd d ts1 0.2v dd d v1a vd hd hd v1a sen 0.8v dd d symbol t s1 t h1 definition sen setup time, activated by the falling edge of hd sen hold time, activated by the falling edge of hd min. typ. max. 0 113 unit ns s ? be sure to maintain a constantly high sen logic level near the falling edge of the hd in the horizontal period during which v1a/b and v3a/b values take the ternary value and during that horizontal period. (within the recommended operating conditions)
10 CXD3606R serial interface clock output variation characteristics normally, the serial interface data is loaded to the CXD3606R at the timing shown in "serial interface clock internal loading characteristics (1)" above. however, one exception to this is when the data such as stb is loaded to the CXD3606R and controlled at the rising edge of sen. see "description of operation". 0.8v dd d sen output signal tpdpulse symbol tpdpulse definition output signal delay, activated by the rising edge of sen min. typ. max. 100 15 unit ns (within the recommended operating conditions) serial interface clock internal loading characteristics (2) th1 enlarged view 0.2v dd d ts1 0.2v dd d vd hd vd hd sen 0.8v dd d example: during frame mode symbol t s1 t h1 definition sen setup time, activated by the falling edge of vd sen hold time, activated by the falling edge of vd min. typ. max. 0 200 unit ns ns ? be sure to maintain a constantly high sen logic level near the falling edge of vd. (within the recommended operating conditions)
11 CXD3606R rst 0.2v dd d tw1 0.2v dd d vd hd ts1 th1 0.2v dd d 0.2v dd d 0.2v dd d rst loading characteristics symbol t w1 definition rst pulse width min. typ. max. 28 unit ns (within the recommended operating conditions) vd and hd phase characteristics symbol t s1 t h1 definition vd setup time, activated by the falling edge of hd vd hold time, activated by the falling edge of hd min. typ. max. 0 0 unit ns ns (within the recommended operating conditions) hd mcko ts1 th1 0.2v dd d 0.8v dd d 0.2v dd d hd loading characteristics symbol t s1 t h1 definition hd setup time, activated by the rising edge of mcko hd hold time, activated by the rising edge of mcko min. typ. max. 20 0 unit ns ns mcko load capacitance = 10pf (within the recommended operating conditions)
12 CXD3606R 0.8v dd d mcko wen, id/exp tpd1 wen and id/exp load capacitance = 10pf (within the recommended operating conditions) symbol tpd1 definition time until the above outputs change after the rise of mcko min. typ. max. 70 25 unit ns output variation characteristics
13 CXD3606R description of operation pulses output from the CXD3606R are controlled mainly by the rst pin and by the serial interface data. the pin status table is shown below, and the details of serial interface control are described on the following pages. pin status table ? 1 it is for output. for input, all items are act . note) act means that the circuit is operating, and dis means that loading is stopped. l indicates a low output level, and h a high output level in the controlled status. also, vh, vm and vl indicate the voltage levels applied to vh (pin 42), vm (pin 38) and vl (pin 45), respectively, in the controlled status. pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 v ss 1 rst sncsl id/exp wen ssgsl v dd 1 v dd 2 rg v ss 2 v ss 3 h1 h2 v dd 3 v dd 4 xshp xshd xrs pblk clpdm v ss 4 obclp adclk v ss 5 act act act act act act act act act act act act act act act act act l l act l l l l l l l l l l act act l l act l l l l l l l l l l l act l l act act act act act act act h h h act 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 cko cki osco osci v dd 5 mcko ssi sck sen vd ? 1 hd ? 1 v ss 6 test1 vm v2 v4 v1a vh v1b v3a vl v3b sub test2 act act act act act act act act act act act act act act act act act act act act act act act act act l l vm vm vh vh vh vh vh l act act act l act act act l l vm vm vh vh vh vh vh act act act act act dis dis dis h h vm vl vm vm vl vl vl symbol cam slp stb rst pin no. symbol cam slp stb rst
14 CXD3606R serial interface control the CXD3606R basically loads and reflects the serial interface data sent in the following format in the readout portion at the falling edge of hd. here, readout portion specifies the horizontal period during which v1a/b and v3a/b, etc. take the ternary value. note that some items reflect the serial interface data at the falling edge of vd or the rising edge of sen. ssi sck sen 00 01 02 03 04 05 06 07 41 42 43 44 45 46 47 these are two categories of serial interface data : the CXD3606R drive control data (hereafter control data ) and electronic shutter data (hereafter shutter data ). the details of each data are described below.
15 CXD3606R control data data d00 to d07 d08 d09 d10 to d12 d13 d14 d15 d16 to d31 d32 d33 d34 d35 d36 d37 d38 d39 d40 to d47 symbol chip ctg mode smd htsg ptsg fgob exp ptob ldad stb function chip enable category switching drive mode switching electronic shutter mode switching ? 1 htsg control switching ? 1 internal ssg function switching wide obclp generation switching ? 2 id/exp output switching obclp waveform pattern switching adclk logic phase adjustment standby control data = 0 data = 1 10000001 enabled other values disabled see d08 to d09 ctg. see d10 to d12 mode. off on off on ntsc pal off on id exp see d34 to d35 ptob. see d36 to d37 ldad. see d38 to d39 stb. rst all 0 all 0 all 0 0 0 0 all 0 0 0 all 0 1 0 all 0 all 0 ? 1 see d13 smd. ? 2 see d32 fgob.
16 CXD3606R shutter data data d00 to d07 d08 d09 d10 to d19 d20 to d31 d32 to d41 d42 to d47 symbol chip ctg svd shd spl function chip enable category switching electronic shutter vertical period specification electronic shutter horizontal period specification high-speed shutter position specification data = 0 data = 1 10000001 enabled other values disabled see d08 to d09 ctg. see d10 to d19 svd. see d20 to d31 shd. see d32 to d41 spl. rst all 0 all 0 all 0 all 0 all 0 all 0
17 CXD3606R detailed description of each data shared data: d08 to d09 ctg [category] of the data provided to the CXD3606R by the serial interface, the CXD3606R loads d10 and subsequent data to each data register as shown in the table below according to the combination of d08 and d09 . d09 0 0 1 d08 0 1 x description of operation loading to control data register loading to shutter data register test mode d11 0 0 1 1 0 1 d12 0 0 0 0 1 1 d10 0 1 0 1 x x description of operation draft mode (sextuple speed: default) frame mode (a field readout) frame mode (b field readout) frame mode af1 mode af2 mode note that the CXD3606R can apply these categories consecutively within the same vertical period. however, care should be taken as the data is overwritten if the same category is applied. control data: d10 to d12 mode [drive mode] the CXD3606R drive mode can be switched as follows. however, the drive mode bits are located to the CXD3606R and reflected at the falling edge of vd. control data: d15 ptsg [internal ssg output pattern] the CXD3606R internal ssg output pattern can be switched as follows. however, the internal ssg output pattern bits are loaded to the CXD3606R and reflected at the falling edge of vd. d15 0 1 description of operation ntsc equivalent pattern output pal equivalent pattern output vd period in each pattern is defined as follows. however, note that the hd period also changes according to the mode. see the timing charts for the actual operation. ntsc equivalent pattern pal equivalent pattern frame mode 885h + 810ck 884h + 1104ck draft mode 285h + 1455ck 2 342h + 2592ck af1 mode 142h + 1384ck + 1383ck 171h + 1296ck af2 mode 71h + 1384ck 85h + 1960ck
18 CXD3606R control data: d32 fgob [wide obclp generation] this controls wide obclp generation during the vertical opb period. see the timing charts for the actual operation. the default is "off". d32 0 1 description of operation wide obclp generation off wide obclp generation on control data: d34 to d35 ptob [obclp waveform pattern] this indicates the obclp waveform pattern. the default is "normal". d35 0 0 1 1 d34 0 1 0 1 waveform pattern (normal) (shifted rearward) (shifted forward) (wide) control data: d36 to d37 ldad [adclk logic phase] this indicates the adclk logic phase adjustment data. the default is "90 " relative to mcko. d37 0 0 1 1 d36 0 1 0 1 degree of adjustment ( ) 0 90 180 270 control data : d38 to d39 stb [standby] the operating mode is switched as follows. however, the standby bits are loaded to the CXD3606R and control is applied immediately at the rising edge of sen. d39 x 0 1 d38 0 1 1 symbol cam slp stb operating mode normal operating mode sleep mode standby mode see the pin status table for the pin status in each mode.
19 CXD3606R control data/shutter data: [electronic shutter] the CXD3606R realizes various electronic shutter functions by using control data d13 smd and d14 htsg and shutter data d10 to d19 svd, d20 to d31 shd and d32 to d41 spl. these functions are described in detail below. first, the various modes are shown below. these modes are switched using control data d13 smd. d13 0 1 description of operation electronic shutter stopped mode electronic shutter mode the electronic shutter data is expressed as shown in the table below using d20 to d31 shd as an example. however, msb (d31) is a reserve bit for the future specification, and it is handled as a dummy on this ic. msb lsb d29 d28 d31 d30 d27 d26 d25 d24 d23 d22 d21 d20 1100 c x001 1 0011 3 shd is expressed as 1c3h . [electronic shutter stopped mode] during this mode, all shutter data items are invalid. sub is not output in this mode, so the shutter speed is the accumulation time for one field. [high-speed/low-speed shutter mode] during this mode, the shutter data items have the following meanings. note) the bit data definition area is assured in terms of the CXD3606R functions, and does not assure the ccd characteristics. the period during which svd and shd are specified together is the shutter speed. an image of the exposure time calculation formula is shown below. in actual operation, the precise exposure time is calculated from the operating frequency, vd and hd periods, decoding value during the horizontal period, and other factors. (exposure time) = svd + {(number of hd per 1v) (shd + 1)} concretely, when specifying high-speed shutter, svd is set to "000h". (see the figure.) during low-speed shutter, or in other words when svd is set to "001h" or higher, the serial interface data is not loaded until this period is finished. the vertical period indicated here corresponds to one field in each drive mode. in addition, the number of horizontal periods applied to shd can be considered as (number of sub pulses 1). symbol svd shd spl data d10 to d19 d20 to d31 d32 to d41 description number of vertical periods specification (000h svd 3ffh) number of horizontal periods specification (000h shd 7ffh) vertical period specification for high-speed shutter operation (000h spl 3ffh)
20 CXD3606R vd shd 1 v1a sub wen smd 000h 002h svd 050h 10fh shd 1 svd exp exposure time vd spl 001 002 000 shd 1 v1a sub wen smd 000h 001h spl 000h 002h svd 0a3h 10fh shd exp exposure time 1 svd further, spl can be used during this mode to specify the sub output at the desired vertical period during the low-speed shutter period. in the case below, sub is output based on shd at the spl vertical period out of (svd + 1) vertical periods. incidentally, spl is counted as "000h", "001h", "002h" and so on in conformance with svd. at this time, even if spl > svd is set, operation conforms to the state when spl = svd. using this function it is possible to achieve smooth exposure time transitions when changing from low-speed shutter to high-speed shutter or vice versa.
21 CXD3606R vd v1a sub wen 0 1 0 htsg 1 0 1 smd vck exposure time exp [htsg control mode] this mode controls the v1a/b and v3a/b ternary level outputs (readout pulse block) using d14 htsg. when control is applied, v pulse modulation does not occur during the readout period, and only normal v transfer is performed. d14 0 1 description of operation readout pulse (sg) normal operation htsg control mode [exp pulse] the id/exp pin (pin 4) output can be switched between the id pulse or the exp pulse using d33 exp. the default is the "id" pulse. see the timing charts for the id pulse. the exp pulse indicates the exposure time when it is high. in draft mode, the transition point is midpoint value (1443ck) of the last sub pulse falling edge and each v1a/b and v3a/b ternary output falling edge. when there is no sub pulse, the later ternary output falling edge (1538ck) is used. in frame mode, the transition point is the last sub pulse falling edge, and each v1a/b and v3a/b ternary level output falling edge (1348ck). when there is no sub pulse, the v pulse modulation falling edge (1386ck) immediately after the ternary output is used. in addition, switching from the id pulse to the exp pulse is performed at the id reset timing (the id transition point during the horizontal period of each v1a/b and v3a/b ternary level output), and the exp pulse is reset low at this point. see the exp pulse indicated in the explanatory diagrams under [electronic shutter] for an image of operation.
22 CXD3606R chart-1 vertical direction timing chart mode frame mode applicable ccd image sensor icx412 vd sub obclp clpdm v1a c high-speed sweep block high-speed sweep block c v1b v2 v3a v3b v4 ccd out 1542 1544 1546 1548 1550 1543 1545 1547 1549 13 2468 4 2 6810 571357911 pblk wide obclp id/exp wen a field b field hd 1 1 886 877 877 886 a b 96 95 101 101 ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id/exp of this chart shows id. id is low for lines where ccd out contains the r component, and high for lines where ccd out con tains the b component. ? the high-speed sweep block is fixed to 1560 stages. ? vd of this chart is ntsc equivalent pattern (885h + 810ck units). for pal equivalent pattern, it is 884h + 1104ck units.
23 CXD3606R chart-2 vertical direction timing chart mode draft mode applicable ccd image sensor icx412 vd hd sub v1a v2 v3a v3b v4 wide obclp clpdm id/exp pblk v1b ccd out 10 3 6 15 22 27 8 1 4 13 20 25 30 28 3 6 10 15 22 27 1 4 8 132025 30 28 wen obclp 1534 1527 1532 1525 1546 1539 1544 1549 1537 1534 1527 1532 1525 1546 1539 1544 1549 1537 287 287 260 1 2 260 2 1 d d ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id/exp of this chart shows id. id is low for lines where ccd out contains the r component, and high for lines where ccd out con tains the b component. ? vd of this chart is ntsc equivalent pattern (285h + 1455ck + 1455ck units). for pal equivalent pattern, it is 342h + 2592ck uni ts.
24 CXD3606R chart-3 vertical direction timing chart mode af1 mode applicable ccd image sensor icx412 vd sub obclp clpdm v1a frame shift block frame shift block v1b v2 v3a v3b v4 ccd out pblk id/exp wen hd 6 4 6 4 d e e ed e 144 144 wide obclp 1119 1114 1117 1112 430 423 428 421 442 435 440 433 430 423 428 421 442 435 440 433 1119 1114 1117 1112 131 2 14 131 2 14 high-speed sweep block high-speed sweep block ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id/exp of this chart shows id. id is low for lines where ccd out contains the r component, and high for lines where ccd out con tains the b component. ? 75 stages are fixed for high-speed sweep block; 68 stages are fixed for frame shift block. ? vd of this chart is ntsc equivalent pattern (142h + 1384ck + 1383ck units). for pal equivalent pattern it is 171h + 1296ck unit s, and the high-speed sweep block starts from 159h.
25 CXD3606R chart-4 vertical direction timing chart mode af2 mode applicable ccd image sensor icx412 vd sub obclp clpdm v1a v1b v2 v3a v3b v4 ccd out pblk id/exp wen hd 6 4 6 4 d e e ed e 72 72 867 862 865 860 682 675 680 673 694 687 692 685 682 675 680 673 694 687 692 685 867 862 865 860 54 2 21 54 2 21 frame shift block frame shift block wide obclp high-speed sweep block high-speed sweep block ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id/exp of this chart shows id. id is low for lines where ccd out contains the r component, and high for lines where ccd out con tains the b component. ? 116 stages are fixed for high-speed sweep block; 110 stages are fixed for frame shift block. ? vd of this chart is ntsc equivalent pattern (71h + 1384ck units). for pal equivalent pattern, it is 85h + 1960ck units, and t he high-speed sweep block starts from 68h. however, in this case the frame rate for ntsc equivalent pattern is 0.5ck longer than for 1/120s.
26 CXD3606R chart-5 horizontal direction timing chart mode frame mode applicable ccd image sensor icx412 hd mcko h1 h2 v1a/b v2 v3a/b v4 sub pblk obclp (1) obclp (2) obclp (3) obclp (4) obclp (wide) clpdm (2544) 0 50 100 200 150 250 300 350 400 450 500 550 id/exp wen 428 456/460/464 52 4 276 162 42 16 34 8 50 8 458 50 50 24 454 430 352 238 314 124 454 52 390 200 120 52 124 124 ? the hd of this chart indicates the actual CXD3606R load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.3 to 19.0s (when the drive frequency is 22.5mhz). this chart shows a pe riod of 124ck (5.5s). internal ssg is at this timing. ? sub is output at the timing shown above when output is controlled by the serial interface data. ? id/exp of this chart shows id. id/exp and wen are output at the timing shown above at the position shown in chart-1. ? obclp (wide) is output at the above timing at the position indicated in chart-1.
27 CXD3606R chart-6 horizontal direction timing chart mode draft mode, af1 mode, af2 mode applicable ccd image sensor icx412 hd mcko h1 h2 v1a/b v2 v3a/b v4 sub pblk obclp (1) obclp (2) obclp (3) obclp (4) obclp (wide) clpdm (2624) 0 50 100 200 150 250 300 350 400 450 500 550 id/exp wen 508 536/540/544 52 4 140 42 16 34 8 50 8 538 50 50 24 534 510 172 204 534 52 156 120 52 124 124 268 188 300 220 252 124 284 236 396 316 348 380 332 412 364 444 476 460 492 428 ? the hd of this chart indicates the actual CXD3606R load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.3 to 19.0s (when the drive frequency is 22.5mhz). this chart shows a peri od of 124ck (5.5s). internal ssg is at this timing. ? sub is output at the timing shown above when output is controlled by the serial interface data. ? id/exp of this chart shows id. id/exp and wen are output at the timing shown above at the position shown in chart-2,3 and 4. ? obclp (wide) is output at the above timing at the position indicated in chart-2,3 and 4.
28 CXD3606R chart-7 horizontal direction timing chart (high-speed sweep: c) mode frame mode applicable ccd image sensor icx412 hd mcko h1 h2 v1a/b v2 v3a/b v4 sub pblk obclp clpdm (2544) 0 50 100 200 150 250 300 350 400 450 500 550 id/exp wen 428 456/460/464 52 4 120 52 52 128 204 280 432 356 508 166 242 318 394 470 546 90 128 204 280 356 432 508 52 90 166 242 318 394 470 546 #4 #2 #3 #1 ? the hd of this chart indicates the actual CXD3606R load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.3 to 19.0s (when the drive frequency is 22.5mhz). this chart shows a peri od of 124ck (5.5s). internal ssg is at this timing. ? sub is output at the timing shown above when output is controlled by the serial interface data. ? id/exp of this chart shows id. ? high-speed sweep of v1a/b, v2, v3a/b, v4 is performed up to 98h 580ck (#1560).
29 CXD3606R chart-8 horizontal direction timing chart (frame shift, high-speed sweep: e) mode af1 mode, af2 mode applicable ccd image sensor icx412 hd mcko h1 h2 v1a/b v2 v3a/b v4 sub pblk obclp clpdm (2624) 0 50 100 200 150 250 300 350 400 450 500 550 id/exp wen 508 536/540/544 52 4 120 52 52 52 42 16 124 132 180 260 308 388 436 516 148 228 276 356 404 484 532 100 116 196 244 324 372 452 500 68 84 164 242 292 340 420 468 548 #2 #1 ? the hd of this chart indicates the actual CXD3606R load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.3 to 19.0s (when the drive frequency is 22.5mhz). this chart shows a peri od of 124ck (5.5s). internal ssg is at this timing. ? sub is output at the timing shown above when output is controlled by the serial interface data. ? id/exp of this chart shows id. pblk, obclp, id/exp and wen are output at the timing shown above at the position shown in chart- 3 and 4. ? frame shift of v1a/b, v2, v3a/b and v4 is performed up to 11h 2548ck (#68) in af1 mode and 18h 308ck (#110) in af2 mode. in addition, high-speed sweep is performed up to 141h 2612ck (#75) in af1 mode and 70h 2612ck (#116) in af2 mode.
30 CXD3606R chart-9 horizontal direction timing chart mode frame mode applicable ccd image sensor icx412 hd [a field] [b field] a b v3b v4 v3b v4 v1a v1b v2 v3a v1a v1b v2 v3a (2544) 0 (2544) 0 1196 1234 1272 1310 1348 1386 124 162 200 238 276 314 352 390 ? the hd of this chart indicates the actual CXD3606R load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.3 to 19.0s (when the drive frequency is 22.5mhz). this chart shows a peri od of 124ck (5.5s). internal ssg is at this timing.
31 CXD3606R chart-10 horizontal direction timing chart mode draft mode, af1 mode, af2 mode applicable ccd image sensor icx412 hd d v3b v4 v1a v1b v2 v3a (2624) 0 (2544) 0 1158 1196 1234 1272 1310 1348 1386 1424 1462 1500 1538 1576 124 156 188 220 252 284 316 348 380 412 444 476 140 172 204 236 268 300 332 364 396 428 460 492 1592 1608 1640 1672 1624 1656 1688 ? the hd of this chart indicates the actual CXD3606R load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.3 to 19.0s (when the drive frequency is 22.5mhz). this chart shows a peri od of 124ck (5.5s). internal ssg is at this timing.
32 CXD3606R chart-11 high-speed phase timing chart mode applicable ccd image sensor icx412 hd hd' cki cko adclk mcko h1 h2 rg xshp xshd xrs 428/508 52 1 ? hd' of this chart indicates the hd which is the actual CXD3606R load timing. ? the phase relationship of each pulse shows the logical position relationship. for the actual output waveform, a delay is added to each pulse. ? the logical phase of adclk can be specified by the serial interface data.
33 CXD3606R chart-12 vertical direction sequence chart mode draft frame draft applicable ccd image sensor icx412 vd v1a v1b v2 v3a v3b v4 sub mechanical shutter exposure time ccd out mode smd shd close open a b c e e f 00000 3 00 11111 0 11 050h 050h 050h 050h 050h 000h 3 0 000h 050h 050h a b c d e f ? this chart is a drive timing chart example of electronic shutter normal operation. ? data exposed at d includes the blooming component. for details, see the ccd image sensor data sheet. ? the CXD3606R does not generate the pulse to control mechanical shutter operation. ? the switching timing of drive mode and electronic shutter data is not the same.
34 CXD3606R application circuit block diagram 26 27 37 48 31 32 34 35 30 25 23 22 20 19 18 17 16 mcko vd hd cko digital out adclk obclp clpdm pblk xrs xshd xshp sck 33 sen ssi test2 test1 osco cki 28 osci ccd out v-dr ssg 6 3 2 5 4 ssgsl sncsl rst wen id/exp 12 13 9 rg h2 h1 41 43 39 v2 v1b v1a 44 46 40 v4 47 sub v3b v3a ccd icx412 cds/adc block tg CXD3606R controller signal processor block notes for power-on of the three 7.5v, +15.0v, +3.3v power supplies, be sure to start up the 7.5v and +15.0v power supplies in the following order to prevent the sub pin of the ccd image sensor from going to negative potential. t1 t2 15.0v 0v 7.5v 20% 20% t2 t1 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
35 CXD3606R package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin copper alloy package structure 48pin lqfp (plastic) 9.0 0.2 ? 7.0 0.1 1 12 13 24 25 36 37 48 (0.22) 0.18 0.03 + 0.08 0.2g lqfp-48p-l01 p-lqfp48-7x7-0.5 (8.0) 0.5 0.2 0.127 0.02 + 0.05 a 1.5 0.1 + 0.2 0.1 palladium plating note: dimension ? does not include mold protrusion. 0.1 0.1 0.5 0.2 0 to 10 detail a 0.13 m 0.5 s s b detail b : palladium 0.127 0.04 0.18 0.03 sony corporation

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