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preliminary technical data blackfin and the blackfi n logo are registered tradem arks of analog devices, inc. blackfin dual core embedded processor adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 rev. prd information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2012 analog devices, inc. all rights reserved. features dual-core symmetric high-performance blackfin processor, up to 500 mhz per core each core contains two 16-bit macs, two 40-bit alus, and a 40-bit barrel shifter risc-like register and instruction model for ease of programming and comp iler-friendly support advanced debug, trace, an d performance monitoring pipelined vision processor prov ides hardware to process sig- nal and image algorithms used for pre- and co-processing of video frames in adas or other video processing applications accepts a range of supply voltages for i/o operation. see operating conditions on page 31 off-chip voltage regulator interface 349-ball (19 mm 19 mm) rohs compliant bga package memory each core contains 148k bytes of l1 sram memory (proces- sor core-accessible) with multi-parity bit protection up to 256k bytes of l2 sram memory with ecc protection dynamic memory controller prov ides 16-bit interface to a single bank of ddr2 or lpddr dram devices static memory controller with asynchronous memory inter- face that supports 8-bit and 16-bit memories flexible booting options from flash, emmc and spi memories and from spi, link port and uart hosts memory management unit provides memory protection figure 1. processor block diagram system control blocks peripherals hardware functions external bus interfaces lpddr ddr2 crc pipelined vision processor pixel compositor dma system 3 ppi 4 link port 2 emac with 2 ieee 1588 emmc/rsi 3 sport 2 spi 2 uart 1 can 8 timer 2 pwm 1 counter 2 twi usb 2.0 hs otg l2 memory 256k byte ecc- protected sram 32k byte rom 112 gp i/o flash sram emulator test & control pll & power management fault management event control dual watchdog core 1 148k byte parity bit protected l1 sram instruction/data b 1 acm 16 16 dynamic memory controller static memory controller video subsystem core 0 148k byte parity bit protected l1 sram instruction/data b
rev. prd | page 2 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 preliminary technical data table of contents features ................................................................. 1 memory ................................................................ 1 general description ................................................. 3 blackfin processor core .......................................... 3 instruction set description ..................................... 4 processor infrastructure ......................................... 5 memory architecture ............................................ 6 video subsystem .................................................. 9 processor safety features ...................................... 10 additional processor peripherals ............................ 11 power and clock management ............................... 14 system debug .................................................... 17 ez-kit lite? evaluation board .............................. 17 designing an emul ator-compatible processor board (target) ................................... 17 related documents ............................................. 18 related signal chains ........................................... 18 signal descriptions ................................................. 19 pin multiplexing ................................................. 20 pin termination and drive characteristics-requirements 24 specifications ........................................................ 31 operating conditions ........................................... 31 electrical characteristics ....................................... 33 processor absolute maximum ratings .................. 34 esd sensitivity ................................................... 34 processor package information ........................... 34 environmental conditions .................................... 35 349-ball csp_bga ball assignments . ......................... 36 outline dimensions ................................................ 42 surface-mount design .......................................... 42 automotive products .............................................. 43 pre release products ............................................... 43 revision history 3/12revision prd : initial public version
preliminary technical data rev. prd | page 3 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 general description the ADSP-BF609 processor is a member of the blackfin family of products, incorporat ing the analog devices/intel micro signal architecture (msa). blackfin processors combine a dual-mac state-of-the-art signal processing engine, the advantages of a clean, orthog onal risc-like microprocessor instruction set, and single-ins truction, multiple-data (simd) multimedia capabili ties into a single instruction-set architecture. the processor offers performance up to 500 mhz, as well as low static power consumpt ion. produced with a low-power and low- voltage design methodology, th ey provide world-class power management and performance. by integrating a rich set of indu stry-leading system peripherals and memory (shown in table 1 ), blackfin processors are the platform of choice for next-gener ation applications that require risc-like programmability, multimedia support, and leading- edge signal processing in one in tegrated package. these applica- tions span a wide arra y of markets, from au tomotive systems to embedded industrial, instrumentation and power/motor con- trol applications. blackfin processor core as shown in figure 1 , the processor integrates two blackfin pro- cessor cores. each core, shown in figure 2 , contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit alus, four video alus, and a 40-bit shifter. the computation units process 8-, 16-, or 32-bit data from the register file. the compute register file contai ns eight 32-bit registers. when performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. all operands for compute operations come from the multiported register file and instruction constant fields. each mac can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. signed and unsigned formats, rounding, and saturation are supported. the alus perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. in addition, many special instructions are included to acce lerate various signal processing tasks. these include bit operations such as field extract and pop- ulation count, modulo 2 32 multiply, divide primitives, saturation and rounding, and sign/exponent detection. the set of video instructions include byte alignment and packing operations, 16-bit and 8-bit adds with cli pping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (saa) operations. also provided are the compar e/select and vector search instructions. for certain instructions, two 16-bit alu operations can be per- formed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a co mpute register). if the second alu is used, quad 16-bit operations are possible. table 1. processor comparison processor feature adsp-bf606 adsp-bf607 adsp-bf608 ADSP-BF609 up/down/rotary counters 1 timer/counters with pwm 8 3-phase pwm units (4-pair) 2 sports 3 spis 2 usb otg 1 parallel peripheral interface 3 removable storage interface 1 can 1 twi 2 uart 2 adc control module (acm) 1 link ports 4 ethernet mac (ieee 1588) 2 pixel compositor (pixc) no 1 1 pipelined vision processor (pvp) 1 no vga hd gpios 112 memory (bytes, per core) l1 instruction sram 64k l1 instruction sram/cache 16k l1 data sram 32k l1 data sram/cache 32k l1 scratchpad 4k l2 data sram 128k 256k l2 boot rom 32k maximum speed grade (mhz) 2 400 500 maximum sysclk (mhz) 250 package options 349-ball csp_bga 1 vga is 640 x 480 pixels per frame, 30 frames per second. hd is 1280 x 960 pixels per frame, 30 frames per second. 2 maximum speed grade is not available with every possible sysclk selection. table 1. processor comparison (continued) processor feature adsp-bf606 adsp-bf607 adsp-bf608 ADSP-BF609
rev. prd | page 4 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 preliminary technical data the 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. the program sequencer controls the flow of instruction execu- tion, including instruction alignment and decoding. for program flow control, the sequ encer supports pc relative and indirect conditional jumps (with static branch prediction), and subroutine calls. hardware supports zero-overhead looping. the architecture is fully interlocked, meaning that the program- mer need not manage the pipeline when executing instructions with data dependencies. the address arithmetic unit prov ides two addresses for simulta- neous dual fetches from memory. it contains a multiported register file consisti ng of four sets of 32-bit index, modify, length, and base registers (for circular buffering), and eight additional 32-bit pointer regist ers (for c-style indexed stack manipulation). blackfin processors support a modified harvard architecture in combination with a hierarchical memory structure. level 1 (l1) memories are those that typically operate at the full processor speed with little or no latency. at the l1 level, the instruction memory holds instructions only. the data memory holds data, and a dedicated scratchpad data memory stores stack and local variable information. in addition, multiple l1 memory blocks are provided, offering a configurable mix of sram an d cache. the memory manage- ment unit (mmu) provides memory protection for individual tasks that may be oper ating on the core and can protect system registers from unintended access. the architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. user mode has restricted access to certain syst em resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources. instruction set description the blackfin processor instruct ion set has been optimized so that 16-bit opcodes represent the most frequently used instruc- tions, resulting in excellent co mpiled code density. complex dsp instructions are encoded into 32-bit opcodes, representing fully featured multifunction inst ructions. blackfin processors support a limited multi-issue ca pability, where a 32-bit instruc- tion can be issued in parallel with two 16-bit instructions, allowing the programmer to use ma ny of the core resources in a single instruction cycle. the blackfin processor family a ssembly language instruction set employs an algebraic syntax designed for ease of coding and readability. the instructions have been specifically tuned to pro- vide a flexible, densely encoded instruction set that compiles to figure 2. blackfin processor core sequencer align decode loop buffer 16 16 8 888 40 40 a0 a1 barrel shifter data arithmetic unit control unit r7.h r6.h r5.h r4.h r3.h r2.h r1.h r0.h r7.l r6.l r5.l r4.l r3.l r2.l r1.l r0.l astat 40 40 32 32 32 32 32 32 32 ld0 ld1 sd dag0 dag1 address arithmetic unit i3 i2 i1 i0 l3 l2 l1 l0 b3 b2 b1 b0 m3 m2 m1 m0 sp fp p5 p4 p3 p2 p1 p0 da1 da0 32 32 32 preg rab 32 to memory
preliminary technical data rev. prd | page 5 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 a very small final memory size. th e instruction set also provides fully featured multifunction instructions that allow the pro- grammer to use many of the proce ssor core resources in a single instruction. coupled with many features more often seen on microcontrollers, this instruction set is very efficient when com- piling c and c++ source code. in addition, the architecture supports both user (algorithm/app lication code) and supervisor (o/s kernel, device drivers, debuggers, isrs) modes of opera- tion, allowing multiple levels of access to core processor resources. the assembly language, which takes advantage of the proces- sors unique architecture, offe rs the following advantages: ? seamlessly integrated dsp/mcu features are optimized for both 8-bit and 16-bit operations. ? a multi-issue load/store modified-harvard architecture, which supports two 16-bit mac or four 8-bit alu + two load/store + two pointer updates per cycle. ? all registers, i/o, and memory are mapped into a unified 4g byte memory space, providing a simplified program- ming model. ? control of all asynchronous and synchronous events to the processor is handled by two subsystems: the core event controller (cec) and the syst em event controller (sec). ? microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and ex traction; integer operations on 8-, 16-, and 32-bit data-typ es; and separate user and supervisor stack pointers. ? code density enhancements, wh ich include intermixing of 16-bit and 32-bit instructions (n o mode switching, no code segregation). frequently used instructions are encoded in 16 bits. processor infrastructure the following sections provide information on the primary infrastructure components of the ADSP-BF609 processor. dma controllers the processor uses direct memo ry access (dma) to transfer data within memory spaces or between a memory space and a peripheral. the processor can spec ify data transfer operations and return to normal processing while the fully integrated dma controller carries out the data transfers independent of proces- sor activity. dma transfers can occur between memory and a peripheral or between one memory and another memory. two channels are used for memory-to-memory dm a where one channel is the source channel, and the second is the destination channel. all dmas can transport data to and from all on-chip and off- chip memories. programs can use two types of dma transfers, descriptor-based or register-bas ed. register-based dma allows the processor to directly progra m dma control registers to ini- tiate a dma transfer. on comple tion, the control registers may be automatically updated with their original setup values for continuous transfer. descriptor -based dma transfers require a set of parameters stored with in memory to initiate a dma sequence. descriptor-based dm a transfers allow multiple dma sequences to be chained together and a dma channel can be programmed to automatically set up and start another dma transfer after the curr ent sequence completes. the dma controller supports th e following dma operations. ? a single linear buffer th at stops on completion. ? a linear buffer with negative, positive or zero stride length. ? a circular, auto-refreshing buffer that interrupts when each buffer becomes full. ? a similar buffer that interrupts on fractional buffers (for example, 1/2, 1/4). ? 1d dma C uses a set of identical ping-pong buffers defined by a linked ring of two-word descriptor sets, each contain- ing a link pointer and an address. ? 1d dma C uses a linked list of 4 word descriptor sets con- taining a link pointer, an address, a length, and a configuration. ? 2d dma C uses an array of on e-word descriptor sets, spec- ifying only the base dma address. ? 2d dma C uses a linked list of multi-word descriptor sets, specifying everything. crc protection the two crc protection modules a llow system software to peri- odically calculate the signature of code and/or data in memory, the content of memory-mapped registers, or communication message objects. dedicated hard ware circuitry compares the signature with pre calculated values and triggers appropriate fault events. for example, every 100 ms the sy stem software might initiate the signature calculation of th e entire memory contents and compare these contents with expected, pre calculated values. if a mismatch occurs, a fault condit ion can be generated (via the processor core or the trigger routing unit). the crc is a hardware module based on a crc32 engine that computes the crc value of the 32-bit data words presented to it. data is provided by the source channel of the memory-to- memory dma (in memory scan mode) and is optionally for- warded to the destination chan nel (memory transfer mode). the main features of the crc peripheral are: ?memory scan mode ?memory transfer mode ?data verify mode ? data fill mode ? user-programmable crc32 polynomial ? bit/byte mirroring option (endianness) ? fault/error interrupt mechanisms ? 1d and 2d fill block to initialize array with constants. ? 32-bit crc signature of a block of a memory or mmr block.
rev. prd | page 6 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 preliminary technical data event handling the processor provides event handling that supports both nest- ing and prioritization. nesting allows multiple event service routines to be active simultaneo usly. prioritization ensures that servicing of a higher-priority event takes precedence over ser- vicing of a lower-priority event. the processor provides support for five different types of events: ? emulation C an emulation ev ent causes the processor to enter emulation mode, allowing command and control of the processor via the jtag interface. ? reset C this event resets the processor. ? nonmaskable interrupt (nmi ) C the nmi event can be generated either by the software watchdog timer, by the nmi input signal to the proce ssor, or by software. the nmi event is frequently used as a power-down indicator to initiate an orderly sh utdown of the system. ? exceptions C events that occur synchronously to program flow (in other words, the exception is taken before the instruction is allowed to complete). conditions such as data alignment violations and undefined instructions cause exceptions. ? interrupts C events that occur asynchronously to program flow. they are caused by inpu t signals, timers, and other peripherals, as well as by an explicit software instruction. core event controller (cec) the cec supports nine general-purpose interrupts (ivg15C7), in addition to the dedicated interrupt and exception events. of these general-purpose interrupts, the two lowest-priority interrupts (ivg15C14) are recomm ended to be reserved for software interrupt handlers. fo r more information, see the adsp-bf60x processor pr ogrammers reference . system event controller (sec) the sec manages the en abling, prioritization, and routing of events from each system interrup t or fault source. additionally, it provides notification and identi fication of the highest priority active system interrupt request to each core and routes system fault sources to its integrated fault management unit. trigger routing unit (tru) the tru provides system-level sequence control without core intervention. the tru maps trigge r masters (generators of trig- gers) to trigger slaves (receivers of triggers). slave endpoints can be configured to respond to tr iggers in various ways. common applications enabled by the tru include: ? automatically triggering the start of a dma sequence after a sequence from another dma channel completes ?software triggering ? synchronization of concurrent activities pin interrupts every port pin on the processor ca n request interrupts in either an edge-sensitive or a level-se nsitive manner with programma- ble polarity. interrupt functionality is decoupled from gpio operation. six system-level in terrupt channels (pint0C5) are reserved for this purpose. each of these interrupt channels can manage up to 32 interrupt pins. the assignment from pin to interrupt is not performed on a pi n-by-pin basis. rather, groups of eight pins (half ports) can be flexibly assigned to interrupt channels. every pin interrupt channel features a special set of 32-bit mem- ory-mapped registers that enab le half-port assignment and interrupt management. this includes masking, identification, and clearing of requests. these re gisters also enable access to the respective pin states and use of the interrupt latches, regardless of whether the interrupt is masked or not. most control registers feature multiple mmr address en tries to write-one-to-set or write-one-to-clear them individually. general-purpose i/o (gpio) each general-purpose port pin ca n be individually controlled by manipulation of the port control, status, and interrupt registers: ? gpio direction control register C specifies the direction of each individual gpio pin as input or output. ? gpio control and status regi sters C a write one to mod- ify mechanism allows any combination of individual gpio pins to be modified in a single instruction, without affecting the level of any other gpio pins. ? gpio interrupt mask register s C allow each individual gpio pin to function as an interrupt to the processor. gpio pins defined as inputs can be configured to generate hardware interrupts, while output pins can be triggered by software interrupts. ? gpio interrupt sensitivity registers C specify whether indi- vidual pins are level- or edge-sensitive and specifyif edge-sensitivewhether just the rising edge or both the ris- ing and falling edges of th e signal are significant. pin multiplexing the processor supports a flexible multiplexing scheme that mul- tiplexes the gpio pins with various peripherals. a maximum of 4 peripherals plus gpio function ality is shared by each gpio pin. all gpio pins ha ve a bypass path feature C that is, when the output enable and the input enable of a gpio pin are both active, the data signal before the pad driver is looped back to the receive path for the same gpio pin. for more information, see pin multiplexing on page 20. memory architecture the ADSP-BF609 processor views memory as a single unified 4g byte address space, using 32- bit addresses. all resources, including internal memory, external memory, and i/o control registers, occupy separate sect ions of this common address space. the memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low- latency core-accessible memory as cache or sram, and larger, lower-cost and performance interface-accessible me mory systems. see figure 3 and figure 4 .
preliminary technical data rev. prd | page 7 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 figure 3. adsp-bf606 internal/external memory map
rev. prd | page 8 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 preliminary technical data figure 4. adsp-bf607/adsp-bf608/ADSP-BF609 internal/external memory map
preliminary technical data rev. prd | page 9 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 internal (core-accessible) memory the l1 memory system is th e highest-performance memory available to the blackf in processor cores. each core has its own private l1 memory. the modified har- vard architecture supports two concurrent 32-bit data accesses along with an instruction fetc h at full processor speed which provides high bandwidth proce ssor performance. two separate 64k-byte of data memory bloc ks partner with an 80k-byte memory block for instruction st orage. each block is multi- banked for efficient data exchange through dma and can be configured as sram. alternativel y, 16k bytes of each block can be configured in l1 cache mode . the four-way set-associative instruction cache and the 2 two-wa y set-associative data caches greatly accelerate memory access performance, especially when accessing external memories. the l1 memory domain also fe atures a 4k-byte scratchpad sram block which is ideal for storing local va riables and the software stack. all l1 memory is protected by a multi-parity bit concept, regardless of whether the memory is operating in sram or cache mode. outside of the l1 domain, l2 and l3 memories are arranged using a von neumann topology. the l2 memory domain is a unified instruction and data memory and can hold any mixture of code and data required by the system design. the l2 memory domain is accessible by both blackfin cores through a dedicated 64-bit interface. it operates at half the frequency of the cores. the processor features up to 256k bytes of l2 sram which is ecc-protected and organized in eight banks. individual banks can be made private to any of the cores or the dma subsystem. there is also a 32k-byte single-bank rom in the l2 domain. it contains boot code and safety functions. static memory controller (smc) the smc can be programmed to control up to four banks of external memories or memory-ma pped devices, with very flexi- ble timing parameters. each bank occupies a 64m byte segment regardless of the size of the devi ce used, so that these banks are only contiguous if each is fu lly populated with 64m bytes of memory. dynamic memory controller (dmc) the dmc includes a controller that supports jesd79-2e com- patible double data rate ( ddr2) sdram and jesd209a low power ddr (lpddr) sdram devices. i/o memory space the processor does not define a separate i/o space. all resources are mapped through the fl at 32-bit address space. on- chip i/o devices have their cont rol registers mapped into mem- ory-mapped registers (mmrs) at addresses near the top of the 4g byte address space. these are separated into two smaller blocks, one which contains the control mmrs for all core func- tions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. the mmrs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals. booting the processor has several mechan isms for automatically loading internal and external memory after a reset. the boot mode is defined by the sys_bmode input pins dedicated for this pur- pose. there are two categories of boot modes. in master boot modes, the processor actively load s data from parallel or serial memories. in slave boot modes, the processor receives data from external host devices. the boot modes are shown in table 2 . these modes are imple- mented by the sys_bmode bits of the reset configuration register and are sampled during power-on resets and software- initiated resets. video subsystem the following sections describe the components of the proces- sors video subsystem. these blocks are shown with blue shading in figure 1 on page 1 . video interconnect (vid) the video interconnect provides a connectivity matrix that interconnects the video subsystem: three ppis, the pixc, and the pvp. the interconnect uses a protocol to manage data transfer among these video peripherals. pipelined vision processor (pvp) the pvp engine provides hardwa re implementation of signal and image processing algorithms that are required for co-processing and pre-processing of monochrome video frames in adas applications, robotic systems, and other machine applications. the pvp works in conjunction with the blackfin cores. it is optimized for convolution and wavelet based object detection and classification, and tracking and verification algorithms. the pvp has the following processing blocks. ? four 5x5 16-bit convolution bl ocks optionally followed by down scaling ? a 16-bit cartesian-to-polar coordinate conversion block ? a pixel edge classifier that supports 1st and 2nd derivative modes ? an arithmetic unit with 32-bit addition, multiply and divide table 2. boot modes sys_bmode setting boot mode 000 no boot/idle 001 memory 010 rsi0 master 011 spi0 master 100 spi0 slave 101 reserved 110 lp0 slave 111 uart0 slave
rev. prd | page 10 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 preliminary technical data ? a 32-bit threshold block with 16 thresholds, a histogram, and run-length encoding ? two 32-bit integral blocks that support regular and diago- nal integrals ? an up- and down-scaling unit with independent scaling ratios for horizontal and vertical components ? input and output formatters for compatibility with many data formats, including bayer input format the pvp can form a pipe of all the constituent algorithmic modules and is dynamically reconfigurable to form different pipeline structures. the pvp supports the simultaneous processing of up to four data streams. the me mory pipe stream operates on data received by dma from any l1, l2, or l3 memory. the three camera pipe streams operate on a common input received directly from any of the three ppi inputs. optionally, the pixc can convert color data received by the ppi and forward luma values to the pvps monochrome engine. each stream has a dedicated dma output. this pr eprocessing concept ensures careful use of available power and bandwidth budgets and frees up the processor cores for other tasks. the pvp provides for direct core mmr access to all control/sta- tus registers. two hardware inte rrupts interface to the system event controller. for optimal perf ormance, the pvp allows reg- ister programming through its control dma interface, as well as outputting selected status re gisters through the status dma interface. this mechanism enables the pvp to automatically process job lists completely inde pendent of the blackfin cores. pixel compositor (pixc) the pixel compositor (pixc) provides image overlays with transparent-color support, alpha blending, and color space con- version capabilities for output to tft lcds and ntsc/pal video encoders. it provides all of the control to allow two data streams from two separate da ta buffers to be combined, blended, and converted into appropriate forms for both lcd panels and digital video outputs. the main image buffer pro- vides the basic backgr ound image, which is presented in the data stream. the over lay image buffer allows the user to add multiple foreground text, graphi cs, or video objects on top of the main image or video data stream. parallel peripheral interface (ppi) the processor provides up to thre e parallel peripheral interfaces (ppis), supporting data widths up to 24 bits. the ppi supports direct connection to tft lcd pa nels, parallel analog-to-digital and digital-to-analog converters, video encoders and decoders, image sensor modules and othe r general-purpose peripherals. the following features are supported in the ppi module: ? programmable data length: 8 bits, 10 bits, 12 bits, 14 bits, 16 bits, 18 bits, and 24 bits per clock. ? various framed, non-framed, and general-purpose operat- ing modes. frame syncs can be generated internally or can be supplied by an external device. ? itu-656 status word error de tection and correction for itu-656 receive modes and it u-656 preamble and status word decode. ? optional packing and unpackin g of data to/from 32 bits from/to 8 bits, 16 bits and 24 bi ts. if packing/unpacking is enabled, endianness can be configured to change the order of packing/unpackin g of bytes/words. ? rgb888 can be converted to rgb666 or rgb565 for trans- mit modes. ?various de-interleaving/inte rleaving modes for receiv- ing/transmitting 4:2:2 ycrcb data. ?configurable lcd data enable (den) output available on frame sync 3. processor safety features the ADSP-BF609 processor has b een designed for functional safety applications. while the level of safety is mainly domi- nated by the system concept, the following primitives are provided by the devices to bu ild a robust safety concept. dual core supervision the processor has been implemented as dual-core devices to separate critical task s to large independency. software models support mutual supervision of th e cores in symmetrical fashion. multi-parity-bit-protected l1 memories in the processors l1 memory sp ace, whether sram or cache, each word is protected by multiple parity bits to detect the single event upsets that occur in all rams. this applies both to l1 instruction and data memory spaces. ecc-protected l2 memories error correcting codes (ecc) are used to correct single event upsets. the l2 memory is protected with a single error correct- double error detect (sec-ded ) code. by default ecc is enabled, but it can be disabled on a per-bank basis. single-bit errors are transparently corrected. dual-bit errors can issue a system event or fault if enabled. ecc protection is fully trans- parent to the user, even if l2 memory is read or written by 8-bit or 16-bit entities. crc-protected memories while parity bit and ecc protecti on mainly protect against ran- dom soft errors in l1 and l2 memory cells, the crc engines can be used to protect against system atic errors (pointer errors) and static content (instruction code ) of l1, l2 and even l3 memo- ries (ddr2, lpddr). the processors feature two crc engines which are embedded in the me mory-to-memory dma control- lers. crc check sums can be calc ulated or compared on the fly during memory transfers, or one or multiple memory regions can be continuously scrubbed by single dma work unit as per dma descriptor chain instructio ns. the crc engine also pro- tects data loaded during the boot process.
preliminary technical data rev. prd | page 11 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 memory protection the blackfin cores feature a memo ry protection concept, which grants data and/or instruction accesses from enabled memory regions only. a supervisor mode vs. user mode programming model supports dynamically varying access rights. increased flexibility in memory page si ze options supports a simple method of static memory partitioning. system protection all system resources and l2 memo ry banks can be controlled by either the processor cores, me mory-to-memory dma, or the system debug unit (sdu). a sy stem protection unit (spu) enables write accesses to specific resources that are locked to any of four masters: core 0, core 1, memory dma, and the sys- tem debug unit. system protec tion is enabled in greater granularity for some modules (l2, sec and gpio controllers) through a global lock concept. watchpoint protection the primary purpose of watchpoints and hardware breakpoints is to serve emulator needs. when enabled, they signal an emula- tor event whenever user-defined system resources are accessed or a core executes from user -defined addresses. watchdog events can be configured such that they signal the events to the other blackfin core or to the fault management unit. dual watchdog the two on-chip watchdog timers each may supervise one blackfin core. bandwidth monitor all dma channels that operate in memory-to-memory mode (memory dma, pvp memory pipe dma, pixc dma) are equipped with a bandwidth monitor mechanism. they can sig- nal a system event or fault when transactions tend to starve because system buses are fully loaded with higher-priority traffic. signal watchdogs the eight general-purpose timers feature two new modes to monitor off-chip signals. the watchdog period mode monitors whether external signals toggle with a period within an expected range. the watchdog width mode monitors whether the pulse widths of external signals are in an expected range. both modes help to detect incorrect undesired toggling (or lack thereof) of system-level signals. up/down count mismatch detection the up/down counter can monitor external signal pairs, such as request/grant strobes. if the ed ge count mismatch exceeds the expected range, the up/down counte r can flag this to the proces- sor or to the fault management unit. fault management the fault management unit is part of the system event controller (sec). any system event, whether a dual-bit uncorrectable ecc error, or any peripheral status interrupt, can be defined as being a fault. additionally, the system events can be defined as an interrupt to the cores. if define d as such, the sec forwards the event to the fault management unit which may automatically reset the entire device for reboot, or simply toggle the sys_fault output pins to signal off-chip hardware. option- ally, the fault management unit can delay the action taken via a keyed sequence, to provide a fina l chance for the blackfin cores to resolve the crisis and to preve nt the fault action from being taken. additional processor peripherals the processor contains a rich set of peripherals connected to the core via several high-bandwidth buses, providing flexibility in system configuration as well as excellent overall system perfor- mance (see the block diagram on page 1 ). the processors contain high-speed serial and pa rallel ports, an interrupt con- troller for flexible management of interrupts from the on-chip peripherals or external sources, and power management control functions to tailor the performance and power characteristics of the processor and system to many application scenarios. the following sections describe additional peripherals that were not described in the previous sections. timers the processor includes several ti mers which are described in the following sections. general-purpose timers there is one gp timer unit and it provides eight general-pur- pose programmable timers. each timer has an external pin that can be configured either as a pulse width modulator (pwm) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. these timers can be synchronized to an external clock input on the tmrx pins, an external clock tmrclk input pin, or to the internal sclk0. the timer units can be used in conjunction with the uarts and the can controller to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels. the timers can generate interrupts to the processor core, pro- viding periodic events for synchr onization to either the system clock or to external signals. timer events can also trigger other peripherals via the tru (for in stance, to signal a fault). core timers each processor core al so has its own dedicated timer. this extra timer is clocked by the internal processor clock and is typically used as a system tick clock fo r generating periodic operating system interrupts. watchd og timers each core includes a 32-bit time r, which may be used to imple- ment a software watchdog function. a software watchdog can improve system availabi lity by forcing the processor to a known state, via generation of a hardwa re reset, nonmaskable interrupt (nmi), or general-purpose interrup t, if the timer expires before
rev. prd | page 12 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 preliminary technical data being reset by software. the pr ogrammer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. thereafter, the software must reload the counter before it counts to ze ro from the programmed value. this protects the system from remaining in an unknown state where software, which would no rmally reset the timer, has stopped running due to an external noise condition or software error. after a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the timer control register, which is set only upon a watchdog gener- ated reset. 3-phase pwm units the two 3-phase pwm generation units each feature: ? 16-bit center-based pwm generation unit ?programmable pwm pulse width ? single/double update modes ? programmable dead time and switching frequency ? twos-complement implementation which permits smooth transition to full on and full off states ? dedicated asynchronous pwm shutdown signal each pwm block integrates a flexible and programmable 3-phase pwm waveform generator that can be programmed to generate the required switching patterns to drive a 3-phase volt- age source inverter for ac induction motor (acim) or permanent magnet synchronous motor (pmsm) control. in addition, the pwm block contains special functions that con- siderably simplify the generation of the required pwm switching patterns for control of the electronica lly commutated motor (ecm) or brushless dc motor (bdcm). software can enable a special mode for swit ched reluctance motors (srm). the eight pwm output signals (p er pwm unit) consist of four high-side drive signals and four low-side drive signals. the polarity of a generated pwm signal can be set with software, so that either active hi or ac tive lo pwm patterns can be produced. pulses synchronous to the switch ing frequency can be generated internally and output on the pwm_sync pin. the pwm unit can also accept externally generated synchronization pulses through pwm_sync. each pwm unit features a dedi cated asynchronous shutdown pin which (when brought low) in stantaneously places all six pwm outputs in the off state. link ports four dma-enabled, 8-bit-wide link ports can connect to the link ports of other dsps or pr ocessors. link ports are bidirec- tional ports having eight data lines, an acknowledge line and a clock line. serial ports (sports) three synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as analog devices ad183x family of audio codecs, adcs, and dacs. the serial ports are made up of two data lines, a clock, and frame sync. the data lines can be pro- grammed to either transmit or re ceive and each data line has a dedicated dma channel. serial port data can be automatically transferred to and from on-chip memory/external memory via dedicated dma chan- nels. each of the serial ports can work in conjunction with another serial port to provide tdm support. in this configura- tion, one sport provides two tr ansmit signals while the other sport provides the two receive signals. the frame sync and clock are shared. serial ports operate in five modes: ? standard dsp serial mode ?multichannel (tdm) mode ?i 2 s mode ?packed i 2 s mode ? left-justified mode acm interface the adc control module (acm) provides an interface that synchronizes the controls betwee n the processor and an analog- to-digital converter (adc). the analog-to-digital conversions are initiated by the processor, based on external or internal events. the acm allows for flexible sche duling of sampling instants and provides precise sampling signals to the adc. figure 5 shows how to connect an external adc to the acm and one of the sports. figure 5. adc, acm, and sport connections sportx spt_ad1 spt_ad0 spt_clk spt_fs adc d out b d out a adsclk cs range sgl/ diff a[2:0] acm acm_fs acm_clk acm_a4 acm_a3 acm_a[2:0] adsp-bf60x sport select mux
preliminary technical data rev. prd | page 13 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 the acm synchronizes the adc conversion process, generat- ing the adc controls, the adc conversion start signal, and other signals. the actual data acquisition from the adc is done by a peripheral such as a sport or a spi. the processor interfaces direct ly to many adcs without any glue logic required. general-purpose counters a 32-bit counter is provided th at can operate in general-pur- pose up/down count modes and can sense 2-bit quadrature or binary codes as typically emitted by industrial drives or manual thumbwheels. count direction is either controlled by a level- sensitive input pin or by two edge detectors. a third counter input can provide flexible zero marker support and can alternatively be used to input the push-button signal of thumb wheels. all three pins have a programmable debouncing circuit. internal signals forwarded to ea ch general-purpos e timer enable these timers to measure the intervals between count events. boundary registers enable auto-z ero operation or simple system warning by interrupts when programmable count values are exceeded. serial peripheral interface (spi) ports the processors have two spi-co mpatible ports that allow the processor to communicate with multiple spi-compatible devices. in its simplest mode, the spi inte rface uses three pins for trans- ferring data: two data pins (master output-slave input, mosi, and master input-slave output, miso) and a clock pin (serial clock, sck). an spi chip select input pin (spiss ) lets other spi devices select the processor, and seven spi chip select output pins (spisel7C1 ) let the processor select other spi devices. the spi select pins are reconfigured general-purpose i/o pins. using these pins, the spi port provides a full-duplex, synchronous serial interface, which supports both master/slave modes and multimaster environments. the spi ports baud rate and clock phase/polarities are pro- grammable, and it has integrated dma channels for both transmit and receive data streams. uart ports the processors provide two full -duplex universa l asynchronous receiver/transmitter (uart) port s, which are fully compatible with pc-standard uarts. each uart port provides a simpli- fied uart interface to other pe ripherals or hosts, supporting full-duplex, dma-supported, asynch ronous transfers of serial data. a uart port includes suppo rt for five to eight data bits, and none, even, or odd parity. op tionally, an additional address bit can be transferred to inte rrupt only addressed nodes in multi-drop bus (mdb) systems. a frame is terminates by one, one and a half, two or two and a half stop bits. the uart ports support automatic hardware flow control through the clear to send (cts) input and request to send (rts) output with programmab le assertion fifo levels. to help support the local inte rconnect network (lin) proto- cols, a special command causes th e transmitter to queue a break command of programmable bit leng th into the transmit buffer. similarly, the number of stop bits can be extended by a pro- grammable inter-frame space. the capabilities of the uarts are further extended with sup- port for the infrared data association (irda?) serial infrared physical layer link specification (sir) protocol. twi controller interface the processors include a 2-wire interface (twi) module for providing a simple exchange method of control data between multiple devices. the twi modu le is compatible with the widely used i 2 c bus standard. the tw i module offers the capabilities of simultaneous master and slave operation and support for both 7-bit addressing and multimedia data arbitra- tion. the twi interface utilizes two pins for transferring clock (twi_scl) and data (twi_sda) and supports the protocol at speeds up to 400k bits/sec. the twi interface pins are compati- ble with 5 v logic levels. additionally, the twi module is fully compatible with serial camera control bus (sccb) functionality for easier control of various cmos camera sensor devices. removable storage interface (rsi) the removable storage interface (r si) controller acts as the host interface for multimedia cards (mmc), secure digital memory cards (sd), secure digital inpu t/output cards (sdio), and ce- ata hard disk drives. the followi ng list describes the main fea- tures of the rsi controller. ? support for a single mmc, sd memory, sdio card or ce- ata hard disk drive ? support for 1-bit and 4-bit sd modes ? support for 1-bit, 4-bit, and 8-bit mmc modes ? support for 4-bit and 8-bit ce-ata hard disk drives ? support for emmc 4.3 embedded nand flash devices ? a ten-signal external interf ace with clock, command, and up to eight data lines ? card interface clock generation from sclk0 ? sdio interrupt and read wait features ? ce-ata command completion signal recognition and disable controller area network (can) a can controller implements the can 2.0b (active) protocol. this protocol is an asynchronous communications protocol used in both industrial and au tomotive control systems. the can protocol is well suited for control applications due to its capability to communicate reliab ly over a network. this is because the protocol incorporat es crc checking, message error tracking, and fault node confinement.
rev. prd | page 14 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 preliminary technical data the can controller offers the following features: ? 32 mailboxes (8 receive only , 8 transmit only, 16 configu- rable for receive or transmit). ? dedicated acceptance masks for each mailbox. ? additional data filtering on first two bytes. ? support for both the standard (11-bit) and extended (29- bit) identifier (id) message formats. ? support for remote frames. ? active or passive network support. ? can wakeup from hibernation mode (lowest static power consumption mode). ? interrupts, including: tx complete, rx complete, error and global. an additional crystal is not required to supply the can clock, as the can clock is derived from a system clock through a pro- grammable divider. 10/100 ethernet mac the processor can directly connec t to a network by way of an embedded fast ethernet media access controller (mac) that supports both 10-baset (10m bits/sec) and 100-baset (100m bits/sec) operation. the 10/100 et hernet mac peripheral on the processor is fully compliant to the ieee 802.3-2002 standard and it provides programmable features designed to minimize supervision, bus use, or message processing by the rest of the processor system. some standard features are: ? support and rmii protocols for external phys ? full duplex and half duplex modes ? media access management (in half-duplex operation) ? flow control ? station management: generation of mdc/mdio frames for read-write access to phy registers some advanced features are: ? automatic checksum computat ion of ip header and ip payload fields of rx frames ? independent 32-bit descriptor-driven receive and transmit dma channels ? frame status delivery to me mory through dma, including frame completion semaphores for efficient buffer queue management in software ? tx dma support for separate descriptors for mac header and payload to eliminate buffer copy operations ? convenient frame alignment modes ? 47 mac management statistics counters with selectable clear-on-read behavi or and programmable interrupts on half maximum value ? advanced power management ? magic packet detection and wakeup frame filtering ? support for 802.3q tagged vlan frames ? programmable mdc clock rate and preamble suppression ieee 1588 support the ieee 1588 standard is a pr ecision clock synchronization protocol for networked measurement and control systems. the processor includes hardware support for ieee 1588 with an integrated precision time protocol synchronization engine (ptp_tsync). this engine prov ides hardware assisted time stamping to improve the accuracy of clock synchronization between ptp nodes. the main features of the engine are: ? support for both ieee 1588-2002 and ieee 1588-2008 pro- tocol standards ? hardware assisted ti me stamping capable of up to 12.5 ns resolution ? lock adjustment ? automatic detection of ipv4 and ipv6 packets, as well as ptp messages ? multiple input clock sources (sclk0, rmii clock, external clock) ? programmable pulse per second (pps) output ? auxiliary snapshot to time stamp external events usb 2.0 on-the-go dual-r ole device controller the usb 2.0 otg dual-role device controller provides a low- cost connectivity solution for th e growing adoption of this bus standard in industrial applications, as well as consumer mobile devices such as cell phones, digi tal still cameras, and mp3 play- ers. the usb 2.0 controller allows these devices to transfer data using a point-to-point usb conn ection without the need for a pc host. the module can operat e in a traditional usb periph- eral-only mode as well as the host mode presented in the on- the-go (otg) supplement to the usb 2.0 specification. the usb clock (usb_clkin) is provided through a dedicated external crystal or crystal oscillator. the usb on-the-go dual-role device controller includes a phase locked loop with programm able multipliers to generate the necessary internal clocking frequency for usb. power and clock management the processor provides four operating modes, each with a dif- ferent performance/power profile. when configured for a 0 volt internal supply voltage (v dd_int ), the processor enters the hiber- nate state. control of clocki ng to each of the processor peripherals also reduces power consumption. see table 5 for a summary of the power se ttings for each mode. crystal oscillator (sys_xtal) the processor can be clocked by an external crystal, ( figure 6 ) a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. if an external clock is used, it should be a ttl compatible signal and must not be halted, changed, or operated below the specified fr equency during normal opera- tion. this signal is connecte d to the processors sys_clkin
preliminary technical data rev. prd | page 15 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 pin. when an external clock is used, the sys_xtal pin must be left unconnected. alternatively, because the processor includes an on-chip oscillator circuit, an external crystal may be used. for fundamental frequency operat ion, use the circuit shown in figure 6 . a parallel-resonant, fund amental frequency, micro- processor grade crystal is co nnected across the clkin and xtal pins. the on-chip resistance between clkin and the xtal pin is in the 500 k range. further paralle l resistors are typically not recommended. the two capacitors and the series resistor shown in figure 6 fine tune phase and amplitude of the sine frequency. the capacitor and resistor va lues shown in figure 6 are typical values only. the capacitor values are depend ent upon the crystal manufac- turers load capacitance recommendations and the pcb physical layout. the resistor value depends on the drive level specified by the crystal manufacturer. the user should verify the customized values based on careful investigat ions on multiple devices over temperature range. a third-overtone crystal can be used for frequencies above 25 mhz. the circuit is then modified to ensure crystal operation only at the third overtone by ad ding a tuned inductor circuit as shown in figure 6 . a design procedure fo r third-overtone oper- ation is discussed in detail in application note (ee-168) using third overtone crystals with the adsp-218x dsp on the ana- log devices website (www.analog.com)use site search on ee-168. usb crystal oscillator the usb can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. if an external cl ock is used, it should be a ttl compatible signal and must not be halted, changed, or operated below the specified frequency during normal operation. this signal is connected to the proc essors usb_xtal pin. alterna- tively, because the processor in cludes an on-chip oscillator circuit, an external crystal may be used. for fundamental frequency operat ion, use the circuit shown in figure 7 . a parallel-resonant, fund amental frequency, micro- processor grade crystal is connected between the usb_xtal pin and ground. a load capacitor is placed in parallel with the crystal. the combined capacitive value of the board trace para- sitic, the case capacitance of the crystal (from crystal manufacturer) and the parallel ca pacitor in the diagram should be in the range of 8 pf to 15 pf. the crystal should be chosen so that its rated load capacitance matches the nominal total capacitance on this node. a series resistor may be added between the usb_xtal pin and the par- allel crystal and capacitor comb ination, in order to further reduce the drive level of the crystal. the parallel capacitor and the series resistor shown in figure 7 fine tune phase and amplitude of the sine frequency. the capac- itor and resistor values shown in figure 7 are typical values only. the capacitor values are dependent upon the crystal man- ufacturers load capacitance recommendations and the pcb physical layout. the resistor va lue depends on the drive level specified by the crystal manufact urer. the user should verify the customized values based on careful investigations on multiple devices over temperature range. clock generation the clock generation unit (cgu ) generates all on-chip clocks and synchronization signals. mu ltiplication factors are pro- grammed to the pll to define the pllclk frequency. programmable values divide the pllclk frequency to generate the core clock (cclk), the syst em clocks (sysclk, sclk0 and sclk1), the lpddr or ddr2 cl ock (dclk) and the output clock (oclk). this is illustrated in figure 8 on page 32 . writing to the cgu control registers does not affect the behav- ior of the pll immediately. regi sters are first programmed with a new value, and the pll logic ex ecutes the changes so that it transitions smoothly from the current conditions to the new ones. sys_clkin oscillations start wh en power is applied to the v dd_ext pins. the rising edge of sys_hwrst can be applied after all voltage supplies are within specifications (see operating conditions on page 31 ), and sys_clkin oscillations are stable. figure 6. external crystal connection sys_clkin to pll circuitry for overtone operation only: note: values marked with * must be customized, depending on the crystal and layout. please analyze carefully. for frequencies above 33 mhz, the suggested capacitor value of 18pf should be treated as a maximum, and the suggested 5(6,67259$/8(6+28/'%(5('8&('72 18 pf* 18 pf * * blackfin sys_xtal f 7. e us b c c to usb pll blackfin 2 5-12 pf 1, 2 notes: 1. capacitance value shown includes board parasitics 2. values are a preliminary estimate.
rev. prd | page 16 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 preliminary technical data clock out/external clock the sys_clkout output pin ha s programmable options to output divided-down versions of the on-chip clocks, including usb clocks. note that the usbclk is provided for debug pur- poses only and is not supported or guaranteed for clocking customer applications. by default, the sys_clkout pin drives a buffered version of the sys_clkin input. clock generation faults (for example pll unlock) may trigger a rese t by hardware. the clocks shown in table 3 can be outputs from sys_clkout. power management as shown in table 4 , the processor supports five different power domains, which maximizes flexibility while maintaining com- pliance with industry standards and conventions. there are no sequencing requirements for the various power domains, but all domains must be powered ac cording to the appropriate specifi- cations table for processor operating conditions; even if the feature/peripheral is not used. the dynamic power management feature of the processor allows the processors core clock frequency (f cclk ) to be dynam- ically controlled. the power dissipated by a processo r is largely a function of its clock frequency and the square of the operating voltage. for example, reducing the clock freq uency by 25% re sults in a 25% reduction in dynamic power dissipation. full-on operating modemaximum performance in the full-on mode, the pll is enabled and is not bypassed, providing capability for maximum operational frequency. this is the power-up default execut ion state in which maximum per- formance can be achieved. the processor cores and all enabled peripherals run at full speed. active operating modemoderate dynamic power savings in the active mode, the pll is enabled but bypassed. because the pll is bypassed, the processors core clocks and system clocks run at the input clock (sys_clkin) frequency. dma access is available to appropriately configured l1 memories. for more information about pll controls, see the dynamic power management chapter in the adsp-bf60x blackfin pro- cessor hardware reference . see table 5 for a summary of the powe r settings for each mode. deep sleep operating modemaximum dynamic power savings the deep sleep mode maximizes dynamic power savings by dis- abling the clocks to the proce ssor core and to all synchronous peripherals. asynchronous periph erals may still be running but cannot access internal reso urces or external memory. hibernate statemaximum static power savings the hibernate state maximizes stat ic power savings by disabling the voltage and clocks to the processor cores and to all of the peripherals. this setting signal s the external voltage regulator supplying the v dd_int pins to shut off using the sys_extwake signal, wh ich provides the lowest static power dissipation. any critical information stored internally (for example, memory contents, regi ster contents, and other infor- mation) must be written to a non- volatile storage device prior to removing power if the processo r state is to be preserved. since the v dd_ext pins can still be supplied in this mode, all of the external pins three-state, unless otherwise specified. this allows other devices that may be connected to the processor to still have power applied without drawing unwanted current. reset control unit reset is the initial state of th e whole processor or one of the cores and is the result of a hardware or software triggered event. in this state, all control registers are set to their default values table 3. clock dividers clock source divider cclk (core clock) by 4 sysclk (system clock) by 2 sclk0 (system clock for pvp, all peripherals not covered by sclk1) none sclk1 (system clock for sports, spi, acm) none dclk (lpddr/ddr2 clock) by 2 oclk (output clock) programmable usbclk none clkbuf none, direct from sys_clkin usbclkbuf none, direct from usb_clkin table 4. power domains power domain vdd range all internal logic v dd_int ddr2/lpddr v dd_dmc usb v dd_usb thermal diode v dd_td all other i/o (includes sys, jtag, and ports pins) v dd_ext table 5. power settings mode/state pll pll bypassed f cclk f sysclk , f dclk , f sclk0 , f sclk1 core power full on enabled no enabled enabled on active enabled/ disabled yes enabled enabled on deep sleep disabled disabled disabled on hibernate disabled disabled disabled off
preliminary technical data rev. prd | page 17 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 and functional units are idle. ex iting a full system reset starts with core-0 only being ready to boot. exiting a core-n only reset starts with this core-n being ready to boot. the reset control unit (rcu) co ntrols how all the functional units enter and exit reset. diff erences in functional require- ments and clocking constraints define how reset signals are generated. programs must guarantee that none of the reset functions puts the system into an undefined state or causes resources to stall. this is part icularly important when only one of the cores is reset (programs must ensure that there is no pending system activity involving the core that is being reset). from a system perspective reset is defined by both the reset tar- get and the reset source as described below. target defined: ? hardware reset C all functional units are set to their default states without exception. history is lost. ? system reset C all functional units except the rcu are set to their default states. ? core-n only reset C affects co re-n only. the system soft- ware should guarantee that the core in reset state is not accessed by any bus master. source defined: ? hardware reset C the sys_hwrst input signal is asserted active (pulled down). ? system reset C may be triggered by software (writing to the rcu_ctl register) or by another functional unit such as the dynamic power management (dpm) unit (hibernate) or any of the system event co ntroller (sec), trigger routing unit (tru), or emulator inputs. ? core-n-only reset C triggered by software. ? trigger request (peripheral). voltage regulation the processor requires an external voltage regulator to power the v dd_int pins. to reduce standby power consumption, the external voltage regulator can be signaled through sys_extwake to remove powe r from the processor core. this signal is high-true for power-up and may be connected directly to the low-true shut-down input of many common regulators. while in the hibernate state, all external supply pins (v dd_ext , v dd_usb , v dd_dmc ) can still be powered, eliminating the need for external buffers. the external vo ltage regulator can be activated from this power down state by asserting the sys_hwrst pin, which then initiates a boot sequence. sys_extwake indicates a wakeup to the external voltage regulator. system debug the processor includes various fe atures that allow for easy sys- tem debug. these are described in the following sections. system watchpoint unit the system watchpoint unit (swu) is a single module which connects to a single system bu s and provides for transaction monitoring. one swu is attached to the bus going to each sys- tem slave. the swu provides po rts for all system bus address channel signals. each swu contains four match groups of regis- ters with associated hardware . these four swu match groups operate independently, but sh are common event (interrupt, trigger and others) outputs. system debug unit the system debug unit (sdu) provides ieee-1149.1 support through its jtag interface. in ad dition to traditional jtag fea- tures, present in legacy blackf in products, the sdu adds more features for debugging the chip without halting the core processors. ez-kit lite? evaluation board for evaluation of adsp -bf606/adsp-bf607/adsp- bf608/ADSP-BF609 processors , use the ez-kit lite ? boards available from analog devices. order using part numbers adzs-bf609-ezlite. the boards come with on-chip emula- tion capabilities and are eq uipped to enable software development. multiple daughter cards are available. designing an emulator-compatible processor board (target) the analog devices family of em ulators are tools that every sys- tem developer needs in order to test and debug hardware and software systems. analog de vices has supplied an ieee 1149.1 jtag test access port (tap) on each processor. the emulator uses the tap to access the intern al features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. the proces- sor must be halted to send da ta and commands, but once an operation has been completed by the emulator, the processor system is set running at full speed with no impact on system timing. to use these emulators, the target board must include a header that connects the processors jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor conne ctions, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see (ee-68) analog devices jtag emulation technical reference on the analog devices website ( www.analog.com ) use site search on ee-68. this document is updated regularly to keep pace with improvements to emulator support.
rev. prd | page 18 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 preliminary technical data related documents the following publications that describe the adsp- bf606/adsp-bf607/adsp-bf608/ ADSP-BF609 processors (and related processors) can be ordered from any analog devices sales office or accessed electronically on our website: ? getting started with blackfin processors ? adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 blackfin processor hardware reference ? blackfin processor programming reference related signal chains a signal chain is a series of signal-conditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stor ed data) in tandem, with the output of one portion of the ch ain supplying input to the next. signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. for more information about this term and related topics, see the signal chain entry in the glossary of ee terms on the analog devices website. analog devices eases signal proc essing system development by providing signal proc essing components that are designed to work together well. a tool for viewing relationships between specific applications and related components is available on the www.analog.com website. the application signal chains pa ge in the circuits from the lab tm site ( http:\\www.analog.com\circuits ) provides: ? graphical circuit block diag ram presentation of signal chains for a variety of circuit types and applications ? drill down links for components in each chain to selection guides and application information ? reference designs applying best practice design techniques
preliminary technical data rev. prd | page 19 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 signal descriptions the processors signal definitions are shown in table 6 . table 6. processor signal descriptions signal name function driver type power domain ports pins pa00 C pa15 port a 00 C port a 15 a v dd_ext pb00 C pb15 port b 00 C port b 15 a v dd_ext pc00 C pc15 port c 00 C port c 15 a v dd_ext pd00 C pd15 port d 00 C port d 15 a v dd_ext pe00 C pe15 port e 00 C port e 15 a v dd_ext pf00 C pf15 port f 00 C port f 15 a v dd_ext pg00 C pg15 port g 00 C port g 15 a v dd_ext dynamic memory controller dmc0_a00 C dmc0_a13 dmc0 address 0 C dmc0 address 13 b v dd_dmc dmc0_ba0 dmc0 bank address input 0 b v dd_dmc dmc0_ba1 dmc0 bank address input 1 b v dd_dmc dmc0_ba2 dmc0 bank address input 2 b v dd_dmc dmc0_cas dmc0 column address strobe b v dd_dmc dmc0_ck dmc0 clock c v dd_dmc dmc0_ck dmc0 clock (complement) c v dd_dmc dmc0_cke dmc0 clock enable b v dd_dmc dmc0_cs0 dmc0 chip select 0 b v dd_dmc dmc0_dq00 C dmc0_dq15 dmc0 data 0 C dmc0 data 15 b v dd_dmc dmc0_ldm dmc0 data mask for lower byte b v dd_dmc dmc0_ldqs dmc0 data strobe for lower byte c v dd_dmc dmc0_ldqs dmc0 data strobe for lower byte (complement) c v dd_dmc dmc0_odt dmc0 on-die termination b v dd_dmc dmc0_ras dmc0 row address strobe b v dd_dmc dmc0_udm dmc0 data mask for upper byte b v dd_dmc dmc0_udqs dmc0 data strobe for upper byte c v dd_dmc dmc0_udqs dmc0 data strobe for upper byte (complement) c v dd_dmc dmc0_we dmc0 write enable b v dd_dmc jtag test access port jtg_emu jtg emulation output a v dd_ext jtg_tck jtg clock v dd_ext jtg_tdi jtg serial data in v dd_ext jtg_tdo jtg serial data out a v dd_ext jtg_tms jtg mode select v dd_ext jtg_trst jtg reset v dd_ext static memory controller smc0_a01 smc0 address 1 a v dd_ext smc0_a02 smc0 address 2 a v dd_ext smc0_ams0 smc0 memory select 0 a v dd_ext smc0_aoe /smc0_nordv smc0 output enab le/smc0 nor data valid a v dd_ext smc0_ardy/smc0_norwt smc0 asynchronous ready/smc0 nor wait v dd_ext smc0_are smc0 read enable a v dd_ext smc0_awe smc0 write enable a v dd_ext smc0_br smc0 bus request v dd_ext smc0_d00 C smc0_d15 smc0 data 0 C smc0 data 15 a v dd_ext
rev. prd | page 20 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 preliminary technical data pin multiplexing in table 7 , the default state is shown in plain text, while the alternate functions are shown in italics. system booting, clocking and control sys_bmode0 sys boot mode control 0 v dd_ext sys_bmode1 sys boot mode control 1 v dd_ext sys_bmode2 sys boot mode control 2 v dd_ext sys_clkin sys clock/crystal input v dd_ext sys_clkout sys processor clock output a v dd_ext sys_extwake sys external wake control a v dd_ext sys_fault sys fault output a v dd_ext sys_fault sys complementary fault output a v dd_ext sys_nmi /sys_resout sys non-maskable interrupt/sys reset output a v dd_ext sys_pwrgd sys power good indicator v dd_ext sys_hwrst sys processor reset control v dd_ext sys_tda sys thermal diode anode v dd_thd sys_tdk sys thermal diode cathode v dd_thd sys_xtal sys crystal output v dd_ext 2-wire interface twi0_scl twi0 serial clock d v dd_ext twi0_sda twi0 serial data d v dd_ext twi1_scl twi1 serial clock d v dd_ext twi1_sda twi1 serial data d v dd_ext universal serial bus usb0_clkin usb0 clock/crystal input v dd_usb usb0_dm usb0 data C v dd_usb usb0_dp usb0 data + v dd_usb usb0_id usb0 otg id v dd_usb usb0_vbc usb0 vbus control v dd_usb usb0_vbus usb0 bus voltage v dd_usb table 6. processor signal descriptions (continued) signal name function driver type power domain table 7. processor multiplexing scheme signal name function port a pa_00/ smc0_a03/eppi2_d00/lp0_d0 pa position 0/ smc0 address 3/eppi2 data 0/lp0 data 0 pa_01/ smc0_a04/eppi2_d01/lp0_d1 pa position 1/ smc0 address 4/eppi2 data 1/lp0 data 1 pa_02/ smc0_a05/eppi2_d02/lp0_d2 pa position 2/ smc0 address 5/eppi2 data 2/lp0 data 2 pa_03/ smc0_a06/eppi2_d03/lp0_d3 pa position 3/ smc0 address 6/eppi2 data 3/lp0 data 3 pa_04/ smc0_a07/eppi2_d04/lp0_d4 pa position 4/ smc0 address 7/eppi2 data 4/lp0 data 4 pa_05/ smc0_a08/eppi2_d05/lp0_d5 pa position 5/ smc0 address 8/eppi2 data 5/lp0 data 5 pa_06/ smc0_a09/eppi2_d06/lp0_d6 pa position 6/ smc0 address 9/eppi2 data 6/lp0 data 6 pa_07/ smc0_a10/eppi2_d07/lp0_d7 pa position 7/ smc0 address 10/eppi2 data 7/lp0 data 7 pa_08/ smc0_a11/eppi2_d08/lp1_d0 pa position 8/ smc0 address 11/eppi2 data 8/lp1 data 0 pa_09/ smc0_a12/eppi2_d09/lp1_d1 pa position 9/ smc0 address 12/eppi2 data 9/lp1 data 1 pa_10/ smc0_a14/eppi2_d10/lp1_d2 pa position 10/ smc0 address 14/eppi2 data 10/lp1 data 2 pa_11/ smc0_a15/eppi2_d11/lp1_d3 pa position 11/ smc0 address 15/eppi2 data 11/lp1 data 3 pa_12/ smc0_a17/eppi2_d12/lp1_d4 pa position 12/ smc0 address 17/eppi2 data 12/lp1 data 4 pa_13/ smc0_a18/eppi2_d13/lp1_d5 pa position 13/ smc0 address 18/eppi2 data 13/lp1 data 5
preliminary technical data rev. prd | page 21 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 pa_14/ smc0_a19/eppi2_d14/lp1_d6 pa position 14/ smc0 address 19/eppi2 data 14/lp1 data 6 pa_15/ smc0_a20/eppi2_d15/lp1_d7 pa position 15/ smc0 address 20/eppi2 data 15/lp1 data 7 port b pb_00/ smc0_norclk/eppi 2_clk/lp0_clk pb position 0/ smc0 nor clock/eppi2 clock/lp0 clock pb_01/ smc0_ams1 /eppi2_fs1/lp0_ack pb position 1/ smc0 memory select 1/eppi2 frame sync 1 (hsync)/lp0 acknowledge pb_02/ smc0_a13/eppi2_fs2/lp1_ack pb position 2/ smc0 address 13/eppi2 frame sync 2 (vsync)/lp1 acknowledge pb_03/ smc0_a16/eppi2_fs3/lp1_clk pb position 3/ smc0 address 16/eppi2 frame sync 3 (field)/lp1 clock pb_04/ smc0_ams2 /smc0_abe0/spt0_afs pb position 4/ smc0 memory select 2/smc0 byte enable 0/sport0 channel a frame sync pb_05/ smc0_ams3 /smc0_abe1/spt0_aclk pb position 5/ smc0 memory select 3/smc0 byte enable 1/sport0 channel a clock pb_06/ smc0_a21/spt0_atdv/tm0_aclk4 pb position 6/ smc0 address 21/sport0 channel a transmit data valid/ timer0 alternate clock 4 pb_07/ smc0_a22/eppi2_d16/spt0_bfs pb position 7/ smc0 address 22/eppi2 data 16/sport0 channel b frame sync pb_08/ smc0_a23/eppi2_d17/spt0_bclk pb position 8/ smc0 address 23/eppi2 data 17/sport0 channel b clock pb_09/ smc0_bgh /spt0_ad0/tm0_aclk2 pb position 9/ smc0 bus grant hang/sport0 channel a data 0/timer0 alternate clock 2 pb_10/ smc0_a24/spt0_bd1/tm0_aclk0 pb position 10/ smc0 address 24/sport0 channel b data 1/timer0 alternate clock 0 pb_11/ smc0_a25/spt0_bd0/tm0_aclk3 pb position 11/ smc0 address 25/sport0 channel b data 0/timer0 alternate clock 3 pb_12/ smc0_bg /spt0_btdv/spt0_ad1/ tm0_aclk1 pb position 12/ smc0 bus grant/sport0 channel b transmit data valid/ sport0 channel a data 1/timer0 alternate clock 1 pb_13/ eth0_txen/eppi1_fs1/tm0_aci6 pb position 13/ eth0 transmit enable/eppi1 frame sync 1 (hsync)/ timer0 alternate capture input 6 pb_14/ eth0_refclk/eppi1_clk pb position 14/ eth0 reference clock/eppi1 clock pb_15/ eth0_ptppps/eppi1_fs3 pb position 15/ eth0 ptp pulse-per-second output/eppi1 frame sync 3 (field) port c pc_00/ eth0_rxd0/eppi1_d00 pc position 0/ eth0 receive data 0/eppi1 data 0 pc_01/ eth0_rxd1/eppi1_d01 pc position 1/ eth0 receive data 1/eppi1 data 1 pc_02/ eth0_txd0/eppi1_d02 pc position 2/ eth0 transmit data 0/eppi1 data 2 pc_03/ eth0_txd1/eppi1_d03 pc position 3/ eth0 transmit data 1/eppi1 data 3 pc_04/ eth0_rxerr/eppi1_d04 pc position 4/ eth0 receive error/eppi1 data 4 pc_05/ eth0_crs/eppi1_d05 pc position 5/ eth0 carrier sense/rmii receive data valid/eppi1 data 5 pc_06/ eth0_mdc/eppi1_d06 pc position 6/ eth0 management channel clock/eppi1 data 6 pc_07/ eth0_mdio/eppi1_d07 pc position 7/ eth0 management channel serial data/eppi1 data 7 pc_08/ eppi1_d08 pc position 8/ eppi1 data 8 pc_09/ eth1_ptppps/eppi1_d09 pc position 9/ eth1 ptp pulse-per-second output/eppi1 data 9 pc_10/ eppi1_d10 pc position 10/ eppi1 data 10 pc_11/ eppi1_d11/eth_ptpauxin pc position 11/ eppi1 data 11/eth ptp auxiliary trigger input pc_12/ spi0_sel7 /eppi1_d12 pc position 12/ spi0 slave select output 7/eppi1 data 12 pc_13/ spi0_sel6 /eppi1_d13/eth_ptpclkin pc position 13/ spi0 slave select output 6/eppi1 data 13/eth ptp clock input pc_14/ spi1_sel7 /eppi1_d14 pc position 14/ spi1 slave select output 7/eppi1 data 14 pc_15/ spi0_sel4 /eppi1_d15 pc position 15/ spi0 slave select output 4/eppi1 data 15 port d pd_00/ spi0_d2/eppi1_d16/spi0_sel3 pd position 0/ spi0 data 2/eppi1 data 16/spi0 slave select output 3 pd_01/ spi0_d3/eppi1_d17/spi0_sel2 pd position 1/ spi0 data 3/eppi1 data 17/spi0 slave select output 2 pd_02/ spi0_miso pd position 2/ spi0 master in, slave out pd_03/ spi0_mosi pd position 3/ spi0 master out, slave in pd_04/ spi0_clk pd position 4/ spi0 clock pd_05/ spi1_clk/tm0_aclk7 pd position 5/ spi1 clock/timer0 alternate clock 7 pd_06/ eth0_phyint /eppi1_fs2/tm0_aci5 pd position 6/ eth0 rmii management data interrupt/eppi1 frame sync 2 (vsync)/ timer0 alternate capture input 5 pd_07 /uart0_tx /tm0_aci3 pd position 7/ uart0 transmit/timer0 alternate capture input 3 table 7. processor multiplexing scheme (continued) signal name function
rev. prd | page 22 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 preliminary technical data pd_08/ uart0_rx /tm0_aci0 pd position 8/ uart0 receive/timer0 alternate capture input 0 pd_09/ spi0_sel5 /uart0_rts /spi1_sel4 pd position 9/ spi0 slave select output 5/uart0 request to send/spi1 slave select output 4 pd_10/ spi0_rdy/uart0_cts /spi1_sel3 pd position 10/ spi0 ready/uart0 clear to send/spi1 slave select output 3 pd_11/ spi0_sel1 /spi0_ss pd position 11/ spi0 slave select output 1/spi0 slave select input pd_12/ spi1_sel1 /eppi0_d20/spt1_ad1/ spi1_ss pd position 12/ spi1 slave select output 1/eppi0 data 20/sport1 channel a data 1/ spi1 slave select input pd_13/ spi1_mosi/tm0_aclk5 pd position 13/ spi1 master out, slave in/timer0 alternate clock 5 pd_14/ spi1_miso/tm0_aclk6 pd position 14/ spi1 master in, slave out/timer0 alternate clock 6 pd_15/ spi1_sel2 /eppi0_d21/spt1_ad0 pd position 15/ spi1 slave select output 2/eppi0 data 21/sport1 channel a data 0 port e pe_00/ spi1_d3/eppi0_d18/spt1_bd1 pe position 0/ spi1 data 3/eppi0 data 18/sport1 channel b data 1 pe_01/ spi1_d2/eppi0_d19/spt1_bd0 pe position 1/ spi1 data 2/eppi0 data 19/sport1 channel b data 0 pe_02/ spi1_rdy/eppi0_d22/spt1_aclk pe position 2/ spi1 ready/eppi0 data 22/sport1 channel a clock pe_03/ eppi0_d16/acm0_fs/spt1_bfs pe position 3/ eppi0 data 16/acm0 frame sync/sport1 channel b frame sync pe_04/ eppi0_d17/acm0_clk/spt1_bclk pe position 4/ eppi0 data 17/acm0 clock/sport1 channel b clock pe_05/ eppi0_d23/spt1_afs pe position 5/ eppi0 data 23/sport1 channel a frame sync pe_06/ spt1_atdv/eppi0_fs3/lp3_clk pe position 6/ sport1 channel a transmit data valid/eppi0 frame sync 3 (field)/lp3 clock pe_07/ spt1_btdv/eppi0_fs2/lp3_ack pe position 7/ sport1 channel b transmit data valid/ eppi0 frame sync 2 (vsync)/lp3 acknowledge pe_08/ pwm0_sync/eppi0_fs1/lp2_ack/ acm0_t0 pe position 8/ pwm0 sync/eppi0 frame sync 1 (hsync)/lp2 acknowledge/ acm0 external trigger 0 pe_09/ eppi0_clk/lp2_clk/pwm0_trip0 pe position 9/ eppi0 clock/lp2 clock/pwm0 shutdown input 0 pe_10/ eth1_mdc/pwm1_dl/rsi0_d6 pe position 10/ eth1 management channel clock/pwm1 channel d low side/rsi0 data 6 pe_11/ eth1_mdio/pwm1_dh/rsi0_d7 pe position 11/ eth1 management channel serial data/pwm1 channel d high side/rsi0 data 7 pe_12/ eth1_phyint /pwm1_cl/rsi0_d5 pe position 12/ eth1 rmii management data interrupt/pwm1 channel c low side/rsi0 data 5 pe_13/ eth1_crs/pwm1_ch/rsi0_d4 pe position 13/ eth1 carrier sense/rmii receive da ta valid/pwm1 channel c high side/ rsi0 data 4 pe_14/ eth1_rxerr/spt2_atdv/tm0_tmr0 pe position 14/ eth1 receive error/sport2 channel a transmit data valid/ timer0 timer 0 pe_15/ eth1_rxd1/pwm1_bl/rsi0_d3 pe position 15/ eth1 receive data 1/pwm1 channel b low side/rsi0 data 3 port f pf_00/ pwm0_al/eppi0_d00/lp2_d0 pf position 0/ pwm0 channel a low side/eppi0 data 0/lp2 data 0 pf_01/ pwm0_ah/eppi0_d01/lp2_d1 pf position 1/ pwm0 channel a high side/eppi0 data 1/lp2 data 1 pf_02/ pwm0_bl/eppi0_d02/lp2_d2 pf position 2/ pwm0 channel b low side/eppi0 data 2/lp2 data 2 pf_03/ pwm0_bh/eppi0_d03/lp2_d3 pf position 3/ pwm0 channel b high side/eppi0 data 3/lp2 data 3 pf_04 /pwm0_cl/eppi0_d04/lp2_d4 pf position 4/ pwm0 channel c low side/eppi0 data 4/lp2 data 4 pf_05/ pwm0_ch/eppi0_d05/lp2_d5 pf position 5/ pwm0 channel c high side/eppi0 data 5/lp2 data 5 pf_06/ pwm0_dl/eppi0_d06/lp2_d6 pf position 6/ pwm0 channel d low side/eppi0 data 6/lp2 data 6 pf_07/ pwm0_dh/eppi0_d07/lp2_d7 pf position 7/ pwm0 channel d high side/eppi0 data 7/lp2 data 7 pf_08/ spi1_sel5 /eppi0_d08/lp3_d0 pf position 8/ spi1 slave select output 5/eppi0 data 8/lp3 data 0 pf_09/ spi1_sel6 /eppi0_d09/lp3_d1 pf position 9/ spi1 slave select output 6/eppi0 data 9/lp3 data 1 pf_10/ acm0_a4/eppi0_d10/lp3_d2 pf position 10/ acm0 address 4/eppi0 data 10/lp3 data 2 pf_11/ eppi0_d11/lp3_d3/pwm0_trip1 pf position 11/ eppi0 data 11/lp3 data 3/pwm0 shutdown input 1 pf_12/ acm0_a2/eppi0_d12/lp3_d4 pf position 12/ acm0 address 2/eppi0 data 12/ lp3 data 4 pf_13/ acm0_a3/eppi0_d13/lp3_d5 pf position 13/ acm0 address 3/eppi0 data 13/ lp3 data 5 pf_14/ acm0_a0/eppi0_d14/lp3_d6 pf position 14/ acm0 address 0/eppi0 data 14/ lp3 data 6 pf_15/ acm0_a1/eppi0_d15/lp3_d7 pf position 15/ acm0 address 1/eppi0 data 15/ lp3 data 7 port g pg_00/ eth1_rxd0/pwm1_bh/rsi0_d2 pg position 0/ eth1 receive data 0/pwm1 channel b high side/rsi0 data 2 pg_01/ spt2_afs/tm0_tmr2/can0_tx pg position 1/ sport2 channel a frame sync/timer0 timer 2/can0 transmit table 7. processor multiplexing scheme (continued) signal name function
preliminary technical data rev. prd | page 23 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 pg_02/ eth1_txd1/pwm1_al/rsi0_d1 pg position 2/ eth1 transmit data 1/pwm1 channel a low side/rsi0 data 1 pg_03/ eth1_txd0/pwm1_ah/rsi0_d0 pg position 3/ eth1 transmit data 0/pwm1 channel a high side/rsi0 data 0 pg_04/ spt2_aclk/tm0_tmr1/can0_rx/ tm0_aci2 pg position 4/ sport2 channel a clock/time r0 timer 1/can0 receive/ timer0 alternate capture input 2 pg_05/ eth1_txen/rsi0_cmd/pwm1_sync/ acm0_t1 pg position 5/ eth1 transmit enable/r si0 command/pwm1 sync/ acm0 external trigger 1 pg_06/ eth1_refclk/rsi0_clk/spt2_btdv/ pwm1_trip0 pg position 6/ eth1 reference clock/rsi0 clock/sport2 channel b transmit data valid/ pwm1 shutdown input 0 pg_07/ spt2_bfs/tm0_tmr5/cnt0_zm pg position 7/ sport2 channel b frame sync/ timer0 timer 5/cnt0 count zero marker pg_08/ spt2_ad1/tm0_tmr3/pwm1_trip1 pg position 8/ sport2 channel a data 1/timer0 timer 3/pwm1 shutdown input pg_09/ spt2_ad0/tm0_tmr4 pg position 9/ sport2 channel a data 0/timer0 timer 4 pg_10/ uart1_rts /spt2_bclk pg position 10/ uart1 request to send/sport2 channel b clock pg_11/ spt2_bd1/tm0_tmr6/cnt0_ud pg position 11/ sport2 channel b data 1/timer0 timer 6/cnt0 count up and direction pg_12/ spt2_bd0/tm0_tmr7/cnt0_dg pg position 12/ sport2 channel b data 0/timer0 timer 7/cnt0 count down and gate pg_13/ uart1_cts /tm0_clk pg position 13/ uart1 clear to send/timer0 clock pg_14/ uart1_rx /sys_idle1 /tm0_aci1 pg position 14/ uart1 receive/sys core 1 idle indicator/timer0 alternate capture input 1 pg_15/ uart1_tx /sys_idle0/sys_sleep / tm0_aci4 pg position 15/ uart1 transmit/sys core 0 idle indica tor/sys processor sleep indicator/ timer0 alternate capture input 4 table 7. processor multiplexing scheme (continued) signal name function
rev. prd | page 24 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 preliminary technical data pin termination and drive characteristics-requirements table 8 identifies how each signal on the chip is internally ter- minated and driven. in addi tion, external termination requirements are provided. in this table the following columns are used. ? internal termination C specifies the termination present when the processor is not in the reset or hibernate state. ? reset termination C specif ies the termination present when the processor is in the reset state. ? reset drive C specifies the acti ve drive on the signal when the processor is in the reset state. ? hibernate termination C specifies the termination present when the processor is in the hibernate state. ? hibernate drive C specifies th e active drive on the signal when the processor is in the hibernate state. ? notes C specifies any special requirements or characteris- tics for the signal. if no special requirements are listed the signal may be left unconnected if it is not used. table 8. adsp-bf60x pad table signal name internal termination reset termination reset drive hibernate termination hibernate drive notes dmc0_a00 none none none none none no notes dmc0_a01 none none none none none no notes dmc0_a02 none none none none none no notes dmc0_a03 none none none none none no notes dmc0_a04 none none none none none no notes dmc0_a05 none none none none none no notes dmc0_a06 none none none none none no notes dmc0_a07 none none none none none no notes dmc0_a08 none none none none none no notes dmc0_a09 none none none none none no notes dmc0_a10 none none none none none no notes dmc0_a11 none none none none none no notes dmc0_a12 none none none none none no notes dmc0_a13 none none none none none no notes dmc0_ba0 none none none none none no notes dmc0_ba1 none none none none none no notes dmc0_ba2 none none none none none for lpddr leave unconnected. dmc0_cas none none none none none no notes dmc0_ck none none low none low no notes dmc0_ck none none low none low no notes dmc0_cke none none low none low no notes dmc0_cs0 none none none none none no notes dmc0_dq00 none none none none none no notes dmc0_dq01 none none none none none no notes dmc0_dq02 none none none none none no notes dmc0_dq03 none none none none none no notes dmc0_dq04 none none none none none no notes dmc0_dq05 none none none none none no notes dmc0_dq06 none none none none none no notes dmc0_dq07 none none none none none no notes dmc0_dq08 none none none none none no notes dmc0_dq09 none none none none none no notes dmc0_dq10 none none none none none no notes dmc0_dq11 none none none none none no notes
preliminary technical data rev. prd | page 25 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 dmc0_dq12 none none none none none no notes dmc0_dq13 none none none none none no notes dmc0_dq14 none none none none none no notes dmc0_dq15 none none none none none no notes dmc0_ldm none none none none none no notes dmc0_ldqs none none none none none for lp ddr a 100k pull-down is required. dmc0_ldqs none none none none none for single ended ddr2 connect to vref_dmc. for lpddr leave unconnected. dmc0_odt none none none none none for lpddr leave unconnected. dmc0_ras none none none none none no notes dmc0_udm none none none none none no notes dmc0_udqs none none none none none for lp ddr a 100k pull-down is required. dmc0_udqs none none none none none for single ended ddr2 connect to vref_dmc. for lpddr leave unconnected. dmc0_we none none none none none no notes gnd none none none none none no notes jtg_emu none none none none none no notes jtg_tck pull-down none none none none functional during reset. jtg_tdi pull-up none none none none functional during reset. jtg_tdo none none none none none functional during reset, three-state when jtg_trst is asserted. jtg_tms pull-up none none none none functional during reset. jtg_trst pull-down none none none none functional during reset. pa00 weak keeper weak keeper none weak keeper none no notes pa01 weak keeper weak keeper none weak keeper none no notes pa02 weak keeper weak keeper none weak keeper none no notes pa03 weak keeper weak keeper none weak keeper none no notes pa04 weak keeper weak keeper none weak keeper none no notes pa05 weak keeper weak keeper none weak keeper none no notes pa06 weak keeper weak keeper none weak keeper none no notes pa07 weak keeper weak keeper none weak keeper none no notes pa08 weak keeper weak keeper none weak keeper none no notes pa09 weak keeper weak keeper none weak keeper none no notes pa10 weak keeper weak keeper none weak keeper none no notes pa11 weak keeper weak keeper none weak keeper none no notes pa12 weak keeper weak keeper none weak keeper none no notes pa13 weak keeper weak keeper none weak keeper none no notes pa14 weak keeper weak keeper none weak keeper none no notes pa15 weak keeper weak keeper none weak keeper none no notes pb00 weak keeper weak keeper none weak keeper none no notes pb01 weak keeper weak keeper none weak keeper none no notes pb02 weak keeper weak keeper none weak keeper none no notes pb03 weak keeper weak keeper none weak keeper none no notes pb04 weak keeper weak keeper none weak keeper none no notes pb05 weak keeper weak keeper none weak keeper none no notes pb06 weak keeper weak keeper none weak keeper none no notes table 8. adsp-bf60x pa d table (continued) signal name internal termination reset termination reset drive hibernate termination hibernate drive notes
rev. prd | page 26 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 preliminary technical data pb07 weak keeper weak keeper none weak keeper none no notes pb08 weak keeper weak keeper none weak keeper none no notes pb09 weak keeper weak keeper none weak keeper none no notes pb10 weak keeper weak keeper none weak keeper none no notes pb11 weak keeper weak keeper none weak keeper none no notes pb12 weak keeper weak keeper none weak keeper none no notes pb13 weak keeper weak keeper none weak keeper none no notes pb14 weak keeper weak keeper none weak keeper none no notes pb15 weak keeper weak keeper none weak keeper none no notes pc00 weak keeper weak keeper none weak keeper none no notes pc01 weak keeper weak keeper none weak keeper none no notes pc02 weak keeper weak keeper none weak keeper none no notes pc03 weak keeper weak keeper none weak keeper none no notes pc04 weak keeper weak keeper none weak keeper none no notes pc05 weak keeper weak keeper none weak keeper none no notes pc06 weak keeper weak keeper none weak keeper none no notes pc07 weak keeper weak keeper none weak keeper none no notes pc08 weak keeper weak keeper none weak keeper none no notes pc09 weak keeper weak keeper none weak keeper none no notes pc10 weak keeper weak keeper none weak keeper none no notes pc11 weak keeper weak keeper none weak keeper none no notes pc12 weak keeper weak keeper none weak keeper none no notes pc13 weak keeper weak keeper none weak keeper none no notes pc14 weak keeper weak keeper none weak keeper none no notes pc15 weak keeper weak keeper none weak keeper none no notes pd00 weak keeper weak keeper none weak keeper none no notes pd01 weak keeper weak keeper none weak keeper none no notes pd02 weak keeper weak keeper none weak keeper none no notes pd03 weak keeper weak keeper none weak keeper none no notes pd04 weak keeper weak keeper none weak keeper none no notes pd05 weak keeper weak keeper none weak keeper none no notes pd06 weak keeper weak keeper none weak keeper none no notes pd07 weak keeper weak keeper none weak keeper none no notes pd08 weak keeper weak keeper none weak keeper none no notes pd09 weak keeper weak keeper none weak keeper none no notes pd10 weak keeper weak keeper none weak keeper none no notes pd11 weak keeper weak keeper none weak keeper none no notes pd12 weak keeper weak keeper none weak keeper none no notes pd13 weak keeper weak keeper none weak keeper none no notes pd14 weak keeper weak keeper none weak keeper none no notes pd15 weak keeper weak keeper none weak keeper none no notes pe00 weak keeper weak keeper none weak keeper none no notes pe01 weak keeper weak keeper none weak keeper none no notes pe02 weak keeper weak keeper none weak keeper none no notes pe03 weak keeper weak keeper none weak keeper none no notes table 8. adsp-bf60x pa d table (continued) signal name internal termination reset termination reset drive hibernate termination hibernate drive notes
preliminary technical data rev. prd | page 27 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 pe04 weak keeper weak keeper none weak keeper none no notes pe05 weak keeper weak keeper none weak keeper none no notes pe06 weak keeper weak keeper none weak keeper none no notes pe07 weak keeper weak keeper none weak keeper none no notes pe08 weak keeper weak keeper none weak keeper none no notes pe09 weak keeper weak keeper none weak keeper none no notes pe10 weak keeper weak keeper none weak keeper none has an optional internal pull-up for use with rsi. see the rsi chapter in the hrm for more details. pe11 weak keeper weak keeper none weak keeper none has an optional internal pull-up for use with rsi. see the rsi chapter in the hrm for more details. pe12 weak keeper weak keeper none weak keeper none has an optional internal pull-up for use with rsi. see the rsi chapter in the hrm for more details. pe13 weak keeper weak keeper none weak keeper none has an optional internal pull-up for use with rsi. see the rsi chapter in the hrm for more details. pe14 weak keeper weak keeper none weak keeper none no notes pe15 weak keeper weak keeper none weak keeper none has an optional internal pull-up for use with rsi. see the rsi chapter in the hrm for more details. pf00 weak keeper weak keeper none weak keeper none no notes pf01 weak keeper weak keeper none weak keeper none no notes pf02 weak keeper weak keeper none weak keeper none no notes pf03 weak keeper weak keeper none weak keeper none no notes pf04 weak keeper weak keeper none weak keeper none no notes pf05 weak keeper weak keeper none weak keeper none no notes pf06 weak keeper weak keeper none weak keeper none no notes pf07 weak keeper weak keeper none weak keeper none no notes pf08 weak keeper weak keeper none weak keeper none no notes pf09 weak keeper weak keeper none weak keeper none no notes pf10 weak keeper weak keeper none weak keeper none no notes pf11 weak keeper weak keeper none weak keeper none no notes pf12 weak keeper weak keeper none weak keeper none no notes pf13 weak keeper weak keeper none weak keeper none no notes pf14 weak keeper weak keeper none weak keeper none no notes pf15 weak keeper weak keeper none weak keeper none no notes pg00 weak keeper weak keeper none weak keeper none has an optional internal pull-up for use with rsi. see the rsi chapter in the hrm for more details. pg01 weak keeper weak keeper none weak keeper none no notes pg02 weak keeper weak keeper none weak keeper none has an optional internal pull-up for use with rsi. see the rsi chapter in the hrm for more details. pg03 weak keeper weak keeper none weak keeper none has an optional internal pull-up for use with rsi. see the rsi chapter in the hrm for more details. table 8. adsp-bf60x pa d table (continued) signal name internal termination reset termination reset drive hibernate termination hibernate drive notes
rev. prd | page 28 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 preliminary technical data pg04 weak keeper weak keeper none weak keeper none no notes pg05 weak keeper weak keeper none weak keeper none has an optional internal pull-up for use with rsi. see the rsi chapter in the hrm for more details. pg06 weak keeper weak keeper none weak keeper none no notes pg07 weak keeper weak keeper none weak keeper none no notes pg08 weak keeper weak keeper none weak keeper none no notes pg09 weak keeper weak keeper none weak keeper none no notes pg10 weak keeper weak keeper none weak keeper none no notes pg11 weak keeper weak keeper none weak keeper none no notes pg12 weak keeper weak keeper none weak keeper none no notes pg13 weak keeper weak keeper none weak keeper none no notes pg14 weak keeper weak keeper none weak keeper none no notes pg15 weak keeper weak keeper none weak keeper none no notes smc0_a01 weak keeper weak keeper none weak keeper none no notes smc0_a02 weak keeper weak keeper none weak keeper none no notes smc0_ams0 pull-up pull-up none pull-up none no notes smc0_aoe _nordv weak keeper weak keeper none weak keeper none no notes smc0_ardy_norwt none none none none non e requires an external pull-up. smc0_are pull-up pull-up none pull-up none no notes smc0_awe pull-up pull-up none pull-up none no notes smc0_br none none none none none requires an external pull-up. smc0_d00 weak keeper weak keeper none weak keeper none no notes smc0_d01 weak keeper weak keeper none weak keeper none no notes smc0_d02 weak keeper weak keeper none weak keeper none no notes smc0_d03 weak keeper weak keeper none weak keeper none no notes smc0_d04 weak keeper weak keeper none weak keeper none no notes smc0_d05 weak keeper weak keeper none weak keeper none no notes smc0_d06 weak keeper weak keeper none weak keeper none no notes smc0_d07 weak keeper weak keeper none weak keeper none no notes smc0_d08 weak keeper weak keeper none weak keeper none no notes smc0_d09 weak keeper weak keeper none weak keeper none no notes smc0_d10 weak keeper weak keeper none weak keeper none no notes smc0_d11 weak keeper weak keeper none weak keeper none no notes smc0_d12 weak keeper weak keeper none weak keeper none no notes smc0_d13 weak keeper weak keeper none weak keeper none no notes smc0_d14 weak keeper weak keeper none weak keeper none no notes smc0_d15 weak keeper weak keeper none weak keeper none no notes sys_bmode0 none none none none none no notes sys_bmode1 none none none none none no notes sys_bmode2 none none none none none no notes sys_clkin none none none none none active during reset. sys_clkout none none low none none no notes sys_extwake none none high none low drives low during hibernate and high all other times. table 8. adsp-bf60x pa d table (continued) signal name internal termination reset termination reset drive hibernate termination hibernate drive notes
preliminary technical data rev. prd | page 29 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 sys_fault none none none none none open source, requires an external pull- down. sys_fault none none none none none open drain, requires an external pull-up. sys_hwrst none none none none none active during reset. sys_nmi _resout none none low none none requires an external pull-up. sys_pwrgd none none none none none if hibernate isn't used or the internal power good counter is used connect to vdd_ext. sys_tda none none none none none active during reset and hibernate. if the thermal diode is not used connect to ground. sys_tdk none none none none none active during reset and hibernate. if the thermal diode is not used connect to ground. sys_xtal none none none none none leave unconnected if an oscillator is used to provide sys_clkin. active during reset. state during hibernate is controlled by dpm_hib_dis. twi0_scl none none none none none open drain, requires external pull up. consult version 2.1 of the i2c specification for the proper resistor value. if twi is not used connect to ground. twi0_sda none none none none none open drain, requires external pull up. consult version 2.1 of the i2c specification for the proper resistor value. if twi is not used connect to ground. twi1_scl none none none none none open drain, requires external pull up. consult version 2.1 of the i2c specification for the proper resistor value. if twi is not used connect to ground. twi1_sda none none none none none open drain, requires external pull up. consult version 2.1 of the i2c specification for the proper resistor value. if twi is not used connect to ground. usb0_clkin none none none none none if usb is not used connect to ground. active during reset. usb0_dm none none none none none pull low if not using usb. for complete documentation of hibernate behavior when usb is used see the usb chapter in the hrm. usb0_dp none none none none none pull low if not using usb. for complete documentation of hibernate behavior when usb is used see the usb chapter in the hrm. usb0_id none none none pull-up none if usb is not used connect to ground. when usb is being used the internal pull-up that is present during hibernate is programmable. see the usb chapter in the hrm. active during reset. usb0_vbc none none none none none if usb is not used pull low. usb0_vbus none none none none none if usb is not used connect to ground. vdd_dmc none none none none none if the dmc is not used connect to vdd_int. vdd_ext none none none none none must be powered. vdd_int none none none none none must be powered. table 8. adsp-bf60x pa d table (continued) signal name internal termination reset termination reset drive hibernate termination hibernate drive notes
rev. prd | page 30 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 preliminary technical data vdd_td none none none none none if the thermal diode is not used connect to ground. vdd_usb none none none none none if usb is not used connect to vdd_ext. vref_dmc none none none none none if the dmc is not used connect to vdd_int. table 8. adsp-bf60x pa d table (continued) signal name internal termination reset termination reset drive hibernate termination hibernate drive notes
preliminary technical data rev. prd | page 31 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 specifications for information about product specifications please contact your adi representative. operating conditions parameter conditions min nominal max unit v dd_int 1 1 the expected nominal value is 1.25 v 5%, and initial customer designs s hould design with a prog rammable regulator that can be adjusted from 1.1 v to 1.35 v in 50 mv st eps. internal supply voltage tbd mhz tbd tbd tbd v v dd_ext 2 2 must remain powered (even if the as sociated function is not used). external supply voltage tbd 1.8, 3.3 tbd v v dd_dmc ddr2/lpddr supply voltage tbd 1.8 tbd v v dd_usb 3 3 if not used, connect to 1.8 v or 3.3 v. usb supply voltage tbd 3.3 tbd v v dd_td thermal diode supply voltage tbd 3.3 tbd v v ih 4 4 parameter value applies to all input and bidi rectional pins, except twi_sda and twi_scl. high level input voltage v dd_ext = maximum tbd tbd tbd v v ih 4 high level input voltage v dd_ext = maximum tbd tbd tbd v v ihtwi 5 5 parameter applies to twi_sda and twi_scl. high level input voltage v dd_ext = maximum tbd tbd tbd v v il 4 low level input voltage v dd_ext = maximum tbd tbd tbd v v il 4 low level input voltage v dd_ext = maximum tbd tbd tbd v v iltwi 5 low level input voltage v dd_ext = maximum tbd tbd tbd v t j junction temperature t ambient = tbdc to +tbdc C40 tbd 105 c t j junction temperature t ambient = tbdc to +tbdc C40 tbd 125 c
rev. prd | page 32 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 preliminary technical data clock related operating conditions table 9 describes the core clock timing requirements. the data presented in the tables applies to all speed grades (found in automotive products on page 43 ) except where expressly noted. figure 8 provides a graphical repr esentation of the various clocks and their available divider values. table 9. clock operating conditions parameter maximum unit f cclk core clock frequency (cclk sysclk, csel syssel) tbd mhz f sysclk sysclk frequency (syssel dsel) tbd mhz f sclk0 1, 2 sclk0 frequency tbd mhz f sclk1 1, 2 sclk1 frequency tbd mhz f dclk ddr2/lpddr clock frequency tbd mhz f oclk output clock frequency tbd mhz 1 t sclk0/1 is equal to 1/f sclk0/1 . 2 rounded number. actual test specific ation is a period of [tbd] ns. table 10. phase-locked loop operating conditions parameter minimum maximum unit f pllclk pll clock frequency tbd speed grade mhz figure 8. clock relationships and divider values clkin pll dclk sysclk cclk sclk1 (sports, spi, acm) sclk0 (pvp, all other peripherals) csel (1 - 32) syssel (1 - 32) s0sel (1 - 4) s1sel (1 - 4) dsel (1 - 32) oclk osel (1 - 128) pllclk
preliminary technical data rev. prd | page 33 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 electrical characteristics parameter test conditions min typical max unit v oh high level output voltage v dd_ext = 1.7 v, i oh = C0.5 ma tbd v v oh high level output voltage v dd_ext = 3.13 v, i oh = C0.5 ma tbd v v ol low level output voltage v dd_ext = 1.7 v/3.13 v, i ol = 2.0 ma tbd v v oltwi 1 1 applies to bidirectional pins twi_scl and twi_sda. low level output voltage v dd_ext = 1.7 v/3.13 v, i ol =2.0ma tbd v i ih 2 2 applies to input pins. high level input current v dd_ext =3.47 v, v in = 3.47 v tbd a i il 2 low level input current v dd_ext =3.47 v, v in = 0 v tbd a i ihp 3 3 applies to jtag input pins (jtg_tck, jtg_tdi, jtg_tms, jtg_trst) . high level input current jtag v dd_ext = 3.47 v, v in = 3.47 v tbd a i ozh 4 4 applies to three-statable pins. three-state leakage current v dd_ext = 3.47 v, v in = 3.47 v tbd a i ozhtwi 1 three-state leakage current v dd_ext =3.13 v, v in = 5.5 v tbd a i ozl 4 three-state leakage current v dd_ext = 3.47 v, v in = 0 v tbd a c in 5, 6 5 guaranteed, but not tested. 6 applies to all signal pins. input capacitance f in = 1 mhz, t ambient = 25c, v in =2.5v tbd tbd pf i dd_deepsleep 7 7 see the adsp-bf60x blackfin processor hardware reference manual for definition of deep sleep and hibernate operating modes. v dd_int current in deep sleep mode tbd tbd ma i dd_idle v dd_int current in idle tbd tbd ma i dd_typ v dd_int current tbd tbd ma i dd_hibernate 7, 8 8 applies to tbd supply pins only. clock inputs are tied high or low. hibernate state current tbd tbd a i dd_deepsleep v dd_int current in deep sleep mode tbd tbd ma i dd_int v dd_int current tbd tbd ma
rev. prd | page 34 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 preliminary technical data total power dissipation total power dissipation has two components: 1. static, including leakage current 2. dynamic, due to transistor switchin g characteristics many operating conditions can also affect po wer dissipation, including temperature, voltage, operating frequency, and pro- cessor activity. electrical characteristics on page 33 shows the current dissipation for internal circuitry (v dd_int ). i dd_deepsleep specifies static power dissi pation as a function of voltage (v dd_int ) and temperature, and i dd_int specifies the total power specification for the listed test conditions, including the dynamic component as a function of voltage (v dd_int ) and frequency. there are two parts to the dynami c component. the first part is due to transistor switching in the core clock (cclk) domain. this part is subject to an acti vity scaling factor (asf) which represents application code runn ing on the processor core and l1 memories. the asf is combined with the cclk frequency and v dd_int dependent data to calculate this part. the second part is due to transistor switching in the syst em clock (sclk) domain, which is included in the i dd_int specification equation. processor absolute maximum ratings stresses greater than those listed in the table may cause perma- nent damage to the device. these are stress ratings only. functional operation of the device at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd sensitivity processor package information the information presented in figure 9 and table 12 provides details about package branding. for a complete listing of prod- uct availability, see automotive products on page 43 . parameter rating internal supply voltage (v dd_int )tbd external (i/o) supply voltage (v dd_ext )tbd input voltage 1, 2 1 applies to 100% transient duty cycle. for other duty cycles see table 11 . 2 applies only when v dd_ext is within specif ications. when v dd_ext is outside specifications, the range is v dd_ext 0.2 volts. tbd input voltage 1, 2, 3 3 applies to pins twi_scl and twi_sda. tbd output voltage swing tbd load capacitance tbd storage temperature range tbd junction temperature under bias tbd table 11. maximum duty cycle for input transient voltage 1 v in min (v) v in max (v) maximum duty cycle tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd 1 applies to all signal pins with the exception of sys_clkin, sys_xtal, sys_extwake. figure 9. product information on package table 12. package brand information brand key field description adsp-bf60x product name 1 1 see product names in the automotive products on page 43 . t temperature range pp package type z rohs compliant designation ccc see ordering guide vvvvvv.x assembly lot code n.n silicon revision yyww date code esd (e l ectrostatic discharge) sensitive device. charged devi c es and c ir c uit boards c an dis c harge without dete c tion. a l though this produ c t features patented or proprietary prote c tion c ir c uitry, damage may o cc ur on devi c es sub j e c ted to high energy esd. t herefore, proper esd pre c autions shou l d be taken to avoid performan c e degradation or l oss of fun c tiona l ity. d a t a t b d
preliminary technical data rev. prd | page 35 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 environmental conditions to determine the junction te mperature on the application printed circuit board use: where: t j = junction temperature (c) t case = case temperature (c) measured by customer at top center of package. jt = from table 13 p d = power dissipation (see total power dissipation on page 34 for the method to calculate p d ) values of ja are provided for packag e comparison and printed circuit board design considerations. ja can be used for a first order approximation of t j by the equation: where: t a = ambient temperature (c) values of jc are provided for packag e comparison and printed circuit board design considerations when an external heat sink is required. in table 13 , airflow measurements comply with jedec stan- dards jesd51-2 and jesd51-6. the junction-to-case measurement complies with mil-std-883 (method 1012.1). all measurements use a 2s2p jedec test board. thermal diode the processor incorporates ther mal diode/s to monitor the die temperature. the thermal diode is a grounded collector, pnp bipolar junction transistor (b jt). the sys_tda pin is con- nected to the emitter and the sy s_tdk pin is connected to the base of the transistor . these pins can be used by an external temperature sensor (such as adm 1021a or lm86 or others) to read the die temperature of the chip. the technique used by the extern al temperature sensor is to measure the change in v be when the thermal diode is operated at two different currents. this is shown in the following equation: where: n = multiplication factor clos e to 1, depending on process variations k = boltzmanns constant t = temperature (c) q = charge of the electron n = ratio of the two currents the two currents are usually in the range of 10 micro amperes to 300 micro amperes for the common temperature sensor chips available. table 14 contains the thermal diod e specifications using the transistor model. note that me asured ideality factor already takes into effect variations in beta ( ). table 13. thermal characteristics parameter condition typical unit ja 0 linear m/s air flow 16.7 c/w jma 1 linear m/s air flow 14.6 c/w jma 2 linear m/s air flow 13.9 c/w jc 4.41 c/w jt 0 linear m/s air flow 0.11 c/w jt 1 linear m/s air flow 0.24 c/w jt 2 linear m/s air flow 0.25 c/w t j t case jt p d () + = t j t a ja p d () + = v be n kt q ------ in(n) = table 14. thermal diode parameters C transistor model symbol parameter min typ max unit i fw 1 forward bias current tbd tbd a i e emitter current tbd tbd a n q 2, 3 transistor ideality tbd tbd tbd r t 3, 4 series resistance tbd tbd tbd 1 analog devices does not reco mmend operation of the the rmal diode under reverse bias. 2 not 100% tested. specified by design characterization. 3 the ideality factor, nq, represents the deviation from ideal diode behavior as exem plified by the diode equation: i c = i s (e qvbe/nqkt C1), where i s = saturation current, q = electronic charge, v be = voltage across the diode, k = boltzmann constant, and t = absolute temperature (kelvin). 4 the series resistance (r t ) can be used for more acc urate readings as needed.
rev. prd | page 36 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 preliminary technical data 349-ball csp_bga ball assignments table 15 lists the csp_bga package by ball number for the ADSP-BF609. table 16 lists the csp_bga package by signal. table 15. 349-ball csp_bga ball assign ment (numerical by ball number) ball no. signal name ball no. signal name ball no. signal name ball no. signal name a01 gnd aa19 pg_07 b15 smc0_d01 e03 jtg_tms a02 usb0_dm aa20 pg_13 b16 smc0_d15 e05 v dd_usb a03 usb0_dp aa21 gnd b17 smc0_d09 e20 dmc0_cas a04 pb_10 aa22 gnd b18 smc0_d02 e21 dmc0_dq10 a05 pb_07 ab01 gnd b19 smc0_d13 e22 dmc0_dq13 a06 pa_14 ab02 pd_05 b20 smc0_d05 f01 sys_fault a07 pa_12 ab03 pd_14 b21 gnd f02 sys_fault a08 pa_10 ab04 pe_01 b22 smc0_aoe _nordv f03 sys_nmi_resout a09 pa_08 ab05 pe_04 c01 usb0_clkin f06 v dd_ext a10 pa_06 ab06 pf_15 c02 usb0_vbc f07 v dd_int a11 pa_04 ab07 pf_13 c03 gnd f08 v dd_int a12 pa_02 ab08 pf_11 c04 pb_12 f09 v dd_int a13 pa_00 ab09 pf_09 c05 pb_09 f10 v dd_int a14 smc0_a01 ab10 p f_07 c06 pb_06 f11 v dd_ext a15 smc0_d00 ab11 p f_05 c07 pb_05 f12 v dd_ext a16 smc0_ams0 ab12 pf_03 c08 pb_04 f13 v dd_int a17 smc0_d03 ab13 p f_01 c09 pb_03 f14 v dd_int a18 smc0_d04 ab14 pe_13 c10 pb_02 f15 v dd_int a19 smc0_d07 ab15 p g_03 c11 pb_01 f16 v dd_int a20 smc0_d10 ab16 p g_06 c12 pb_00 f17 v dd_dmc a21 smc0_awe ab17 pg_02 c13 smc0_br f20 dmc0_cs0 a22 gnd ab18 pg_12 c14 smc0_d06 f21 dmc0_dq15 aa01 pd_11 ab19 pg_14 c15 smc0_d12 f22 dmc0_dq08 aa02 gnd ab20 pg_15 c16 smc0_are g01 gnd aa03 pd_13 ab21 pg_10 c17 smc0_d08 g02 sys_hwrst aa04 pe_00 ab22 gnd c18 smc0_d11 g03 sys_bmode2 aa05 pe_03 b01 usb0_vbus c19 smc0_d14 g06 v dd_ext aa06 pf_14 b02 gnd c20 gnd g07 v dd_ext aa07 pf_12 b03 usb0_id c21 twi1_scl g08 v dd_int aa08 pf_10 b04 pb_11 c22 twi0_scl g09 v dd_int aa09 pf_08 b05 pb_08 d01 jtg_tdi g10 v dd_ext aa10 pf_06 b06 pa_15 d02 jtg_tdo g11 v dd_ext aa11 pf_04 b07 pa_13 d03 jtg_tck g12 v dd_ext aa12 pf_02 b08 pa_11 d11 v dd_ext g13 v dd_ext aa13 pf_00 b09 pa_09 d12 gnd g14 v dd_int aa14 pg_00 b10 pa_07 d20 smc0_ardy_norwt g15 v dd_int aa15 pe_15 b11 pa_05 d21 twi1_sda g16 v dd_dmc aa16 pe_14 b12 pa_03 d22 twi0_sda g17 v dd_dmc aa17 pg_05 b13 pa_01 e01 jtg_trst g20 dmc0_udm aa18 pg_08 b14 smc0_a02 e02 jtg_emu g21 dmc0_udqs
preliminary technical data rev. prd | page 37 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 g22 dmc0_udqs l06 v dd_ext n20 dmc0_we u01 pc_14 h01 sys_clkin l08 gnd n21 dmc0_dq04 u02 pc_13 h02 sys_xtal l09 gnd n22 dmc0_dq03 u03 pd_09 h03 sys_bmode1 l10 gnd p01 pc_08 u06 v dd_ext h06 v dd_ext l11 gnd p02 pc_07 u07 v dd_int h07 v dd_ext l12 gnd p03 pd_06 u08 v dd_int h16 v dd_dmc l13 gnd p06 v dd_ext u09 v dd_int h17 v dd_dmc l14 gnd p09 gnd u10 v dd_int h20 dmc0_ras l15 gnd p10 gnd u11 v dd_ext h21 dmc0_dq09 l17 v dd_dmc p11 gnd u12 v dd_ext h22 dmc0_dq14 l19 vref_dmc p12 gnd u13 v dd_int j01 gnd l20 dmc0_ck p13 gnd u14 v dd_int j02 sys_pwrgd l21 dmc0_dq06 p14 gnd u15 v dd_int j03 sys_bmode0 l22 dmc0_dq07 p17 v dd_dmc u16 v dd_int j06 v dd_ext m01 pc_04 p20 dmc0_cke u17 v dd_dmc j09 gnd m02 pc_03 p21 dmc0_dq02 u20 dmc0_a09 j10 gnd m03 pb_15 p22 dmc0_dq05 u21 dmc0_a05 j11 gnd m04 gnd r01 pc_10 u22 dmc0_a01 j12 gnd m06 v dd_ext r02 pc_09 v01 pd_00 j13 gnd m08 gnd r03 pd_07 v02 pc_15 j14 gnd m09 gnd r06 v dd_ext v03 pd_10 j17 v dd_dmc m10 gnd r07 v dd_ext v20 dmc0_ba1 j20 dmc0_odt m11 gnd r16 v dd_dmc v21 dmc0_a13 j21 dmc0_dq12 m12 gnd r17 v dd_dmc v22 dmc0_a11 j22 dmc0_dq11 m13 gnd r20 dmc0_ba2 w01 pd_04 k01 pc_00 m14 gnd r21 dmc0_ba0 w02 pd_01 k02 sys_extwake m15 gnd r22 dmc0_a10 w03 pd_12 k03 pb_13 m17 v dd_dmc t01 pc_12 w11 gnd k06 v dd_ext m19 gnd t02 pc_11 w12 v dd_td k08 gnd m20 dmc0_ck t03 pd_08 w20 dmc0_a04 k09 gnd m21 dmc0_dq00 t06 v dd_ext w21 dmc0_a06 k10 gnd m22 dmc0_dq01 t07 v dd_ext w22 dmc0_a08 k11 gnd n01 pc_06 t08 v dd_int y01 pd_03 k12 gnd n02 pc_05 t09 v dd_int y02 pd_02 k13 gnd n03 sys_clkout t10 v dd_ext y03 gnd k14 gnd n06 v dd_ext t11 v dd_ext y04 pd_15 k15 gnd n08 gnd t12 v dd_ext y05 pe_02 k17 v dd_dmc n09 gnd t13 v dd_ext y06 pe_05 k20 dmc0_ldm n10 gnd t14 v dd_int y07 pe_06 k21 dmc0_ldqs n11 gnd t15 v dd_int y08 pe_07 k22 dmc0_ldqs n12 gnd t16 v dd_dmc y09 pe_08 l01 pc_02 n13 gnd t17 v dd_dmc y10 pe_09 l02 pc_01 n14 gnd t20 dmc0_a03 y11 sys_tdk l03 pb_14 n15 gnd t21 dmc0_a07 y12 sys_tda l04 v dd_ext n17 v dd_dmc t22 dmc0_a12 y13 pe_12 table 15. 349-ball csp_bga ball assign ment (numerical by ball number) ball no. signal name ball no. signal name ball no. signal name ball no. signal name
rev. prd | page 38 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 preliminary technical data y14 pe_10 y19 pg_11 y15 pe_11 y20 gnd y16 pg_09 y21 dmc0_a00 y17 pg_01 y22 dmc0_a02 y18 pg_04 table 15. 349-ball csp_bga ball assign ment (numerical by ball number) ball no. signal name ball no. signal name ball no. signal name ball no. signal name
preliminary technical data rev. prd | page 39 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 table 16. 349-ball csp_bga ball assignme nt (alphabetical by signal name) signal name ball no. signal name ball no. signal name ball no. signal name ball no. dmc0_a00 y21 dmc0_udqs g22 gnd m19 pb_03 c09 dmc0_a01 u22 dmc0_we n20 gnd n08 pb_04 c08 dmc0_a02 y22 gnd a01 gnd n09 pb_05 c07 dmc0_a03 t20 gnd a22 gnd n10 pb_06 c06 dmc0_a04 w20 gnd aa02 gnd n11 pb_07 a05 dmc0_a05 u21 gnd aa21 gnd n12 pb_08 b05 dmc0_a06 w21 gnd aa22 gnd n13 pb_09 c05 dmc0_a07 t21 gnd ab01 gnd n14 pb_10 a04 dmc0_a08 w22 gnd ab22 gnd n15 pb_11 b04 dmc0_a09 u20 gnd b21 gnd p09 pb_12 c04 dmc0_a10 r22 gnd c20 gnd p10 pb_13 k03 dmc0_a11 v22 gnd d12 gnd p11 pb_14 l03 dmc0_a12 t22 gnd g01 gnd p12 pb_15 m03 dmc0_a13 v21 gnd j01 gnd p13 pc_00 k01 dmc0_ba0 r21 gnd j09 gnd p14 pc_01 l02 dmc0_ba1 v20 gnd j10 gnd w11 pc_02 l01 dmc0_ba2 r20 gnd j11 gnd y03 pc_03 m02 dmc0_cas e20 gnd j12 gnd y20 pc_04 m01 dmc0_ck m20 gnd j13 gnd c03 pc_05 n02 dmc0_cke p20 gnd j14 gnd b02 pc_06 n01 dmc0_ck l20 gnd k08 jtg_emu e02 pc_07 p02 dmc0_cs0 f20 gnd k09 jtg_tck d03 pc_08 p01 dmc0_dq00 m21 gnd k10 jtg_tdi d01 pc_09 r02 dmc0_dq01 m22 gnd k11 jtg_tdo d02 pc_10 r01 dmc0_dq02 p21 gnd k12 jtg_tms e03 pc_11 t02 dmc0_dq03 n22 gnd k13 jtg_trst e01 pc_12 t01 dmc0_dq04 n21 gnd k14 pa_00 a13 pc_13 u02 dmc0_dq05 p22 gnd k15 pa_01 b13 pc_14 u01 dmc0_dq06 l21 gnd l08 pa_02 a12 pc_15 v02 dmc0_dq07 l22 gnd l09 pa_03 b12 pd_00 v01 dmc0_dq08 f22 gnd l10 pa_04 a11 pd_01 w02 dmc0_dq09 h21 gnd l11 pa_05 b11 pd_02 y02 dmc0_dq10 e21 gnd l12 pa_06 a10 pd_03 y01 dmc0_dq11 j22 gnd l13 pa_07 b10 pd_04 w01 dmc0_dq12 j21 gnd l14 pa_08 a09 pd_05 ab02 dmc0_dq13 e22 gnd l15 pa_09 b09 pd_06 p03 dmc0_dq14 h22 gnd m04 pa_10 a08 pd_07 r03 dmc0_dq15 f21 gnd m08 pa_11 b08 pd_08 t03 dmc0_ldm k20 gnd m09 pa_12 a07 pd_09 u03 dmc0_ldqs k22 gnd m10 pa_13 b07 pd_10 v03 dmc0_ldqs k21 gnd m11 pa_14 a06 pd_11 aa01 dmc0_odt j20 gnd m12 pa_15 b06 pd_12 w03 dmc0_ras h20 gnd m13 pb_00 c12 pd_13 aa03 dmc0_udm g20 gnd m14 pb_01 c11 pd_14 ab03 dmc0_udqs g21 gnd m15 pb_02 c10 pd_15 y04
rev. prd | page 40 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 preliminary technical data pe_00 aa04 pg_13 aa20 usb0_clkin c01 v dd_ext t10 pe_01 ab04 pg_14 ab19 usb0_dm a02 v dd_ext t11 pe_02 y05 pg_15 ab20 usb0_dp a03 v dd_ext t12 pe_03 aa05 smc0_a01 a14 usb0_id b03 v dd_ext t13 pe_04 ab05 smc0_a0 2 b14 usb0_vbc c02 v dd_ext u06 pe_05 y06 smc0_ams0 a16 usb0_vbus b01 v dd_ext u11 pe_06 y07 smc0_aoe _nordv b22 v dd_dmc f17 v dd_ext u12 pe_07 y08 smc0_ardy_norwt d20 v dd_dmc g16 v dd_int f07 pe_08 y09 smc0_are c16 v dd_dmc g17 v dd_int f08 pe_09 y10 smc0_awe a21 v dd_dmc h16 v dd_int f09 pe_10 y14 smc0_br c13 v dd_dmc h17 v dd_int f10 pe_11 y15 smc0_d00 a15 v dd_dmc j17 v dd_int f13 pe_12 y13 smc0_d01 b15 v dd_dmc k17 v dd_int f14 pe_13 ab14 smc0_d02 b18 v dd_dmc l17 v dd_int f15 pe_14 aa16 smc0_d03 a17 v dd_dmc m17 v dd_int f16 pe_15 aa15 smc0_d04 a18 v dd_dmc n17 v dd_int g08 pf_00 aa13 smc0_d05 b20 v dd_dmc p17 v dd_int g09 pf_01 ab13 smc0_d06 c14 v dd_dmc r16 v dd_int g14 pf_02 aa12 smc0_d07 a19 v dd_dmc r17 v dd_int g15 pf_03 ab12 smc0_d08 c17 v dd_dmc t16 v dd_int t08 pf_04 aa11 smc0_d09 b17 v dd_dmc t17 v dd_int t09 pf_05 ab11 smc0_d10 a20 v dd_dmc u17 v dd_int t14 pf_06 aa10 smc0_d11 c18 v dd_ext d11 v dd_int t15 pf_07 ab10 smc0_d12 c15 v dd_ext f06 v dd_int u07 pf_08 aa09 smc0_d13 b19 v dd_ext f11 v dd_int u08 pf_09 ab09 smc0_d14 c19 v dd_ext f12 v dd_int u09 pf_10 aa08 smc0_d15 b16 v dd_ext g06 v dd_int u10 pf_11 ab08 sys_bmode0 j03 v dd_ext g07 v dd_int u13 pf_12 aa07 sys_bmode1 h03 v dd_ext g10 v dd_int u14 pf_13 ab07 sys_bmode2 g03 v dd_ext g11 v dd_int u15 pf_14 aa06 sys_clkin h01 v dd_ext g12 v dd_int u16 pf_15 ab06 sys_clkout n03 v dd_ext g13 v dd_td w12 pg_00 aa14 sys_extwake k02 v dd_ext h06 v dd_usb e05 pg_01 y17 sys_fault f02 v dd_ext h07 vref_dmc l19 pg_02 ab17 sys_fault f01 v dd_ext j06 pg_03 ab15 sys_nmi_resout f03 v dd_ext k06 pg_04 y18 sys_pwrgd j02 v dd_ext l04 pg_05 aa17 sys_hwrst g02 v dd_ext l06 pg_06 ab16 sys_tda y12 v dd_ext m06 pg_07 aa19 sys_tdk y11 v dd_ext n06 pg_08 aa18 sys_xtal h02 v dd_ext p06 pg_09 y16 twi0_scl c22 v dd_ext r06 pg_10 ab21 twi0_sda d22 v dd_ext r07 pg_11 y19 twi1_scl c21 v dd_ext t06 pg_12 ab18 twi1_sda d21 v dd_ext t07 table 16. 349-ball csp_bga ball assignme nt (alphabetical by signal name) signal name ball no. signal name ball no. signal name ball no. signal name ball no.
preliminary technical data rev. prd | page 41 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 figure 10. 349-ball csp_bga ball configuration a1 ball pad corner 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 17 18 19 20 21 22 m b c d e f g h j k l n r t a u v w y aa ab p vdd_int vdd_ext gnd i/o signals d vdd_dmc d d d d d d d d d d d d d d d d u u vdd_usb a1 ball pad corner 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 17 18 19 20 21 22 m b c d e f g h j k l n r t a u v w y aa ab p d d d d d d d d d d d d d d d d u top view bottom view t vdd_td t t
rev. prd | page 42 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 preliminary technical data outline dimensions dimensions for the 19 mm 19 mm csp_bga package in figure 11 are shown in millimeters. surface-mount design table 17 is provided as an aid to pcb design. for industry-stan- dard design recommendations, refer to ipc-7351, generic requirements for surface-mount design and land pattern standard . figure 11. 349-ball chip scale package ball grid array [csp_bga] (bc-349-1) dimensions shown in millimeters compliant to jedec standards mo-275-ppab-2. 1.10 ref a b c d e f g h j k l m n p r t v w aa ab u y 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16 17 18 19 20 21 22 16.80 bsc sq 0.50 0.45 0.40 19.10 19.00 sq 18.90 coplanarity 0.20 bottom view detail a top view 1.50 1.36 1.21 0.35 nom 0.30 min ball diameter seating plane a1 ball corner a1 ball corner detail a 0.80 bsc 1.11 1.01 0.91 table 17. bga data for use with surface-mount design package package ball attach type package solder mask opening package ball pad size bc-349-1 solder mask defined 0.4 mm diameter 0.5 mm diameter
preliminary technical data rev. prd | page 43 of 44 | march 2012 adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609 automotive products the tbd model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that these automotive models may have spec- ifications that differ from the commercial models and designers should review the product specif ications section of this data sheet carefully. only the automo tive grade products shown in below are available for use in automotive applications. contact your local adi account represen tative for specific product ordering information and to obtain the specific automotive reliability reports for these models. pre release products model temperature range 1 package description package option processor instruction rate (max) tbd tbd 349-ball chip scale package ball grid array bc-349-1 500 mhz 1 referenced temperature is ambient temperature. the ambie nt temperature is not a sp ecification. please see operating conditions on page 31 for the junction temperature (tj) specification wh ich is the only tempe rature specification. model temperature range 1 1 referenced temperature is ambient temperature. the ambie nt temperature is not a sp ecification. please see operating conditions on page 31 for the junction temperature (tj) specification wh ich is the only tempe rature specification. package description package option processor instruction rate (max) ADSP-BF609-eng tbd 349-ball chip scale package ball grid array bc-349-1 500 mhz
rev. prd | page 44 of 44 | march 2012 preliminary technical data ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. pr10659-0-3/12(prd) adsp-bf606/adsp-bf607/adsp-bf608/ADSP-BF609

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