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? 2004 fairchild semiconductor corporation www.fairchildsemi.com september 2006 fms6501 rev. 1.0.2 fms6501 12 input / 9 ou tput video switch matrix with input clamp, input bias circuitry, and output drivers fms6501 12 input / 9 output video switch matrix with input clamp, input bias circuitry, and output drivers features 12 x 9 crosspoint matrix supports sd, ps, and hd 1080i/1080p video input clamp / bias circuitry ac or dc-coupled inputs ac or dc-coupled outputs dual-load (75 ) output drivers with high-impedance disable one-to-one or one-to-many input to output switching programmable gain: +6, +7, +8, or +9db i 2 c tm compatible digital interface, standard mode 3.3v or 5v single-supply operation lead-free ssop-28 package applications cable and satellite set-top boxes tv and hdtv sets a/v switchers personal video recorders (pvr) security / surveillance video distribution automotive (in-cabin entertainment) description the fms6501 switch matrix provides flexible options for today?s video applications. the 12 inputs that can be routed to any of nine outputs. each input can be routed to one or more outputs, but only one input may be routed to any one output. the input to output routing is con- trolled via an i 2 c?-compatible digital interface. each input supports an integrated clamp option to set the output sync tip level of video with sync to ~300mv. alter- natively, the input may be internally biased to center sig- nals without sync (chroma, pb, pr) at ~1.25v. these dc output levels are for the 6db gain setting. higher gain settings increase the dc output levels accordingly. the input clamp / bias mode is selected via i 2 c. unused outputs may be powered down to reduce power dissipation. ordering information part number pb-free temperature range package container quantity fms6501msa28 yes 0c to 85c ssop-28 rail 47 fms6501msa28x yes 0c to 85c ssop-28 reel 2000
fms6501 12 input / 9 ou tput video switch matrix with input clamp, input bias circuitry, and output drivers ? 2004 fairchild semiconductor corporation www.fairchildsemi.com fms6501 rev. 1.0.2 2 block diagram figure 1. fms6501 block diagram c / b in1 out1 out2 out9 c / b in2 c / b in12 sda scl vcc (2) gnd (2) programmable gain 6, 7, 8, or 9db addr programmable enable/disable
fms6501 12 input / 9 ou tput video switch matrix with input clamp, input bias circuitry, and output drivers ? 2004 fairchild semiconductor corporation www.fairchildsemi.com fms6501 rev. 1.0.2 3 pin configuration figure 2. pin configuration in1 in3 out2 vcco out7 20 19 18 1 2 3 4 5 6 7 scl out6 out5 out3 17 16 15 8 9 10 out1 11 12 13 21 22 23 24 25 26 14 27 28 in2 out4 gndo out8 out9 sda addr in7 in8 in9 in5 in4 vcc in6 in12 in11 in10 gnd fairchild fms6501 28l ssop pin assignments pin# name type description 1 in1 input input, channel 1 2 in2 input input, channel 2 3 in3 input input, channel 3 4 in4 input input, channel 4 5 in5 input input, channel 5 6 in6 input input, channel 6 7 vcc input positive power supply 8 gnd input must be tied to ground 9 in7 input input, channel 7 10 in8 input input, channel 8 11 in9 input input, channel 9 12 in10 input input, channel 10 13 in11 input input, channel 11 14 in12 input input, channel 12 15 addr input selects i 2 c address. ?0? = 0x06 (0000 0110), ?1? = 0x86 (1000 0110) 16 scl input serial clock for i 2 c port 17 sda input serial data for i 2 c port 18 out9 output output, channel 9 19 out8 output output, channel 8 20 out7 output output, channel 7 21 gndo input must be tied to ground 22 vcco input positive power supply for output drivers 23 out6 output output, channel 6 24 out5 output output, channel 5 25 out4 output output, channel 4 26 out3 output output, channel 3 27 out2 output output, channel 2 28 out1 output output, channel 1
fms6501 12 input / 9 ou tput video switch matrix with input clamp, input bias circuitry, and output drivers ? 2004 fairchild semiconductor corporation www.fairchildsemi.com fms6501 rev. 1.0.2 4 absolute maximum ratings the ?absolute maximum ratings? are those values beyond wh ich the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum ratings. the ?r ecommended operating conditions? table defines the condi- tions for actual device operation. reliability information recommended oper ating conditions parameter min. max. unit dc supply voltage -0.3 6.0 v analog and digital i/o -0.3 v cc + 0.3 v output current any one channel, do not exceed 40 ma symbol parameter min. typ. max. unit t j junction temperature 150 c t stg storage temperature range -65 150 c t l lead temperature (soldering, 10 seconds) 300 c ja thermal resistance, jedec standard multilayer test board, still air 50 c/w symbol parameter min. typ. max. unit t a operating temperature range 0 85 c v cc supply voltage range 3.135 5.000 5.250 v
fms6501 12 input / 9 ou tput video switch matrix with input clamp, input bias circuitry, and output drivers ? 2004 fairchild semiconductor corporation www.fairchildsemi.com fms6501 rev. 1.0.2 5 digital interface the i 2 c-compatible interface is used to program output enables, input to output routing, input clamp / bias, and output gain. the i 2 c address of the fms6501 is 0x06 (0000 0110) with the ability to offset it to 0x86 (1000 0110) by tying the addr pin high. both data and address data, of eight bits each, are writ- ten to the i 2 c address to access al l the control functions. there are separate internal addresses for each output. each output?s address includes bits to select an input channel, adjust the output gain, and enable or disable the output amplifier. more th an one output can select the same input channel for one-to-many routing. when the outputs are disabled, they are placed in a high-imped- ance state. this allows multiple fms6501 devices to be paralleled to create a larger switch matrix. typical output power-up time is less than 500ns. the clamp / bias control bits are written to their own internal address, since they should always remain the same regardless of signal routing. they are set based on the input signal connected to the fms6501. all undefined addresses may be written without effect. output control register contents and defaults notes: 1. power down places the output in a high-impedance state so multiple fms 6501 devices may be paralleled. power down also de-selects any input r outed to the specified output. 2. when all inputs are off, the amplifier input is tied to approximately 150mv and the output goes to approximately 300mv with the 6db gain setting. output control register map notes: 1. in4 is provided for forward compatibility and should always be written as ?0? in the fms6501. clamp control register contents and defaults clamp control register map control name width type default bit(s) description enable 1 bit write 0 7 channel enable: 1=enable, 0=power down (1) gain 2 bits write 0 6:5 channel gain: 00=6db, 01=7db, 10=8db, 11=9db inx 5 bits write 0 4:0 input selected to drive this output: 00000=off (2) , 00001=in1, 00010=in2... 01100=in12 register name register address bit 7 bit 6 bit5 bit4 (1) bit3 bit2 bit1 bit0 out1 0x01 enable gain1 gain0 in4 in3 in2 in1 in0 out2 0x02 enable gain1 gain0 in4 in3 in2 in1 in0 out3 0x03 enable gain1 gain0 in4 in3 in2 in1 in0 out4 0x04 enable gain1 gain0 in4 in3 in2 in1 in0 out5 0x05 enable gain1 gain0 in4 in3 in2 in1 in0 out6 0x06 enable gain1 gain0 in4 in3 in2 in1 in0 out7 0x07 enable gain1 gain0 in4 in3 in2 in1 in0 out8 0x08 enable gain1 gain0 in4 in3 in2 in1 in0 out9 0x09 enable gain1 gain0 in4 in3 in2 in1 in0 control name width type default bit(s) description clmp 1 bit write 0 7:0 clamp / bias selection: 1 = clamp, 0 = bias register name register address bit 7 bit 6 bit 5bit4bit3bit2bit1bit0 clamp1 0x1d clmp8 clmp7 clmp6 clmp5 clmp4 clmp3 clmp2 clmp1 clamp2 0x1e resv?d resv?d resv?d resv?d clmp12 clmp11 clmp10 clmp9
fms6501 12 input / 9 ou tput video switch matrix with input clamp, input bias circuitry, and output drivers ? 2004 fairchild semiconductor corporation www.fairchildsemi.com fms6501 rev. 1.0.2 6 dc electrical characteristics t a = 25c, v cc = 5v, v in = 1v pp , input bias mode, one-to-one routing, 6db gain, all inputs ac coupled with 0.1f, unused inputs ac-terminated through 75 to gnd, all outputs ac coupled with 220f into 150 loads, referenced to 400khz, unless otherwise noted. notes: 1. 100% tested at 25c. ac electrical characteristics t a = 25c, v cc = 5v, v in = 1v pp , input bias mode, one-to-one routing, 6db gain, all inputs ac coupled with 0.1f, unused inputs ac-terminated through 75 to gnd, all outputs ac coupled with 220f into 150 loads, referenced to 400khz, unless otherwise noted. notes: 1. 100% tested at 25c. 2. adjacent input pair to adjacent output pair. interfering inpu t is through an open switch. 3. adjacent input pair to adjacent output pair. interfering input is through a closed switch. 4. crosstalk of eight synchronous switching output s onto single, asynchronous switching output. 5. signal-to-noise ration (snr) = 20 * log (714mv / rms noise). symbol parameter conditions min. typ. max units i cc supply current 1 no load, all outputs enabled 80 100 ma v out video output range 2.8 v pp r off off channel output impedance output disabled 3.0 k v clamp dc output level 1 clamp mode 0.2 0.3 0.4 v v bias dc output level 1 bias mode 1.15 1.25 1.35 v psrr power supply rejection ratio all channels, dc 50 db symbol parameter conditions min. typ. max units av sd channel gain (1) error all channels, all gain settings, dc -0.2 0 +0.2 db av step gain step (1) all channels, dc 0.9 1.0 1.1 db f +1db 1db peaking bandwidth v out = 1.4v pp 65 mhz f -1db -1db bandwidth v out = 1.4v pp 90 mhz f c -3db bandwidth v out = 1.4v pp 115 mhz dg differential gain 3.58mhz 0.1 % dp differential phase 3.58mhz 0.2 deg thd sd sd output distortion v out = 1.4v pp , 5mhz 0.05 % thd hd hd output distortion v out = 1.4v pp , 22mhz 0.6 % x talk1 input crosstalk 1mhz, v out = 2v pp (2) -72 db x talk2 input crosstalk 15mhz, v out = 2v pp (2) -50 db x talk3 output crosstalk 1mhz, v out = 2v pp (3) -68 db x talk4 output crosstalk 15mhz, v out = 2v pp (3) -61 db x talk5 multi-channel crosstalk standard video, v out = 2v pp (4) -45 db snr sd signal-to-noise ratio (5) ntc-7 weighting, 4.2mhz lp, 100khz hp 73 db v noise channel noise 400khz to 100mhz, input referred 20 nv/rthz amp on amplifier recovery time post i 2 c programming 300 ns
fms6501 12 input / 9 ou tput video switch matrix with input clamp, input bias circuitry, and output drivers ? 2004 fairchild semiconductor corporation www.fairchildsemi.com fms6501 rev. 1.0.2 7 i 2 c bus characteristics t a = 25c and v cc = 5v unless otherwise noted. notes: 1. 100% tested at 25c. figure 3. i 2 c bus timing symbol parameter conditions min. typ. max units v il digital input low (1) sda, scl, addr 0 1.5 v v ih digital input high (1) sda, scl, addr 3.0 v cc v f scl clock frequency sck 100 khz tr input rise time 1.5v to 3v 1000 ns tf input fall time 1.5v to 3v 300 ns t low clock low period 4.7 s t high clock high period 4.0 s t su,dat data set-up time 300 ns t hd,dat data hold time 0 ns t su,sto set-up time from clock high to stop 4 s t buf start set-up time following a stop 4.7 s t hd,sta start hold time 4 s t su,sta start set-up time following clock low to high 4.7 s sda scl sda t buf t low t f t hd,sta t r t hd,dat t high t su,dat t su,sto t su,sta
fms6501 12 input / 9 ou tput video switch matrix with input clamp, input bias circuitry, and output drivers ? 2004 fairchild semiconductor corporation www.fairchildsemi.com fms6501 rev. 1.0.2 8 i 2 c interface figure 4. bit transfer figure 5. definition of start and stop conditions operation the i 2 c-compatible interface conforms to the i 2 c spec- ification for standard mode. individual addresses may be written. there is no read capability. the interface consists of two lines. these is a serial data line (sda) and a serial clock line (scl), both of which must be connected to a positive supply through an external resistor. data transfer may be initiated only when the bus is not busy. bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse. changes in the line during this time are interpreted as a control signal. data line stable; data valid scl sda change of data allowed start and stop conditions the data and clock lines remain high when the bus is not busy. a high-to-low tr ansition of the data line, while the clock is high, is defined as start condition (s). a low-to-high transitio n of the data line, while the clock is high, is defined as stop condition (p). sp start condition stop condition scl sda
fms6501 12 input / 9 ou tput video switch matrix with input clamp, input bias circuitry, and output drivers ? 2004 fairchild semiconductor corporation www.fairchildsemi.com fms6501 rev. 1.0.2 9 acknowledge the data bytes transferred between the start and stop conditions from transm itter to receiver is unlim- ited. each byte of eight bits is followed by an acknowl- edge bit. the acknowledge bit is a high-level signal put on the bus by the transmitter, during which the master generates an extra acknowle dge-related clock pulse. a slave receiver must generate an acknowledge after the reception of each byte. a ma ster receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges must pull down the sda line during the acknowledge clock pulse so the sda line is stable low during the high period of the acknowl- edge-related clock pulse (set-up and hold times must be taken into consideration). a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. figure 6. acknowledgement on the i 2 c bus i 2 c bus protocol before any data is transmitted on the i 2 c bus, the device that should respond is addressed first. the addressing is always carried out with the first byte transmitted after the start procedure. the i 2 c bus configuration for a data write to the fms6501 is shown in figure 5. figure 7. write a register address to the pointer register, then write data to the selected register scl from master data output by transmitter data output by receiver start condition 12 89 clock pulse for acknowledgement a6 a5 a4 a3 a2 a1 a0 19 r/w d7 d6 d5 d4 d3 d2 d1 d0 1 9 ack. by fms6501 ack. by fms6501 frame1 serial bus address byte frame 2 address pointer register byte 19 d7 d6 d5 d4 d3 d2 d1 d0 ack. by fms6501 frame 3 data byte scl sda start by master stop by master scl (continued) sda (continued)
fms6501 12 input / 9 ou tput video switch matrix with input clamp, input bias circuitry, and output drivers ? 2004 fairchild semiconductor corporation www.fairchildsemi.com fms6501 rev. 1.0.2 10 applications information input clamp / bias circuitry the fms6501 accommodates ac- or dc-coupled inputs. internal clamping and bias circuitry are provided to sup- port ac-coupled inputs. these are selectable through the clmp bits via the i 2 c compatible interface. for dc-coupled inputs, the device should be pro- grammed to use the 'bias' inpu t configuration. in this con- figuration, the input is inter nally biased to 625mv through a 100k resistor. distortion is optimized with the output levels set between 250mv above ground and 500mv below the power supply. these constraints, along with the desired channel gain, need to be considered when configuring the input signal levels for input dc coupling. with ac-coupled inputs, the fms6501 uses a simple clamp rather than a full dc-restore circuit. for video sig- nals with and without sync (y,c v,r,g,b), the lowest volt- age at the output pins is clamped to approximately 300mv above ground when the 6db gain setting is selected. if symmetric ac-coupled input signals are used (chroma,pb,pr,cb,cr), the bias circuit described above can be used to center them within the input common range. the average dc value at the output is approxi- mately 1.27v with a 6db gain setting. this value changes depending upon the selected gain setting. figure 8 shows the clamp mode input circuit and the internally controlled voltage at the input pin for ac-cou- pled inputs. figure 8. clamp mode input circuit figure 9 shows the bias mode input circuit and internally controlled voltage at the input pin for ac-coupled inputs. figure 9. bias mode input circuit output configuration the fms6501 outputs may be either ac or dc coupled. resistive output loads can be as low as 75 , represent- ing a dual, doubly terminated video load. high imped- ance, capacitive loads up to 20pf can also be driven without loss of signal in tegrity. for standard 75 video loads, a 75 matching resistor should be placed in series to allow for a doubly terminated load. dc-coupled outputs should be connected as shown in figure 10. figure 10. dc-coupled load connection if multiple low-impedance loads are dc coupled, increased power and thermal issues need to be addressed. in this case, the use of a multilayer board with a large ground plane to help dissipate heat is rec- ommended. if a two-layer board is used under these conditions, an extended ground plane directly under the device is recommended. this plane should extend at least 0.5 inches beyond the device. pc board layout issues are covered in the layout considerations section. ac-coupled loads should be configured as in figure 11: figure 11. ac-coupled load connection gain setting clamp voltage bias voltage 6db 300mv 1.27v 7db 330mv 1.43v 8db 370mv 1.60v 9db 420mv 1.80v fms6501 input clamp 75 0.1f video source must be ac-coupled lowest voltage set to 125mv fms6501 input bias 75 0.1f video source must be ac-coupled lowest voltage set to 625mv 75 fms6501 output amplifier 75 75 fms6501 output amplifier 220f 75
fms6501 12 input / 9 ou tput video switch matrix with input clamp, input bias circuitry, and output drivers ? 2004 fairchild semiconductor corporation www.fairchildsemi.com fms6501 rev. 1.0.2 11 thermal issues are significantly reduced with ac-cou- pled outputs, alleviating special pc layout requirements. each of the outputs can be independently powered down and placed in a high-impedance state with the enable bit. this function can be used to mute video signals, to parallel multiple fms6501 outputs, or to save power. when the output amplifier is disabled, the high-imped- ance output presents a 3k load to ground. the output amplifier typically enters and recovers from the power- down state in less than 300ns after being programmed. when an output channel is not connected to an input, the input to that channel?s amplifier is forced to approxi- mately 150mv. the output amplifier is still active unless specifically disabled by the i 2 c interface. voltage output levels depend on the programmed gain for that channel. crosstalk crosstalk is an important consideration when using the fms6501. input and output crosstalk are defined to rep- resent the two major coupling modes in a typical applica- tion. input crosstalk is crosstalk in the input pins and switches when the interfering signal drives an open switch. it is dominated by inductive coupling in the pack- age lead frame between adjacent leads. it decreases rapidly as the interfering signal moves farther away from the pin adjacent to the input signal selected. output crosstalk is coupling from one driven output to another active output. it decreases with increasing load imped- ance, as it is caused main ly by ground and power cou- pling between output amplifiers. if a signal is driving an open switch, its crosstalk is main ly input crosstalk. if it is driving a load through an active output, its crosstalk is mainly output crosstalk. input and output crosstalk measurements are performed with the test configurat ion shown in figure 12. figure 12. test configuration for crosstalk for input crosstalk, the switch is open. all inputs are in bias mode. channel 1 input is driven with a 1v pp signal, while all other inputs are ac terminated with 75 . all out- puts are enabled and crosstalk is measured from in1 to any output. for output crosstalk, the swit ch is closed. crosstalk from out1 to any output is measured. crosstalk from multiple sources into a given channel was measured with the setup shown in figure 6. input in1 is driven with a 1v pp pulse source and is connected to out- puts out1 to out8. input in9 is driven with a secondary, asynchronous, gray-field video signal, and is connected to out9. all other inputs are ac terminated with 75 . crosstalk effects on the gray field are measured and cal- culated with respect to a standard 1v pp output measured at the load. if not all inputs and outputs are needed, avoid using adjacent channels, where possible, to reduce crosstalk. disable all unused channels to further reduce crosstalk and power dissipation. figure 13. test configuration for multi-channel crosstalk bias in1 out1 bias in12 out9 gain = 6db out1 = 2.0vpp input crosstalk from in1 to outx output crosstalk from out1 to outx termination in2 - in12 are ac-term to ground with in1 = 1vpp open switch for input crosstalk close switch for output crosstalk 75 bias in1 out1 bias in12 out9 gain = 6db out1 = 2.0vpp measure crosstalk from channels 1-8 into channel 9 termination bias in9 in1 driven with sd videio 1vpp in9 driven with asynchronous sd video 1vpp in2-8 + in10-12 driven with a c term to gnd with 75
fms6501 12 input / 9 ou tput video switch matrix with input clamp, input bias circuitry, and output drivers ? 2004 fairchild semiconductor corporation www.fairchildsemi.com fms6501 rev. 1.0.2 12 layout considerations general layout and supply bypassing play major roles in high-frequency performance and thermal characteristics. fairchild offers a demonstration board, fms6501demo, to use as a guide for layout and to aid in device testing and characterization. the fms6501demo is a 4-layer board with a full power and ground plane. for optimum results, follow the steps be low as a basis for high fre- quency layout. include 10f and 0.1f bypass capacitors. place the 10f capacitor within 0.75 inches of the power pin. place the 0.1f capacitor within 0.1 inches of the power pin. connect all external ground pins as tightly as possible, preferably with a large ground plane under the package. layout channel connections to reduce mutual trace inductance. minimize all trace lengths to reduce series induc- tances. if routing across a board, place device such that longer traces are at the inputs rather than the outputs. if using multiple, low-impedance, dc-coupled outputs, special layout techniques may be employed to help dissi- pate heat. if a multilayer board is used, a large ground plane directly under the device helps reduce package case temperature. for dual-layer boards, an extended plane can be used. worst-case, additional die power due to dc loading can be estimated at (v cc 2 /4r load ) per output channel. this assumes a constant dc output voltage of v cc /2. for 5v v cc with a dual-dc video load, add 25/(4*75) = 83mw, per channel. fms6501 video switch matrix applications the increased demand for consumer multimedia sys- tems has created a challe nge for system designers to provide cost-effective solutions to capitalize on the growth potential in graphics display technologies. these applications requires cost-effective video switching and filtering solutions to deploy high-quality display technolo- gies rapidly and effectively to the target audience. areas of specific interest include hdtv, media centers, and automotive ?infotainment? (includes navigation, in-cabin entertainment, and back-up camera). in all cases, the advantages an integrated video switch matrix provides are high quality video switching specific to the applica- tion, as well as video input clamps and on-chip, low- impedance output cable driv ers with switchable gain. generally the largest application for a video switch is for the front end of an hdtv, where it takes multiple inputs and routes them to appropriate signal paths (main pic- ture and picture in picture - pip). these are normally routed into adcs followed by decoders. there are many different technologies for hdtv; including lcd, plasma, and crt, with similar analog switching circuitry. an example of a hdtv application is shown in figure 14. this system combines a video switch matrix and two three-channel switchable anti-aliasing filters. there are two three-channel signal paths in the system; one for the main picture, the other for ?picture in picture? (pip). vipdemo tm control software the fms6501 is configured via an i 2 c-compatible digital interface. to facilitate dem onstration, fairchild semicon- ductor had developed the vipdemo tm gui-based con- trol software to write to the fms6501 register map. this software is included in the fms6501demo kit. also included is a parallel port i 2 c adapter and an interface cable to connect to the demo board. besides using the full fms6501 interface, the vipdemo tm can also be used to control single-register read and writes for i 2 c. figure 14. hdtv application using the fms6501 video switch matrix rf/tuner adc v ideo decoder fms6501 video switch matrix controller chip scaling engine pci interface antenna catv / satellite cvbs s-video 1 s-video 2 yprpb (sd) yprpb (hd) lcd display lvds (tx) lvds (rx) adc v ideo decoder fms6407 anti- aliasing filter 3 3 fms6407 anti- aliasing filter 3 3 cvbs 3 3 main picture picture in picture 2 2
fms6501 12 input / 9 ou tput video switch matrix with input clamp, input bias circuitry, and output drivers ? 2004 fairchild semiconductor corporation www.fairchildsemi.com fms6501 rev. 1.0.2 13 physical dimensions dimensions are in millimet ers unless otherwise noted. ssop-28 figure 15. fms6501 28-lead small scale outline package (ssop)
fms6501 12 input / 9 ou tput video switch matrix with input clamp, input bias circuitry, and output drivers ? 2004 fairchild semiconductor corporation www.fairchildsemi.com fms6501 rev. 1.0.2 14

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