pll102 - 108 programmable ddr zero delay clock driver 47745 fremont blvd., fremont, california 94538 t el (510) 492 - 0990 fax (510) 492 - 0991 rev 03/29/02 page 1 features pll clock distribution optimized for double data rate sdram application up to 266mhz. distributes one clock input to one bank of ten differential ou t puts. track spread spectrum clocking for emi reduction. programmable delay between clk_int and cl k[t/c] from ? 0.8ns to +3.1ns by programming clkint and fbout skew channel, or from ? 1.1ns to +3.5ns if additional ddr skew cha n nels are enabled. four independent programmable ddr skew chan - nels from ? 0.3ns to +0.4ns with step size 100ps. support 2 - wire i2 c serial bus interface. 2.5v operating voltage. available in 48 - pin 300mil ssop. descriptions the pll102 - 108 is a zero delay buffer that distri b utes a single - ended clock input to ten pairs of diffe r ential clock outputs and one feedback clock output. outp ut signal duty cycles are adjusted to 50%, ind e pendent of the duty cycle at clk_int. the pll can be b y passed for test purposes by strapping av dd to ground. pin configuration block diagram pll102-108 clkt4 clkt3 clkc3 gnd agnd avdd vdd n/c sclk vdd clkc2 gnd gnd clkt1 vdd clkt0 clkc0 gnd gnd clkc4 vdd clkt2 gnd gnd clkc7 clkt7 vdd sdata n/c fb_int vdd fb_outt n/c gnd clkc5 clkt5 vdd clkt6 clkc6 gnd vdd clkc8 clkt8 clkc9 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 41 42 44 43 45 46 47 48 clk_int clkc1 clkt9 clk_int fb_int control logic fb_outt clkt0 clkc0 clkt1 clkc1 clkt5 clkc5 clkt2 clkc2 clkt3 clkc3 clkt4 clkc4 clkt7 clkc7 clkt8 clkc8 clkt9 clkc9 clkt6 clkc6 av dd av dd -600~+800ps 200ps step -300~+400ps 100ps step -300~+400ps 100ps step -300~+400ps 100ps step -300~+400ps 100ps step (0~2.5ns) +170ps step pll programmable delay channel programmable skew channel
pll102 - 108 programmable ddr zero delay clock driver 47 745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 rev 03/29/02 page 2 pin descriptions name number type description vdd 4,11,15,21, 28,34, 38,45 p 2.5v power supply. gnd 1,7,8,18,24, 25,31,41,42,48 p ground avdd 16 p analog power supply (2.5v). agnd 17 p analog ground. clkt(0:9) 3,5,10,20,22,46, 44,39,29,27 i ?true? clocks of differential pair outputs. clkc(0:9) 2,6,9,19,23,47, 43, 40,30,26 i ?complementary? clocks of differential pair outputs. clk_int 13 i single - ended 3.3v tolerant input. n/c 14,32,36 not connected. fb_outt 33 o ?true? feedback output. dedicated for external feedback. it switches at the same frequency as the cl k_int. fb_int 35 i ?true? feedback input, provides feedback signal to the internal pll for synchronization with clk_int to eliminate phase error. sdata 37 b sclk 12 i serial data input for serial interface port. functionality inputs outputs avdd clk_int clk_inc clkt clkc fb_outt pll state 2.5v (nom) l h l h l on 2.5v (nom) h l h l h on gnd l h l h l bypass/off gnd h l h l h bypass/off
pll102 - 108 programmable ddr zero delay clock driver 47 745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 rev 03/29/02 page 3 i2c bus configuration setting address assignment a6 a5 a4 a3 a2 a1 a0 r/w 1 1 0 1 0 0 1 _ slave r e- ceiver/transmitter provides both slave write and readback functionality data transfer rate standard mode at 100kbits/s data protocol this serial protocol is designed to allow both blocks write and read from the controller. the bytes must be accessed in sequential order from lowest to highest byte. each byte transferred must be followed by 1 acknowledge bit. a byte transferred without acknowledged bit will term i- nate the transfer. the write or read block both begins with the master sending a slave address and a write condition (0xd4) or a read condition (0xd5). following the acknowledge of this address byte, in write mode: the command byte and byte count byte must be sent by the master but ignored by the slave, in read mode: the byte count byte will be read by the master then all other data byte . byte count byte default at power - up is = (0x09). i2c control regi sters 1. byte 0: outputs register (1=enable, 0=disable) bit pin# default description bit 7 39,40 1 clkt7, clkc7 (1= active, 0=inactive) bit 6 43,44 1 clkt6, clkc6 (1= active, 0=inactive) bit 5 46,47 1 clkt5, clkc5 (1= active, 0=inactive) bit 4 22,23 1 clkt4, clkc4 (1= active, 0=inactive) bit 3 19,20 1 clkt3, clkc3 (1= active, 0=inactive) bit 2 9,10 1 clkt2, clkc2 (1= active, 0=inactive) bit 1 5,6 1 clkt1, clkc1 (1= active, 0=inactive) bit 0 2,3 1 clkt0, clkc0 (1= active, 0=inactive)
pll102 - 108 programmable ddr zero delay clock driver 47 745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 rev 03/29/02 page 4 table 1: outp ut signals skew programming summary: bit<2:0> ddr skew setting ( 10 0ps/step) fbout skew setting ( 200ps/step) 111 +400ps +800ps 110 +300ps +600ps 101 +200ps +400ps 100 +100ps +200ps 011 default default 010 - 100ps - 200ps 001 - 200ps - 400ps 000 - 300ps setting applies to the following outputs: 1. ddra: clk0, clk1, clk5 2. ddrb: clk7, clk8, clk9 3. ddrc: clk2, clk3, clk4 4. ddrd: clk6 - 600ps setting applies to the following ou t- puts: 1. fb_outt 2. byte 1: skew register (1=enable, 0=disabl e) bit name default description bit 7 26,27 1 clkt9, clkc9 (1= active, 0=inactive) bit 6 29,30 1 clkt8, clkc8 (1= active, 0=inactive) bit 5 bit <2> 0 bit 4 bit <1> 1 bit 3 skew ddra bit <0> 1 these three bits will adjust timing of ddra signals (clk0, clk1, clk5) either pos i tive or ne gative delay up to +400ps or ? 300ps with 100ps per step. (see table 1) bit 2 bit <2> 0 bit 1 bit <1> 1 bit 0 skew ddrb bit <0> 1 these three bits will adjust timing of ddrb signals (clk7, clk8, clk9) either pos i tive or negative delay up to +400ps or ? 300ps with 100ps per step. (see table 1) 3. byte 2: skew register (1=enable, 0=disable) bit name default description bit 7 ddr - skewen 1 1= disable, 0= enable bit 6 fbout - skewen 1 1= disable, 0= enable bit 5 bit <2> 0 bit 4 bit <1> 1 bit 3 sk ew ddrc bit <0> 1 these three bits will adjust timing of ddrc signals (clk2, clk3, clk4) either pos i tive or negative delay up to +400ps or ? 300ps with 100ps per step. (see table 1) bit 2 bit <2> 0 bit 1 bit <1> 1 bit 0 skew ddrd bit <0> 1 these t hree bits will adjust timing of ddrd signals (clk6) either pos i tive or negative delay up to +400ps or ? 300ps with 100ps per step. (see table 1)
pll102 - 108 programmable ddr zero delay clock driver 47 745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 rev 03/29/02 page 5 4 . byte 3: outputs register (1=enable, 0=disable) bit name default desc ription bit 7 - 1 reserved bit 6 bit <2> 0 bit 5 bit <1> 1 bit 4 skew fbout bit <0> 1 these three bits will adjust timing of fboutt signal either pos i tive or negative delay up to +800ps or ? 600ps with 200ps per step. (see table 1) bit 3 bit <3> 0 bit 2 bit <2> 0 bit 1 bit <1> 0 bit 0 delay cl kint bit <0> 0 these four bits will program the propagation delay from clk_int to the i n put of pll within the range between 0ps and 2.5ns with 170ps step size. (see table 2) table 2: clk_int delay programming summary: bit<3:0> clk_int to clk delay 1111 +2,550 ps 1110 +2,380 ps 1101 +2,210 ps 1100 +2,040 ps 1011 +1,870 ps 1010 +1,700 ps 1001 +1,530 ps 1000 +1,360 ps 0111 +1,190 ps 0110 +1,020 ps 0101 +850 ps 0100 +680 ps 0011 +510 ps 0 010 +340 ps 0001 +170 ps 0000 default
pll102 - 108 programmable ddr zero delay clock driver 47 745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 rev 03/29/02 page 6 table 3: output drive strength programming summary: bit<2:0> programming setting 111 +40% 110 +30% 101 +20% 100 +10% 011 d e fault 010 - 10% 001 - 20% 000 - 30% setting applies to the fo l lowing outputs 1. ddra (clk0, clk1, clk5) 2. ddrb (clk7, clk8, clk9) 3. ddrc (clk2, clk3, clk4) 4. ddrd ( clk6) 5. fbout 5. byte 4: buffer drive strength control register bit name default description bit 7 - 1 reserved. bit 6 - 1 reserved. bit 5 bit <2> 0 bit 4 bit <1> 1 bit 3 ddra strength bit <0> 1 these thre e bits will program drive strength for clk0, clk1 and clk5 output clocks (see table 3). bit 2 bit <2> 0 bit 1 bit <1> 1 bit 0 ddrb strength bit <0> 1 these three bits will program drive strength for clk7, clk8 and clk9 output clocks (see table 3). 6. byte 5: buffer drive strength control register bit name default description bit 7 - 1 reserved. bit 6 - 1 reserved. bit 5 bit <2> 0 bit 4 bit <1> 1 bit 3 ddrc strength bit <0> 1 these three bits will program drive strength for clk2, clk3 and cl k4 output clocks (see table 3). bit 2 bit <2> 0 bit 1 bit <1> 1 bit 0 ddrd strength bit <0> 1 these three bits will program drive strength for clk6 output clock (see table 3).
pll102 - 108 programmable ddr zero delay clock driver 47 745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 rev 03/29/02 page 7 7 . byte 6: buffer drive strength control register bit name default description bit 7 - 1 reserved. bit 6 - 1 reserved. bit 5 - 1 reserved. bit 4 - 1 reserved. bit 3 - 1 reserved. bit 2 bit <2> 0 bit 1 bit <1> 1 bit 0 fbout strength bit <0> 1 these three bits will program drive strength for fboutt output clock (see table 3).
pll102 - 108 programmable ddr zero delay clock driver 47 745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 rev 03/29/02 page 8 electrical specifica tions 1. absolute maximum ratings parameters symbol min. max. units supply voltage range v cc - 0.5 3.6 v input voltage range v i - 0.5 v cc + 0.5 v output voltage range v o - 0.5 v cc + 0.5 v storage temperature t s - 65 150 c maximum power dissipation at t a = 55 0 c in still air pw 0.7 w exposure of the device under conditions beyond the limits specified by maximum ratings for extended periods may cause permanent damage to the device and affec t product reliability. these conditions represent a stress rating only, and functional operations of the device at these or any other co n- ditions above the operational limits noted in this specification is not implied. 2. electrical characteristics paramet ers sy m bol conditions min. typ. max. units i dd2.5 cl = 0 pf (fclk=100mhz) 250 ma operating supply current i ddpd cl = 0 pf 100 ua high impedance output current i oz vdd=2.7v, v out =vdd or gnd 10 ua input clamp voltage v ik i in = - 18ma - 1.2 v inp ut capacitance c in v i = vdd or gnd 2 pf output capacitance c out v o = vdd or gnd 3 pf vdd = min to max, i oh = - 1ma vdd - 0.1 v high level output voltage v oh vdd = 2.3v, i oh = - 12ma 1.7 v vdd = min to max, i ol = 1ma 0.1 v low level output voltage v ol vdd = 2.3v, i ol = 12ma 0.6 v output differential - pair crossing voltage v oc (vdd/2) - 0.2 (vdd/ 2)+0.2 v
pll102 - 108 programmable ddr zero delay clock driver 47 745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 rev 03/29/02 page 9 3. recommended operating conditions parameters symbol min. typ. max. units output supply voltage v cc 2.3 2.5 2.7 v analog supply vo ltage a cc 2.3 2.5 2.7 v high level input voltage v ih 0.7 x v cc v low level input voltage v il 0.3 x v cc v operating free - air temperature t a 0 70 c 4. timing requirements symbol parameters min. max. units f clk input clock frequency 66 266 mhz d i n input clock duty cycle 40 60 % t s stabilization time after power up 0.1 ms 5. switching characteristics parameters sy m bol conditions min. typ. max. units low to high level propagation delay time t plh clk_int to any output 0 high to low level pr opagation delay time t phl clk_int to any output 0 ns 66mhz 120 jitter (peak to peak) t p - p 100/133/200/266mhz 75 ps 66mhz 110 jitter (cycle to cycle) t cyc - cyc 100/133/200/266mhz 65 ps phase error t (phase error) - 150 150 output to output skew t oskew 100 pulse skew t pskew all differential input and output terminals are terminated with 120 w/ 16pf 100 ps 66mhz to 100mhz 49.5 50.5 duty cycle d t 101mhz to 266mhz 49 51 % rise time, fall time t r, t f load = 120 w/ 16pf 650 800 950 ps
pll102 - 108 programmable ddr zero delay clock driver 47 745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 rev 03/29/02 page 10 package inform a tion ordering info rmation phaselink corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. the information fu r- nished by phaselink is believed to be accurate and reliable. however, phaselink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. life support policy : phaselink?s products are not authorized for use as critical components in life support devices or systems without the e x- press written approval of the president of phaselink corporation. for part ordering, pleas e contact our sales department: 47745 fremont blvd., fremont, ca 94538, usa tel: (510) 492 - 0990 fax: (510) 492 - 0991 part number the order number for this device is a combination of the following: device number, package type and operating temperature range pll102 - 108 x c part number temperaturature c=commercial m=military i=industral package type x=ssop 0.008 - 0.016 (0.203 - 0.406) 0.620 - 0.630 (15.75 - 16.00) (0.254 - 0.406) 45 0 0.010 - 0.016 0.050 (1.27) min 3 0 -6 0 0.015 (0.381) 0.088 - 0.096 (2.235 - 2.438) 0.097 - 0.104 (2.464 - 2.642) 0.025 0.635 0.400 - 0.410 10.160 - 10.414 0.292 - 0.299 7.417 - 7.595 0.008 - 0.0135 0.203 - 0.343 48pin ssop
|
