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| ? october 2003 - revision 1.2 (working document) 1/19 this is preliminary information on a new product foreseen to be developed. details are subject to change without notice. overtemp. 1 v cc gnd input1 output1 overvoltage logic driver 1 status1 v cc clamp undervoltage clamp 1 openload on 1 current limiter 1 openload off 1 output2 driver 2 clamp 2 openload on 2 openload off 2 overtemp. 2 input2 status2 current limiter 2 vnd830p double channel high side driver (*) per each channel n cmos compatible inputs n open drain status outputs n on state open load detection n off state open load detection n shorted load protection n undervoltage and overvoltage shutdown n loss of ground protection n very low stand-by current n reverse battery protection (**) description the vnd830p is a monolithic device made by using stmicroelectronics vipower m0-3 technology, intended for driving any kind of load with one side connected to ground. active v cc pin voltage clamp protects the devices against low energy spikes (see iso7637 transient compatibility table). active current limitation combined with thermal shutdown and automatic restart protects the device against overload. the device detects open load condition both is on and off state. output shorted to v cc is detected in the off state. device automatically turns off in case of ground pin disconnection. type r ds(on) i out v cc vnd830p 60 m w (*) 6 a (*) 36 v so-16l order codes package tube t&r so-16l vnd830p vnd830p13tr block diagram (**) see application schematic at page 8 target specification
2/19 vnd830p absolute maximum rating connection diagram (top view) symbol parameter value unit v cc dc supply voltage 41 v - v cc reverse dc supply voltage - 0.3 v - i gnd dc reverse ground pin current - 200 ma i out dc output current internally limited a - i out reverse dc output current - 6 a i in dc input current +/- 10 ma i stat dc status current +/- 10 ma v esd electrostatic discharge (human body model: r=1.5k w; c=100pf) - input - status - output - v cc 4000 4000 5000 5000 v v v v e max maximum switching energy (l=1.8mh; r l =0 w ; v bat =13.5v; t jstart =150oc; i l =9a) 102 mj p tot power dissipation t lead =25c 8.3 w t j junction operating temperature internally limited c t c case operating temperature - 40 to 150 c t stg storage temperature - 55 to 150 c i s i gnd output 2 v cc gnd status 2 input 2 i out2 i in2 i stat2 v stat2 v in2 v cc v out2 output 1 i out1 v out1 input 1 i in1 status 1 i stat1 v in1 v stat1 current and voltage conventions v cc output 2 output 2 output 2 output 1 v cc output 1 output 1 v cc input 2 status 2 status 1 input 1 v cc gnd n.c. 1 8 9 16 3/19 vnd830p thermal data (*) when mounted on a standard single-sided fr-4 board with 0.5cm 2 of cu (at least 35 m m thick) connected to all v cc pins. horizontal mounting and no artificial air flow. electrical characteristics (8v 4/19 vnd830p electrical characteristics (continued) v cc - output diode status pin protections openload detection symbol parameter test conditions min typ max unit v f forward on voltage -i out =2a; t j =150c 0.6 v symbol parameter test conditions min typ max unit v stat status low output voltage i stat = 1.6 ma 0.5 v i lstat status leakage current normal operation; v stat = 5v 10 m a c stat status pin input capacitance normal operation; v stat = 5v 100 pf v scl status clamp voltage i stat = 1ma i stat = - 1ma 66.8 -0.7 8v v symbol parameter test conditions min typ max unit t tsd shut-down temperature 150 175 200 c t r reset temperature 135 c t hyst thermal hysteresis 7 15 c t sdl status delay in overload conditions t j >t tsd 20 m s i lim current limitation v cc =13v 5.5v < v cc < 36v 6915 15 a a v demag turn-off output clamp voltage i out =2a; l= 6mh v cc -41 v cc -48 v cc -55 v symbol parameter test conditions min typ max unit i ol openload on state detection threshold v in =5v 50 100 200 ma t dol(on) openload on state detection delay i out =0a 200 m s v ol openload off state voltage detection threshold v in =0v 1.5 2.5 3.5 v t dol(off) openload detection delay at turn off 1000 m s 2 v inn v statn t dol(off) open load status timing (with external pull-up) v inn v statn overtemp status timing t sdl i out < i ol v out > v ol t dol(on) t j > t tsd t sdl 5/19 vnd830p t t v outn v inn 80% 10% dv out /dt (on) t d(off) 90% dv out /dt (off) t d(on) switching time waveforms truth table conditions input output status normal operation l h l h h h current limitation l h h l x x h (t j < t tsd ) h (t j > t tsd ) l overtemperature l h l l h l undervoltage l h l l x x overvoltage l h l l h h output voltage > v ol l h h h l h output current < i ol l h l h h l 6/19 vnd830p iso t/r 7637/1 test pulse test levels i ii iii iv delays and impedance 1 -25 v -50 v -75 v -100 v 2 ms 10 w 2 +25 v +50 v +75 v +100 v 0.2 ms 10 w 3a -25 v -50 v -100 v -150 v 0.1 m s 50 w 3b +25 v +50 v +75 v +100 v 0.1 m s 50 w 4 -4 v -5 v -6 v -7 v 100 ms, 0.01 w 5 +26.5 v +46.5 v +66.5 v +86.5 v 400 ms, 2 w iso t/r 7637/1 test pulse test levels results i ii iii iv 1c c c c 2c c c c 3acccc 3bcccc 4c c c c 5c e e e electrical transient requirements on v cc pin class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. 7/19 vnd830p 1 figure1: waveforms open load without external pull-up status n input n normal operation undervoltage v cc v usd v usdhyst input n overvoltage v cc status n input n status n status n input n status n input n open load with external pull-up undefined overtemperature input n status n t tsd t r t j output voltage n v cc 8/19 vnd830p gnd protection network against reverse battery solution 1: resistor in the ground line (r gnd only). this can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1) r gnd 600mv / i s(on)max . 2) r gnd 3 (- v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the devices datasheet. power dissipation in r gnd (when v cc <0: during reverse battery situations) is: p d = (-v cc ) 2 /r gnd this resistor can be shared amongst several different hsd. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not common with the device ground then the r gnd will produce a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift will vary depending on many devices are on in the case of several high side drivers sharing the same r gnd . if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the st suggests to utilize solution 2 (see below). solution 2: a diode (d gnd ) in the ground line. a resistor (r gnd =1k w) should be inserted in parallel to d gnd if the device will be driving an inductive load. this small signal diode can be safely shared amongst several different hsd. also in this case, the presence of the ground network will produce a shift ( j 600mv) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. this shift will not vary if more than one hsd shares the same diode/resistor network. series resistor in input and status lines are also required to prevent that, during battery voltage transient, the current exceeds the absolute maximum rating. safest configuration for unused input and status pin is to leave them unconnected. load dump protection d ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds v cc max dc rating. the same applies if the device will be subject to transients on the v cc line that are greater than the ones shown in the iso t/r 7637/1 table. application schematic v cc output2 d ld +5v r prot output1 status1 input1 +5v status2 input2 gnd +5v m c r prot r prot r prot d gnd r gnd v gnd 9/19 vnd830p m c i/os protection: if a ground protection network is used and negative transient are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the m c i/os pins to latch-up. the value of these resistors is a compromise between the leakage current of m c and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of m c i/os. -v ccpeak /i latchup r prot (v oh m c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = - 100v and i latchup 3 20ma; v oh m c 3 4.5v 5k w r prot 65k w . recommended r prot value is 10k w. 10/19 vnd830p 1 open load detection in off state off state open load detection requires an external pull-up resistor (r pu ) connected between output pin and a positive supply voltage (v pu ) like the +5v line used to supply the microprocessor. the external resistor has to be selected according to the following requirements: 1) no false open load indication when load is connected: in this case we have to avoid v out to be higher than v olmin ; this results in the following condition v out =(v pu /(r l +r pu ))r l 12/19 vnd830p input hysteresis voltage input low level on state resistance vs t case on state resistance vs v cc input high level openload on state detection threshold -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 20 40 60 80 100 120 140 160 ron (mohm) iout=2a vcc=8v; 13v & 36v 5 10152025303540 vcc (v) 0 10 20 30 40 50 60 70 80 90 100 110 120 ron (mohm) iout=5a tc= - 40c tc=25c tc=150c -50 -25 0 25 50 75 100 125 150 175 tc (oc) 750 800 850 900 950 1000 1050 1100 1150 1200 1250 iol (ma) vcc=13v vin=5v -50 -25 0 25 50 75 100 125 150 175 tc (c) 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vih (v) -50 -25 0 25 50 75 100 125 150 175 tc (c) 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 vil (v) -50 -25 0 25 50 75 100 125 150 175 tc (c) 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 vhyst (v) 13/19 vnd830p overvoltage shutdown turn-on voltage slope turn-off voltage slope i lim vs t case openload off state voltage detection threshold -50 -25 0 25 50 75 100 125 150 175 tc (c) 30 32 34 36 38 40 42 44 46 48 50 vov (v) -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 vol (v) vin=0v -50 -25 0 25 50 75 100 125 150 175 tc (oc) 0 100 200 300 400 500 600 700 800 dvout/dt(on) (v/ms) vcc=13v rl=6.5ohm -50 -25 0 25 50 75 100 125 150 175 tc (oc) 200 250 300 350 400 450 500 550 600 dvout/dt(off) (v/ms) vcc=13v rl=6.5ohm -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 2 4 6 8 10 12 14 16 18 20 ilim (a) vcc=13v 14/19 vnd830p maximum turn off current versus load inductance a = single pulse at t jstart =150oc b= repetitive pulse at t jstart =100oc c= repetitive pulse at t jstart =125oc conditions: v cc =13.5v values are generated with r l =0 w in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves b and c. v in , i l t demagnetization demagnetization demagnetization 1 10 100 0.1 1 10 100 l(mh) i lmax (a) a b c 15/19 vnd830p so-16l pc board r thj-amb vs pcb copper area in open box free air condition so-16l thermal data layout condition of r th and z th measurements (pcb fr4 area= 41mm x 48mm, pcb thickness=2mm, cu thickness=35 m m, copper areas: 0.5cm 2 , 6cm 2 ). 40 45 50 55 60 65 70 01234567 pcb cu heatsink area (cm^2) rth j-amb (c/w) 16/19 vnd830p thermal fitting model of a double channel hsd in so-16l pulse calculation formula thermal parameter area/island (cm 2 )0.56 r1 (c/w) 0.15 r2 (c/w) 0.8 r3 ( c/w) 2.2 r4 (c/w) 12 r5 (c/w) 15 r6 (c/w) 37 22 c1 (w.s/c) 0.0006 c2 (w.s/c) 2.10e-03 c3 (w.s/c) 1.50e-02 c4 (w.s/c) 0.14 c5 (w.s/c) 1 c6 (w.s/c) 3 5 z th d r th d z thtp 1 d C () + = where d t p t = so-16l thermal impedance junction ambient single pulse 0.1 1 10 100 1000 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (c/w) 0.5 cm 2 6 cm 2 t_amb pd1 c1 r4 c3 c4 r3 r1 r6 r5 r2 c5 c6 c2 pd2 r2 c1 c2 r1 tj_1 tj_2 17/19 vnd830p 1 dim. mm. inch min. typ max. min. typ. max. a 2.65 0.104 a1 0.1 0.2 0.004 0.008 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 c 0.5 0.020 c1 45 (typ.) d 10.1 10.5 0.397 0.413 e 10.0 10.65 0.393 0.419 e 1.27 0.050 e3 8.89 0.350 f 7.4 7.6 0.291 0.300 l 0.5 1.27 0.020 0.050 m 0.75 0.029 s8 (max.) so-16l mechanical data 18/19 vnd830p 1 so-16l tube shipment (no suffix) 1 all dimensions are in mm. base q.ty 50 bulk q.ty 1000 tube length ( 0.5) 532 a 3.5 b 13.8 c ( 0.1) 0.6 tape and reel shipment (suffix 13tr) base q.ty 1000 bulk q.ty 1000 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 16.4 n (min) 60 t (max) 22.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb 1986 all dimensions are in mm. tape width w 16 tape hole spacing p0 ( 0.1) 4 component spacing p 12 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 7.5 compartment depth k (max) 6.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed a c b reel dimensions 19/19 vnd830p information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this p ublication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a trademark of stmicroelectronics ? 2003 stmicroelectronics - printed in italy- all rights reserved. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com |
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