View ISL6307BIRZ_5192540.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ? fn9225.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. dynamic vid? is a trademark of intersil americas inc. copyright ? intersil americas inc. 2006. all rights reserved all other trademarks mentioned are the property of their respective owners. isl6307b 6-phase vr11 pwm controller with 8-bit vid code capable of precision r ds(on) or dcr differential current sensing for applications in which supply voltage is higher than 5v the isl6307b controls micr oprocessor core voltage regulation by driving up to 6 synchronous-rectified buck channels in parallel. multiphase buck converter architecture uses interleaved timing to multiply channel ripple frequency and reduce input and output ripple currents. lower ripple results in fewer components, lower component cost, reduced power dissipation, and smaller implementation area. microprocessor loads can generate load transients with extremely fast edge rates. th e isl6307b features a high bandwidth control loop and ripple frequencies up to 6mhz to provide optimal response to the transients. today?s microprocessors require a tightly regulated output voltage position versus load current (droop). the isl6307b senses current by utilizing patented techniques to measure the voltage across the on resistance, r ds(on) , of the lower mosfets or dcr, of the output inductor during the lower mosfet conduction intervals. current sensing provides the needed signals for precision droop, channel-current balancing, and overcurrent protection. a programmable internal temperature compensa tion function is implemented to effectively compensate for th e temperature coefficient of the current sense element. a unity gain, differential amplifier is provided for remote voltage sensing. any potential difference between remote and local grounds can be completely eliminated using the remote-sense amplifier. eliminating ground differences improves regulation and protec tion accuracy. the threshold- sensitive enable input is available to accurately coordinate the start up of the isl6307b with any other voltage rail. dynamic-vid? technology allows seamless on-the-fly vid changes. the offset pin allows accurate voltage offset settings that are independent of vid setting. features ? precision multiphase core voltage regulation - differential remote voltage sensing - 0.5% system accuracy over life, load, line and temperature - adjustable precision reference-voltage offset ? precision r ds(on) or dcr current sensing - accurate load-line programming - accurate channel-current balancing - differential current sense ? microprocessor voltag e identification input - dynamic vid? technology - 8-bit vid input with selectable vr11 code and extended vr10 code at 6.25mv step - 0.5v to 1.600v operation range ? threshold-sensitive enable function for power sequencing and vtt enable ? thermal monitoring ? internal 5v shunt regulator ? programmable temperature compensation ? overcurrent protection ? overvoltage protection with ovp output indication ? 2, 3, 4, 5 or 6 phase operation ? adjustable switching frequency up to 1mhz per phase ? qfn package option - qfn compliant to jedec pub95 mo-220 qfn - quad flat no leads - product outline - qfn near chip scale package footprint; improves pcb efficiency, thinner in profile ? pb-free plus anneal available (rohs compliant) ordering information part number temp. (c) package pkg. dwg. # isl6307bcrz (note) 0 to 70 48 ld 7x7 qfn (pb-free) l48.7x7 ISL6307BIRZ (note) -40 to 85 48 ld 7x7 qfn (pb-free) l48.7x7 add ?-t? suffix for tape and reel. note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet march 9, 2006
2 fn9225.0 march 9, 2006 pinout isl6307b (48 ld qfn) top view vid6 vid5 vid4 vid3 vid2 vid0 ofs vid1 tm vr_rdy vr_fan vr_hot fs en_vtt en_pwr vrsel vid7 vcc isen2+ pwm2 pwm3 isen3+ isen3- isen1- isen1+ pwm1 pwm4 isen4+ tcomp vsen rgnd fb comp pwm5 idroop iout dac isen2- isen4- isen5+ vdiff ovp isen6- isen6+ pwm6 ref isen5- ss 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 gnd isl6307b
3 fn9225.0 march 9, 2006 isl6307b block diagram i_trip ovp drive channel pwm1 pwm2 pwm3 pwm6 gnd fb fs s clock and vid5 vid4 vid3 vid2 comp vsen generator sawtooth vid1 rgnd vdiff vr_rdy ovp en_pwr 0.875v i_tot dynamic vid d/a temperature current balance channel detect ofs three-state channel current sense ovp vid0 soft-start and fault logic offset ref +200mv r x1 e/a oc1 pwm pwm pwm pwm q een_vtt dac iout 0.875v vid6 vid7 vrsel pwm4 pwm pwm5 pwm idroop temperature compensation tcomp tm vr_hot vr_fan thermal monitoring ss 2v oc2 1 n gain compensation power-on reset (por) shunt regulator vcc isen3- isen4+ isen1+ isen2- isen4- isen3+ isen2+ isen1- isen5- isen6+ isen6- isen5+ isl6307b
4 fn9225.0 march 9, 2006 typical application - 6-ph ase buck converter with r ds(on) sensing and external tcomp vid6 +12v pwm vcc boot ugate phase lgate gnd +12v vin vid7 vr_rdy vid5 vsen vdiff fb comp vcc gnd rgnd en_pwr pwm6 isen6- pwm4 isen4+ pwm2 isen2+ pwm1 isen1+ isl6307b p load isen6+ isen4- isen2- isen1- tcomp ref dac fs ofs pvcc en_vtt vtt idroop isl6612 driver +12v r t vid4 vid3 vr_fan vr_hot tm +5v ntc r ofs pwm vcc boot ugate phase lgate gnd +12v vin pvcc isl6612 driver pwm vcc boot ugate phase lgate gnd +12v vin pvcc isl6612 driver pwm vcc boot ugate phase lgate gnd +12v vin pvcc isl6612 driver pwm vcc boot ugate phase lgate gnd +12v vin pvcc isl6612 driver pwm vcc boot ugate phase lgate gnd +12v vin pvcc isl6612 driver isen3- pwm5 pwm3 isen3+ isen5- isen5+ ntc2 ss vid2 vid1 vid0 vrsel ovp iout r ss r iout external tcomp compensation network 300 ? isl6307b
5 fn9225.0 march 9, 2006 typical application - 6-ph ase buck converter with r ds(on) sensing and integrated tcomp pwm vcc boot ugate phase lgate gnd +12v vin vsen vdiff fb comp vcc gnd rgnd en_pwr pwm6 isen6- pwm4 isen4+ pwm2 isen2+ pwm1 isen1+ isl6307b p load isen6+ isen4- isen2- isen1- tcomp ref dac fs ofs pvcc en_vtt vtt idroop isl6612 driver +12v r t vr_fan vr_hot tm +5v ntc r ofs pwm vcc boot ugate phase lgate gnd +12v vin pvcc isl6612 driver pwm vcc boot ugate phase lgate gnd +12v vin pvcc isl6612 driver pwm vcc boot ugate phase lgate gnd +12v vin pvcc isl6612 driver pwm vcc boot ugate phase lgate gnd +12v vin pvcc isl6612 driver pwm vcc boot ugate phase lgate gnd +12v vin pvcc isl6612 driver isen3- pwm5 pwm3 isen3+ isen5- isen5+ ss +5v vid6 vid7 vr_rdy vid5 vid4 vid3 vid2 vid1 vid0 vrsel ovp iout r iout r ss +12v 300 ? isl6307b
6 fn9225.0 march 9, 2006 typical application - 6-phase buck converter with dcr se nsing and external tcomp +12v pwm vcc boot ugate phase lgate gnd +12v vin vsen vdiff fb comp vcc gnd rgnd en_pwr pwm6 isen6- pwm4 isen4+ pwm2 isen2+ pwm1 isen1+ isl6307b p load isen6+ isen4- isen2- isen1- tcomp ref dac fs ofs pvcc en_vtt vtt idroop isl6612 driver +12v r t vr_fan vr_hot tm +5v ntc r ofs pwm vcc boot ugate phase lgate gnd +12v vin pvcc isl6612 driver pwm vcc boot ugate phase lgate gnd +12v vin pvcc isl6612 driver pwm vcc boot ugate phase lgate gnd +12v vin pvcc isl6612 driver pwm vcc boot ugate phase lgate gnd +12v vin pvcc isl6612 driver pwm vcc boot ugate phase lgate gnd +12v vin pvcc isl6612 driver isen3- pwm5 pwm3 isen3+ isen5- isen5+ ntc2 ss vid6 vid7 vr_rdy vid5 vid4 vid3 vid2 vid1 vid0 vrsel ovp iout r iout r ss external tcomp compensation network 300 ? isl6307b
7 fn9225.0 march 9, 2006 typical application - 6-phase buck converter with dcr se nsing and integrated tcomp +12v pwm vcc boot ugate phase lgate gnd +12v vin vsen vdiff fb comp vcc gnd rgnd en_pwr pwm6 isen6- pwm4 isen4+ pwm2 isen2+ pwm1 isen1+ isl6307b p load isen6+ isen4- isen2- isen1- tcomp ref dac fs ofs pvcc en_vtt vtt idroop isl6612 driver +12v r t vr_fan vr_hot tm +5v ntc r ofs pwm vcc boot ugate phase lgate gnd +12v vin pvcc isl6612 driver pwm vcc boot ugate phase lgate gnd +5v vin en isl6612 driver pwm vcc boot ugate phase lgate gnd +12v vin en isl6612 driver pwm vcc boot ugate phase lgate gnd +12v vin pvcc isl6612 driver pwm vcc boot ugate phase lgate gnd +12v vin pvcc isl6612 driver isen3- pwm5 pwm3 isen3+ isen5- isen5+ ss +5v vid6 vid7 vr_rdy vid5 vid4 vid3 vid2 vid1 vid0 vrsel ovp iout r iout r ss 300 ? isl6307b
8 fn9225.0 march 9, 2006 absolute m aximum ratings voltage at vcc when it is connected to enxternal >5v input through a resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6v iall pins . . . . . . . . . . . . . . . . . . . . . . . . . . gnd -0.3v to v cc + 0.3v esd (human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>2kv esd (machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>200v esd (charged device model . . . . . . . . . . . . . . . . . . . . . . . . . >1.5kv operating conditions voltage at vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v 5% ambient temperature (isl6307bcrz) . . . . . . . . . . . . . 0c to 70c ambient temperature (ISL6307BIRZ) . . . . . . . . . . . . .-40c to 85c thermal information thermal resistance (notes 1, 2) ja (c /w) jc (c /w) qfn package. . . . . . . . . . . . . . . . . . . . 32 6.5 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c caution: stress above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress onl y rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. notes: 1. ja is measured in free air with the component mounted on a high e ffective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside . electrical specifications operating conditions: vcc = 5v or icc < 25ma (note 3). unless otherwise specified parameter test conditions min typ max units shunt regulator vcc voltage vcc tied to 12vdc thru 300 ? resistor, r t = 100k ? -5- v vcc sink current vcc tied to 12vdc thru 300 ? resistor, r t = 100k ? --25ma power-on reset and enable por threshold vcc rising 4.3 4.5 4.70 v vcc falling 3.7 3.9 4.20 v en_pwr threshold rising 0.850 0.875 0.910 v hysteresis - 130 - mv falling 0.720 0.745 0.775 v en_vtt threshold rising 0.850 0.875 0.910 v hysteresis - 130 - mv falling 0.720 0.745 0.775 v reference voltage and dac system accuracy of isl6307bcrz (vid = 1v-1.6v), t j = 0cto 70c) (note 3) -0.5 - 0.5 %vid system accuracy of isl6307bcrz (vid = 0.5v-1v),t j = 0c to 70c) (note 3) -0.9 - 0.9 %vid system accuracy of ISL6307BIRZ (vid = 1v-1.6v), t j = -40c to 85c) (note 3) -0.6 - 0.6 %vid system accuracy of ISL6307BIRZ (vid = 0.5v-1v),t j = -40c to 85c) (note 3) -1 - 1 %vid vid pull up -60 -40 -20 a vid input low level --0.4v vid input high level 0.8 - - v vrsel input low level --0.4v vrsel input high level 0.8 - - v dac source current --7ma dac sink current - - 300 a ref source current 45 50 55 a ref sink current 45 50 55 a isl6307b
9 fn9225.0 march 9, 2006 pin-adjustable offset voltage at ofs pin for isl6307bcrz offset resistor connected to ground 392 400 408 mv voltage below vcc, offset resistor connected to vcc 1.568 1.600 1.632 v voltage at ofs pin for ISL6307BIRZ offset resistor connected to ground 388 400 412 mv voltage below vcc, offset resistor connected to vcc 1.552 1.600 1.648 v oscillators accuracy of switching frequency setting r t = 100k ? 225 250 275 khz adjustment range of switching frequency (note 4) 0.08 - 1.0 mhz soft-start ramp rate (notes 5, 6) r ss = 100k ? -1.563- mv/ s adjustment range of soft-start ramp rate (note 4) 0.625 - 6.25 mv/ s pwm generator sawtooth amplitude -1.5- v max duty cycle -66.7- % error amplifier open-loop gain r l = 10k ? to ground (note 4) - 96 - db open-loop bandwidth c l = 100pf, r l = 10k ? to ground (note 4) - 20 - mhz slew rate c l = 100pf - 9 - v/ s maximum output voltage 3.8 4.3 4.9 v output high voltage @ 2ma 3.6 - - v output low voltage @ 2ma --1.2v remote-sense amplifier bandwidth (note 4) - 20 - mhz output high current vsen - rgnd = 2.5v -500 - 500 a output high current vsen - rgnd = 0.6 -500 - 500 a pwm output pwm output voltage low threshold iload = 500 a--0.5v pwm output voltage high threshold iload = 500 a4.3--v sense current output (idroop and iout) sensed current tolerance isen1 = isen2 = isen3 = isen4 = isen5 = isen6 = 80 a768084 a overcurrent trip level 90 100 110 a maximum voltage at idroop and iout pins -2- v thermal monitoring and fan control tm input voltage for vr_fan trip 1.6 1.65 1.69 v tm input voltage for vr_fan reset 1.89 1.93 1.98 v tm input voltage for vr_hot trip 1.35 1.4 1.44 v tm input voltage for vr_hot reset 1.6 1.65 1.69 v leakage current of vr_hot with external pull-up resistor connected to 5v - - 30 a vr_hot low voltage with 1.250k ? resistor pull up to 5v, i vr_hot = 4ma - - 0.3 v leakage current of vr_fan with external pull-up resistor connected to 5v - - 30 a vr_fan low voltage with 1.250k ? resistor pull up to 5v, i vr_fan = 4ma - - 0.3 v vr ready and protection monitors leakage current of vr_rdy with external pull-up resistor connected to 5v - - 30 a vr_rdy low voltage i vr_rdy = 4ma - - 0.3 v under voltage trip of vr-rdy vsen falling 48 50 52 %vid electrical specifications operating conditions: vcc = 5v or icc < 25ma (note 3). unless otherwise specified (continued) parameter test conditions min typ max units isl6307b
10 fn9225.0 march 9, 2006 functional pin description vcc - supplies all the power necessary to operate the chip. the controller starts to operate when the voltage on this pin exceeds the rising por threshold and shuts down when the voltage on this pin drops below the falling por threshold. connect this pin through a series 390 ? resistor to a +12v supply and a 1f capacitor from this pin to gnd. gnd - bias and reference ground for the ic. the bottom metal base of isl6307b is the gnd. en_pwr - this pin is a threshold- sensitive enable input for the controller. connecting the 12v supply to en_pwr through an appropriate resistor divider provides a means to synchronize power-up of the controller and the mosfet driver ics. when en_pwr is driven above 0.875v, the isl6307b is active depending on status of en_vtt, the internal por, and pending fault states. driving en_pwr below 0.745v will clear all fault states and prime the isl6307b to soft-start when re-enabled. en_vtt - this pin is another th reshold-sensitive enable input for the controller. it?s typically connected to vtt output of vtt voltage regulator in the computer mother board. when en_vtt is driven above 0.875v, the isl6307b is active depending on status of enll, the internal por, and pending fault states. driving en_vtt below 0.745v will clear all fault states and prime the isl6307b to soft-start when re- enabled. fs - use this pin to set up the desired switching frequency. a resistor, placed from fs to ground will set the switching frequency. the relationship between the value of the resistor and the switching frequency will be described by an approximate equation 40. ss - use this pin to set up the desired start-up oscillator frequency. a resistor, placed from ss to ground will set up the soft-start ramp rate.the relationship between the value of the resistor and the soft -start ramp up time will be described by approximate equation. vid7, vid6, vid5, vid4, vid3 , vid2, vid1 and vid0 - these are the inputs to the in ternal dac that provides the reference voltage for output regulation. connect these pins either to open-drain outputs with or without external pull-up resistors or to active-pull-up outputs. vid7-vid0 have 40a internal pull-up current sources that diminish to zero as the voltage rises above the logic-high level. these inputs can be pulled up as high as vcc plus 0.3v. when a vid code causes a shut-o ff, the controller needs to be reset before it will start again. vrsel - vrsel is the pin used to select internal vid code. when it is connected to g nd, the extended vr10 code is selected. when it?s floated or pulled to high, vr11 code is selected. this input can be pulled up as high as vcc plus 0.3v. vdiff, vsen, and rgnd - vsen and rgnd form the precision differential remote-sense amplifier. this amplifier converts the differential voltage of the remote output to a single-ended voltage referenced to local ground. vdiff is the amplifier?s output and t he input to the regulation and protection circuitry. connect vsen and rgnd to the sense pins of the remote load. fb and comp - inverting input and output of the error amplifier respectively. fb is connected to vdiff through a resistor. a negative current, proportional to output current is present on the fb pin. a properly sized resistor between vdiff and fb sets the load line (droop). the droop scale factor is set by the ratio of the isen resistors and the lower mosfet r ds(on) . comp is tied back to fb through an external r-c network to compensate the regulator. dac and ref - the dac output pin is the output of the precision internal dac reference. the ref input pin is the positive input of the error amp. in typical applications, a 1k ? , 1% resistor is used between dac and ref to generate a precise offset voltage. this vo ltage is proportional to the offset current determined by the offset resistor from ofs to ground or vcc. a capacitor is used between ref and ground to smooth the voltage transition during dynamic vid? operations. vr-rdy reset voltage vdiff rising 58 60 62 %vid overvoltage protection threshold before valid vid 1.250 1.275 1.300 v after valid vid, the voltage above vid 150 175 200 mv overvoltage reset threshold 0.38 0.40 0.42 v ovp output high voltage i ovp = 4ma 4.5 - - v ovp output low voltage i ovp = 4ma - - 0.25 v notes: 3. these parts are designed and adjusted for accuracy with all errors in the voltage loop included. 4. spec guaranteed by design. 5. during soft-start, vdac rises from 0 to 1.1v first and then ramp to vid voltage after receiving valid vid input. 6. soft-start ramp rate is determined by the adjustable soft- start oscillator frequency at the speed of 6.25mv per cycle. electrical specifications operating conditions: vcc = 5v or icc < 25ma (note 3). unless otherwise specified (continued) parameter test conditions min typ max units isl6307b
11 fn9225.0 march 9, 2006 pwm1, pwm2, pwm3, pw m4, pwm5, pwm6 - pulse- width modulation outputs. connect these pins to the pwm input pins of the intersil driver ic. the number of active channels is determined by the state of pwm3, pwm4, pwm5 and pwm 6. tie pwm3 to vcc to configure for 2-phase operation. tie pwm4 to vcc to configure for 3-phase operation. tie pwm5 to vcc to configure for 4-phase operation. tie pwm6 to vcc to configure for 5-phase operation. isen1+, isen1-; isen2+, isen2-; isen3+, isen3-; isen4+, isen4-; i sen5+, isen5-; i sen6+, isen6- - the isen+ and isen- pins are current sense inputs to individual differential amplifiers. the sensed current is used as a reference for channel balancing, protection, and regulation. inactive channels should have their respective current sense inputs left open (for example, for 3-phase operation open isen4+). for dcr sensing, connect each isen- pin to the node between the rc sense elements. tie the isen+ pin to the other end of the sense capacitor through a resistor, r isen . the voltage across the sense capacitor is proportional to the inductor current. the sense current is proportional to the output current, and scaled by the dcr of the inductor and r isen . when configured for r ds(on) current sensing, the isen1-, isen2-, isen3-, isen4-, isen5-, isen6- pins are grounded at the lower mosfet sour ces. the isen1+, isen2+, isen3+, isen4+, isen5+, isen6+ pins are then held at a virtual ground, such that a resistor connected between them, and the drain terminal of the associated lower mosfet, will carry a current proportional to the current flowing through that channel. the current is determined by the negative voltage developed across the lower mosfet?s r ds(on) , which is the channel current scaled by r ds(on) and r isen . vr_rdy - vr_rdy is used as an indication of the end of soft-start with certain delay per intel vr11. it is an open- drain logic output that is low impedance until the soft-start is completed. it will be pulled low again once the undervoltage point is reached. ofs - the ofs pin provides a means to program a dc offset current for generating a dc offset voltage at the ref input. the offset current is gen erated via an external resistor and precision internal voltage references. the polarity of the offset is selected by connecting the resistor to gnd or vcc. for no offset, the ofs pin should be left unterminated. tcomp - temperature compensation scaling input. the voltage sensed on the tm pin is utilized as the temperature input to adjust ldroop and the ov ercurrent protection limit to effectively compensate for the temperature coefficient of the current sense element. to implement the integrated temperature compensation, a re sistor divider circuit is needed with one resistor being connected from tcomp to vcc of the controller and anot her resistor being connected from tcomp to gnd. changing the ratio of the resistor values will set the gain of the integrated thermal compensation. when integrated temperature compensation function is not used, connect tcomp to gnd. ovp - the overvoltage protection output indication pin. this pin can be pulled to vcc and is latched when an overvoltage condition is detected. when no t used, keep this pin open. idroop - the output pin of sensed average channel current which is probational to load current. in the application which does not require loadline, leave this pin open. in the application which requires load line, connect this pin to fb so that the sensed average current will flow through the resistor between fb and vdiff to create a voltage drop which is probational to load current. iout - iout has the same output as idroop with additional ocp adjustment function. in actual application, a resistor needs to be placed between iout and gnd to ensure the proper operation. the voltage at iout pin will be proportional to the load current. if the voltage is higher than 2v, isl6307b will go into ocp mode, this means shut down first and then hiccup. the additional ocp trip level can be adjusted by changing the resistor value. tm - tm is an input pin for vr temperature measurement. connect this pin through ntc thermistor to gnd and a resistor to 5v. the voltage at this pin is proportional to vr temperature. isl6307 monitor the vr temperature based the voltage at tm pin and output vr_hot and vr_fan control singles. vr_hot - an indication output pin of high vr temperature. it is an open-drain logic out put with low impedance. it will be pulled high when measured vr temperature reaches certain level. vr_fan - an indication output pin of vr temperature high warning with open-drain logic. it will be pulled high when measured vr temperature reaches certain level. vr_fan will be pulled to high before vr_hot. operation multiphase power conversion microprocessor load current profiles have changed to the point that the advantages of multiphase power conversion are impossible to ignore. the technical challenges associated with producing a single-phase converter which is both cost-effective and thermally viable, have forced a change to the cost-saving approach of multiphase. the isl6307b controller helps reduce the complexity of implementation by integrating vital functions and requiring minimal output components. the block diagrams on pages 4, 5, 6 and 7 provide top level views of multiphase power conversion using the isl6307b controller. isl6307b
12 fn9225.0 march 9, 2006 interleaving the switching of each channel in a multiphase converter is timed to be symmetrically out of phase with each of the other channels. in a 3-phase converte r, each channel switches 1/3 cycle after the previous chann el and 1/3 cycle before the following channel. as a result, the three-phase converter has a combined ripple frequency three times greater than the ripple frequency of any one phas e. in addition, the peak-to- peak amplitude of the combined inductor currents is reduced in proportion to the number of phases (equations 1 and 2). increased ripple frequency and lower ripple amplitude mean that the designer can use less per-channel inductance and lower total output capacitance for any performance specification. figure 1 illustrates the multiplica tive effect on output ripple frequency. the three channel currents (il1, il2, and il3) combine to form the ac ripple current and the dc load current. the ripple component has three times the ripple frequency of each individual channel current. each pwm pulse is terminated 1/3 of a cycle after the pwm pulse of the previous phase. the peak-to- peak current for each phase is about 7a, and the dc components of the inductor currents combine to feed the load. to understand the reduction of ripple current amplitude in the multiphase circuit, examine the equation representing an individual channel?s peak-to-peak inductor current. in equation 1, v in and v out are the input and output voltages respectively, l is the single-channel inductor value, and f s is the switching frequency. the output capacitors conduct the ripple component of the inductor current. in the case of multiphase converters, the capacitor current is the sum of the ripple currents from each of the individual channels. compare equation 1 to the expression for the peak-to-peak current after the summation of n symmetrically phase-shifted inductor currents in equation 2. peak-to-peak ripple current decreases by an amount proportional to the number of channels. output- voltage ripple is a function of capacitance, capacitor equivalent series resistance (esr), and inductor ripple current. reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors. another benefit of interleaving is to reduce input ripple current. input capacitance is determined in part by the maximum input ripple current. multiphase topologies can improve overall system cost and size by lowering input ripple current and allowing the designer to reduce the cost of input capacitance. the example in figure 2 illustrates input currents from a three-phase converter combining to reduce the total input ripple current. the converter depicted in figure 2 delivers 36a to a 1.5v load from a 12v input. the rms input capacitor current is 5.9a. compare this to a single-phase converter also stepping down 12v to 1.5v at 36a. the si ngle-phase converter has 11.9a rms input capacitor current. the single-phase converter must use an input capacitor bank with twice the rms current capacity as the equivalent three-phase converter. figures 22, 23 and 24 in the section entitled input capacitor selection can be used to determine the input-capacitor rms current based on load current , duty cycle, and the number of channels. they are provided as aids in determining the optimal input capacitor solution. figure 25 shows the single phase input-capacitor rms current for comparison. figure 1. pwm and inductor-current waveforms for 3-phase converter 1s/div pwm2, 5v/div pwm1, 5v/div il2, 7a/div il1, 7a/div il1 + il2 + il3, 7a/div il3, 7a/div pwm3, 5v/div i p-p v in v out ? () v out lf s v in ----------------------------------------------------- - = (eq. 1) figure 2. channel input currents and input- capacitor rms current for 3-phase converter channel 1 input current 10a/div channel 2 input current 10a/div channel 3 input current 10a/div input-capacitor current, 10a/div 1s/div i cp-p , v in nv out ? () v out lf s v in ----------------------------------------------------------- - = (eq. 2) isl6307b
13 fn9225.0 march 9, 2006 pwm operation the timing of each converter leg is set by the number of active channels. the default channel setting for the isl6307b is four. one switching cycle is defined as the time between pwm1 pulse termination signals. the pulse termination signal is an internally generated clock signal which triggers the falling ed ge of pwm1. the cycle time of the pulse termination signal is the inverse of the switching frequency set by the resistor between the fs pin and ground. each cycle begins when the clock signal commands the channel-1 pwm output to go low. the pwm1 transition signals the channel-1 mosfet driver to turn off the channel-1 upper mosfet and turn on the channel-1 synchronous mosfet. in the def ault channel configuration, the pwm2 pulse terminates 1/4 of a cycle after pwm1. the pwm3 output follows another 1/4 of a cycle after pwm2. pwm4 terminates another 1/4 of a cycle after pwm3. if pwm3 is connected to v cc, two channel operation is selected and the pwm2 pulse terminates 1/2 of a cycle later. connecting pwm4 to vcc selects three channel operation and the pulse-termination times are spaced in 1/3 cycle increments. connecting both pwm3 and pwm4 to vcc selects single-channel operation. once a pwm signal transitions low, it is held low for a minimum of 1/3 cycle. this forc ed off time is required to ensure an accurate current sample. current sensing is described in the next section. after the forced off time expires, the pwm output is enabled. the pwm output state is driven by the position of t he error amplifier output signal, v comp , minus the current correction signal relative to the sawtooth ramp as illustrated in figure 7. when the modified v comp voltage crosses the sawtooth ramp, the pwm output transitions high. the mosfet driver detects the change in state of the pwm signal and turns off the synchronous (lower) mosfet and turns on the upper mosfet. the pwm signal will remain high until the pulse termination signal marks the begi nning of the next cycl e by triggering the pwm signal low. current sampling during the forced off-time following a pwm transition low, the associated channel current sense amplifier uses the isen inputs to reproduce a signal proportional to the inductor current, i l . this current gets sampled starting 1/6 period after each pwm goes low and continuously gets sampled for 1/3 period, or until the pwm goes high, whichever comes first. no matter the current sense method, the sense current, i sen , is simply a scaled version of the inductor current. coincident with the falling edge of the pwm signal, the sample and hold circuitry samples the sensed current signal i sen , as illustrated in figure 3. therefore, the sample current, i n , is proportional to the output current and held for one switching cycle. the sample current is used for current balance, load-line regulation, and overcurrent protection. current sensing the isl6307b supports induc tor dcr sensing, mosfet r ds(on) sensing, or resistive sensing techniques. the internal circuitry, shown in figures 4, 5, and 6, represents one channel of an n-channel converter. this circuitry is repeated for each channel in the converter, but may not be active depending on the status of the pwm3 and pwm4 pins, as described in the pwm operation section. inductor dcr sensing an inductor?s winding is characteristic of a distributed resistance as measured by the dcr (direct current resistance) parameter. consider the inductor dcr as a separate lumped quantity, as shown in figure 4. the channel current i l , flowing through the inductor, will also pass through the dcr. equation 3 shows the s-domain equivalent voltage across the inductor v l . a simple r-c network across th e inductor extracts the dcr voltage, as shown in figure 4. the voltage on the capacitor v c , can be shown to be proportional to the channel current i l , see equation 4. if the r-c network components are selected such that the rc time constant (= r*c) matches the inductor time constant (= l/dcr), the voltage across the capacitor v c is equal to the voltage drop across the dcr, i.e. proportional to the channel current. figure 3. sample and hold timing time pwm i l switching period i sen 0.5tsw sample current, i n v l i l sl dcr + ? () ? = (eq. 3) v c s l dcr ------------- ? 1 + ?? ?? dcr i l ? () ? src 1 + ? () -------------------------------------------------------------------- - = (eq. 4) isl6307b
14 fn9225.0 march 9, 2006 with the internal low-offset cu rrent amplifier, the capacitor voltage v c is replicated across the sense resistor r isen . therefore the current out of isen+ pin, i sen , is proportional to the inductor current. equation 5 shows that the ratio of the channel current to the sensed current i sen is driven by the value of the sense resistor and the dcr of the inductor. resistive sensing for accurate current sense, a dedicated current-sense resistor r sense in series with each output inductor can serve as the current sense element (see figure 5). this technique is more accurate, but reduces overall converter efficiency due to the additional power loss on the current sense element r sense . equation 6 shows the ratio of the channel current to the sensed current i sen . mosfet r ds(on) sensing the controller can also sens e the channel load current by sampling the voltage across the lower mosfet r ds(on) (see figure 6). the amplifier is ground-reference by connecting the isen- pin to the source of the lower mosfet. isen+ pin is connected to the phase node through the current sense resistor r isen . the voltage across r isen is equivalent to the voltage drop across the r ds(on) of the lower mosfet while it is conducting. the resulting current out of the i sen+ pin is proportional to the channel current i l . equation 7 shows the ratio of the channel current to the sensed current i sen . both inductor dcr and mosfet r ds(on) value will increase as the temperatur e increases. therefore the sensed current will increase as the temperature of the current sense element increases . in order to compensate figure 4. dcr sensing configuration i n i sen i l dcr r isen ------------------- = - + isen-(n) sample & hold isl6307b internal circuit v in isen+(n) pwm(n) isl6612 r isen(n) dcr l inductor r v out c out (ptc) - + v c (s) c i l s () - + v l i sen i l dcr r isen ----------------- - ? = (eq. 5) i sen i l r sense r isen ----------------------- ? = (eq. 6) figure 5. sense resistor in series with inductors i n i sen i l r sense r isen -------------------------- = - + isen-(n) sample & hold isl6307b internal circuit isen+(n) r isen(n) r sense l v out c out i l figure 6. mosfet r ds(on) current-sensing circuit i n i sen i l r ds on () r isen --------------------------- - = - + isen+(n) r isen sample & hold isl6307b internal circuit external circuit v in n-channel mosfets - + i l xr ds on () i l isen-(n) (ptc) i sen i l r ds on () r isen ------------------------ - = (eq. 7) isl6307b
15 fn9225.0 march 9, 2006 the temperature effect on the sensed current signal, a positive temperature coefficient (ptc) resistor can be selected for the sense resistor r isen , or the integrated temperature compensation function of isl6307b should be utilized. the integrated temper ature compensation function is described in the temperature compensation section. channel-current balance the sensed current i n from each active channel are summed together and divided by the nu mber of active channels. the resulting average current i avg provides a measure of the total load current. channel current balance is achieved by comparing the sampled current of each channel to the average current to make an ap propriate adjustment to the pwm duty cycle of each channel. intersil?s patented current- balance method is illustrated in figure 7. in the figure, the average current combines with the channel 1 current i 1 to create an error signal i er . the filtered error signal modifies the pulse width commanded by v comp to correct any unbalance and force i er toward zero. the same method for error signal correction is applied to each active channel. channel current balance is essential in achieving the thermal advantage of multiphase operation. with good current balance, the power loss is equally dissipated over multiple devices and a greater area. voltage regulation the integrating compensation network shown in figure 8 assures that the steady-state e rror in the output voltage is limited only to the error in t he reference voltage (output of the dac) and offset errors in the ofs current source, remote-sense and error amplifiers. intersil specifies the guaranteed tolerance of the isl6307b to include the combined tolerances of each of these elements. the output of the error amplifier, v comp , is compared to the sawtooth waveform to generate the pwm signals. the pwm signals control the timing of the intersil mosfet drivers and regulate the converter output to the specified reference voltage. the internal and external circuitry which control voltage regulation is illustrated in figure 8. the isl6307b incorporates an internal differential remote- sense amplifier in the feedba ck path. the amplifier removes the voltage error encountered when measuring the output voltage relative to the local controller ground reference point resulting in a more accurate means of sensing output voltage. connect the microprocessor sense pins to the non- inverting input, vsen, and inverting input, rgnd, of the remote-sense amplifier. t he remote-sense output, v diff , is connected to the inverting input of the error amplifier through an external resistor. a digital to analog converter (dac) generates a reference voltage based on the state of logic signals at pins vid7 through vid0. the dac decodes the 8-bit logic signal (vid) into one of the discrete voltages shown in table 1. each vid input offers a 45 a pull-up to an internal 2.5v source for use with open-drain outputs. the pul l-up current diminishes to zero above the logic threshold to protect voltage-sensitive output devices. external pull-up resistors can augment the pull-up current sources if case leakage into the driving device is greater than 45 a. load-line regulation some microprocessor manufacturers require a precisely- controlled output resistance. this dependence of output voltage on load current is often termed ?droop? or ?load line? regulation. by adding a well controlled output impedance, the output voltage can effectively be level shifted in a direction which works to achieve the load-line regulation required by these manufacturers. figure 7. channel-1 pwm function and current- balance adjustment n i avg i 5 i 4 i 3 - + + - + - f(j ) pwm1 i 1 v comp sawtooth signal i er filter i 6 i 2 figure 8. output voltage and load-line regulation with offset adjustment i avg external circuit isl6307b internal circuit comp r c r fb fb vdiff vsen rgnd - + v droop error amplifier - + v out + differential remote-sense amplifier v comp c c ref dac r ref c ref - + v out - idroop isl6307b
16 fn9225.0 march 9, 2006 table 1. vr10 vid table (with 6.25mv extension) vid4 400mv vid3 200mv vid2 100mv vid1 50mv vid0 25mv vid5 12.5mv vid6 6.25mv voltage (v) 010101 11.6 010101 0 1.59375 010110 1 1.5875 010110 0 1.58125 010111 1 1.575 010111 0 1.56875 011000 1 1.5625 011000 0 1.55625 011001 11.55 011001 0 1.54375 011010 1 1.5375 011010 0 1.53125 011011 1 1.525 011011 0 1.51875 011100 1 1.5125 011100 0 1.50625 011101 11.5 011101 0 1.49375 011110 1 1.4875 011110 0 1.48125 011111 1 1.475 011111 0 1.46875 100000 1 1.4625 100000 0 1.45625 100001 11.45 100001 0 1.44375 100010 1 1.4375 100010 0 1.43125 100011 1 1.425 100011 0 1.41875 100100 1 1.4125 100100 0 1.40625 100101 11.4 100101 0 1.39375 100110 1 1.3875 100110 0 1.38125 100111 1 1.375 100111 0 1.36875 101000 1 1.3625 101000 0 1.35625 101001 11.35 101001 0 1.34375 101010 1 1.3375 101010 0 1.33125 101011 1 1.325 101011 0 1.31875 101100 1 1.3125 101100 0 1.30625 101101 11.3 101101 0 1.29375 101110 1 1.2875 101110 0 1.28125 101111 1 1.275 101111 0 1.26875 110000 1 1.2625 110000 0 1.25625 110001 11.25 110001 0 1.24375 110010 1 1.2375 110010 0 1.23125 110011 1 1.225 110011 0 1.21875 110100 1 1.2125 110100 0 1.20625 110101 11.2 110101 0 1.19375 110110 1 1.1875 110110 0 1.18125 110111 1 1.175 110111 0 1.16875 111000 1 1.1625 111000 0 1.15625 111001 11.15 111001 0 1.14375 111010 1 1.1375 111010 0 1.13125 111011 1 1.125 111011 0 1.11875 table 1. vr10 vid table (with 6.25mv extension) vid4 400mv vid3 200mv vid2 100mv vid1 50mv vid0 25mv vid5 12.5mv vid6 6.25mv voltage (v) isl6307b
17 fn9225.0 march 9, 2006 111100 1 1.1125 111100 0 1.10625 111101 11.1 111101 0 1.09375 111110 1off 111110 0off 111111 1off 111111 0off 000000 1 1.0875 000000 0 1.08125 000001 1 1.075 000001 0 1.06875 000010 1 1.0625 000010 0 1.05625 000011 11.05 000011 0 1.04375 000100 1 1.0375 000100 0 1.03125 000101 1 1.025 000101 0 1.01875 000110 1 1.0125 000110 0 1.00625 000111 11 000111 0 0.99375 001000 1 0.9875 001000 0 0.98125 001001 1 0.975 001001 0 0.96875 001010 1 0.9625 001010 0 0.95625 001011 10.95 001011 0 0.94375 001100 1 0.9375 001100 0 0.93125 001101 1 0.925 001101 0 0.91875 001110 1 0.9125 001110 0 0.90625 001111 10.9 table 1. vr10 vid table (with 6.25mv extension) vid4 400mv vid3 200mv vid2 100mv vid1 50mv vid0 25mv vid5 12.5mv vid6 6.25mv voltage (v) 001111 0 0.89375 010000 1 0.8875 010000 0 0.88125 010001 1 0.875 010001 0 0.86875 010010 1 0.8625 010010 0 0.85625 010011 10.85 010011 0 0.84375 010100 1 0.8375 010100 0 0.83125 table 2. vr11 vid 8-bit vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage 00000000 off 00000001 off 000000101.60000 000000111.59375 000001001.58750 000001011.58125 000001101.57500 000001111.56875 000010001.56250 000010011.55625 000010101.55000 000010111.54375 000011001.53750 000011011.53125 000011101.52500 000011111.51875 000100001.51250 000100011.50625 000100101.50000 000100111.49375 000101001.48750 000101011.48125 000101101.47500 000101111.46875 000110001.46250 000110011.45625 table 1. vr10 vid table (with 6.25mv extension) vid4 400mv vid3 200mv vid2 100mv vid1 50mv vid0 25mv vid5 12.5mv vid6 6.25mv voltage (v) isl6307b
18 fn9225.0 march 9, 2006 000110101. 45000 000110111. 44375 000111001. 43750 000111011. 43125 000111101. 42500 000111111. 41875 001000001. 41250 001000011. 40625 001000101. 40000 001000111. 39375 001001001. 38750 001001011. 38125 001001101. 37500 001001111. 36875 001010001. 36250 001010011. 35625 001010101. 35000 001010111. 34375 001011001. 33750 001011011. 33125 001011101. 32500 001011111. 31875 001100001. 31250 001100011. 30625 001100101. 30000 001100111. 29375 001101001. 28750 001101011. 28125 001101101. 27500 001101111. 26875 001110001. 26250 001110011. 25625 001110101. 25000 001110111. 24375 001111001. 23750 001111011. 23125 001111101. 22500 001111111. 21875 010000001. 21250 010000011. 20625 table 2. vr11 vid 8-bit (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage 010000101.20000 010000111.19375 010001001.18750 010001011.18125 010001101.17500 010001111.16875 010010001.16250 010010011.15625 010010101.15000 010010111.14375 010011001.13750 010011011.13125 010011101.12500 010011111.11875 010100001.11250 010100011.10625 010100101.10000 010100111.09375 010101001.08750 010101011.08125 010101101.07500 010101111.06875 010110001.06250 010110011.05625 010110101.05000 010110111.04375 010111001.03750 010111011.03125 010111101.02500 010111111.01875 011000001.01250 011000011.00625 011000101.00000 011000110.99375 011001000.98750 011001010.98125 011001100.97500 011001110.96875 011010000.96250 011010010.95625 table 2. vr11 vid 8-bit (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage isl6307b
19 fn9225.0 march 9, 2006 in other cases, the designer may determine that a more cost-effective solution can be achieved by adding droop. droop can help to reduce the output-voltage spike that results from fast load-current demand changes. 011010100. 95000 011010110. 94375 011011000. 93750 011011010. 93125 011011100. 92500 011011110. 91875 011100000. 91250 011100010. 90625 011100100. 90000 011100110. 89375 011101000. 88750 011101010. 88125 011101100. 87500 011101110. 86875 011110000. 86250 011110010. 85625 011110100. 85000 011110110. 84375 011111000. 83750 011111010. 83125 011111100. 82500 011111110. 81875 100000000. 81250 100000010. 80625 100000100. 80000 100000110. 79375 100001000. 78750 100001010. 78125 100001100. 77500 100001110. 76875 100010000. 76250 100010010. 75625 100010100. 75000 100010110. 74375 100011000. 73750 100011010. 73125 100011100. 72500 100011110. 71875 100100000. 71250 100100010. 70625 table 2. vr11 vid 8-bit (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage 100100100.70000 100100110.69375 100101000.68750 100101010.68125 100101100.67500 100101110.66875 100110000.66250 100110010.65625 100110100.65000 100110110.64375 100111000.63750 100111010.63125 100111100.62500 100111110.61875 101000000.61250 101000010.60625 101000100.60000 101000110.59375 101001000.58750 101001010.58125 101001100.57500 101001110.56875 101010000.56250 101010010.55625 101010100.55000 101010110.54375 101011000.53750 101011010.53125 101011100.52500 101011110.51875 101100000.51250 101100010.50625 101100100.50000 11111110 off 11111111 off table 2. vr11 vid 8-bit (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage isl6307b
20 fn9225.0 march 9, 2006 the magnitude of the spike is dictated by the esr and esl of the output capacitors selected. by positioning the no-load voltage level near the upper s pecification limit, a larger negative spike can be sustained without crossing the lower limit. by adding a well cont rolled output impedance, the output voltage under load can effectively be level shifted down so that a larger positive spike can be sustained without crossing the upper specification limit. as shown in figure 8, a current proportional to the average current in all active channels, i avg , flows from fb through a load-line regulation resistor, r fb . the resulting voltage drop across r fb is proportional to the output current, effectively creating an output voltage droo p with a steady-state value defined as the regulated output voltage is reduced by the droop voltage v droop . the output voltage as a func tion of load current is derived by combining equat ion 8 with the appropriate sample current expression defined by the current sense method employed. where v ref is the reference voltage, v ofs is the programmed offset voltage, i out is the total output current of the converter, r isen is the sense resistor in the isen line, n is the number of active channels, and r fb is the feedback resistor. r x has a value of dcr, resistor or r ds(on) , or r sense depending on the sensing method. therefore the equivalent loadl ine impedance, i.e. droop impedance, is equal to: output-voltage offset programming the isl6307b allows the designer to accurately adjust the offset voltage. when a resistor, r ofs , is connected between ofs to vcc, the voltage across it is regulated to 1.6v. this causes a proportional current (i ofs ) to flow into ofs. if r ofs is connected to ground, the voltage across it is regulated to 0.4v, and i ofs flows out of ofs. a resistor between dac and ref, r ref , is selected so that the product (i ofs x r ofs ) is equal to the desired offset voltage. these functions are shown in figure 9. as it may be noticed in figure 9, the ofsout pin must be connected to the ref pin for this current injection to function in isl6307b. the current flow through r ref creates an offset at the ref pin, which is ultimately duplicated at the output of the regulator. once the desired output offset voltage has been determined, use the following formulas to set r ofs : for positive offset (connect r ofs to vcc): for negative offset (connect r ofs to gnd): dynamic vid modern microprocessors need to make changes to their core voltage as part of norma l operation. they direct the core-voltage regulator to do this by making changes to the vid inputs during regulator operation. the power management solution is required to monitor the dac inputs and respond to on-the-fly vid changes in a controlled manner. supervising the safe out put voltage transition within the dac range of the processo r without discontinuity or disruption is a necessary function of the core-voltage regulator. the isl6307b checks the vid inputs six times every switching cycle. if the vid code is found to have been changed, the controller waits ha lf of a complete cycle before executing a 12.5mv change. if during the hal f-cycle wait period, the difference between dac level and the new vid code changes, no change is made. if the vid code is more than 1-bit higher or lower than the dac (not recommended), v droop i avg r fb = (eq. 8) v out v ref v offset ? i out 6 ------------- r x r isen ----------------- -r fb ?? ?? ?? ? = (eq. 9) r ll r fb n ------------ r x r isen ----------------- - = (eq. 10) r ofs 1.6 r ref v offset ----------------------------- - = (eq. 11) r ofs 0.4 r ref v offset ----------------------------- - = (eq. 12) dynamic vid d/a e/a vcc dac fb ref ofs vcc gnd + - + - 0.4v 1.6v or gnd r ofs r ref isl6307bcr figure 9. output voltag e offset programming with isl6307b isl6307b
21 fn9225.0 march 9, 2006 the controller will execute 12.5mv changes six times per cycle until vid and dac are equal. it is for this reason that it is important to carefully contro l the rate of vid stepping in 1-bit increments. in order to ensure the smooth transition of output voltage during vid change, a vid step change smoothing network composed of r ref and c ref is required for an isl6307b based voltage regulator. the selection of r ref is based on the desired offset as detailed above in output-voltage offset programming . the selection of c ref is based on the time duration for 1-bit vid change and the allowable delay time. assuming the microprocessor controls the vid change at 1-bit every t vid , the relationship between the time constant of r ref and c ref network and t vid is given by equation 13. operation initialization prior to converter initialization, proper conditions must exist on the enable inputs and vcc. when the conditions are met, the controller begins soft-sta rt. once the output voltage is within the proper window of o peration, vr_rdy asserts a logic 1. enable and disable while in shutdown mode, the pwm outputs are held in a high-impedance state to assure the drivers remain off. the following input conditions must be met before the isl6307b is released from shutdown mode. 1. the bias voltage applied at vcc must reach the internal power-on reset (por) rising threshold. once this threshold is reached, proper operation of all aspects of the isl6307b is guaranteed . hysteresis between the rising and falling thresholds assure that once enabled, the isl6307b will not inadvertently turn off unless the bias voltage drops substantially (see electrical specifications ). 2. the isl6307b features an enable input (en_pwr) for power sequencing between the controller bias voltage and another voltage rail. the enable comparator holds the isl6307b in shutdown until the voltage at en_pwr rises above 0.875v. the enable comparator has about 130mv of hysteresis to prev ent bounce. it is important that the driver ics reach their por level before the isl6307b becomes enabled. the schematic in figure 10 demonstrates sequencing the isl6307b with the isl66xx family of intersil mosfet drivers, which require 12v bias. 3. the voltage on en_vtt must be higher than 0.875v to enable the controller. this pin is typically connected to the output of vtt vr. when all conditions above are satisfied, isl6307b begins the soft-start and ramps the outpu t voltage to 1.1v first. after remaining at 1.1v for some time, isl6307b reads the vid code at vid input pins. if the vid code is valid, isl6307b will regulate the output to the final vid setting. if the vid code is off code, isl6307b will shut down. cycling vcc, en_pwr or en_vtt is needed to restart. soft-start isl6307b based vr has 4 periods during soft-start, as shown in figure 11. after vcc, en_vtt and en_pwr reach their por and enable thresholds, the controller will have fixed delay period td1. after this delay period, the vr will begin first soft-start ramp until the output voltage reaches 1.1v, vboot voltage. then, the c ontroller will regulate the vr voltage at 1.1v for another fix ed period, td3. at the end of td3 period, isl6307b will read the vid signals. if the vid code is valid, isl6307b will in itiate the second soft-start ramp until the voltage reaches the vid voltage minus offset voltage. the soft-start time is the sum of the 4 periods as shown in the following equation. td1 is the fixed delay with typical value as 1.36ms. td3 is determined by the fixed 85s plus the time to obtain valid vid voltage. if the vid is valid before the output reaches the 1.1v, the minimum time to valid the vid input is 500ns. therefore the minimum td3 is about 86s. during td2 and td4, isl6307b digitally controls the dac voltage change at 6.25mv per step. the time for each step is c ref r ref t vid = (eq. 13) figure 10. power sequencing using threshold- sensitive enable (en) function - + 0.875v external circuit isl6307b internal circuit en_pwr +12v por circuit 10k ? 91 0? enable comparator soft-start and fault logic en_vtt vcc + - 0.875v t ss td1td2td3td4 +++ = (eq. 14) isl6307b
22 fn9225.0 march 9, 2006 determined by the frequency of the soft-start oscillator which is defined by the resistor r ss from ss pin to gnd. the 2 soft-start ramp times, assuming the output voltage is 0v before soft-start, td2 and td 4 can be calculated based on the following equations. for example, when vid is set to 1.5v and the rss is set at 100k ? , the first soft-start ramp time td2 will be 704s and the second soft-start ramp time td4 will be 256s. fault monitoring and protection the isl6307b actively monitors output voltage and current to detect fault conditions. fault monitors trigger protective measures to prevent damage to a microprocessor load. one common power good indicator is provided for linking to external system monitors. th e schematic in figure 12 outlines the interaction between the fault monitors and the power good signal. vr_rdy signal the vr_rdy pin is an open-drain logic output to indicate that the soft-start period is co mpleted and the output voltage is within the regulated range. vr_rdy is pulled low during shutdown and releases high after a successful soft-start and a fix delay time, td5. td5 is fixed delay with typical value at 85s. vr_rdy will be pulled low when an undervoltage or overvoltage condition is detect ed, or the controller is disabled by a reset from en_pwr, en_vtt, por, or vid off-code. undervoltage detection the undervoltage threshold is set at 50% of the vid voltage. when the output voltage at vsen is below the undervoltage threshold, vr_rdy gets pulled low. when the output voltage comes back to 60% of the vid voltage, vr_rdy will return back to high. overvoltage protection regardless of the vr being enabled or not, the isl6307b overvoltage protection (ovp) circuit will be active after its por. the ovp thresholds are different under different operation conditions. when vr is not enabled and before the 2nd soft-start, the ovp threshold is 1.275v. once the controller detects a valid vid input, the ovp trip point will be changed to the vid voltage plus 175mv. two actions are taken by the isl6307b to protect the microprocessor load when an overvoltage condition occurs. at the inception of an overvo ltage event, all pwm outputs are commanded low instantly (less than 20ns) until the voltage at vdiff falls below 0.4v. this causes the intersil drivers to turn on the lower mosfets and pull the output voltage below a level that might cause damage to the load. the pwm outputs remain low until vdiff falls below 0.4v, and then pwm signals enter a high-impedance state. the intersil drivers respond to the high-impedance input by turning off both upper and lower mosfets. if the overvoltage condition reoccurs, the isl6307b will again command the lower mosfets to turn on. the isl6307b will continue to protect the load in this fashion as long as the overvoltage condition recurs. td2 1.1xr ss 6.25x25 ----------------------- - s () = (eq. 15) td4 v vid 1.1 ? () xr ss 6.25x25 ------------------------------------------------ s () = (eq. 16) figure 11. soft-start waveforms vout, 500mv/div en_vtt, 1v/div 500s/div td1 td2 td3 td4 td5 vr_rdy, 5v/div figure 12. power good and protection circuitry ovp - + vid + 0.175v vdiff - + 100a i avg - + dac reference ov oc1 uv vr_rdy 50% soft-start, fault and control logic - + oc i 1 repeat for each channel 100a - + oc2 iout r iout i avg 2v isl6307b
23 fn9225.0 march 9, 2006 once an overvoltage condition is detected, normal pwm operation ceases until the isl6307b is reset. cycling the voltage on en_pwr, en_vtt or vcc below the por- falling threshold will reset the controller. cycling the vid codes will not reset the controller. overcurrent protection isl6307b has two levels of overcurrent protection. each phase is protected from a sust ained overcurrent condition on a delayed basis, while the combined phase currents are protected on an instantaneous basis. in instantaneous protection mode, the isl6307b takes advantage of the proportionality between the load current and the average current, i avg , to detect an overcurrent condition. see the channel-current balance section for more detail on how the average current is measured. the average current is continual ly compared with a constant 100 a reference current as shown in figure 12. once the average current exceeds the reference current, a comparator triggers the converter to shutdown. in individual overcurrent pr otection mode, the isl6307b continuously compares the curre nt of each channel with the same 100 a reference current. if any channel current exceeds the reference current continuously for eight consecutive cycles, the comparator triggers the converter to shutdown. the overcurrent protection le vel for the above two ocp modes can be adjusted by c hanging the value of current sensing resistors. in addition, isl6307 can also adjust the average ocp threshold level by adjusting the value of the resistor from iout to gnd. th is provides additional safety for the voltage regulator. the following equation can be used to calculate the value of the resistor r iout based on the desired ocp level i avg, ocp2 . at the beginning of overcurre nt shutdown, the controller places all pwm signals in a high-impedance state within 20ns commanding the intersil mosfet driver ics to turn off both upper and lower mosfets. the syst em remains in this state a period of 4096 switching cycl es. if the controller is still enabled at the end of this wait period, it will attempt a soft- start. if the fault remains, t he trip-retry cycles will continue indefinitely (as shown in figure 13) until either controller is disabled or the fault is cl eared. note that the energy delivered during trip-retry cycl ing is much less than during full-load operation, so there, there is no thermal hazard during this kind of operation. current sense output the isl6307b has 2 current s ense output pins idroop and iout; they are identical. in ty pical application, idroop pin is connected to fb pin for the application where load line is required. iout pin was designed for load current measurement. as shown in typical application schematics on pages 4 to 7, load current information can be obtained by measuring the voltage at iout pin with a resistor connecting iout pin to ground. when the programmable temperature compensation function of isl6307b is properly used, the output current at iout pin is proportional to load current as shown in figure 14. r iout 2 i avg ocp2 , ------------------------------- = (eq. 17) 0a 0v 2ms/div output current, 50a/div figure 13. overcurrent behavior in hiccup mode. f sw = 500khz output voltage, 500mv/div isl6307b
24 fn9225.0 march 9, 2006 thermal monitoring (vr_hot/vr_fan) there are two thermal signals to indicate the temperature status of the voltage regulator: vr_hot and vr_fan. both vr_fan and vr_hot are open-drain output, and external pull-up resistors are required. vr_fan signal indicates that the temperature of the voltage regulator is high and more cooling airflow is needed. vr_hot signal can be used to inform the system that the temperature of the voltage regu lator is too high and the cpu should reduce its power consumption. vr_hot signal may be tied to the cpu?s prochot# signal. the diagram of thermal monitoring function block is shown in figure 15. one ntc resistor should be placed close to the power stage of the voltage regulator to sense the operational temperature, and one pull-up resi stor is needed to form the voltage divider for tm pin. as the temperature of the power stage increases, the resistance of the ntc will reduce, resulting in the reduced voltage at tm pin. figure 16 shows the tm voltage over the temperature for a typical design with a recommended 6.8k ? ntc (p/n: nths0805n02n6801 from vishay) and 1k ? resistor rtm1. we recommend using those resistors for the accurate temperature compensation. there are two comparators with hysteresis to compare the tm pin voltage to the fixed thresholds for vr_fan and vr_hot signals respectively. vr _fan signal is set to high when tm voltage is lower than 33% of vcc voltage, and is pulled to gnd when tm voltage increases to above 39% of vcc voltage. vr_hot is set to high when tm voltage goes below 28% of vcc voltage, and is pulled to gnd when tm voltage goes back to above 33% of vcc voltage. figure 17 shows the operation of those signals. figure 14. voltage at iout pin with a ntc network placed between iout to ground when load current changes v_iout, 200mv/div 100a 50a 0a figure 15. block diagram of thermal monitoring function 0.28v cc 0.33v cc o c r tm1 r ntc vcc tm vr_fan vr_hot figure 16. the ratio of tm voltage to ntc temperature with recommended parts v tm / v cc vs. tem perature 20% 30% 40% 50% 60% 70% 80% 90% 100% 0 20 40 60 80 100 120 140 temperature ( o c) v tm / v cc figure 17. vr_hotand vr_fan signal vs tm voltage tm vr_fan vr_hot 0.39*vcc 0.33*vcc 0.28*vcc temperature t1 t2 t3 isl6307b
25 fn9225.0 march 9, 2006 based on the ntc temperatur e characteristics and the desired threshold of vr_hot signal, the pull-up resistor rtm1 of tm pin is given by: r ntc(t3) is the ntc resistance at the vr_hot threshold temperature t3. the ntc resistance at the set point t2 and release point t1 of vr_fan signal can be calculated as: with the ntc resistance value obtained from equations 19 & 20, the temperature value t2 and t1 can be found from the ntc datasheet. temperature compensation isl6307b supports inductor dcr sensing, mosfet r ds(on) sensing, or resistive sensing techniques. both inductor dcr and msofet r ds(on) have the positive temperature coefficient, which is about +0.38%/c. because the voltage across inductor or mosfet is sensed for the output current information, the sensed current has the same positive temperature coefficient as the inductor dcr or mosfet r ds(on) . in order to obtain the correct current information, there should be a way to correct th e temperature impact on the current sense component. isl6307b provides two methods: integrated temperature compensation and external temperature compensation. integrated temperature compensation when tcomp voltage is equal or greater than vcc/15, isl6307b will utilize the voltage at tm and tcomp pins to compensate the temperature impact on the sensed current. the block diagram of this function is shown in figure 18. when the tm ntc is placed close to the current sense component (inductor or mosfet ), the temperature of the ntc will track the temperat ure of the current sense component. therefore, the tm voltage can be utilized to obtain the temperature of the current sense component. based on vcc voltage, isl6307b converts the tm pin voltage to a 6-bit tm digital signal for temperature compensation. with the non-linear a/d converter of isl6307b, tm digital signal is linearly proportional to the ntc temperature. for accurate temperature compensation, the ratio of the tm voltage to the ntc temperature of the practical design should be similar to that in figure 16. depending on the location of the ntc and the air-flowing, the ntc may be cooler or hotter than the current sense component. tcomp pin voltage can be utilized to correct the temperature difference between ntc and the current sense component. when a different ntc type or different voltage divider is used for the tm function, tcomp voltage can also be used to compensate for the difference between the recommended tm voltage curve in figure 16 and that of the actual design. according to the vcc voltage, isl6307b converts the tcomp pin voltage to a 4-bit tcomp digital signal as tcomp factor n. tcomp factor n is an integer between 0 and 15. the integrated temperature compensati on function is disabled for n = 0. for n = 4, the ntc te mperature is equal to the temperature of the current sense component. for n < 4, the ntc is hotter than the current sense component. the ntc is cooler than the current sense component for n > 4. when n>4, the larger tcomp factor n, the larger the difference between the ntc temperature and the temperature of the current sense component. r tm1 2.75xr ntc t3 () = (eq. 18) r ntc t2 () 1.267xr ntc t3 () = (eq. 19) r ntc t1 () 1.644xr ntc t3 () = (eq. 20) figure 18. block diagram of integrated temperature compensation o c r tm1 r ntc tm r tc1 r tc2 tcomp v cc non-linear a/d 4-bit a/d droop, iout & over current protection k i d/a v cc i sen4 i sen3 i sen2 i sen1 i 1 i 2 i 3 i 4 i 5 i 6 i sen6 i sen5 channel current sense isl6307b
26 fn9225.0 march 9, 2006 isl6307b multiplexes the tcomp factor n with the tm digital signal to obtain the adjustment gain to compensate the temperature impact on the sensed channel current. the compensated channel current signal is used for droop and overcurrent protection functions. design procedure: 1. properly choose the voltage divider for tm pin to match the tm voltage vs temperature curve with the recommended curve in figure 16. 2. run the actual board under th e full load and the desired cooling condition. 3. after the board reaches the th ermal steady state, record the temperature (t csc ) of the current sense component (inductor or mosfet) and the voltage at tm and vcc pins. 4. use the following equation to calculate the resistance of the tm ntc, and find out the corresponding ntc temperature t ntc from the ntc datasheet. 5. use the following equation to calculate the tcomp factor n: 6. choose an integral number close to the above result for the tcomp factor. if this factor is higher than 15, use n=15. if it is less than 1, use n = 1. 7. choose the pull-up resistor r tc1 (typical 10k ? ). 8. if n = 15, do not need the pull-down resistor r tc2 , otherwise obtain r tc2 by the following equation: 9. run the actual board under full load again with the proper resistors to tcomp pin. 10. record the output voltage as v1 immediately after the output voltage is stable with the full load; record the output voltage as v2 after the vr reaches the thermal steady state. 11. if the output voltage increases over 2mv as the temperature increases, i.e. v2-v1 > 2mv, reduce n and redesign r tc2 ; if the output voltage decreases over 2mv as the temperature increases, i.e. v1-v2 > 2mv, increase n and redesign r tc2 . the design spreadsheet is available for those calculations. external temperature compensation by setting the voltage of tcomp pin to 0, the integrated temperature compensation function is disabled. and one external temperature compensation network, shown in figure 18, can be used to canc el the temperature impact on the droop (i.e. load line). the sensed current will flow out of idroop pin and develop the droop voltage across the resistor (r fb ) between fb and vdiff pins. if rfb resistance reduces as the temperature increases, the temperature impact on the droop can be compensated. a ntc resistor can be placed close to the power stage and used to form r fb . due to the non-linear temperature characteristics of t he ntc, a resistor network is needed to make the equivalent resistance between fb and vdiff pin is reverse proportional to the temperature. the external temperature co mpensation network can only compensate the temperature impact on the droop, while it has no impact to the sensed current inside isl6307b. therefore this network cannot compensate for the temperature impact on the over current protection function. general design guide this design guide is intended to provide a high-level explanation of the steps neces sary to create a multiphase power converter. it is assumed th at the reader is familiar with many of the basic skills and te chniques referenced below. in addition to this guide, intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications. power stages the first step in designing a multiphase converter is to determine the number of phases. this determination depends heavily on the cost analysis which in turn depends on system constraints that differ from one design to the next. principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board; whether through-hole components are permitted; and the total board space available for power-supply circuitry. generally speaking, the most economical solutions are those in which each phase handles between 15 and 20a. all surface-mount designs will tend toward the lower end of this current range. if through-hole mosfets and inductors can r ntc t ntc () v tm xr tm1 v cc v ? tm ------------------------------- - = (eq. 21) n 209x t csc t ? ntc () 3xt ntc 400 + ------------------------------------------------------- - 4 + = (eq. 22) r tc2 nxr tc1 15 n ? ----------------------- = (eq. 23) figure 19. voltage at idroop pin with a resistor placed from idroop pin to gnd when load current changes fb o c vdiff comp idroop isl6307b
27 fn9225.0 march 9, 2006 be used, higher per-phase currents are possible. in cases where board space is the limiting constraint, current can be pushed as high as 40a per phase, but these designs require heat sinks and forced air to cool the mosfets, inductors and heat-dissipating surfaces. mosfets the choice of mosfets depends on the current each mosfet will be required to conduct; the switching frequency; the capability of the mosfets to dissipate heat; and the availability and nature of heat sinking and air flow. lower mosfet power calculation the calculation for heat dissipated in the lower mosfet is simple, since virtually all of the heat loss in the lower mosfet is due to current conducted through the channel resistance (r ds(on) ). in equation 24, i m is the maximum continuous output current; i p-p is the peak-to-peak inductor current (see equation 1); d is the duty cycle (v out /v in ); and l is the per-channel inductance. an additional term can be added to the lower-mosfet loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower-mosfet body diode. this term is dependent on the diode forward voltage at i m , v d(on) ; the switching frequency, f s ; and the length of dead times, t d1 and t d2 , at the beginning and the end of the lower-mosfet conduction interval respectively. thus the total maximum power dissipated in each lower mosfet is approximated by the summation of p low,1 and p low,2 . upper mosfet power calculation in addition to r ds(on) losses, a large portion of the upper- mosfet losses are due to currents conducted across the input voltage (v in ) during switching. since a substantially higher portion of the upper-mosfet losses are dependent on switching frequency, the power calculation is more complex. upper mosfet loss es can be divided into separate components in volving the upper-mosfet switching times; the lower-mo sfet body-diode reverse- recovery charge, q rr ; and the upper mosfet r ds(on) conduction loss. when the upper mosfet turns off, the lower mosfet does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. once the lower mosfet begins conducting, the current in the upper mosfet falls to zero as the current in the lower mosfet ramps up to assume the full inductor current. in equation 26, the required time for this commutation is t 1 and the approximated associated power loss is p up,1 . at turn on, the upper mosfet begins to conduct and this transition occurs over a time t 2 . in equation 27, the approximate power loss is p up,2 . a third component involves the lower mosfet?s reverse- recovery charge, q rr . since the inductor current has fully commutated to the upper mosfet before the lower- mosfet?s body diode can draw all of q rr , it is conducted through the upper mosfet across vin. the power dissipated as a result is p up,3 and is approximately finally, the resistive part of t he upper mosfet?s is given in equation 29 as p up,4 . the total power dissipated by the upper mosfet at full load can now be approximated as the summation of the results from equations 26, 27, 28 and 29. since the power equations depend on mosfet parameters, choosing the correct mosfets can be an it erative process involving repetitive solutions to the loss equations for different mosfets and different switching frequencies. current sensing resistor the resistors connected between these isen+ pins and the respective phase nodes or output side of the output inductor determine the gains in the load-line regulation loop and the channel-current balance loop as well as setting the overcurrent trip point. select values for these resistors based on the room temperature r ds(on) of the lower mosfets, dcr of inductor or additional resistor; the full-load operating current, i fl ; and the number of phases, n using equation 30. in certain circumstances, it ma y be necessary to adjust the value of one or more isen resistors. when the components of one or more channels are inhibited from effectively dissipating their heat so that the affected channels run hotter than desired, choose new, sma ller values of risen for the affected phases (see the section entitled channel-current balance ). choose r isen,2 in proportion to the desired p low 1 , r ds on () i m n ----- - ?? ?? ?? 2 1d ? () i lp-p , 2 1d ? () 12 ---------------------------------- - + = (eq. 24) p low 2 , v don () f s i m n ----- - i p-p 2 ---------- - + ?? ?? t d1 i m n ----- - i p-p 2 ---------- - ? ?? ?? ?? t d2 + = (eq. 25) p up 1 , v in i m n ----- - i p-p 2 ---------- - + ?? ?? t 1 2 ---- ?? ?? ?? f s (eq. 26) p up 2 , v in i m n ----- - i p-p 2 ---------- - ? ?? ?? t 2 2 ---- ?? ?? ?? f s (eq. 27) p up 3 , v in q rr f s = (eq. 28) p up 4 , r ds on () i m n ----- - ?? ?? ?? 2 d i p-p 2 12 ---------- - d + (eq. 29) r isen r x 50 10 6 ? ----------------------- i fl n ------- - = (eq. 30) isl6307b
28 fn9225.0 march 9, 2006 decrease in temperature rise in order to cause proportionally less current to flow in the hotter phase. in equation 31, make sure that ? t 2 is the desired temperature rise above the ambient temperature, and ? t 1 is the measured temperature rise above the am bient temperature. while a single adjustment according to equation 31 is usually sufficient, it may occasionally be necessary to adjust r isen two or more times to achieve optimal thermal balance between all channels. load-line regulation resistor the load-line regulation resistor is labeled r fb in figure 8. its value depends on the desired full-load droop voltage (v droop in figure 8). if equation 30 is used to select each isen resistor, the load-line regulation resistor is as shown in equation 32. if one or more of the isen re sistors are adjusted for thermal balance, as in equation 31, the load-line regulation resistor should be selected according to equation 33 where i fl is the full-load operating current and r isen(n) is the isen resistor connected to the n th isen pin. compensation the two opposing goals of compensating the voltage regulator are stability and speed. depending on whether the regulator employs the optiona l load-line regulation as described in load-line regulati on, there are two distinct methods for achieving these goals. compensating load-line regulated converter the load-line regulated converter behaves in a similar manner to a peak-current mode controller because the two poles at the output-filter l- c resonant frequency split with the introduction of current information into the control loop. the final location of these poles is determined by the system function, the gain of the current signal, and the value of the compensation components, r c and c c . since the system poles and zero are affected by the values of the components that are meant to compensate them, the solution to the system equatio n becomes fairly complicated. fortunately there is a simple approximation that comes very close to an optimal solution. tr eating the system as though it were a voltage-mode regulator by compensating the l-c poles and the esr zero of the voltage-mode approximation yields a solution that is always stable with very close to ideal transient performance. the feedback resistor, r fb , has already been chosen as outlined in load-line regulation resistor . select a target bandwidth for the compensated system, f 0 . the target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the per- channel switching frequency. the values of the compensation components depend on the relationships of f 0 to the l-c pole frequency and the esr zero frequency. for each of the three cases which follow, there are a separate set of equations for the compensation components. r isen 2 , r isen ? t 2 ? t 1 ---------- = (eq. 31) r fb v droop 50 10 6 ? ------------------------ - = (eq. 32) r fb v droop i fl r ds on () --------------------------------- -r isen n () n = (eq. 33) figure 20. compensation configuration for load-line regulated isl6307b circuit isl6307b comp c c r c r fb fb idroop vdiff - + v droop c 2 (optional) 1 2 lc ------------------- f 0 > r c r fb 2 f 0 v p-p lc 0.75v in -------------------------------------- - = c c 0.75v in 2 v p-p r fb f 0 -------------------------------------- = case 1: 1 2 lc ------------------- f 0 1 2 c esr () ----------------------------- - < r c r fb v p-p 2 () 2 f 0 2 lc 0.75 v in ---------------------------------------------- = c c 0.75v in 2 () 2 f 0 2 v p-p r fb lc --------------------------------------------------------------- = case 2: (eq. 34) f 0 1 2 c esr () ----------------------------- - > r c r fb 2 f 0 v p-p l 0.75 v in esr () ------------------------------------------ = c c 0.75v in esr () c 2 v p-p r fb f 0 l ------------------------------------------------- = case 3: isl6307b
29 fn9225.0 march 9, 2006 in equation 34, l is the per-channel filter inductance divided by the number of active channels; c is the sum total of all output capacitors; esr is the equivalent-series resistance of the bulk output-filter capacitance; and v p-p is the peak-to- peak sawtooth signal amplitude as described in figure 7 and electrical specifications . the optional capacitor c 2 , is sometimes needed to bypass noise away from the pwm comparator (see figure 20). keep a position available for c 2 , and be prepared to install a high- frequency capacitor of between 22pf and 150pf in case any leading-edge jitter problem is noted. once selected, the compensation values in equation 34 assure a stable converter with reasonable transient performance. in most cases, transient performance can be improved by making adjustments to r c . slowly increase the value of r c while observing the transient performance on an oscilloscope until no further improvement is noted. normally, c c will not need adjustment. keep the value of c c from equation 34 unless some performance issue is noted. compensation without load-line regulation the non load-line regulated converter is accurately modeled as a voltage-mode regulator with two poles at the l-c resonant frequency and a zero at the esr frequency. a type iii controller, as shown in figure 21, provides the necessary compensation. the first step is to choose the desired bandwidth, f 0 , of the compensated system. choose a frequency high enough to assure adequate transient perf ormance but not higher than 1/3 of the switching frequency. the type-iii compensator has an extra high-frequency pole, f hf . this pole can be used for added noise rejection or to assure adequate attenuation at the error-amplifier high-order pole and zero frequencies. a good general rule is to choose f hf = 10f 0 , but it can be higher if desired. choosing f hf to be lower than 10f 0 can cause problems with too much phase shift below the system bandwidth. in the solutions to the compensation equations, there is a single degree of freedom. for the solutions presented in equation 35, r fb is selected arbitrarily. the remaining compensation components are then selected according to equation 35. in equation 35, l is the per-channel filter inductance divided by the number of active channel s; c is the sum total of all output capacitors; esr is the equivalent-series resistance of the bulk output-filter capacitance; and v p-p is the peak-to- peak sawtooth signal amplitude as described in figure 7 and electrical specifications . output filter design the output inductors and the ou tput capacitor bank together to form a low-pass filter responsible for smoothing the pulsating voltage at the phase nodes. the output filter also must provide the transient en ergy until the regulator can respond. because it has a low bandwidth compared to the switching frequency, the output filter necessarily limits the system transient response. th e output capacitor must supply or sink load current while the current in the output inductors increases or decreases to meet the demand. in high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. output filter design begins with minimizing the cost of this part of the circuit. the critical load parameters in choosing the output capacitors are the maximum size of the load step, ? i; the load-current slew rate, di/dt; and the maximum allowable output-voltage deviation under transient loading, ? v max . capacitors are characterized according to their capacitance, esr, and esl (equivalent series inductance). at the beginning of the load tr ansient, the output capacitors supply all of the transient cu rrent. the output voltage will initially deviate by an amount approximated by the voltage drop across the esl. as the load current increases, the figure 21. compensation circuit for isl6307b based converter without load-line regulation isl6307b comp c c r c r fb fb idroop vdiff c 2 c 1 r 1 c c 0.75v in 2 f hf lc 1 ? ?? ?? 2 () 2 f 0 f hf lcr fb v p-p -------------------------------------------------------------------- - = r c v pp 2 ?? ?? 2 f 0 f hf lcr fb - 0.75 v in 2 f hf lc 1 ? ?? ?? ----------------------------------------------------------------------- = r 1 r fb c esr () lc c esr () ? ---------------------------------------- - = c 1 lc c esr () ? r fb ---------------------------------------- - = c 2 0.75v in 2 () 2 f 0 f hf lcr fb v p-p -------------------------------------------------------------------- - = (eq. 35) isl6307b
30 fn9225.0 march 9, 2006 voltage drop across the esr increases linearly until the load current reaches its final value. the capacitors selected must have sufficiently low esl and esr so that the total output- voltage deviation is less than the allowable maximum. neglecting the contribution of i nductor current and regulator response, the output voltage initially deviates by an amount the filter capacitor must have sufficiently low esl and esr so that ? v < ? v max . most capacitor solutions rely on a mixture of high-frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. minimizing the esl of the high-frequency capacitors allows them to support the output voltage as the current increases. minimizing the esr of the bulk capacitors allows them to supply the increased current with less output voltage deviation. the esr of the bulk capacitors also creates the majority of the output-voltage ripple. as the bulk capacitors sink and source the inductor ac ripple current (see interleaving and equation 2), a voltage develops across the bulk-capacitor esr equal to i c,p-p (esr). thus, once the output capacitors are selected, the maximum allowable ripple voltage, v p-p(max) , determines the lower limit on the inductance. since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. the output inductors must be capable of assuming the entire load current before the output voltage decreases more than ? v max . this places an upper limit on inductance. equation 38 gives the upper limit on l for the cases when the trailing edge of the current transient causes a greater output-voltage deviation than the leading edge. equation 39 addresses the leading edge. normally, the trailing edge dictates the selection of l because duty cycles are usually less than 50%. nevertheless, both inequalities should be evaluated, and l should be selected based on the lower of the two results. in each equation, l is the per-channel inductance, c is the total output capacitance, and n is the number of active channels. input supply voltage the vcc input of sl6307b needs to be connected to +12v through a 300 ? resistor with one 1f cap be connected from vcc to gnd. switching frequency there are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper-mosfet loss calcul ation. these effects are outlined in mosfets , and they establish the upper limit for the switching frequency. the lowe r limit is established by the requirement for fast transi ent response and small output- voltage ripple as outlined in output filter design . choose the lowest switching frequency that allows the regulator to meet the transient-response requirements. switching frequency is determi ned by the selection of the frequency-setting resistor, r t (see the figures labeled typical application on pages 4, 5, 6 and 7). equation 40 is provided to assist in selecting the correct value for r t . input capacitor selection the input capacitors are responsible for sourcing the ac component of the input curr ent flowing into the upper mosfets. their rms current capa city must be sufficient to handle the ac component of the current drawn by the upper mosfets that is related to duty cycle and the number of active phases. ? v esl () di dt ---- -esr ()? i + (eq. 36) l esr () v in nv out ? ?? ?? v out f s v in v p-p max () ----------------------------------------------------------- - (eq. 37) l 2ncv o ? i () 2 --------------------- ? v max ? i esr () ? (eq. 38) l 1.25 () nc ? i () 2 ------------------------- - ? v max ? iesr () ? v in v o ? ?? ?? (eq. 39) (eq. 40) r t 2.5x10 10 f sw ------------------------- - = 0.3 0.1 0 0.2 input-capacitor current (i rms /i o ) figure 22. normalized input-capacitor rms current vs duty cycle for 2-phase converter 00.4 1.0 0.2 0.6 0.8 duty cycle (v o /v in ) i l,p-p = 0 i l,p-p = 0.5 i o i l,p-p = 0.75 i o isl6307b
31 fn9225.0 march 9, 2006 for a two phase design, use figure 22 to determine the input-capacitor rms current requirement given the duty cycle, maximum sustained output current (i o ), and the ratio of the per-phase peak-to-peak inductor current (i l,p-p ) to i o . select a bulk capacitor with a ripple current rating which will minimize the total number of input capacitors required to support the rms current calculated. the voltage rating of the capacitors should also be at least 1.25 times greater than the maximum input voltage. figures 23 and 24 provide the same input rms current information for three and four phase designs respectively. use the same approach to selecting the bulk capacitor type and number as described above. low capacitance, high-frequency ceramic capacitors are needed in addition to the bulk capacitors to suppress leading and falling edge voltage spikes. the result from the high current slew rates produced by the upper mosfets turning on and off. select low esl ceramic capacitors and place one as close as possible to each upper mosfet drain to minimize board parasitic impedances and maximize suppression. multiphase rms improvement figure 25 is provided as a reference to demonstrate the dramatic reductions in input-capacitor rms current upon the implementation of the multipha se topology. for example, compare the input rms current requirements of a two-phase converter versus that of a single phase. assume both converters have a duty cycle of 0.25, maximum sustained output current of 40a, and a ratio of i l,p-p to i o of 0.5. the single phase converter would require 17.3arms current capacity while the two-phase converter would only require 10.9arms. the advantages become even more pronounced when output current is increas ed and additional phases are added to keep the component cost down relative to the single phase approach. duty cycle (v o/ v in ) figure 23. normalized input-capacitor rms current vs duty cycle for 3-phase converter 00.4 1.0 0.2 0.6 0.8 input-capacitor current (i rms/ i o ) 0.3 0.1 0 0.2 i l,p-p = 0 i l,p-p = 0.25 i o i l,p-p = 0.5 i o i l,p-p = 0.75 i o input-capacitor current (i rms/ i o ) figure 24. normalized input-capacitor rms current vs duty cycle for 4-phase converter 00.4 1.0 0.2 0.6 0.8 duty cycle (v o/ v in ) 0.3 0.1 0 0.2 i l,p-p = 0 i l,p-p = 0.25 i o i l,p-p = 0.5 i o i l,p-p = 0.75 i o figure 25. normalized input-capacitor rms current vs duty cycle for single-phase converter 00.4 1.0 0.2 0.6 0.8 duty cycle (v o/ v in ) input-capacitor current (i rms/ i o ) 0.6 0.2 0 0.4 i l,p-p = 0 i l,p-p = 0.5 i o i l,p-p = 0.75 i o isl6307b
32 fn9225.0 march 9, 2006 layout considerations the following layout strategies are intended to minimize the impact of board parasitic impedances on converter performance and to optimize the heat-dissipating capabilities of the printed-circuit board. t hese sections highlight some important practices which should not be overlooked during the layout process. component placement within the allotted implementation area, orient the switching components first. the switching components are the most critical because they carry larg e amounts of energy and tend to generate high levels of noise. switching component placement should take into account power dissipation. align the output inductors and mosfets such that spaces between the components are minimized while creating the phase plane. place the intersil mosfet driver ic as close as possible to the mosfets they control to reduce the parasitic impedances due to trace length between critical driver input and output signals. if possible, duplicate the same placement of these components for each phase. next, place the input and output capacitors. position one high-frequency ceramic input capacitor next to each upper mosfet drain. place the bulk input capacitors as close to the upper mosfet drains as dictated by the component size and dimensions. long distances between input capacitors and mosfet drains result in too much trace inductance and a reduction in capacitor performance. locate the output capacitors between the inductors and the load, while keeping them in close proximity to the microprocessor socket. the isl6307b can be placed off to one side or centered relative to the individual phase switching components. routing of sense lines and pwm signals will guide final placement. critical small signal components to place close to the controller include the isen resistors, r t resistor, feedback resistor, and compensation components. bypass capacitors for the isl6307b and isl66xx driver bias supplies must be placed next to their respective pins. trace parasitic impedances will reduce their effectiveness. plane allocation and routing dedicate one solid layer, usually a middle layer, for a ground plane. make all critical comp onent ground connections with vias to this plane. dedicate one additional layer for power planes; breaking the plane up into smaller islands of common voltage. use the remaining layers for signal wiring. route phase planes of copper fi lled polygons on the top and bottom once the switching component placement is set. size the trace width between the driver gate pins and the mosfet gates to carry 4a of current. when routing components in the switching path, use short wide traces to reduce the associated parasitic impedances. isl6307b
33 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9225.0 march 9, 2006 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l48.7x7 48 lead quad flat no-lead plastic package (compliant to jedec mo-220vkkd-2 issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.18 0.23 0.30 5, 8 d 7.00 bsc - d1 6.75 bsc 9 d2 4.15 4.30 4.45 7, 8 e 7.00 bsc - e1 6.75 bsc 9 e2 4.15 4.30 4.45 7, 8 e 0.50 bsc - k0.25 - - - l 0.30 0.40 0.50 8 l1 - - 0.15 10 n482 nd 12 3 ne 12 3 p- -0.609 --129 rev. 1 10/02 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm. isl6307b

▲Up To Search▲

Price & Availability of ISL6307BIRZ

	To Download ISL6307BIRZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .