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128 tm 80c286/883 high performance microprocessor with memory management and protection description the intersil 80c286/883 is a static cmos version of the nmos 80286 microprocessor. the 80c286/883 is an advanced, high-performance microprocessor with specially optimized capabilities for multiple user and multi-tasking sys- tems. the 80c286/883 has built-in memory protection that supports operating system and task isolation as well as pro- gram and data privacy within tasks. the 80c286/883 includes memory management capabilities that map 230 (one gigabyte) of virtual address space per task into 2 24 bytes (16 megabytes) of physical memory. the 80c286/883 is upwardly compatible with 80c86 and 80c88 software (the 80c286/883 instruction set is a super- set of the 80c86/80c88 instruction set). using the 80c286/ 883 real address mode, the 80c286/883 is object code com- patible with existing 80c86 and 80c88 software. in pro- tected virtual address mode, the 80c286/883 is source code compatible with 80c86 and 80c88 software but may require upgrading to use virtual address as supported by the 80c286/883?s integrated memory management and protec- tion mechanism. both modes operate at full 80c286/883 performance and execute a superset of the 80c86 and 80c88 instructions. the 80c286/883 provides special operations to support the efficient implementation and execution of operating systems. for example, one instruction can end execution of one task, save its state, switch to a new task, load its state, and start execution of the new task. the segment-not-present excep- tion and restartable instructions. features ? this circuit is processed in accordance to mil-std- 883 and is fully conformant under the provisions of paragraph 1.2.1. ? compatible with nmos 80286/883 ? static cmos design for low power operation - iccsb = 5ma maximum - iccop = 185ma maximum (80c286-10/883) - iccop = 220ma maximum (80c286-12/883) ? large address space - 16 megabytes physical - 1 gigabyte virtual per task ? integrated memory management, four-level memory protection and support for virtual memory and operating systems ? two 80c86 upward compatible operating modes - 80c286/883 real address mode - protected virtual address mode ? compatible with 80287 numeric data co-processor march 1997 ordering information package temp. range 10mhz 12.5mhz 16mhz 20mhz 25mhz pkg. no. 68 pin pga 0 o c to +70 o c - cg80c286-12 cg80c286-16 cg80c286-20 - g68.b -40 o c to +85 o c ig80c286-10 ig80c286-12 - - - g68.b -55 o c to +125 o c mg80c286-10/883 mg80c286-12/883 - - - g68.b 5962-9067801mxc 5962-9067802mxc - - - g68.b fn2948.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
129 80c286/883 pinout 68 lead pga, component pad view as viewed from underside of the component when mounted on the board. p.c. board view as viewed from the component side of the p.c. board. 68 66 64 62 60 58 56 54 52 53 51 55 57 59 61 63 65 67 2 1 3 5 7 9 10 4 6 8 12 11 13 14 16 15 17 19 18 21 20 22 24 26 28 30 32 34 23 25 27 29 31 33 36 35 37 38 40 39 41 42 44 43 45 46 48 47 49 50 error d7 d6 d5 d4 d3 d2 d1 d0 nc s1 peack a22 a21 a19 a17 a15 a12 d0 a1 clk reset a4 a6 a8 a10 a12 error nc intr nmi pereq ready hlda m/io nc nc busy nc nc v ss v cc hold cod/inta lock d15 d14 d13 d12 d11 d10 d9 d8 v ss bhe nc s0 a23 v ss a20 a18 a16 a14 a0 a2 v cc a3 a5 a7 a9 a11 a13 pin 1 indicator 68 66 64 62 60 58 56 54 52 53 51 55 57 59 61 63 65 67 2 13 579 10 4 68 12 11 13 14 16 15 17 19 18 21 20 22 24 26 28 30 32 34 23 25 27 29 31 33 36 35 37 38 40 39 41 42 44 43 45 46 48 47 49 50 error d7 d6 d5 d4 d3 d2 d1 d0 nc s1 peack a22 a21 a19 a17 a15 a12 d0 a1 clk reset a4 a6 a8 a10 a12 error nc intr nmi pereq ready hlda m/io nc nc busy nc nc v ss v cc hold cod/inta lock d15 d14 d13 d12 d11 d10 d9 d8 v ss bhe nc s0 a23 v ss a20 a18 a16 a14 a0 a2 v cc a3 a5 a7 a9 a11 a13 pin 1 indicator
130 80c286/883 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0v input, output or i/o voltage applied. . . . . . gnd -1.0v to v cc +1.0v storage temperature range . . . . . . . . . . . . . . . . . -65 o c to +150 o c junction temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c lead temperature (soldering 10s). . . . . . . . . . . . . . . . . . . . +300 o c esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 thermal resistance (typical) ja jc pga package . . . . . . . . . . . . . . . . . . . . . 35 o c/w 6 o c/w gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22,500 gates caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not i mplied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. operating conditions operating voltage range . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v operating temperature range. . . . . . . . . . . . . . . . -55 o c to +125 o c system clock (clk) rise time (from 1.0v to 3.6v . . . . 8ns (max) system clock (clk) fall time (from 3.6v to 1.0v) . . . . 8ns (max) input rise and fall time (from 0.8v to 2.0v 80c286-10/883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns (max) 80c286-12/883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8ns (max) table 1. 80c286/883 d.c. electrical performance specifications device guaranteed and 100% tested parameter symbol conditions group a sub- groups temperature limits units min max input low voltage v il v cc = 4.5v 1, 2, 3 -55 o c t a +125 o c-0.5 0.8 v input high voltage v ih v cc = 5.5v 1, 2, 3 -55 o c t a +125 o c2.0 v cc +0.5 v clk input low voltage v ilc v cc = 4.5v 1, 2, 3 -55 o c t a +125 o c-0.5 1.0 v clk input high voltage v ihc v cc = 5.5v 1, 2, 3 -55 o c t a +125 o c3.6 v cc +0.5 v output low voltage v ol i ol = 2.0ma, v cc = 4.5v 1, 2, 3 -55 o c t a +125 o c- 0.4 v output high voltage v oh i oh = -2.0ma, v cc = 4.5v 1, 2, 3 -55 o c t a +125 o c3.0 - v i oh = -100 a, v cc = 4.5v v cc -0.4 - v input leakage current i i v in = gnd or v cc , v cc = 5.5v, pins 29, 31, 57, 59, 61, 63-64 1, 2, 3 -55 o c t a +125 o c-10 10 a input sustaining current low i bhl v cc = 4.5v and 5.5v, v in = 1.0v, note 1 1, 2, 3 -55 o c t a +125 o c38 200 a input sustaining current high i bhh v cc = 4.5v and 5.5v, v in = 3.0v, note 2 1, 2, 3 -55 o c t a +125 o c -50 -400 a input sustaining current on busy and error pins i sh v cc = 4.5v and 5.5v v in = gnd, note 5 1, 2, 3 -55 o c t a +125 o c -30 -500 a output leakage current i o v o = gnd or v cc v cc = 5.5v, pins 1, 7-8, 10-28, 32-34 1, 2, 3 -55 o c t a +125 o c-10 10 a active power supply current i ccop 80c286-10/883, note 4 1, 2, 3 -55 o c t a +125 o c- 185 ma 80c286-12/883, note 4 - 220 ma standby power supply current i ccsb v cc = 5.5v, note 3 1, 2, 3 -55 o c t a +125 o c- 5 ma notes: 2. i bhl should be measured after lowering v in to gnd and then raising to 1.0v on the following pins: 36-51, 66, 67. 3. i bhh should be measured after raising v in to v cc and then lowering to 3.0v on the following pins: 4-6, 36-51, 66-68. 4. i ccsb should be tested with the clock stopped in phase two of the processor clock cycle. v in = v cc or gnd, v cc = 5.5v, outputs unloaded. 5. i ccop measured at 10mhz for the 80c286-10/883 and 12.5mhz for the 80c286-12/883. v in = 2.4v or 0.4v, v cc = 5.5v, outputs unloaded. 6. i sh should be measured after raising v in to v cc and then lowering to 0v on pins 53 and 54.
131 80c286/883 table 2. 80c286/883 ac electrical performance specifications ac timings are referenced to 0.8v and 2.0v points of the signals as illustrated in datasheet waveforms, unless otherwise noted. device guaranteed and 100% tested. parameter symbol conditions group a subgroups temperature 80c286/883 units 10mhz 12.5mhz min max min max system clock (clk) period 1v cc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c50 - 40 - ns system clock (clk) low time 2v cc = 4.5v and 5.5v at 1.0v 9, 10, 11 -55 o c t a +125 o c12 - 11 - ns system clock (clk) high time 3v cc = 4.5v and 5.5v at 3.6v 9, 10, 11 -55 o c t a +125 o c16 - 13 - ns asynchronous inputs setup time (note 1) 4v cc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c20 - 15 - ns asynchronous inputs hold time (note 1) 5v cc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c20 - 15 - ns reset setup time 6 v cc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c19 - 10 - ns reset hold time 7 v cc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c0 - 0 - ns read data setup time 8v cc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c8 - 5 - ns read data hold time 9v cc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c4 - 4 - ns ready setup time 10 v cc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c26 - 20 - ns ready hold time 11 v cc = 4.5v and 5.5v 9, 10, 11 -55 o c t a +125 o c25 - 20 - ns status/peack active delay, (note 4) 12a v cc = 4.5v and 5.5v, c l = 100pf i l = |2ma| 9, 10, 11 -55 o c t a +125 o c1 22 1 21 ns status/peack inactive delay (note 3) 12b v cc = 4.5v and 5.5v, c l = 100pf i l = |2ma| 9, 10, 11 -55 o c t a +125 o c1 30 1 24 ns address valid delay (note 2) 13 v cc = 4.5v and 5.5v, c l = 100pf i l = |2ma| 9, 10, 11 -55 o c t a +125 o c1 35 1 32 ns write data valid delay, (note 2) 14 v cc = 4.5v and 5.5v, c l = 100pf i l = |2ma| 9, 10, 11 -55 o c t a +125 o c0 40 0 31 ns
132 80c286/883 hlda valid delay (note 5) 15 v cc = 4.5v and 5.5v, c l = 100pf il = |2ma| 9, 10, 11 -55 o c t a +125 o c0 47 0 25 ns notes: 1. asynchronous inputs are intr, nmi, hold, pereq, error, and busy. this specification is given only for testing purposes, to as sure recognition at a specific clk edge. 2. delay from 1.0v on the clk to 0.8v or 2.0v. 3. delay from 1.0v on the clk to 0.8v for min (hold time) and to 2.0v for max (inactive delay). 4. delay from 1.0v on the clk to 2.0v for min (hold time) and to 0.8v for max (active delay). 5. delay from 1.0v on the clk to 2.0v. table 3. 80c286/883 electrical performance specifications parameter symbol conditions notes temperature 80c286/883 units 10mhz 12.5mhz min max min max clk input capacitance c clk freq = 1mhz 5 t a = +25 o c-10-10pf other input capacitance c in freq = 1mh 5 t a = +25 o c-10-10pf i/o capacitance c i/o freq = 1mh 5 t a = +25 o c-10-10pf address/status/data float delay 15 1, 3, 4, 5 -55 o c t a +125 o c047032 ns address valid to status setup time 19 i l = | 2.0ma| 1, 2, 5 -55 o c t a +125 o c27 - 20 - ns notes: 1. output load: c l = 100pf. 2. delay measured from address either reaching 0.8v or 2.0v (valid) to status going active reaching 0.8v or status going inactiv e reaching 2.0v. 3. delay from 1.0v on the clk to float (no current drive) condition. 4. i l = -6ma (v oh to float), i l = 8ma (v ol to float). 5. the parameters listed in table 3 are controlled via design or process parameters and are not directly tested. these parameter s are char- acterized upon initial design and after major process and/or design changes. table 4. applicable subgroups conformance groups method subgroups initial test 100%/5004 - interim test 100%/5004 1, 7, 9 pda 100% 1 final test 100% 2, 3, 8a, 8b, 10, 11 group a - 1, 2, 3, 7, 8a, 8b, 9, 10, 11 group c & d samples/5005 1, 7, 9 table 2. 80c286/883 ac electrical performance specifications (continued) ac timings are referenced to 0.8v and 2.0v points of the signals as illustrated in datasheet waveforms, unless otherwise noted. device guaranteed and 100% tested. parameter symbol conditions group a subgroups temperature 80c286/883 units 10mhz 12.5mhz min max min max
133 80c286/883 ac electrical specifications 82c284 and 82c288 timing specifications are given for reference only, and no guarantee is implied. 82c284 timing symbol parameter 10mhz 12.5mhz unit test condition min max min max timing requirements 11 srdy /srdyen setup time 15 - 15 - ns 12 srdy /srdyen hold time 2 - 2 - ns 13 ardy /ardyen setup time 5 - 5 - ns (note 1) 14 ardy /ardyen hold time 30 - 25 - ns (note 1) timing responses 19 pclk delay 0 20 0 16 ns c l = 75pf, i ol = 5ma, i oh = -1ma note: 1. these times are given for testing purposes to ensure a predetermined action. 82c288 timing symbol parameter 10mhz 12.5mhz unit test condition min max min max timing requirements 12 cmdly setup time 15 - 15 - ns 13 cmdly hold time 1 - 1 - ns timing responses 16 ale active delay 1 16 1 16 ns 17 ale inactive delay - 19 - 19 ns 19 dt/r read active delay - 23 - 23 ns c l = 150pf 20 den read active delay 0 21 0 21 ns i ol = 16ma max 21 den read inactive delay 3 23 3 21 ns i oh = -1ma max 22 dt/r read inactive delay 5 24 5 18 ns 23 den write active delay - 23 - 23 ns 24 den write inactive delay 3 23 3 23 ns 29 command active delay from clk 3 21 3 21 ns c l = 300pf 30 command inactive delay from clk 3 20 3 20 ns i ol = 32ma max
134 80c286/883 ac specifications note: 1. for ac testing, input rise and fall times are driven at 1ns per volt. figure 1. ac drive and measure points - clk input clk input 4.0v 0.45v 3.6v 3.6v 1.0v 1.0v 1.0v 1.0v 3.6v 3.6v 4.0v 2.0v 0.8v 0.8v 2.0v 0.8v 2.0v t delay (max) t delay (min) t hold t setup clk input 0.45v 2.4v other 0.4v device device input output
135 80c286/883
136 80c286/883 waveforms notes: 1. the modified timing is due to the cmdly signal being active. 2. 82c254 and 82c288 timing waveforms are shown for reference only, and no guarantee is inplied. figure 2. major cycle timing 3 1 2 12a 12b 2 2 1 2 1 2 1 2 1 2 1 clk v ol v oh t i t s t c t s t c t c s1 ? s0 19 13 19 13 m / io , a 23 - a 0 bhe , lock valid address valid address valid if t s 13 13 valid control valid control valid write data 9 8 14 11 10 15 d 15 - d 0 11 10 11 12 19 14 13 19 19 20 16 17 12 13 13 12 12 13 29 30 (see note 1) 29 30 19 20 21 22 23 24 read (t i or t s ) read cycle illustrated with zero wait states write cycle illustrated with one wait state ready srdy + ardy + pclk alf cmdly mwtc mrdc dt/r ardyen srdyen cod inta 80c286/883 82c284 (see note 2) 82c288 (see note 2) bus cycle type den valid read data
137 80c286/883 notes: 1. pclk indicates which processor cycle phase will occur on the next clk. pclk may not indicate the correct phase until the first cycle is performed. 2. these inputs are asynchronous. the setup and hold times shown assure recognition for testing purposes. figure 3. 80c286/883 asynchronous input signal timing note: 1. when reset meets the setup time shown, the next clk will start or repeat 1 of a processor cycle. figure 4. 80c286/883 reset input timing and subse- quent processor cycle phase waveforms (continued) 2 bus cycle type v ch v cl clk 1 pclk (see note 1) t x intr, nmi hold, pereq (see note 2) error , busy (see note 2) 19 19 4 5 5 4 2 7 reset 1 1 2 6 v ch v cl clk (see note 1) t x v ch clk v cl reset t x 2 2 1 7 6 (see note 1)
138 80c286/883 notes: 1. these signals may not be driven by the 80c286/883 during the time shown. the worst case in terms of latest float time is show n. 2. the data bus will be driven as shown if the last cycle before t i in the diagram was a write t c . 3. the 80c286/883 puts its status pins in a high impedance logic one state during t h . 4. for hold request set up to hlda, refer to figure 8. 5. bhe and lock are driven at this time but will not become valid until t s . 6. the data bus will remain in a high impedance state if a read cycle is performed. figure 5. exiting and entering hold waveforms (continued) 16 2 1 2 1 2 1 2 1 t h t i t h t h or t i bus cycle type v ch clk hilda v cl 16 (see note 4) 12a (note 3) 15 (see note 3) 12b 15 if t s s1 ? s0 peack bhe , lock a 23 - a 0 , m/io , cod/inta (see note 5) 13 (see note 1) 15 valid 14 (see note 6) (see note 2) 15 valid if write d 15 - d 0 pclk 80c286/883 80c284 if npx transfer
139 80c286/883 notes: 1. peack always goes active during the first bus operation of a processor extension data operand transfer sequence. the first bus opera tion will be either a memory read at operand address or i/o read at port address 00fa(h). 2. to prevent a second processor extension data operand transfer, the worst case maximum time (shown above) is 3 x - 12a max -(4) min the actual, configuration dependent, maximum time is: 3 x - 12a max - (4) min +n x 2 x (1) . n is the number of extra t c states added to either the first or second bus operation of the processor extension data operand transfer sequence. figure 6. 80c286/883 pereq/peack timing for one transfer only notes: 1. setup time for reset may be violated with the consideration that 1 of the processor clock may begin one system clk period later. 2. setup and hold times for reset must be met for proper operation, but reset may occur during 1 or 2. 3. the data bus is only guaranteed to be in a high impedance state at the time shown. figure 7. initial 80c286/883 pin state during reset waveforms (continued) 1 12a 2 clk 1 2 2 1 2 1 1 2 t i t s t c t s t c t i v ch v cl clk s1 ? s0 peack m/io , a 23 -a 0 cod inta pereq memory address if proc. ext. to memory transfer i/o port address 00fa(h) if memory to proc. ext. transfer 12b 5 4 i/o port address 00fa(h) if proc. ext. to memory transfer memory address if memory to proc. ext. transfer bus cycle type (see note 1) (see note 2) i/0 read if proc. ext. to memory memory read if memory to proc. ext memory write if proc. ext. to memory i/o write if memory to proc. ext. 1 1 12b t x s1 ? s0 bus cycle type 2 2 2 2 2 1 1 1 1 t x t x t i clk v ch v cl 6 7 6 (see note 1) peack a 23 - a 0 bhe m/io cod/inta at least 16 clk periods unknown unknown unknown unknown unknown 13 13 13 15 (see note 3) lock data hilda 16 (see note 2) reset (see note 5) t h 2 1 t h 2 1 t h 2 1 bus hold acknowledge t s 2 1 t c 2 1 t c 2 1 t c 2 1 t i 2 1 t h 2 1 bus hold acknowledge write cycle bus cycle type clk
140 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com 80c286/883 die characteristics die dimensions: 286 x 283 x 19 1mils metallization: type: si-al thickness: 8k ? glassivation: type: nitrox thickness: 10k ? worst case current density: 2 x 10 5 a/cm 2 lead temperature: (10s soldering): 300 o c metallization mask layout 80c286/883 spec number

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