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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 fax (510) 668-7017 www.exar.com xr xrk49911 3.3v high-speed (110 mhz) programmable skew clock buffer october 2005 rev. 1.0.1 functional description the xrk49911 is a 3.3v high-speed low-voltage programmable skew clock buffer. it is intended for high-performance computer systems and offers user selectable control over system clock functions to optimize timing. eight outputs, arranged in four banks, can each drive 50 ? terminated transmission lines while delivering minimal and specified output skews and full-swing low voltage ttl logic levels. each bank (two outputs per bank) can be individually selected for one of nine delay or function configurations through two dedicated tri-level inputs. these outputs are able to lead or lag the clkin input reference clock by up to 6 time units from their nominal ?zero? skew position. the integrated pll allows external load and transmission line delay effects to be canceled achieving zero delay capability. combining the zero delay capability with the selectable output skew functions, output-to-output delays of up to 12 time units can be created. the xrk49911?s divide functions (divide-by-two and divide-by-four) allow distribution of a low-frequency clock that can be multiplied by two or four at the clock destination. this feature facilitates clock distribution while allowing maximum system clock flexibility. features ? 3.75- to 110-mhz output operation ? all output pair skew <100 ps typical ? three skew grades -2 : t skew0 <250ps -5 : t skew0 <500ps -7 : t skew0 <700ps ? selectable output functions skew adjustments of +/- 6t u (up to 18 ns) inverted and non-inverted operation at 1 / 2 and 1 / 4 input frequency operation at 2x and 4x input frequency ? cycle-cycle jitter < 25 ps (rms) < 200 ps (pk-pk) ? zero input-to-output delay ? 50% duty-cycle outputs ? lvttl outputs drive 50 ? terminated lines ? operates from a single 3.3v supply ? 32-pin plcc package ? green packaging ? lead free lead frame available f igure 1. b lock d iagram of the xrk49911 pll clkin fb_in fsel* pll_bypass* bank ?skew? control qa0 qa1 qb0 qb1 qc0 qc1 qd0 qd1 sela[1:0]* selb[1:0]* selc[1:0]* seld[1:0]* * tri-level inputs l m h ref feedback 2 2 2 2
xrk49911 xr 3.3v high-speed (110 mhz) programmable skew clock buffer rev. 1.0.1 2 product ordering information p roduct n umber a ccuracy t emperature r ange XRK49911IJ-2 250 ps -40c to +85c xrk49911cj-2 250 ps 0c to +70c xrk49911ij-5 500 ps -40c to +85c xrk49911cj-5 500 ps 0c to +70c xrk49911cj-7 750 ps 0c to +70c f igure 2. p in o ut of the xrk49911 qc1 qc0 v ccn fb_in v ccn qb1 qb0 xrk49911 selc0 fsel v ccq clkin gnd pll_bypass selb1 selc1 seld0 seld1 v ccq v ccn qd1 qdo gnd gnd 5 6 7 8 9 10 11 12 13 selb0 gnd sela1 sela0 v ccn qa0 qa1 gnd gnd 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20 4 3 2 1 323130
xr xrk49911 rev. 1.0.1 3.3v high-speed (110 mhz) programmable skew clock buffer 3 pin descriptions p in n ame p in # t ype d escription clkin 1 i reference clock input. fb_in 17 i pll?s feedback input. (normally connected to one of the eight outputs) fsel 3 i tri-level frequency range select. see table 1 pll_bypass 31 i tri-level select. see pll_bypass section. sela0 sela1 26 27 i tri-level select inputs for bank a outputs (qa0, qa1). see table 2. selb0 selb1 29 30 i tri-level select inputs for bank b outputs (qb0, qb1). see table 2. selc0 selc1 4 5 i tri-level select inputs for bank c outputs (qc0, qc1). see table 2. seld0 seld1 6 7 i tri-level select inputs for bank d outputs (qd0, qd1). see table 2. qa0 qa1 24 23 o bank a output pair. see table 2. qb0 qb1 20 19 o bank b output pair. see table 2. qc0 qc1 15 14 o bank c output pair. see table 2. qd0 qd1 11 10 o bank d output pair. see table 2. v ccn 9 16 18 25 pwr power supply for output drivers. v ccq 2 8 pwr power supply for internal circuitry. gnd 12 13 21 22 28 32 pwr ground.
xrk49911 xr 3.3v high-speed (110 mhz) programmable skew clock buffer rev. 1.0.1 4 skew select control the skew select control consists of four independent banks. each bank has two low-skew, high-fanout drivers (qx0, qx1), and two corresponding tri-level function select (selx0, selx1) inputs. the nine possible output states for each bank are shown in table 2 as determined by each bank?s select inputs. all timing measurements are made with respect to the clkin input with the output connected to the fb_in input configured for 0 t u operation. n otes : 1. for all tri-level (three-state) inputs, high indicates a connection to v cc , low indicates a connection to gnd, and mid indicates an open connection. internal termination circuitry holds an unconnected input to v cc /2. 2. the level to be set on fsel is determined by the ?normal? operating frequency (f nom ) of the pll. nominal frequency (f nom ) always appears at qa0 and the other outputs when they are operated in their undivided modes (see table 2). the frequency appearing at the clkin and fb_in inputs will be f nom when the output connected to fb_in is undivided. the frequency of the clkin and fb_in inputs will be f nom 2 or f nom 4 when the part is configured for a frequency multiplication. 3. when the fsel pin is selected high, the clkin input must not transition upon power-up until v cc has reached 2.8v. t able 1: f requency r ange s elect and t u c alculation [1] f nom (mh z ) t u = 1 / ( f nom x n) a pproximate f requency (mh z ) at which t u = 1.0 ns fsel [2] m in m ax where n = low 15 30 44 22.7 mid 25 50 26 38.5 high [3] 40 110 16 62.5 t able 2: p rogrammable s kew c onfigurations [1] f unction s elect i nputs o utput f unctions sel x 1 sel x 0 qa[1:0], qb[1:0] qc[1:0] qd[1:0] low low -4t u 2 2 low mid -3t u -6t u -6t u low high -2t u -4t u -4t u mid low -1t u -2t u -2t u mid mid 0t u 0t u 0t u mid high +1t u +2t u +2t u high low +2t u +4t u +4t u high mid +3t u +6t u +6t u high high +4t u 4 inverted
xr xrk49911 rev. 1.0.1 3.3v high-speed (110 mhz) programmable skew clock buffer 5 pll_bypass the pll_bypass input is a tri-level input. in normal system operation, this pin is connected to ground. in normal operation (tied low) all outputs will function based only on the connection of their own function select inputs (selx[1:0]) and the waveform characteristics of the pll. if the pll_bypass input is forced to its mid or high state the device will operate in pll bypass mode, with the phase locked loop disconnected, and clkin waveforms will directly control all outputs. relative output to output timing is controlled by the selx[1:0], the same as in normal mode. f igure 3. t ypical o utputs with fb_in c onnected to a z ero -s kew o utput (n/a) lm ll lh lm (n/a) lh ml ml (n/a) mm mm mh (n/a) hl mh hm (n/a) hh hl (n/a) hm (n/a) ll/hh (n/a) hh(d) -6t u -4t u -3t u -2t u -1t u 0t u +1t u +2t u +3t u +4t u +6t u divided invert sela[1:0] selc[1:0] selb[1:0] seld[1:0] fb_in clkin t 0 -6t u t 0 -5t u t 0 -4t u t 0 -3t u t 0 -2t u t 0 -1t u t 0 t 0 +1t u t 0 +2t u t 0 +3t u t 0 +4t u t 0 +5t u t 0 +6t u
xrk49911 xr 3.3v high-speed (110 mhz) programmable skew clock buffer rev. 1.0.1 6 electrical specifications absolute maximum ratings operating range storage temperature ?65 c to +150 c ambient temperature with power applied ?55 c to +125 c supply voltage to ground potential ?0.5v to +7.0v dc input voltage ?0.5v to +7.0v output current into outputs (low) 64 ma static discharge voltage (per mil-std-883, method 3015) >3000v latch-up current. >200 ma r ange a mbient t emperature vcc industrial -40 c to +85 c 3.3 + 10% commercial 0 c to +70 c 3.3 + 10% electrical characteristics over the 3.3v + 10% operating range s ymbol d escription m in m ax u nit c ondition v oh output high voltage 2.4 v v cc = min., i oh = -18ma v ol output low voltage 0.45 v v cc = min., i ol = 35ma v ih input high voltage 2.0 v cc v (clkin and fb_in inputs only) v il input low voltage -0.5 0.8 v v ihh tri-level input high voltage (fsel, selx[1:0], test) [4] 0.87*v cc v cc v min. < v cc < max. v imm tri-level input mid voltage (fsel, selx[1:0], test) [4] 0.47*v cc 0.53 * v cc v min. < v cc < max. v ill tri-level input low voltage (fsel, selx[1:0], test) [4] 0.0 0.13 * v cc v min. < v cc < max. i ih input high leakage current (clkin and fb_in inputs only) 20 ? v cc = max., v in = max. i il input low leakage current (clkin and fb_in inputs only) -20 ? v cc = max., v in = 0.4v i ihh input high current (fsel, selx[1:0], test) 200 ? v in = v cc i imm input mid current (fsel, selx[1:0], test) -50 50 a v in = v cc /2 i ill input low current (fsel, selx[1:0], test) -200 a v in = gnd
xr xrk49911 rev. 1.0.1 3.3v high-speed (110 mhz) programmable skew clock buffer 7 n otes : 4. these inputs are normally wired to v cc , gnd or left unconnected (actual threshold voltages vary as a percentage of v cc ). internal termination resistors hold unconnected inputs at v cc /2. if these inputs are switched, the function and timing of the outputs may glitch and the pll may require an additional t lock time before all data sheet limits are achieved. 5. xrk49911 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. room temperature only. 6. total output current per output pair can be approximated by the following expression that includes device current plus load current: xrk49911: i ccn = {(4+0.11f) + [(835-3f)/z + (.0022fc)]n} x 1.1 where: f = frequency in mhz c = capacitive load in pf z = line impedance in ohms n = number of loaded outputs; 0, 1, or 2 7. total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to the load circuit: pd = {(22 + 0.61f) + [(1550 + 2.7f)/z) + .0125fc]n} x 1.1 see note 6 for variable definition. 8. applies to clkin and fb_in inputs only. i os short circuit current [5] -200 ma v cc = max, v out = gnd (25 only) i ccq operating current used by inter - nal circuitry com?l 95 ma v ccn = v ccq = max., all inputs selects open ind 100 i ccn output buffer current per output pair [6] 19 ma v ccn = v ccq = max., i out = 0 ma inputs selects open, f max pd power dissipation per output pair [7] 104 mw v ccn = v ccq = max., i out = 0 ma input selects open, f max capacitance [8 ] s ymbol d escription m ax . u nit c ondition c in input capacitance 10 pf t a = 25c, f=1mhz, v cc =3.3v electrical characteristics over the 3.3v + 10% operating range s ymbol d escription m in m ax u nit c ondition
xrk49911 xr 3.3v high-speed (110 mhz) programmable skew clock buffer rev. 1.0.1 8 f igure 4. ac t est l oad f igure 5. i nput t est w aveform switching characteristics over the operating range [2,9 ] s ymbol d escription m in m ax u nit f nom operating clock frequency in mhz fsel = low [1, 2] 15 30 mhz fsel = mid [1, 2] 25 50 fsel = high [1, 2, 3] 40 110 c l r2 r1 v cc load r1 = 100 r2 = 100 c l = 30pf (includes fixture and probe capacitances ) 0.0v 2.0v v th = 1.5v 0.8v 2.0v v th = 1.5v 0.8v <1ns <1ns 3.0v
xr xrk49911 rev. 1.0.1 3.3v high-speed (110 mhz) programmable skew clock buffer 9 n otes : 9. test measurement levels for the xrk49911 are ttl levels (1.5v to 1.5v). test conditions assume signal transition times of 2 ns or less and output loading as shown in the ac test loads and waveforms unless otherwise specified. 10. skew is defined as the time between the earliest and the latest output transition among all outputs for which the same t u delay has been selected when all are loaded with 30pf and terminated with 50 ? to v cc /2. switching characteristics over the 3.3v + 10% operating range [2,9 ] s ymbol d escription xrk49911-2 xrk49911-5 xrk49911-7 u nit m in t yp m ax m in t yp m ax m in t yp m ax t rpwh clkin pulse width high 4 4 4 ns t rpwl clkin pulse width low 4 4 4 ns t u programmable skew unit see table 1 t skewpr zero output matched-pair skew (qx[1:0]) [10, 11] 0.05 0.2 0.1 0.25 0.1 0.25 ns t skew0 zero output skew (all outputs) [10, 12] 0.1 0.25 0.25 0.5 0.3 0.75 ns t skew1 output skew (rise-rise, fall-fall, same class outputs) [10, 13] 0.25 0.5 0.6 0.7 0.6 1 ns t skew2 output skew (rise-fall, nominal- inverted, divided-divided) [10, 13] 0.3 1 0.5 1 1 1.5 ns t skew3 output skew (rise-rise, fall-fall, different class outputs) [10, 13] 0.25 0.5 0.5 0.7 0.7 1.2 ns t skew4 output skew (rise-fall, nominal- divided, divided-inverted [10, 13] 0.5 0.9 0.5 1 1.2 1.7 ns t dev device-to-device skew [14, 15] 0.75 1.25 1.65 ns t pd propagation delay, clkin rise to fb_in rise -0.25 0 0.25 -0.5 0 0.5 -0.7 0 0.7 ns t odcv output duty cycle variation [16] -0.65 0 0.65 -1 0 1 -1.2 0 1.2 ns t pwh output high time deviation from 50% [17] 2.0 2.5 3 ns t pwl output low time deviation from 50% [17] 1.5 3 3.5 ns t orise output rise time [17, 18] 0.15 1 1.2 0.15 1 1.5 0.15 1.5 2.5 ns t ofall output fall time [17, 18] 0.15 1 1.2 0.15 1 1.5 0.15 1.5 2.5 ns t lock pll lock time [19] 0.5 0.5 0.5 ms t jr cycle-to-cycle output jitter rms [14] 25 25 25 ps peak-to-peak [14] 200 200 200
xrk49911 xr 3.3v high-speed (110 mhz) programmable skew clock buffer rev. 1.0.1 10 11. t skewpr is defined as the skew between a pair of outputs (qx0 and qx1) when all eight outputs are selected for 0t u . 12. t skew0 is defined as the skew between outputs when they are selected for 0t u . other outputs are divided or inverted but not shifted 13. there are three classes of outputs: nominal (multiple of t u delay), inverted (qd[1:0] only with seld0 = seld1 = high), and divided (qc[1:0] and qd[1:0] only in divide-by-2 or divide-by-4 mode). 14. guaranteed by statistical correlation. tested initially and after any design or process changes that may affect these parameters. 15. t dev is the output-to-output skew between any two devices operating under the same conditions (v cc ambient temperature, air flow, etc.) 16. t odcv is the deviation of the output from a 50% duty cycle. output pulse width variations are included in t skew2 and t skew4 specifications. 17. specified with outputs loaded with 30pf for the xrk49911-5 and -7 devices. devices are terminated through 50 ? to v cc /2. t pwh is measured at 2.0v. t pwl is measured at 0.8v. 18. t orise and t ofall measured between 0.8v and 2.0v. 19. t lock is the time that is required before synchronization is achieved. this specification is valid only after v cc is stable and within normal operating limits. this parameter is measured from the application of a new signal or frequency at clkin or fb_in until t pd is within specified limits f igure 6. ac t iming d iagrams clkin fb_in qxx output other qxx output inverted qxx output clkin divided by 2 t ref t rpwh t rpwl t pd t odcv t odcv t jr t skewpr, t skew0, 1 t skewpr, t skew0, 1 t skew2 t skew2 clkin divided by 4 t skew3, 4 t skew3, 4 t skew3, 4 t skew1, 3, 4 t skew2, 4
xr xrk49911 rev. 1.0.1 3.3v high-speed (110 mhz) programmable skew clock buffer 11 package dimensions b1 b a a1 c d2 e r seating plane a2 corner chamfer 30 x h1 72 deg typ. e3 d3 1 232 d d1 e e1 45 x h2 symbol min max min max a 0.120 0.140 3.05 3.56 a1 0.075 0.095 1.91 2.41 a2 0.020 --- 0.51 --- b 0.013 0.021 0.33 0.53 b1 0.026 0.032 0.66 0.81 c 0.008 0.013 0.19 0.32 d 0.485 0.495 12.33 12.58 d1 0.448 0.454 11.39 11.54 d2 0.400 0.440 10.17 11.18 d3 e 0.585 0.595 14.87 15.11 e1 0.545 0.557 13.85 14.15 e2 0.500 0.540 12.71 13.72 e3 e h1 0.023 0.029 0.58 0.74 h2 0.042 0.048 1.07 1.22 r 0.025 0.045 0.64 1.14 note: the control dimension is in inches. 0.050 bsc 1.27 bsc inches millimeters 10.16 typ. 0.400 typ. 0.300 typ. 7.62 typ. 32 lead plastic leaded chip carrier (plcc) rev. 1.00
xrk49911 xr 3.3v high-speed (110 mhz) programmable skew clock buffer rev. 1.0.1 12 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2005 exar corporation datasheet october 2005. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. revision history r evision # d ate d escription 1.0.0 june 17, 2005 initial production release 1.0.1 october 5, 2005 product ordering information: remove "f" product numbers and lead free column.

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