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this document contains information on a new product. specifications and information herein are subject to change without notice. http://www.solomon-systech.com ssd1339 rev 1.1 p 1/59 jul 2005 copyright ? 2005 solomon systech limited advance information 132rgb x 132 with 2 smart icon lines dot matrix oled/pled segment/common driver with controller ssd1339
solomon systech jul 2005 p 2/59 rev 1.1 ssd1339 table of contents 1. gerenal description......................................................................................................... ..........................5 2. features.................................................................................................................... ..........................................5 3. ordering information........................................................................................................ .......................6 4. block diagram............................................................................................................... .................................7 5. die pad floor plan.......................................................................................................... ..............................8 6. pin description............................................................................................................. .................................15 7. functional block discriptions ............................................................................................... ..........19 o scillator c ircuit and d isplay t ime g enerator ...........................................................................................19 r eset c ircuit ............................................................................................................................... ..........................19 c ommand d ecoder and c ommand i nterface ...................................................................................................20 mpu p arallel 6800- series i nterface ................................................................................................................20 mpu p arallel 8080- series i nterface ................................................................................................................20 mpu s erial i nterface ............................................................................................................................... ..........21 g raphic d isplay d ata ram (gddram) ..........................................................................................................22 g ray s cale and g ray s cale t able ...................................................................................................................26 c urrent c ontrol and v oltage c ontrol .........................................................................................................27 s egment d rivers /c ommon d rivers ...................................................................................................................27 dc-dc v oltage c onverter ............................................................................................................................... .28 8. command table ............................................................................................................... .............................29 9. command descriptions ........................................................................................................ ....................34 10. maximum ratings............................................................................................................ ...........................47 11. dc characteristics......................................................................................................... .........................48 12. ac characteristics......................................................................................................... .........................49 13. application example ........................................................................................................ ......................53 14. package information........................................................................................................ .....................54 ssd1339u3 p in a ssignment ............................................................................................................................... ..54 ssd1339u3 cof details dimensions ..................................................................................................................56
ssd1339 rev 1.1 p 3/59 jul 2005 solomon systech table of figures f igure 1 ? b lock d iagram ............................................................................................................................... .........7 f igure 2 ? SSD1339Z pin assignment .......................................................................................................................8 f igure 3 ? SSD1339Z alignment mark dimensions ..............................................................................................13 f igure 4 ? d ie tray information ............................................................................................................................14 f igure 5 ? o scillator c ircuit ............................................................................................................................... .19 f igure 6 ? d isplay data read back procedure - insertion of dummy read .....................................................20 f igure 7 ? d isplay data write procedure in spi mode .......................................................................................21 f igure 8 ? g raphic d isplay d ata ram s tructure .............................................................................................22 f igure 9 ? 262 k color depth data writing sequence in 18- bit mcu interface ..............................................22 f igure 10 ? 262 k color depth data writing sequence in 16- bit mcu interface in o ption 1 ........................23 f igure 11 ? 262 k color depth data writing sequence in 16- bit mcu interface in o ption 2 ........................23 f igure 12 ? 262 k color depth graphic display data writing sequence in 9- bit mcu interface .................23 f igure 13 ? 262 k color depth graphic display data writing sequence in 8- bit mcu interface .................23 f igure 14 ? 65 k color depth graphic display data writing sequence in 16- bit mcu interface .................23 f igure 15 ? 65 k color depth graphic display data writing sequence in 8- bit mcu interface ...................24 f igure 16 ? d isplay data ram writing position for color a, b and c data input in 65 k color mode ......24 f igure 17 ? d isplay data ram writing position for color a, b and c data input in 256 color mode ......25 f igure 18 ? r elation between graphic data ram value and gray scale table entry for three colors 26 f igure 19 ? i llustration of relation between graphic display ram value and gray scale control .....27 f igure 20 ? e xample of column and row address pointer movement .............................................................34 f igure 21 ? a ddress pointer movement of horizontal address increment mode .........................................35 f igure 22 ? a ddress pointer movement of vertical address increment mode ..............................................35 f igure 23 ? e xample of set display start line with no remap ..........................................................................37 f igure 24 ? e xample of set display offset with no remap .................................................................................37 f igure 25 ? e xample of gamma correction by gray scale table setting .......................................................39 f igure 26 ? s egment output current for different contrast control and master current setting .......41 f igure 27 ? e xample of draw line command ........................................................................................................42 f igure 28 ? e xample of draw rectangle command ............................................................................................42 f igure 29 ? e xample of draw circle command ....................................................................................................43 f igure 30 ? e xample of copy command .................................................................................................................44 f igure 31 ? e xample of copy + clear = m ove command ....................................................................................45 f igure 32 ? 6800- series mpu parallel interface characteristics ..................................................................50 f igure 33 ? 8080- series mpu parallel interface characteristics ..................................................................51 f igure 34 ? s erial interface characteristics .....................................................................................................52 f igure 35 ? a pplication example for 8- bit 6800- parallel interface mode ....................................................53 f igure 36 - ssd1339u3 pin assignment ..................................................................................................................54 f igure 37 - ssd1339u3 detail dimensions ............................................................................................................56
solomon systech jul 2005 p 4/59 rev 1.1 ssd1339 list of tables t able 1 ? o rdering i nformation .............................................................................................................................6 t able 2 ? SSD1339Z d ie p ad c oordinates ..............................................................................................................9 t able 3 ? c ommand table ............................................................................................................................... ........29 t able 4 ? g raphic acceleration command ..........................................................................................................32 t able 5 ? r esult of change of brightness by dim window command ..............................................................44 t able 6 ? m aximum ratings ............................................................................................................................... .....47 t able 7 ? dc characteristics ............................................................................................................................... .48 t able 8 ? ac characteristics ............................................................................................................................... .49 t able 9 ? 6800-s eries mpu parallel interface timing characteristics .........................................................50 t able 10 ? 8080-s eries mpu parallel interface timing characteristics ......................................................51 t able 11 ? s erial interface timing characteristics ..........................................................................................52 t able 12 - ssd1339u3 pin assignment ...................................................................................................................55
ssd1339 rev 1.1 p 5/59 jul 2005 solomon systech 1. gerenal description the ssd1339 is a single-chip cmos oled/pled driver with controller for organic/polymer light emitting diode dot-matrix graphic display system. it consists of 396 segments (132rgb), 132 commons and 2 smart icon lines. this ic is designed for common cathode type oled panel. the ssd1339 displays data directly from its internal 132x133x18 bits graphic data ram (gddram). data/commands are sent from general mcu through the hardware selectable 6800/8000 series compatible parallel interface or serial peripheral interface. it has a 256 steps contrast control and 262k color control 2. features support max. 132rgb x 132 matrix panel + icon line power supply: vdd=2.4-3.5v vddio=1.5v - 3.5v vcc=7.0v - 18.0v oled driving output voltage, 16v maximum dc-dc voltage booster controller segment maximum source current: 200ua common maximum sink current: 80ma embedded 132x133x18 bit sram display buffer 16 step master current control, and 256 step current control for the three color components smart icon mode programmable color mode of 256, 65k, 262k programmable frame rate graphic acceleration command set (gac) 8/9/16/18-bit 6800-series parallel interface, 8/9/16/18-bit 8080-series parallel interface and serial peripheral interface. wide range of operating temperature: -40 to 90 c
solomon systech jul 2005 p 6/59 rev 1.1 ssd1339 3. ordering information table 1 ? ordering information ordering part number seg com package form reference remark SSD1339Z 132rgb 132 cog page 8 ? min seg pad pitch: 41.2 m ? min com pad pitch: 41.2 m ssd1339u3 128rgb 128 cof page 54 punched cof
ssd1339 rev 1.1 p 7/59 jul 2005 solomon systech 4. block diagram common drivers (odd) segment drivers common driver s(even) grey scale decoder display timing generator oscillator gddram mcu interface command decoder res# cs# d/c# e (rd#) r/w#(wr#) bs2 bs1 bs0 d 17 ? d 0 vsl vcl v cc v comh v ref v pa v pb v pc i ref com130 com128 | com2 com0 comx sa0 sb0 sc0 sa1 sb1 sc1 | sa131 sb131 sc131 cl cls bggnd vddb vssb gdr rese fb vbref com1 com3 | com129 com131 comx v ddio v dd v ss dc-dc voltage converter seg/com oled driving block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 1 ? block diagram
solomon systech jul 2005 p 8/59 rev 1.1 ssd1339 5. die pad floor plan figure 2 ? SSD1339Z pin assignment + represents the centre of the alignment mark x-pos (m) y-pos (m) -8176.0 307.0 8176.0 307.0 -9140.0 -941.0 9140.0 -941.0 all alignment keys have size 75 m x 75 m die size: 20989um x 2250um die thickness: 457um +/- 25um min i/o pad pitch: 76.2 m min seg pad pitch: 41.2 m min com pad pitch: 41.2 m bump height: nominal 15 m pad #1
ssd1339 rev 1.1 p 9/59 jul 2005 solomon systech pad # pad name x-axis y-axis pad # pad name x-axis y-axis pad # pad name x-axis y-axis 1 nc -10160.275 -1043 81 tr0 -3886.2 -1043 161 vss 2209.8 -1043 2 nc -10084.075 -1043 82 vss -3810 -1043 162 r/w#(wr#) 2286 -1043 3 nc -10007.875 -1043 83 vssb -3733.8 -1043 163 e(rd#) 2362.2 -1043 4 nc -9931.675 -1043 84 vssb -3657.6 -1043 164 vddio 2438.4 -1043 5 nc -9737.3 -1043 85 vssb -3581.4 -1043 165 d0 2514.6 -1043 6 nc -9661.1 -1043 86 vssb -3505.2 -1043 166 d1 2590.8 -1043 7 nc -9584.9 -1043 87 gdr -3429 -1043 167 d2 2667 -1043 8 nc -9508.7 -1043 88 gdr -3352.8 -1043 168 d3 2743.2 -1043 9 nc -9432.5 -1043 89 gdr -3276.6 -1043 169 d4 2819.4 -1043 10 nc -9356.3 -1043 90 gdr -3200.4 -1043 170 d5 2895.6 -1043 11 nc -9280.1 -1043 91 gdr -3124.2 -1043 171 d6 2971.8 -1043 12 nc -9203.9 -1043 92 gdr -3048 -1043 172 d7 3048 -1043 13 nc -9127.7 -1043 93 gdr -2971.8 -1043 173 d8 3124.2 -1043 14 nc -9051.5 -1043 94 gdr -2895.6 -1043 174 d9 3200.4 -1043 15 nc -8975.3 -1043 95 gdr -2819.4 -1043 175 d10 3276.6 -1043 16 nc -8899.1 -1043 96 gdr -2743.2 -1043 176 d11 3352.8 -1043 17 nc -8822.9 -1043 97 gdr -2667 -1043 177 d12 3429 -1043 18 nc -8746.7 -1043 98 gdr -2590.8 -1043 178 d13 3505.2 -1043 19 nc -8670.5 -1043 99 gdr -2514.6 -1043 179 d14 3581.4 -1043 20 nc -8594.3 -1043 100 gdr -2438.4 -1043 180 d15 3657.6 -1043 21 nc -8518.1 -1043 101 gdr -2362.2 -1043 181 vddio 3733.8 -1043 22 nc -8441.9 -1043 102 gdr -2286 -1043 182 ms 3810 -1043 23 nc -8305.8 -1043 103 gdr -2209.8 -1043 183 cls 3886.2 -1043 24 nc -8229.6 -1043 104 gdr -2133.6 -1043 184 d16 3962.4 -1043 25 nc -8153.4 -1043 105 gdr -2057.4 -1043 185 d17 4038.6 -1043 26 vcc -8077.2 -1043 106 gdr -1981.2 -1043 186 vss 4114.8 -1043 27 vcc -8001 -1043 107 vddb -1905 -1043 187 vss 4191 -1043 28 vcc -7924.8 -1043 108 vddb -1828.8 -1043 188 vss 4267.2 -1043 29 vcc -7848.6 -1043 109 vddb -1752.6 -1043 189 vss 4343.4 -1043 30 vcc -7772.4 -1043 110 vddb -1676.4 -1043 190 vss 4419.6 -1043 31 vcc -7696.2 -1043 111 vdd -1600.2 -1043 191 vss 4495.8 -1043 32 vcc -7620 -1043 112 vdd -1524 -1043 192 vcl 4572 -1043 33 vcc -7543.8 -1043 113 vdd -1447.8 -1043 193 vcl 4648.2 -1043 34 vcomh -7467.6 -1043 114 vdd -1371.6 -1043 194 vcl 4724.4 -1043 35 vcomh -7391.4 -1043 115 fb -1295.4 -1043 195 vcl 4800.6 -1043 36 vcomh -7315.2 -1043 116 vss -1219.2 -1043 196 vcl 4876.8 -1043 37 vsl -7239 -1043 117 rese -1143 -1043 197 vcl 4953 -1043 38 vsl -7162.8 -1043 118 vbref -1066.8 -1043 198 vcl 5029.2 -1043 39 vsl -7086.6 -1043 119 vss -990.6 -1043 199 vcl 5105.4 -1043 40 vsl -7010.4 -1043 120 bggnd -914.4 -1043 200 vcl 5181.6 -1043 41 vsl -6934.2 -1043 121 nc -838.2 -1043 201 vcl 5257.8 -1043 42 vsl -6858 -1043 122 vpa -762 -1043 202 vcl 5334 -1043 43 vsl -6781.8 -1043 123 vpb -685.8 -1043 203 vcl 5410.2 -1043 44 vsl -6705.6 -1043 124 vpc -609.6 -1043 204 vdd 5486.4 -1043 45 vsl -6629.4 -1043 125 vss -533.4 -1043 205 vdd 5562.6 -1043 46 vdd -6553.2 -1043 126 nc -457.2 -1043 206 vdd 5638.8 -1043 47 vdd -6477 -1043 127 vss -381 -1043 207 vdd 5715 -1043 48 vdd -6400.8 -1043 128 gpio0 -304.8 -1043 208 vdd 5791.2 -1043 49 vdd -6324.6 -1043 129 gpio1 -228.6 -1043 209 vdd 5867.4 -1043 50 vdd -6248.4 -1043 130 vddio -152.4 -1043 210 vdd 5943.6 -1043 51 vdd -6172.2 -1043 131 icasc -76.2 -1043 211 vdd 6019.8 -1043 52 vdd -6096 -1043 132 icasb 0 -1043 212 vsl 6096 -1043 53 vdd -6019.8 -1043 133 icasa 76.2 -1043 213 vsl 6172.2 -1043 54 vcl -5943.6 -1043 134 vss 152.4 -1043 214 vsl 6248.4 -1043 55 vcl -5867.4 -1043 135 vref 228.6 -1043 215 vsl 6324.6 -1043 56 vcl -5791.2 -1043 136 vcc 304.8 -1043 216 vsl 6400.8 -1043 57 vcl -5715 -1043 137 vmona 381 -1043 217 vsl 6477 -1043 58 vcl -5638.8 -1043 138 vmona 457.2 -1043 218 vsl 6553.2 -1043 59 vcl -5562.6 -1043 139 vcc 533.4 -1043 219 vsl 6629.4 -1043 60 vcl -5486.4 -1043 140 vcc 609.6 -1043 220 vsl 6705.6 -1043 61 vcl -5410.2 -1043 141 vcc 685.8 -1043 221 vsl 6781.8 -1043 62 vcl -5334 -1043 142 vcc 762 -1043 222 vsl 6858 -1043 63 vss -5257.8 -1043 143 vcc 838.2 -1043 223 vsl 6934.2 -1043 64 vss -5181.6 -1043 144 vss 914.4 -1043 224 vddio 7010.4 -1043 65 vss -5105.4 -1043 145 iref 990.6 -1043 225 vddio 7086.6 -1043 66 vss -5029.2 -1043 146 m 1066.8 -1043 226 vcomh 7162.8 -1043 67 vss -4953 -1043 147 cl 1143 -1043 227 vcomh 7239 -1043 68 vss -4876.8 -1043 148 dof# 1219.2 -1043 228 vcomh 7315.2 -1043 69 vssb -4800.6 -1043 149 res# 1295.4 -1043 229 vcomh 7391.4 -1043 70 vssb -4724.4 -1043 150 vss 1371.6 -1043 230 vcomh 7467.6 -1043 71 vssb -4648.2 -1043 151 d/c# 1447.8 -1043 231 vcc 7543.8 -1043 72 vssb -4572 -1043 152 vddio 1524 -1043 232 vcc 7620 -1043 73 tr8 -4495.8 -1043 153 cs# 1600.2 -1043 233 vcc 7696.2 -1043 74 tr7 -4419.6 -1043 154 vss 1676.4 -1043 234 vcc 7772.4 -1043 75 tr6 -4343.4 -1043 155 bs2 1752.6 -1043 235 vcc 7848.6 -1043 76 tr5 -4267.2 -1043 156 vddio 1828.8 -1043 236 vcc 7924.8 -1043 77 tr4 -4191 -1043 157 bs1 1905 -1043 237 vcc 8001 -1043 78 tr3 -4114.8 -1043 158 vss 1981.2 -1043 238 vcc 8077.2 -1043 79 tr2 -4038.6 -1043 159 bs0 2057.4 -1043 239 nc 8153.4 -1043 80 tr1 -3962.4 -1043 160 vddio 2133.6 -1043 240 nc 8229.6 -1043 table 2 ? SSD1339Z die pad coordinates
solomon systech jul 2005 p 10/59 rev 1.1 ssd1339 pad # pad name x-axis y-axis pad # pad name x -axis y-axis pad # pad name x -axis y-axis 241 nc 8305.8 -1043 321 com30 9723.2 1030 401 sa15 6344.8 1030 242 nc 8441.9 -1043 322 com29 9682 1030 402 sb15 6303.6 1030 243 nc 8518.1 -1043 323 com28 9640.8 1030 403 sc15 6262.4 1030 244 nc 8594.3 -1043 324 com27 9599.6 1030 404 sa16 6221.2 1030 245 nc 8670.5 -1043 325 com26 9558.4 1030 405 sb16 6180 1030 246 nc 8746.7 -1043 326 com25 9517.2 1030 406 sc16 6138.8 1030 247 nc 8822.9 -1043 327 com24 9476 1030 407 sa17 6097.6 1030 248 nc 8899.1 -1043 328 com23 9434.8 1030 408 sb17 6056.4 1030 249 nc 8975.3 -1043 329 com22 9393.6 1030 409 sc17 6015.2 1030 250 nc 9051.5 -1043 330 com21 9352.4 1030 410 sa18 5974 1030 251 nc 9127.7 -1043 331 com20 9311.2 1030 411 sb18 5932.8 1030 252 nc 9203.9 -1043 332 com19 9270 1030 412 sc18 5891.6 1030 253 nc 9280.1 -1043 333 com18 9228.8 1030 413 sa19 5850.4 1030 254 nc 9356.3 -1043 334 com17 9187.6 1030 414 sb19 5809.2 1030 255 nc 9432.5 -1043 335 com16 9146.4 1030 415 sc19 5768 1030 256 nc 9508.7 -1043 336 com15 9105.2 1030 416 sa20 5726.8 1030 257 nc 9584.9 -1043 337 com14 9064 1030 417 sb20 5685.6 1030 258 nc 9661.1 -1043 338 com13 9022.8 1030 418 sc20 5644.4 1030 259 nc 9737.3 -1043 339 com12 8981.6 1030 419 sa21 5603.2 1030 260 nc 9931.675 -1043 340 com11 8940.4 1030 420 sb21 5562 1030 261 nc 10007.875 -1043 341 com10 8899.2 1030 421 sc21 5520.8 1030 262 nc 10084.075 -1043 342 com9 8858 1030 422 sa22 5479.6 1030 263 nc 10160.275 -1043 343 com8 8816.8 1030 423 sb22 5438.4 1030 264 nc 10359.7 -1060 344 com7 8775.6 1030 424 sc22 5397.2 1030 265 com65 10359.7 -967 345 com6 8734.4 1030 425 sa23 5356 1030 266 com64 10359.7 -925.8 346 com5 8693.2 1030 426 sb23 5314.8 1030 267 com63 10359.7 -884.6 347 com4 8652 1030 427 sc23 5273.6 1030 268 com62 10359.7 -843.4 348 com3 8610.8 1030 428 sa24 5232.4 1030 269 com61 10359.7 -802.2 349 com2 8569.6 1030 429 sb24 5191.2 1030 270 com60 10359.7 -761 350 com1 8528.4 1030 430 sc24 5150 1030 271 com59 10359.7 -719.8 351 com0 8487.2 1030 431 sa25 5108.8 1030 272 com58 10359.7 -678.6 352 comx 8446 1030 432 sb25 5067.6 1030 273 com57 10359.7 -637.4 353 nc 8404.8 1030 433 sc25 5026.4 1030 274 com56 10359.7 -596.2 354 nc 8363.6 1030 434 sa26 4985.2 1030 275 com55 10359.7 -555 355 nc 8240 1030 435 sb26 4944 1030 276 com54 10359.7 -513.8 356 sa0 8198.8 1030 436 sc26 4902.8 1030 277 com53 10359.7 -472.6 357 sb0 8157.6 1030 437 sa27 4861.6 1030 278 com52 10359.7 -431.4 358 sc0 8116.4 1030 438 sb27 4820.4 1030 279 com51 10359.7 -390.2 359 sa1 8075.2 1030 439 sc27 4779.2 1030 280 com50 10359.7 -349 360 sb1 8034 1030 440 sa28 4738 1030 281 com49 10359.7 -307.8 361 sc1 7992.8 1030 441 sb28 4696.8 1030 282 com48 10359.7 -266.6 362 sa2 7951.6 1030 442 sc28 4655.6 1030 283 com47 10359.7 -225.4 363 sb2 7910.4 1030 443 sa29 4614.4 1030 284 com46 10359.7 -184.2 364 sc2 7869.2 1030 444 sb29 4573.2 1030 285 com45 10359.7 -143 365 sa3 7828 1030 445 sc29 4532 1030 286 com44 10359.7 -101.8 366 sb3 7786.8 1030 446 sa30 4490.8 1030 287 nc 10359.7 -60.6 367 sc3 7745.6 1030 447 sb30 4449.6 1030 288 nc 10359.7 -19.4 368 sa4 7704.4 1030 448 sc30 4408.4 1030 289 nc 10359.7 21.8 369 sb4 7663.2 1030 449 sa31 4367.2 1030 290 nc 10359.7 63 370 sc4 7622 1030 450 sb31 4326 1030 291 nc 10359.7 104.2 371 sa5 7580.8 1030 451 sc31 4284.8 1030 292 nc 10359.7 145.4 372 sb5 7539.6 1030 452 sa32 4243.6 1030 293 nc 10359.7 186.6 373 sc5 7498.4 1030 453 sb32 4202.4 1030 294 nc 10359.7 227.8 374 sa6 7457.2 1030 454 sc32 4161.2 1030 295 nc 10359.7 269 375 sb6 7416 1030 455 sa33 4120 1030 296 nc 10359.7 310.2 376 sc6 7374.8 1030 456 sb33 4078.8 1030 297 nc 10359.7 351.4 377 sa7 7333.6 1030 457 sc33 4037.6 1030 298 nc 10359.7 404.1 378 sb7 7292.4 1030 458 sa34 3996.4 1030 299 nc 10359.7 562.95 379 sc7 7251.2 1030 459 sb34 3955.2 1030 300 nc 10359.7 615.65 380 sa8 7210 1030 460 sc34 3914 1030 301 nc 10359.7 656.85 381 sb8 7168.8 1030 461 sa35 3872.8 1030 302 nc 10359.7 698.05 382 sc8 7127.6 1030 462 sb35 3831.6 1030 303 nc 10359.7 739.25 383 sa9 7086.4 1030 463 sc35 3790.4 1030 304 nc 10359.7 780.45 384 sb9 7045.2 1030 464 sa36 3749.2 1030 305 nc 10359.7 833.15 385 sc9 7004 1030 465 sb36 3708 1030 306 nc 10389.7 1030 386 sa10 6962.8 1030 466 sc36 3666.8 1030 307 nc 10318.5 1030 387 sb10 6921.6 1030 467 sa37 3625.6 1030 308 com43 10258.8 1030 388 sc10 6880.4 1030 468 sb37 3584.4 1030 309 com42 10217.6 1030 389 sa11 6839.2 1030 469 sc37 3543.2 1030 310 com41 10176.4 1030 390 sb11 6798 1030 470 sa38 3502 1030 311 com40 10135.2 1030 391 sc11 6756.8 1030 471 sb38 3460.8 1030 312 com39 10094 1030 392 sa12 6715.6 1030 472 sc38 3419.6 1030 313 com38 10052.8 1030 393 sb12 6674.4 1030 473 sa39 3378.4 1030 314 com37 10011.6 1030 394 sc12 6633.2 1030 474 sb39 3337.2 1030 315 com36 9970.4 1030 395 sa13 6592 1030 475 sc39 3296 1030 316 com35 9929.2 1030 396 sb13 6550.8 1030 476 sa40 3254.8 1030 317 com34 9888 1030 397 sc13 6509.6 1030 477 sb40 3213.6 1030 318 com33 9846.8 1030 398 sa14 6468.4 1030 478 sc40 3172.4 1030 319 com32 9805.6 1030 399 sb14 6427.2 1030 479 sa41 3131.2 1030 320 com31 9764.4 1030 400 sc14 6386 1030 480 sb41 3090 1030
ssd1339 rev 1.1 p 11/59 jul 2005 solomon systech pad # pad name x-axis y-axis pad # pad name x -axis y-axis pad # pad name x -axis y-axis 481 sc41 3048.8 1030 561 sb68 -247.2 1030 641 sa95 -3666.8 1030 482 sa42 3007.6 1030 562 sc68 -288.4 1030 642 sb95 -3708 1030 483 sb42 2966.4 1030 563 sa69 -329.6 1030 643 sc95 -3749.2 1030 484 sc42 2925.2 1030 564 sb69 -370.8 1030 644 sa96 -3790.4 1030 485 sa43 2884 1030 565 sc69 -412 1030 645 sb96 -3831.6 1030 486 sb43 2842.8 1030 566 sa70 -453.2 1030 646 sc96 -3872.8 1030 487 sc43 2801.6 1030 567 sb70 -494.4 1030 647 sa97 -3914 1030 488 sa44 2760.4 1030 568 sc70 -535.6 1030 648 sb97 -3955.2 1030 489 sb44 2719.2 1030 569 sa71 -576.8 1030 649 sc97 -3996.4 1030 490 sc44 2678 1030 570 sb71 -618 1030 650 sa98 -4037.6 1030 491 sa45 2636.8 1030 571 sc71 -659.2 1030 651 sb98 -4078.8 1030 492 sb45 2595.6 1030 572 sa72 -824 1030 652 sc98 -4120 1030 493 sc45 2554.4 1030 573 sb72 -865.2 1030 653 sa99 -4161.2 1030 494 sa46 2513.2 1030 574 sc72 -906.4 1030 654 sb99 -4202.4 1030 495 sb46 2472 1030 575 sa73 -947.6 1030 655 sc99 -4243.6 1030 496 sc46 2430.8 1030 576 sb73 -988.8 1030 656 sa100 -4284.8 1030 497 sa47 2389.6 1030 577 sc73 -1030 1030 657 sb100 -4326 1030 498 sb47 2348.4 1030 578 sa74 -1071.2 1030 658 sc100 -4367.2 1030 499 sc47 2307.2 1030 579 sb74 -1112.4 1030 659 sa101 -4408.4 1030 500 sa48 2266 1030 580 sc74 -1153.6 1030 660 sb101 -4449.6 1030 501 sb48 2224.8 1030 581 sa75 -1194.8 1030 661 sc101 -4490.8 1030 502 sc48 2183.6 1030 582 sb75 -1236 1030 662 sa102 -4532 1030 503 sa49 2142.4 1030 583 sc75 -1277.2 1030 663 sb102 -4573.2 1030 504 sb49 2101.2 1030 584 sa76 -1318.4 1030 664 sc102 -4614.4 1030 505 sc49 2060 1030 585 sb76 -1359.6 1030 665 sa103 -4655.6 1030 506 sa50 2018.8 1030 586 sc76 -1400.8 1030 666 sb103 -4696.8 1030 507 sb50 1977.6 1030 587 sa77 -1442 1030 667 sc103 -4738 1030 508 sc50 1936.4 1030 588 sb77 -1483.2 1030 668 sa104 -4779.2 1030 509 sa51 1895.2 1030 589 sc77 -1524.4 1030 669 sb104 -4820.4 1030 510 sb51 1854 1030 590 sa78 -1565.6 1030 670 sc104 -4861.6 1030 511 sc51 1812.8 1030 591 sb78 -1606.8 1030 671 sa105 -4902.8 1030 512 sa52 1771.6 1030 592 sc78 -1648 1030 672 sb105 -4944 1030 513 sb52 1730.4 1030 593 sa79 -1689.2 1030 673 sc105 -4985.2 1030 514 sc52 1689.2 1030 594 sb79 -1730.4 1030 674 sa106 -5026.4 1030 515 sa53 1648 1030 595 sc79 -1771.6 1030 675 sb106 -5067.6 1030 516 sb53 1606.8 1030 596 sa80 -1812.8 1030 676 sc106 -5108.8 1030 517 sc53 1565.6 1030 597 sb80 -1854 1030 677 sa107 -5150 1030 518 sa54 1524.4 1030 598 sc80 -1895.2 1030 678 sb107 -5191.2 1030 519 sb54 1483.2 1030 599 sa81 -1936.4 1030 679 sc107 -5232.4 1030 520 sc54 1442 1030 600 sb81 -1977.6 1030 680 sa108 -5273.6 1030 521 sa55 1400.8 1030 601 sc81 -2018.8 1030 681 sb108 -5314.8 1030 522 sb55 1359.6 1030 602 sa82 -2060 1030 682 sc108 -5356 1030 523 sc55 1318.4 1030 603 sb82 -2101.2 1030 683 sa109 -5397.2 1030 524 sa56 1277.2 1030 604 sc82 -2142.4 1030 684 sb109 -5438.4 1030 525 sb56 1236 1030 605 sa83 -2183.6 1030 685 sc109 -5479.6 1030 526 sc56 1194.8 1030 606 sb83 -2224.8 1030 686 sa110 -5520.8 1030 527 sa57 1153.6 1030 607 sc83 -2266 1030 687 sb110 -5562 1030 528 sb57 1112.4 1030 608 sa84 -2307.2 1030 688 sc110 -5603.2 1030 529 sc57 1071.2 1030 609 sb84 -2348.4 1030 689 sa111 -5644.4 1030 530 sa58 1030 1030 610 sc84 -2389.6 1030 690 sb111 -5685.6 1030 531 sb58 988.8 1030 611 sa85 -2430.8 1030 691 sc111 -5726.8 1030 532 sc58 947.6 1030 612 sb85 -2472 1030 692 sa112 -5768 1030 533 sa59 906.4 1030 613 sc85 -2513.2 1030 693 sb112 -5809.2 1030 534 sb59 865.2 1030 614 sa86 -2554.4 1030 694 sc112 -5850.4 1030 535 sc59 824 1030 615 sb86 -2595.6 1030 695 sa113 -5891.6 1030 536 sa60 782.8 1030 616 sc86 -2636.8 1030 696 sb113 -5932.8 1030 537 sb60 741.6 1030 617 sa87 -2678 1030 697 sc113 -5974 1030 538 sc60 700.4 1030 618 sb87 -2719.2 1030 698 sa114 -6015.2 1030 539 sa61 659.2 1030 619 sc87 -2760.4 1030 699 sb114 -6056.4 1030 540 sb61 618 1030 620 sa88 -2801.6 1030 700 sc114 -6097.6 1030 541 sc61 576.8 1030 621 sb88 -2842.8 1030 701 sa115 -6138.8 1030 542 sa62 535.6 1030 622 sc88 -2884 1030 702 sb115 -6180 1030 543 sb62 494.4 1030 623 sa89 -2925.2 1030 703 sc115 -6221.2 1030 544 sc62 453.2 1030 624 sb89 -2966.4 1030 704 sa116 -6262.4 1030 545 sa63 412 1030 625 sc89 -3007.6 1030 705 sb116 -6303.6 1030 546 sb63 370.8 1030 626 sa90 -3048.8 1030 706 sc116 -6344.8 1030 547 sc63 329.6 1030 627 sb90 -3090 1030 707 sa117 -6386 1030 548 sa64 288.4 1030 628 sc90 -3131.2 1030 708 sb117 -6427.2 1030 549 sb64 247.2 1030 629 sa91 -3172.4 1030 709 sc117 -6468.4 1030 550 sc64 206 1030 630 sb91 -3213.6 1030 710 sa118 -6509.6 1030 551 sa65 164.8 1030 631 sc91 -3254.8 1030 711 sb118 -6550.8 1030 552 sb65 123.6 1030 632 sa92 -3296 1030 712 sc118 -6592 1030 553 sc65 82.4 1030 633 sb92 -3337.2 1030 713 sa119 -6633.2 1030 554 sa66 41.2 1030 634 sc92 -3378.4 1030 714 sb119 -6674.4 1030 555 sb66 0 1030 635 sa93 -3419.6 1030 715 sc119 -6715.6 1030 556 sc66 -41.2 1030 636 sb93 -3460.8 1030 716 sa120 -6756.8 1030 557 sa67 -82.4 1030 637 sc93 -3502 1030 717 sb120 -6798 1030 558 sb67 -123.6 1030 638 sa94 -3543.2 1030 718 sc120 -6839.2 1030 559 sc67 -164.8 1030 639 sb94 -3584.4 1030 719 sa121 -6880.4 1030 560 sa68 -206 1030 640 sc94 -3625.6 1030 720 sb121 -6921.6 1030
solomon systech jul 2005 p 12/59 rev 1.1 ssd1339 pad # pad name x-axis y-axis pad # pad name x -axis y-axis 721 sc121 -6962.8 1030 801 nc -10389.7 1030 722 sa122 -7004 1030 802 nc -10359.7 833.15 723 sb122 -7045.2 1030 803 nc -10359.7 780.45 724 sc122 -7086.4 1030 804 nc -10359.7 739.25 725 sa123 -7127.6 1030 805 nc -10359.7 698.05 726 sb123 -7168.8 1030 806 nc -10359.7 656.85 727 sc123 -7210 1030 807 nc -10359.7 615.65 728 sa124 -7251.2 1030 808 nc -10359.7 562.95 729 sb124 -7292.4 1030 809 nc -10359.7 404.1 730 sc124 -7333.6 1030 810 nc -10359.7 351.4 731 sa125 -7374.8 1030 811 nc -10359.7 310.2 732 sb125 -7416 1030 812 nc -10359.7 269 733 sc125 -7457.2 1030 813 nc -10359.7 227.8 734 sa126 -7498.4 1030 814 nc -10359.7 186.6 735 sb126 -7539.6 1030 815 nc -10359.7 145.4 736 sc126 -7580.8 1030 816 nc -10359.7 104.2 737 sa127 -7622 1030 817 nc -10359.7 63 738 sb127 -7663.2 1030 818 nc -10359.7 21.8 739 sc127 -7704.4 1030 819 nc -10359.7 -19.4 740 sa128 -7745.6 1030 820 nc -10359.7 -60.6 741 sb128 -7786.8 1030 821 com111 -10359.7 -101.8 742 sc128 -7828 1030 822 com112 -10359.7 -143 743 sa129 -7869.2 1030 823 com113 -10359.7 -184.2 744 sb129 -7910.4 1030 824 com114 -10359.7 -225.4 745 sc129 -7951.6 1030 825 com115 -10359.7 -266.6 746 sa130 -7992.8 1030 826 com116 -10359.7 -307.8 747 sb130 -8034 1030 827 com117 -10359.7 -349 748 sc130 -8075.2 1030 828 com118 -10359.7 -390.2 749 sa131 -8116.4 1030 829 com119 -10359.7 -431.4 750 sb131 -8157.6 1030 830 com120 -10359.7 -472.6 751 sc131 -8198.8 1030 831 com121 -10359.7 -513.8 752 nc -8240 1030 832 com122 -10359.7 -555 753 nc -8363.6 1030 833 com123 -10359.7 -596.2 754 nc -8404.8 1030 834 com124 -10359.7 -637.4 755 com66 -8446 1030 835 com125 -10359.7 -678.6 756 com67 -8487.2 1030 836 com126 -10359.7 -719.8 757 com68 -8528.4 1030 837 com127 -10359.7 -761 758 com69 -8569.6 1030 838 com128 -10359.7 -802.2 759 com70 -8610.8 1030 839 com129 -10359.7 -843.4 760 com71 -8652 1030 840 com130 -10359.7 -884.6 761 com72 -8693.2 1030 841 com131 -10359.7 -925.8 762 com73 -8734.4 1030 842 comx -10359.7 -967 763 com74 -8775.6 1030 843 nc -10359.7 -1060 764 com75 -8816.8 1030 765 com76 -8858 1030 766 com77 -8899.2 1030 767 com78 -8940.4 1030 768 com79 -8981.6 1030 769 com80 -9022.8 1030 770 com81 -9064 1030 771 com82 -9105.2 1030 772 com83 -9146.4 1030 773 com84 -9187.6 1030 774 com85 -9228.8 1030 775 com86 -9270 1030 x -dimension y-dimension 776 com87 -9311.2 1030 54um 84um 777 com88 -9352.4 1030 110um 50um 778 com89 -9393.6 1030 110um 27um 779 com90 -9434.8 1030 50um 110um 780 com91 -9476 1030 27um 110um 781 com92 -9517.2 1030 782 com93 -9558.4 1030 783 com94 -9599.6 1030 784 com95 -9640.8 1030 marks x-axis y-axis 785 com96 -9682 1030 key_o 9140.000 -941.000 786 com97 -9723.2 1030 key_o -9140.000 -941.000 787 com98 -9764.4 1030 key_t -8176.000 307.000 788 com99 -9805.6 1030 key_x 8176.000 307.000 789 com100 -9846.8 1030 790 com101 -9888 1030 791 com102 -9929.2 1030 792 com103 -9970.4 1030 793 com104 -10011.6 1030 794 com105 -10052.8 1030 795 com106 -10094 1030 796 com107 -10135.2 1030 797 com108 -10176.4 1030 798 com109 -10217.6 1030 799 com110 -10258.8 1030 800 nc -10318.5 1030 264, 298-299, 305, 802, 808-809, 843 265-297, 300-304, 803-807, 810-842 306-307, 800-801 308-799 gold bump face up pad 1, 2 ,3, ? --> pad # 1 - 263 die size: 20989um x 2250um
ssd1339 rev 1.1 p 13/59 jul 2005 solomon systech figure 3 ? SSD1339Z alignment mark dimensions t shape + shape circle *all units are in um
solomon systech jul 2005 p 14/59 rev 1.1 ssd1339 figure 4 ? die tray information spec mm (mil) w1 76.00 +/-0.1 (2992) w2 68.00 +/-0.1 (2677) w3 68.30 +/-0.1 (2689) x1 4.00 +/-0.1 (157) y1 1.55 +/-0.1 (61) px 22.30 +/-0.05 (878) py 4.20 +/-0.1 (165) x 21.14 +/-0.05 (832) y 2.40 +/-0.05 (94) z 0.61 +/-0.05 (24) n 45 remark 1. depth of text is 0.1mm 2. tray material: abs 3. tray color code: black 4. surface resistance 10 9 ~ 10 11 ? - cm 5. tray warpage: max 0.15mm 6. unspecifier dim's tolerance: +/- 0.15mm 7. pocket size: 21.14 x 2.40 x 0.61mm
ssd1339 rev 1.1 p 15/59 jul 2005 solomon systech 6. pin description res# this pin is reset signal input. when the pin is low, initialization of the chip is executed. cs# this pin is the chip select input. the chip is enabled for mcu communication only when cs# is pulled low. d/c# this pin is data/command control pin. when the pin is pulled high, the data at d 7 -d 0 is treated as display data. when the pin is pulled low, the data at d 7 -d 0 will be transferred to the command register. for detail relationship to mcu interface signals, please refer to the timing characteristics diagrams. e (rd#) this pin is mcu interface input. when interfacing to a 6800-series microprocessor, this pin will be used as the enable (e) signal. read/write operation is initiated when this pin is pulled high and the chip is selected. when connecting to an 8080-microprocessor, this pin receives the read (rd#) signal. data read operation is initiated when this pin is pulled low and the chip is selected. r/w# (wr#) this pin is mcu interface input. when interfacing to a 6800-series microprocessor, this pin will be used as read/write (r/w#) selection input. read mode will be carried out when this pin is pulled high and write mode will be carried out when this pin is pulled low. when 8080 interface mode is selected, this pin will be the write (wr#) input. data write operation is initiated when this pin is pulled low and the chip is selected. bs0, bs1, bs2 these pins are mcu interface selection input. see the following table: note: unlike bs0, bs1 and bs2 are controlled by hardware connection, bs3 is controlled by software command, a0. 6800-parallel interface (8 bit) 8080-parallel interface (8 bit) 6800-parallel interface (16 bit) 8080-parallel interface (16 bit) serial interface bs0 0 0 1 1 0 bs1 0 1 0 1 0 bs2 1 1 1 1 0 bs3 0 0 0 0 0 6800-parallel interface (9 bit) 8080-parallel interface (9 bit) 6800-parallel interface (18 bit) 8080-parallel interface (18 bit) bs0 0 0 1 1 bs1 0 1 0 1 bs2 1 1 1 1 bs3 1 1 1 1
solomon systech jul 2005 p 16/59 rev 1.1 ssd1339 d 17 -d 0 these pins are 18-bit bi-directional data bus to be connected to the microprocessor?s data bus. v ddio this pin is a power supply pin of i/o buffer. it should be connected to v dd or external source. all i/o signal should have vih reference to vddio. when i/o signal pins (bs012, m/s, cls, d0-d17, control signals?) pull high, they should be connected to vddio. v dd power supply pin. it must be connected to external source. v ss ground. it also acts as a reference for the logic pins. it must be connected to external ground. cl this pin is the system clock input. when internal clock is enabled, this pin should be left open. nothing should be connected to this pin. when internal oscillator is disabled, this pin receives display clock signal from external clock source. ms this pin must be connected to v dd to enable the chip. cls this pin is internal clock enable. when this pin is pulled high, internal oscillator is selected. the internal clock will be disabled when it is pulled low, an external clock source must be connected to cl pin for normal operation. vddb this is the power supply pin for the internal buffer of the dc-dc voltage converter. it must be connected to v dd when the converter is used. it is also recommended to connect this pin to v dd when the converter is not used to avoid floating node. vssb this is the gnd pin for the internal buffer of the dc-dc voltage converter. it must be connected to v ss when the converter is used. it is also recommended to connect this pin to v ss when the converter is not used to avoid floating node. gdr this output pin drives the gate of the external nmos of the booster circuit. this pin can be left open when the converter is not used. rese this pin connects to the source current pin of the external nmos of the booster circuit. this pin can be left open when the converter is not used.
ssd1339 rev 1.1 p 17/59 jul 2005 solomon systech fb this pin is the feedback resistor input of the booster circuit. it is used to adjust the booster output voltage level (vcc). this pin can be left open when the converter is not used. bggnd this is a ground pin for analog circuits. it must be connected to external ground. vb ref this pin is the internal voltage reference of booster circuit. a stabilization capacitor, typ. 1uf, should be connected to vss. this pin can be left open when the converter is not used. v cc this is the most positive voltage supply pin of the chip. it is supplied either by external high voltage source or internal booster v comh this pin is the input pin for the voltage output high level for com signals. it can be supplied externally or internally. when v comh is generated internally, a capacitor should be connected between this pin and v ss . v ref this pin is the reference for oled driving voltages like v pa , v pb , v pc and v comh . it can be either supplied externally or connected to v cc (v ref v cc ). v pa, v pb, v pc these pins are the driving voltages for oled driving segment pins sa0-sa131, sb0-sb131 and sc0- sc131 respectively. they can be supplied externally or internally generated by vp circuit. when internal vp is used, v pa, v pb, v pc pins should be left open. i ref this pin is the segment output current reference pin. i seg of each color is derived from i ref i seg = (contrast / 256) * i ref * scale factor contrast is set by command c1h scale factor = master current control register setting (c7h) + 1, i.e., with value from 1~16. a resistor should be connected between this pin and v ss to maintain the current around 10ua. vsl this is segment voltage reference pin. this pin should be left open. vcl this is common voltage reference pin. this pin should be connected to v ss externally. com0-com131 these pins provide the common switch signals to the oled panel. these pins are in high impedance state when display is off.
solomon systech jul 2005 p 18/59 rev 1.1 ssd1339 sa0-sa131, sb0-sb131, sc0-sc131 these pins provide the oled segment driving signals. these pins are in high impedance state when display is off. the 396 segment pins are divided into 3 groups, sa, sb and sc. each group can have different color settings for color a, b and c. comx these two pins provide the common switch signals for soft icon line to the oled panel. these pins are in high impedance state when display is off. tr0 ? tr8, vmona, icasa, icasb, icasc, gpio0, gpio1, m, dof# these are reserved pins. no connection is necessary and should be left open individually. nc no connection pins. they should be left open individually.
ssd1339 rev 1.1 p 19/59 jul 2005 solomon systech 7. functional block discriptions oscillator circuit and display time generator divider internal oscillator fosc m u x cl clk dclk display clock cls figure 5 ? oscillator circuit this module is an on-chip low power rc oscillator circuitry. the operation clock (clk) can be generated either from internal oscillator or external source cl pin. this selection is done by cls pin. if cls pin is pulled high, internal oscillator is chosen. pulling cls pin low disables internal oscillator and external clock must be connected to cl pins for proper operation. when the internal oscillator is selected, its output frequency fosc can be changed by command b3h. in some cof packages of ssd1339, cls pin is tied to high internally and the internal oscillator is selected in these packages. the display clock (dclk) for the display timing generator is derived from clk. the division factor can be programmed from 1 to 16 by command b3h. reset circuit when res# input is low, the chip is initialized with the following status: 1. display is off 2. 132x132 display mode 3. normal segment and display data column address and row address mapping (seg0 mapped to address 00h and com0 mapped to address 00h) 4. shift register data clear in serial interface 5. display start line is set at display ram address 0 6. column address counter is set at 0 7. normal scan direction of the com outputs 8. contrast control register is set at 80h
solomon systech jul 2005 p 20/59 rev 1.1 ssd1339 command decoder and command interface this module determines whether the input data is interpreted as data or command. data is interpreted based upon the input of the d/c# pin. if d/c# pin is high, data is written to graphic display data ram (gddram). if it is low, the input at d 7 -d 0 is interpreted as a command and it will be decoded and be written to the corresponding command register. mpu parallel 6800-series interface the parallel interface consists of 18 bi-directional data pins (d 17 -d 0 ) or 8 bi-directional data pins (d 7 -d 0 ), r/w#(wr#), d/c#, e (rd#) and cs#. r/w#(wr#) input high indicates a read operation from the graphic display data ram (gddram) or the status register. rw#/(wr#) input low indicates a write operation to display data ram or internal command registers depending on the status of d/c# input. the e(rd#) input serves as data latch signal (clock) when high provided that cs# is low and high respectively. refer to . figure 32 of parallel timing characteristics for parallel interface timing diagram of 6800-series microprocessors. in order to match the operating frequency of display ram with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. this is shown in figure 6 below. n+2 n+1 write column address dummy read data read1 r/ w#(wr#) data bus n n e(rd#) data read2 data read3 figure 6 ? display data read back procedure - insertion of dummy read mpu parallel 8080-series interface the parallel interface consists of 18 bi-directional data pins (d 17 -d 0 ) or 8 bi-directional data pins (d 7 -d 0 ), e (rd#), r/w#(wr#), d/c# and cs#. the e(rd#) input serves as data read latch signal (clock) when low, provided that cs# is low and high respectively. display data or status register read is controlled by d/c#. r/w#(wr#) input serves as data write latch signal (clock) when high provided that cs# is low and high respectively. display data or command register write is controlled by d/c#. refer to * when 8 bit used: d 0 ~ d 7 instead; when 9 bit used: d 0 ~ d 8 instead; when 16 bit used: d 0 ~ d 15 instead; when 18 bit used: d 0 ~ d 17 instead. figure 33 of parallel timing characteristics for parallel interface timing diagram of 8080-series microprocessor. similar to 6800-series interface, a dummy read is also required before the first actual display data read.
ssd1339 rev 1.1 p 21/59 jul 2005 solomon systech mpu serial interface the serial interface consists of serial clock sclk, serial data sdin, d/c#, cs#. in this mode, d0 acts as sclk, d1 acts as sdin. for the unused data pins, d2 should be left open. d3 to d7, e and r/w pins can be connected to external ground. sdin is shifted into an 8-bit shift register on every rising edge of sclk in the order of d 7 , d 6 , ... d 0 . d/c is sampled on every eighth clock and the data byte in the shift register is written to the display data ram or command register in the same clock. during data writing, an additional nop command should be inserted before the cs# goes high (refer to figure 7. figure 7 ? display data write procedure in spi mode d7 d6 d5 d4 d3 d2 d1 d0 sclk(d0) sdin(d1) db1 db2 dbn nop command cs# d/c sdin/ sclk
solomon systech jul 2005 p 22/59 rev 1.1 ssd1339 graphic display data ram (gddram) the gddram is a bit mapped static ram holding the bit pattern to be displayed. the size of the ram is 132 x 133 x 18bits. for mechanical flexibility, re-mapping on both segment and common outputs can be selected by software. for vertical scrolling of the display, an internal register storing display start line can be set to control the portion of the ram data to be mapped to the display. each pixel has 18-bit data. each sub-pixels for color a, b and c have 6 bits. the arrangement of data pixel in graphic display data ram is shown below. figure 8 ? graphic display data ram structure data access in 262k colors mode in 262k colors depth mode, there are different mcu interface communication modes to access graphic display data ram in oled driver. for 18 bits mode, the communication is made up of one session of 18 data bits. mcu transmits all bits to write one 18-bit pixel data into oled driver. this 18-bit mode can be selected by setting the a[3] bit in command a0 to 1. bit 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data bits c 5 c 4 c 3 c 2 c 1 c 0 b 5 b 4 b 3 b 2 b 1 b 0 a 5 a 4 a 3 a 2 a 1 a 0 figure 9 ? 262k color depth data writing sequence in 18-bit mcu interface for the 1 st option of the two 16-bit modes, the communication is divided into two sessions of 16 data bits. mcu transmits two 16-bit words to write one 18-bit pixel data into oled driver. mode 1 is selected by setting a0h register a[7:6] bits to 10b. in below, a1, b1, c1 are pixel bits for color a, b and c, and ?x? stands for don?t care value. normal : remap : a 4 b5 c4 a 4 b5 c4 a 4 b5 c4 a 4 b5 c4 a 4 b5 c4 a 4 b5 c4 a 3 b4 c3 a 3 b4 c3 a 3 b4 c3 a 3 b4 c3 a 3 b4 c3 a 3 b4 c3 a 2 b3 c2 a 2 b3 c2 a 2 b3 c2 a 2 b3 c2 a 2 b3 c2 a 2 b3 c2 a 1 b2 c1 a 1 b2 c1 a 1 b2 c1 a 1 b2 c1 a 1 b2 c1 a 1 b2 c1 a 0 b1 c0 a 0 b1 c0 a 0 b1 c0 a 0 b1 c0 a 0 b1 c0 a 0 b1 c0 b0 b0 b0 b0 b0 b0 com normal remap outpu t 0 132 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 com0 1 131 com1 2 130 com2 : : : 130 2 com130 131 1 com131 132 0 com132 sa0 sb0 sc0 sa1 sb1 sc1 sa2 sb2 sc2 : sa129 sb129 sc129 sa130 sb130 sc130 sa131 sb131 sc131 : : data format row a ddress 2 129 129 2 0 131 : column a ddress seg output 1 131 0 130 1 130 no. of bits of data in this cell a 5 c5 a 5 c5 c5 c5 c5 c5 a 5 a 5 a 5 a 5
ssd1339 rev 1.1 p 23/59 jul 2005 solomon systech bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 st word x x x x x x x x x x c1 5 c1 4 c1 3 c1 2 c1 1 c1 0 2 nd word x x b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 x x a1 5 a1 4 a1 3 a1 2 a1 1 a1 0 figure 10 ? 262k color depth data writing sequence in 16-bit mcu interface in option 1 for the 2 nd option of the 16-bit modes, the communication is divided into three sessions of 16 data bits. mcu transmits three 16-bit words to write two 18-bit pixels data into oled driver. option 2 is selected by setting a0h register a[7:6] bits to 11b. in below, a1, b1, c1 are first data pixel bits, and a2, b2, c2 are second data pixel bits. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 st word x x c1 5 c1 4 c1 3 c1 2 c1 1 c1 0 x x b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 2 nd word x x a1 5 a1 4 a1 3 a1 2 a1 1 a1 0 x x c2 5 c2 4 c2 3 c2 2 c2 1 c2 0 3 th word x x b2 5 b2 4 b2 3 b2 2 b2 1 b2 0 x x a2 5 a2 4 a2 3 a2 2 a2 1 a2 0 figure 11 ? 262k color depth data writing sequence in 16-bit mcu interface in option 2 for 9-bit modes, the communication is divided into two sessions of 9 data bits. mcu transmits two 9 data bits to write one 18-bit pixel data into oled driver. this 9-bit mode can be selected by setting the a[3] bit in command a0 to 1. bit 8 7 6 5 4 3 2 1 0 1 st 9 data bits c 5 c 4 c 3 c 2 c 1 c 0 b 5 b 4 b 3 2 nd 9 data bits b 2 b 1 b 0 a 5 a 4 a 3 a 2 a 1 a 0 figure 12 ? 262k color depth graphic display data writing sequence in 9-bit mcu interface in 8-bit mcu interface, the communication session is divided into three times. mcu transmit three 8-bit bytes to write one 18-bit pixel data into oled driver. bit 7 6 5 4 3 2 1 0 1 st byte x x c1 5 c1 4 c1 3 c1 2 c1 1 c1 0 2 nd byte x x b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 3 rd byte x x a1 5 a1 4 a1 3 a1 2 a1 1 a1 0 figure 13 ? 262k color depth graphic display data writing sequence in 8-bit mcu interface data access in 65k colors mode writing a 65k pixel in 16-bit mcu interface involves one session as follows. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 st word c1 4 c1 3 c1 2 c1 1 c1 0 b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 a1 4 a1 3 a1 2 a1 1 a1 0 figure 14 ? 65k color depth graphic display data writing sequence in 16-bit mcu interface
solomon systech jul 2005 p 24/59 rev 1.1 ssd1339 the sequence of sending 65k color depth pixel in 8-bit mcu interface is divided into two 8-bit sessions as shown below. bit 7 6 5 4 3 2 1 0 1 st byte c1 4 c1 3 c1 2 c1 1 c1 0 b1 5 b1 4 b1 3 2 nd byte b1 2 b1 1 b1 0 a1 4 a1 3 a1 2 a1 1 a1 0 figure 15 ? 65k color depth graphic display data writing sequence in 8-bit mcu interface with reference to figure 8 conventions, in writing the data into graphic display data ram, the bit positions filled by the input data for each color is shown below. color a bit position a5 a4 a3 a2 a1 a0 input data a1 4 a1 3 a1 2 a1 1 a1 0 a1 4 color b bit position b5 b4 b3 b2 b1 b0 input data b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 color c bit position c5 c4 c3 c2 c1 c0 input data c1 4 c1 3 c1 2 c1 1 c1 0 c1 4 figure 16 ? display data ram writing position for color a, b and c data input in 65k color mode in data ram, each data occupies 6-bit. however, color a and c have 5-bit length only in 65k color mode. therefore, ram positions a0 and c0 are empty originally. these emptied positions are filled as shown above to increase color a and c to 6-bit length in display data ram. data access in 256 colors mode in 256-color mode, each pixel is composed of 8-bit. only 8-bit mcu interface is available to access display data ram. the communication session is done in 1 time by writing 8-bit data into ram. bit 7 6 5 4 3 2 1 0 1 st byte c1 2 c1 1 c1 0 b1 2 b1 1 b1 0 a1 1 a1 0 figure 11 ? 256 color depth graphic display data writing sequence in 8-bit mcu interface with reference to figure 8 conventions, in writing the data into graphic display data ram, the bit positions filled by the input data for each color is shown below. color a bit position a5 a4 a3 a2 a1 a0 input data a1 1 a1 0 a1 1 a1 1 a1 1 a1 1
ssd1339 rev 1.1 p 25/59 jul 2005 solomon systech color b bit position b5 b4 b3 b2 b1 b0 input data b1 2 b1 1 b1 0 b1 2 b1 2 b1 2 color c bit position c5 c4 c3 c2 c1 c0 input data c1 2 c1 1 c1 0 c1 2 c1 2 c1 2 figure 17 ? display data ram writing position for color a, b and c data input in 256 color mode in data ram, each data occupies 6-bit. however, color b and c have 3-bit length and color a has 2-bit only in 256 color mode. therefore, ram positions b2~b0, c2~c0 and a3~a0 are empty originally. these emptied positions are filled as shown above to increase color a, b and c to 6-bit length in display data ram.
solomon systech jul 2005 p 26/59 rev 1.1 ssd1339 gray scale and gray scale table controlling the current pulse widths from the segment driver in the current drive phase produces the gray scale display. the gray scale table stores the corresponding pulse widths (pw0 ~ pw63) of the 64 gray scale levels (gs0~gs63). the wider the pulse width, the brighter the pixel will be. therefore, the brightness of each pixel is defined in the graphic display data ram in term of pulse width in gray scale table. this single gray scale table supports all the three colors a, b and c. the pulse widths are entered by software commands. in graphic display data ram, each color occupies 6-bit length. so color a, b and c each has 64 gray scale levels. color a, b, c ram data (6 bits) gray scale 0 gs 0 1 gs 1 2 gs 2 3 gs 3 4 gs 4 : : : : : : 60 gs 60 61 gs 61 62 gs 62 63 gs 63 figure 18 ? relation between graphic data ram value and gray scale table entry for three colors in 65k and 256 color modes, the length color data are less than 6 bits. they are expanded to 6-bit length as shown in figure 16 and figure 17 respectively.
ssd1339 rev 1.1 p 27/59 jul 2005 solomon systech the meaning of values inside data ram with respect to the gray scale level is best to be illustrated in an example below. gray scale (pulse width) value/dclks pw0 0 pw1 2 pw2 5 : : pw62 120 pw63 125 figure 19 ? illustration of relation between graphic display ram value and gray scale control current control and voltage control this block is used to derive the incoming power sources into the different levels of internal use voltage and current. v cc and v dd are external power supplies. v ref is reference voltage, which is used to derive driving voltage for segments and commons. i ref is a reference current source for segment current drivers. segment drivers/common drivers segment drivers deliver 396 current sources to drive oled panel. the driving current can be adjusted from 0 to 200ua with 256 steps. common drivers generate voltage scanning pulse. segment voltage time color b ram data = 000001b pw1 pulse width = 2 dclks vss color b ram data = 111110b pw62 pulse width = 120 dclks gray scale table
solomon systech jul 2005 p 28/59 rev 1.1 ssd1339 dc-dc voltage converter it is a switching voltage generator circuit, designed for handheld applications. in ssd1339, internal dc- dc voltage converter accompanying with an external application circuit (shown in below figure) can generate a high voltage supply v cc from a low voltage supply input v dd . v cc is the voltage supply to the oled driver block. below application circuit is an example for the input voltage of 3v vdd to generate v cc of 12v @20ma ~ 30ma application. vddb vbref vssb gdr rese fb + vdd agnd + dgnd agnd + agnd + vcc l1 d1 q1 r1 r2 + c4 c3 c2 c1 c5 + c6 + c7 r3 *all paths to agnd should be connected as short as possible passive components selection: components typical value remark l1 inductor, 22h 2a d1 schottky diode 2a, 25v e.g. 1n5822 q1 mosfet n-fet with low r ds (on) and low vth voltage. e.g. mgsf1n02lt1 [on semiconductor] r1, r2 resistor 1%,1/10w r3 resistor, 1.5 ? 1%, 1/2w c1 capacitor, 1f 16v c2 capacitor, 22f low esr, 25v c3 capacitor, 1f 16v c4 capacitor, 10nf 16v c5 capacitor, 1 ~ 10 f 16v c6 capacitor, 0.1 ~ 1f 16v c7 capacitor, 15nf 16v the vcc output voltage level can be adjusted by changing the r1 and r2 resistor values, the reference formula is: vcc = 1.2 x (r1+r2) / r2
ssd1339 rev 1.1 p 29/59 jul 2005 solomon systech 8. command table table 3 ? command table ( c d/ = 0, w r/ ( wr ) = 0, e( rd ) = 1) unless specific setting is stated single byte command ( c d/ = 0), multiple byte command ( c d/ = 0 for first byte, c d/ = 1 for other bytes) d/c hex d7 d6 d5 d4 d3 d2 d2 d0 command description 0 15 0 0 0 1 0 1 0 1 a [7:0]: start address, reset=0d 1 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 b[7:0]: end address, reset=131d 1 b[7:0] b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 set column address range from 0d to 131d 0 75 0 1 1 1 0 1 0 1 a [7:0]: start address, reset=0d 1 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 b[7:0]: end address, reset=131d 1 b[7:0] b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 set row address range from 0d to 131d 0 5c 0 1 0 1 1 1 0 0 write ram command enable mcu to write data into ram 0 5d 0 1 0 1 1 1 0 1 enable mcu to read data from ram read ram command 0 a0 1 0 1 0 0 0 0 0 a[0]=0, horizontal address increment (por) 1 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a[0]=1, vertical address increment a[1]=0, column address 0 is mapped to seg0 (por) a[1]=1, column address 131 is mapped to seg0 a[2]=0, color sequence: a b c (por) a[2]=1, color sequence is swapped: c b a a[3]=0, disable 9/18-bit bus interface (por) a[3]=1, enable 9/18-bit bus interface a[4]=0, scan from com 0 to com [n ?1] (por) a[4]=1, scan from com [n-1] to com0. where n is the multiplex ratio. a[5]=0, disable com split odd even (por) a[5]=1, enable com split odd even a [7:6] set color depth, 00 256 color 01 65k color, (por) 10 262k color, 8/9/18-bit,16 bit (1 st option) mcu interface set re-map / colo r depth(display ram to panel) 11 262k color, 16 - bit mcu interface (2 nd option) 0 a1 1 0 1 0 0 0 0 1 set vertical scroll by ram from 0~131 1 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 set display start line [reset=00d]
solomon systech jul 2005 p 30/59 rev 1.1 ssd1339 d/c hex d7 d6 d5 d4 d3 d2 d2 d0 command description 0 a2 1 0 1 0 0 0 1 0 set vertical scroll by row from 0-131. [reset=00b] 1 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 set display offset 0 a4~a7 1 0 1 0 0 1 x 1 x 0 a 4: all off a 5: all on (all pixels have gs15) a 6 : reset to normal display (por) a 7: inverse display (gs0 -> gs63, gs1 -> gs62, ....) set display mode 0 ad 1 0 1 0 1 1 0 1 a [7:0] should be set as 100011a[1]a[0]b 1 a[7:0] 1 0 0 0 1 a 2 a 1 a 0 a [0]= 0 select external vcc supply at master on a [0] = 1 select internal booster at master on [reset] a [1]= 0 select external vcomh voltage supply at master on a [1] = 1 select internal vcomh regulator at master on [reset] a [2] = 0 select external pre-charge voltage source master configuration a [2] = 1 select internal pre-charge voltage source [reset] 0 ae~af 1 0 1 0 1 1 1 x 0 a e = sleep mode on (display off) set sleep mode on/off a f = sleep mode off (display on) 0 b0 1 0 1 1 0 0 0 0 a [4:0]: 0 0 0 a 4 a 3 a 2 a 1 a 0 00000b = normal 10010b = power saving power saving mode 00101b = reserved 0 b1 1 0 1 1 0 0 0 1 a [3:0] phase 1 period of 1~16 dclk clocks [reset=4h] 1 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a [7:4] phase 2 period of 1~16 dclk clocks [reset=7h] set reset (phase 1) /pre-charge (phase 2) period 0 b3 1 0 1 1 0 0 1 1 a [3:0] [reset=0], divide by divset+1 (i.e. 1 to 16) 1 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a [7:4] osc frequency, frequency increase as level increase [reset=1001b] front clock divider (divset)/ oscillator frequency the next 32 bytes of command set the current drive pulse width of gray scale level gs1, gs3, gs5 ?gs63 as below in unit of dclk. 0 b8 1 0 1 1 1 0 0 0 a [7:0] : pw1, por =1 dclk 1 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 b[7:0] : pw3, por = 5 dclk 1 b[7:0] b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 c[7:0] : pw5, por = 9 dclk 1 . . . . . . . . . . 1 . . . . . . . . . . 1 . . . . . . . . . a e[7:0] : pw61, por = 121 dclk 1 .ae[7:0] ae 7 ae 6 ae 5 ae 4 ae 3 ae 2 ae 1 ae 0 a f[7:0] : pw63, por = 123 dclk 1 af[7:0] af 7 af 6 af 5 af 4 af 3 af 2 af 1 af 0 where pw1 must > 0 look up table for gray scale pulse width pw3 must > pw1+1
ssd1339 rev 1.1 p 31/59 jul 2005 solomon systech d/c hex d7 d6 d5 d4 d3 d2 d2 d0 command description pw5 must > pw3+1 note: gs0 has no pre-charge and current drive stages. for gs2 gs4?gs62, they are derived by driver itself with: pwn = (pwn -1 +pwn +1 )/2 max pulse width is 125 0 b9 1 0 1 1 1 0 0 1 reset to default look up table: pw1 = 1 pw2 = 3 pw3 = 5 pw4 = 7 ... pw62 = 123 use built-in linear lut (reset= linear) pw63 = 125 0 bb 1 0 1 1 1 0 1 1 a [7:0] pre-charge color a [reset = 00011100] 1 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 b[7:0] pre-charge color b [reset = 00011100] 1 b[7:0] c[7:0] pre-charge color c [reset = 00011100] 1 c[7:0] 00000000 0.51*vref ..... 00011111 0.84*vref set pre-charge voltage of color a b c 1xxxxxxx c onnects to vcomh 0 be 1 0 1 1 1 1 1 0 a [6:0] 0000000 0.51*vref 1 a[6:0] * a 6 a 5 a 4 a 3 a 2 a 1 a 0 ..... 0011111 0.84*vref [vcomhset, reset] set vcomh 0 c1 1 1 0 0 0 0 0 1 1 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a [7:0] contrast value color a [reset=1000000b] 1 b[7:0] b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 1 c[7:0] c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 b[7:0] contrast value color b [reset=1000000b] contrast current for color a,b,c c[7:0] contrast value color c [reset=1000000b] 0 c7 1 1 0 0 0 1 1 1 1 a[3:0] * * * * a 3 a 2 a 1 a 0 a [3:0] : 0000 reduce output currents for all colors to 1/16 0001 reduce output currents for all colors to 2/16 .... 1110 reduce output currents for all colors to 15/16 1111 no change [reset = 1111b] master contrast current control
solomon systech jul 2005 p 32/59 rev 1.1 ssd1339 d/c hex d7 d6 d5 d4 d3 d2 d2 d0 command description 0 ca 1 1 0 0 1 0 1 0 1 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 set mux ratio a [7:0] mux ratio 16mux ~ 132mux, [reset=131d], (range from 15d to 131d) 0 e3 1 1 1 0 0 0 1 1 nop command for no operation table 4 ? graphic acceleration command set (gac) ( c d/ = 0, w r/ ( wr ) = 0, e( rd ) = 1) unless specific setting is stated single byte command ( c d/ = 0), multiple byte command ( c d/ = 0 for first byte, c d/ = 1 for other bytes) d/c hex d7 d6 d5 d4 d3 d2 d2 d0 command description 0 83 1 0 0 0 0 0 1 1 a [7:0] : column address of start 1 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 b[7:0] : row address of start 1 b[7:0] b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 c[7:0] : column address of end 1 c[7:0] c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d[7:0] : row address of end 1 d[7:0] d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 e[7:0] : line color - cccccbbb 1 e[7:0] e 7 e 6 e 5 e 4 e 3 e 2 e 1 e 0 f[7:0] : line color - bbbaaaaa 1 f[7:0] f 7 f 6 f 5 f 4 f 3 f 2 f 1 f 0 * a < c < 132 draw line * b < d < 132 0 84 1 0 0 0 0 1 0 0 a [7:0] : column address of start 1 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 b[7:0] : row address of start 1 b[7:0] b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 c[7:0] : column address of end 1 c[7:0] c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d[7:0] : row address of end 1 d[7:0] d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 e[7:0] : line color - cccccbbb 1 e[7:0] e 7 e 6 e 5 e 4 e 3 e 2 e 1 e 0 f[7:0] : line color - bbbaaaaa 1 f[7:0] f 7 f 6 f 5 f 4 f 3 f 2 f 1 f 0 g[7:0] : fill color - cccccbbb 1 g[7:0] g 7 g 6 g 5 g 4 g 3 g 2 g 1 g 0 h[7:0] : fill color - bbbaaaaa 1 h[7:0] h 7 h 6 h 5 h 4 h 3 h 2 h 1 h 0 * a < c < 132 draw rectangle * b < d < 132 0 86 1 0 0 0 0 1 1 0 a [7:0] : column address of centre 1 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 b[7:0] : row address of centre 1 b[7:0] b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 c[7:0] : radius 1 c[7:0] c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d[7:0] : line color - cccccbbb 1 d[7:0] d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 e[7:0] : line color - bbbaaaaa 1 e[7:0] e 7 e 6 e 5 e 4 e 3 e 2 e 1 e 0 f[7:0] : fill color - cccccbbb 1 f[7:0] f 7 f 6 f 5 f 4 f 3 f 2 f 1 f 0 g[7:0] : fill color ? bbbaaaaa 1 g[7:0] g 7 g 6 g 5 g 4 g 3 g 2 g 1 g 0 draw circle 0 8a 1 0 0 0 1 0 1 0 a [7:0] : column address of start 1 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 b[7:0] : row address of start 1 b[7:0] b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 c[7:0] : column address of end 1 c[7:0] c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d[7:0] : row address of end 1 d[7:0] d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 copy e[7:0] : column address of new start
ssd1339 rev 1.1 p 33/59 jul 2005 solomon systech d/c hex d7 d6 d5 d4 d3 d2 d2 d0 command description 1 e[7:0] e 7 e 6 e 5 e 4 e 3 e 2 e 1 e 0 f[7:0] : row address of new start 1 f[7:0] f 7 f 6 f 5 f 4 f 3 f 2 f 1 f 0 * a < c < 132 * b < d < 132 0 8c 1 0 0 0 1 1 0 0 a [7:0] : column address of start 1 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 b[7:0] : row address of start 1 b[7:0] b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 c[7:0] : column address of end 1 c[7:0] c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d[7:0] : row address of end 1 d[7:0] d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 * a < c < 132 * b < d < 132 dim window 0 8e 1 0 0 0 1 1 1 0 a [7:0] : column address of start 1 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 b[7:0] : row address of start 1 b[7:0] b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 c[7:0] : column address of end 1 c[7:0] c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d[7:0] : row address of end 1 d[7:0] d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 * a < c < 132 clear window * b < d < 132 0 92 1 0 0 1 0 0 1 0 1 a[5:0] * * a 5 a 4 a 3 a 2 a 1 a 0 a 0 0 : disable fill for draw rectangle/circle command [reset] 1 : enable fill for draw rectangle/circle command a4 0 : disable reverse copy, reset] 1 : enable reverse during copying. a5 0 : disable x-wrap, [reset] fill enable / disable 1 : enable wrap around in x-direction during copying 0 96 1 0 0 1 0 1 1 0 a [7:0] : 1~124 horizontal offset in number of column invalid entry for value larger than 124 1 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 no horizontal scroll 1 b[7:0] b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b[7:0] : start row address 1 c[7:0] c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 c[7:0] : number of rows to be h-scrolled 1 d[7:0] d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 b+c <= 132 1 e[1:0] * * * * * * e 1 e 0 d[7:0] : reserved e[1:0] : scrolling time interval 0 test mode 1 normal 2 slow 3 slowest horizontal scroll note : operates during display on. 0 9e 1 0 0 1 1 1 1 0 stop moving 0 9f 1 0 0 1 1 1 1 1 start moving
solomon systech jul 2005 p 34/59 rev 1.1 ssd1339 9. command descriptions set column address (15h) this command specifies column start address and end address of the display data ram. this command also sets the column address pointer to column start address. this pointer is used to define the current read/write column address in graphic display data ram. if horizontal address increment mode is enabled by command a0h, after finishing read/write one column data, it is incremented automatically to the next column address. whenever the column address pointer finishes accessing the end column address, it is reset back to start column address. set row address (75h) this command specifies row start address and end address of the display data ram. this command also sets the row address pointer to row start address. this pointer is used to define the current read/write row address in graphic display data ram. if vertical address increment mode is enabled by command a0h, after finishing read/write one row data, it is incremented automatically to the next row address. whenever the row address pointer finishes accessing the end row address, it is reset back to start row address. for example, column start address is set to 2 and column end address is set to 129, row start address is set to 1 and row end address is set to 130. horizontal address increment mode is enabled by command a0h. in this case, the graphic display data ram column accessible range is from column 2 to column 129 and from row 1 to row 130 only. in addition, the column address pointer is set to 2 and row address pointer is set to 1. after finishing read/write one pixel of data, the column address is increased automatically by 1 to access the next ram location for next read/write operation. whenever the column address pointer finishes accessing the end column 129, it is reset back to column 2 and row address is automatically increased by 1. while the end row 130 and end column 129 ram location is accessed, the row address is reset back to 1. the diagram below shows the way of column and row address pointer movement for this example. col 0 col 1 col 2 ?.. ??. col129 col130 col131 row 0 row 1 row 2 : : : : : : row 129 row 130 row 131 figure 20 ? example of column and row address pointer movement
ssd1339 rev 1.1 p 35/59 jul 2005 solomon systech write ram command (5ch) after this single byte command, data entries will be written into the display ram until another command is written. address pointer is increased accordingly. this command must be sent before write data into ram. read ram command (5dh) after this single byte command, data is read from display ram until another command is written. address pointer is increased accordingly. this command must be sent before read data from ram. set re-map & color depth (a0h) this command has multiple configurations and each bit setting is described as follows. ? address increment mode (a[0]) when it is set to 0, the driver is set as horizontal address increment mode. after the display ram is read/written, the column address pointer is increased automatically by 1. if the column address pointer reaches column end address, the column address pointer is reset to column start address and row address pointer is increased by 1. the sequence of movement of the row and column address point for horizontal address increment mode is shown in figure 21. col 0 col 1 ?.. col 130 col 131 row 0 row 1 : : : : : : row 130 row 131 figure 21 ? address pointer movement of horizontal address increment mode when a[0] is set to 1, the driver is set to vertical address increment mode. after the display ram is read/written, the row address pointer is increased automatically by 1. if the row address pointer reaches the row end address, the row address pointer is reset to row start address and column address pointer is increased by 1. the sequence of movement of the row and column address point for vertical address increment mode is shown in figure 22. col 0 col 1 ?.. col 130 col 131 row 0 ?.. row 1 ?.. : : row 130 ?.. row 131 ?.. figure 22 ? address pointer movement of vertical address increment mode ? column address mapping (a[1]) this command bit is made for flexible layout of segment signals in oled module with segment arranged from left to right or vice versa. ? color remap (a[2]) this command bit is made for flexible layout of color sequence a b c or c b and a.
solomon systech jul 2005 p 36/59 rev 1.1 ssd1339 ? mcu interface selection (a[3]) this command bit is made for setting the 6800 or 8080 parallel bus interface for to either 8/16-bit or 9/18-bit. ? com remap (a[4]) this bit determines the scanning direction of the common for flexible layout of common signals in oled module either from up to down or vice versa. ? odd even split of com pins (a[5]) this bit can set the odd even arrangement of com pins. a[5] = 0: disable com split odd even, pin assignment of common is in sequential as com131 com129 .... com 33 com32..sc131..sa0..com0 com1.... com30 com31 a[5] = 1: enable com split odd even, pin assignment of common is in odd even split as com131 com129.... com3 com1..sc131..sa0..com0 com2.... com60 com62 ? display color mode (a[7:6]) select either 262k, 65k or 256 color mode. in 262k colors mode, if 16-bit mcu interface is selected, there are two communication modes. in mode 1, one pixel data in transmitted in two 16-bit words. in mode 2, one communication session is consisted of three 16-bit words to transmit two pixel data. please refer to section ?data access in 262k colors mode? for details. in all other 8/9/18-bit parallel or spi mcu interfaces, there is no difference between mode 1 and mode 2 selections. the display ram data format in different mode is described in section ?graphic display data ram (gddram)?.
ssd1339 rev 1.1 p 37/59 jul 2005 solomon systech set display start line (a1h) this command is to set display start line register to determine starting address of display ram to be displayed by selecting a value from 0 to 131. the figure below shows an example of this command. in there, ?row? means the graphic display data ram row. 132 132 130 130 mux ratio com pin 0 4 0 4 display start line com0 row0 row4 row0 row4 com1 row1 row5 row1 row5 com2 row2 row6 row2 row6 com3 row3 row7 row3 row7 : : : : : : : : : : com125 row125 row129 row125 row129 com126 row126 row130 row126 row130 com127 row127 row131 row127 row131 com128 row128 row0 row128 row0 com129 row129 row1 row129 row1 com130 row130 row2 - - com131 row131 row3 - - figure 23 ? example of set display start line with no remap set display offset (a2h) this command specifies the mapping of display start line (it is assumed that com0 is the display start line, display start line register equals to 0) to one of com0-131. the figure below shows an example of this command. in there, ?row? means the graphic display data ram row. 132 132 130 130 mux ratio com pin 0 4 0 4 display offset com0 row0 row4 row0 row4 com1 row1 row5 row1 row5 com2 row2 row6 row2 row6 com3 row3 row7 row3 row7 : : : : : : : : : : com125 row125 row129 row125 row129 com126 row126 row130 row126 - com127 row127 row131 row127 - com128 row128 row0 row128 row0 com129 row129 row1 row129 row1 com130 row130 row2 - row2 com131 row131 row3 - row3 figure 24 ? example of set display offset with no remap
solomon systech jul 2005 p 38/59 rev 1.1 ssd1339 set display mode (a4h ~ a7h) these are single byte command and they are used to set normal display, entire display on, entire display off and inverse display. ? set entire display on (a5h) forces the entire display to be at ?gs63? regardless of the contents of the display data ram. ? set entire display off (a4h) forces the entire display to be at gray level ?gs0? regardless of the contents of the display data ram. ? inverse display (a7h) the gray level of display data are swapped such that ?gs0? <-> ?gs63?, ?gs1? <-> ?gs62?, ?. ? normal display (a6h) reset the above effect and turn the data to on at the corresponding gray level. master configuration (adh) this command contains multiple bits to control several functionalities of the driver. ? select dc-dc converter (a[0]) 0 = disable selection of dc-dc converter and vcc is supplied externally. 1 (por) = enable selection of dc-dc converter to supply high voltage to vcc. the output voltage of the converter is set by values of external resistors. please refer to section ?dc-dc voltage converter? for details. ? select v comh supply (a[1]) 0 = select external v comh voltage from v comh pin for the common waveform high voltage level supply. it is recommended to set the voltage of v comh such that the oled pixel diode is not turned on (prefer in reverse bias state) when the segment pin is either driven to v pa , v pb or v pc level. 1 = select internal v comh voltage generated by regulator from v ref . the level of v comh can be programmed by command beh. ? select pre-charge voltage supply (a[2]) 0 = select pre-charge voltage sources from external pins v pa , v pb , v pc for color a, b and c respectively. 1 = select pre-charge voltage supply internally. the level of v pa , v pb , v pc can be set by command bbh for color a, b and c respectively. set sleep mode on/off (aeh/afh) these single byte commands are used to turn the oled panel display on or off. when the display is on, the selected circuits by set master configuration command will be turned on. when the display is off, those circuits will be turned off and the segment and common output are in high impedance state. power saving mode (b0h) this command sets the driver ic either in normal power mode and power saving mode. set reset (phase 1)/ pre-charge (phase 2) period (b1h) this command sets the length of phase 1 and 2 of segment waveform of the driver. ? phase 1 (a[3:0]): set the period from 1 to 16 in the unit of dclks. a larger capacitance of the oled pixel may require longer period to discharge the previous data charge completely. ? phase 2 (a[7:4]): set the period from 1 to 16 in the unit of dclks. a longer period is needed to charge up a larger capacitance of the oled pixel to the target voltage v pa , v pb , v pc for color a, b and c respectively.
ssd1339 rev 1.1 p 39/59 jul 2005 solomon systech front clock divider (divset)/ oscillator frequency (b3h) this command consists of two functions: ? display clock divide ratio (a[3:0]) set the divide ratio to generate dclk (display clock) from clk. the divide ratio is from 1 to 16, with power on reset value = 1. please refer to section ?oscillator circuit and display time generator? for the details of dclk and clk. ? oscillator frequency (a[7:4]) program the oscillator frequency fosc which is the source of clk if cls pin is pulled high. the 4-bit value results in 16 different frequency setting available as shown below. the default value is 1101b. look up table for gray scale pulse width (b8h) this command is used to set the gray scale table for the display. except gray scale entry 0, which is zero as it has no pre-charge and current drive, each odd entry gray scale level is programmed in the length of current drive stage pulse width with unit of dclk. the longer the length of the pulse width, the brighter is the oled pixel when it?s turned on. please refer to section ?graphic display data ram (gddram)? for more detailed explanation of relation of display data ram, gray scale table and the pixel brightness. following the command b8h, the user has to set the pulse width from pw1, pw3, pw5, ?, pw59, pw61, pw63 one by one in sequence and complies the following conditions. pw1 > 0; pw3 > pw1 + 1; pw5 > pw3 + 1; ?? afterwards, the driver automatically derives the pulse width of even entry of gray scale table pw2, pw4, ?, pw62 with the formula like below. pwn = (pwn-1 + pwn+1) / 2 for example, if pw1 = 3 dclks and pw3 = 7 dclks, pw2 = (3+7)/2 = 5 dclks the setting of gray scale table entry can perform gamma correction on oled panel display. normally, it is desired that the brightness response of the panel is linearly proportional to the image data value in display data ram. however, the oled panel is somehow responded in non-linear way. appropriate gray scale table setting like example below can compensate this effect. figure 25 ? example of gamma correction by gray scale table setting use built-in linear lut (b9h) this command reloads the preset linear gray scale table as pw1 = 1, pw2 = 3, pw3 = 5, ?., pw62 = 123, pw63 = 125 dclks. pulse width gray scale panel response brightness brightness pulse width gray scale gray scale table setting result in linear response
solomon systech jul 2005 p 40/59 rev 1.1 ssd1339 set pre-charge voltage of color a, b and c (bbh) this command is used to set v pa , v pb and v pc phase 2 voltage level for color a, b and c respectively. the command is valid in condition that these voltages are selected to generate internally by command adh. it can be programmed to set the pre-charge voltage reference to v ref or v comh . voltage level increases linearly when set value increases. set v comh (beh) this command sets the high voltage level of common pins, v comh , when it is selected to generate internally by command adh. the level of v comh is programmed with reference to v ref . voltage level increases linearly when set value increases. contrast current for color a, b, c (c1h) this command is to set contrast current of each color a, b and c. the chip has three contrast control circuits for color a, b and c. each contrast circuit has 256 contrast steps from 00h to ffh. the segment output current i seg increases linearly with the contrast step, which results in brighter of the color. this relation is shown in figure 26. in many situations, the output brightness of color a, b and c pixels are different under the same segment current condition. the contrasts of color a, b and c are set such that the brightness of each color are the same on the oled panel
ssd1339 rev 1.1 p 41/59 jul 2005 solomon systech master contrast current control (c7h) this command is to control the segment output current by a scale factor. this factor is common to color a, b and c. the chip has 16 master control steps. the factor is ranged from 1 [0000] to 16 [1111]. por is 16 [1111]. the smaller the master current value, the dimmer the oled panel display is set. for example, if original segment output current of a color is 160ua at scale factor = 16, setting scale factor to 8 to reduce the current to 80ua. please see figure 26. segment output current 0 50 100 150 200 00 0f 1f 2f 3f 4f 5f 6f 7f 8f 9f af bf cf df ef ff contrast setting output current iseg (ua) master current setting 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 figure 26 ? segment output current for different contrast control and master current setting set multiplex ratio (cah) this command switches default 1:132 multiplex mode to any multiplex mode from 16 to 132. for example, when multiplex ratio is set to 16, only 16 common pins are enabled. the starting and the ending of the enabled common pins are depended on the setting of ?display offset? register programmed by command a2h. change contrast control moves along the contrast curve with constant slope change master current selects different contrast slope.
solomon systech jul 2005 p 42/59 rev 1.1 ssd1339 graphic acceleration command set description draw line (83h) this command draws a line by the given start, end column and row coordinates and the color of the line. figure 27 ? example of draw line command for example, the line above can be drawn by the following command sequence. 1. enter into draw line mode by command 21h 2. send column start address of line, column1, for example = 1h 3. send row start address of line, row 1, for example = 10h 4. send column end address of line, column 2, for example = 28h 5. send row end address of line, row 2, for example = 4h 6. send color c, b and a of line, for example = 35d, 0d, 0d for blue color draw rectangle (84h) given the starting point (row 1, column 1) and the ending point (row 2, column 2), specify the outline and fill area colors, a rectangle that will be drawn with the color specified. remarks: if fill color option is disabled, the enclosed area will not be filled. figure 28 ? example of draw rectangle command the following example illustrates the rectangle drawing command sequence. 1. enter the ?draw rectangle mode? by execute the command 22h 2. set the starting column coordinates, column 1. e.g., 03h. 3. set the starting row coordinates, row 1. e.g., 02h. 4. set the finishing column coordinates, column 2. e.g., 12h 5. set the finishing row coordinates, row 2. e.g., 15h 6. set the outline color c, b and a. e.g., (28d, 0d, 0d) for blue color 7. set the filled color c, b and a. e.g., (0d, 0d, 40d) for red color row 1, column 1 row 2, column 2 line color row 1, column 1 row 2, column 2 outline color filled color
ssd1339 rev 1.1 p 43/59 jul 2005 solomon systech draw circle (86h) by providing the center coordination (column and row address) and radius length, specify the outline and fill area colors, a circle will be drawn with the colors specified. figure 29 ? example of draw circle command the following example illustrates the circle drawing command sequence. 1. enter the ?draw circle mode? by execute the command 86h 2. set the circle center column coordinates, e.g., 03h. 3. set the circle center row coordinates. e.g., 10h. 4. set the radius of circle. e.g., 12h 5. set the outline color c, b and a. e.g., (0d, 0d, 40d) for red color 6. set the filled color c, b and a. e.g., (28d, 0d, 0d) for blue color outline color filled color radius center column & row address
solomon systech jul 2005 p 44/59 rev 1.1 ssd1339 copy (8ah) copy the rectangular region defined by the starting point (row 1, column 1) and the ending point (row 2, column 2) to location (row 3, column 3). if the new coordinates are smaller than the ending points, the new image will overlap the original one. the following example illustrates the copy procedure. 1. enter the ?copy mode? by execute the command 23h 2. set the starting column coordinates, column 1. e.g., 00h. 3. set the starting row coordinates, row 1. e.g., 00h. 4. set the finishing column coordinates, column 2. e.g., 05h 5. set the finishing row coordinates, row 2. e.g., 05h 6. set the new column coordinates, column 3. e.g., 03h 7. set the new row coordinates, row 3. e.g., 03h figure 30 ? example of copy command dim window (8ch) this command will dim the window area specify by starting point (row 1, column 1) and the ending point (row 2, column 2). after the execution of this command, the selected window area will become darker as follow. table 5 ? result of change of brightness by dim window command original gray scale new gray scale after dim window command gs0 ~ gs15 no change gs16 ~ gs19 gs4 gs20 ~ gs23 gs5 : : gs60 ~ gs63 gs15 additional execution of this command over the same window area will not change the data content. row 3 + row 2, column 3 + column 2 row 1, column 1 row 3, column 3 original image new copied image
ssd1339 rev 1.1 p 45/59 jul 2005 solomon systech clear window (8eh) this command sets the window area specify by starting point (row 1, column 1) and the ending point (row 2, column 2) to clear the window display. the graphic display data ram content of the specified window area will be set to zero. this command can be combined with copy command to make as a ?move? result. the following example illustrates the copy plus clear procedure and results in moving the window object. 1. enter the ?copy mode? by execute the command 23h 2. set the starting column coordinates, column 1. e.g., 00h. 3. set the starting row coordinates, row 1. e.g., 00h. 4. set the finishing column coordinates, column 2. e.g., 05h 5. set the finishing row coordinates, row 2. e.g., 05h 6. set the new column coordinates, column 3. e.g., 06h 7. set the new row coordinates, row 3. e.g., 06h 8. enter the ?clear mode? by execute the command 24h 9. set the starting column coordinates, column 1. e.g., 00h. 10. set the starting row coordinates, row 1. e.g., 00h. 11. set the finishing column coordinates, column 2. e.g., 05h 12. set the finishing row coordinates, row 2. e.g., 05h figure 31 ? example of copy + clear = move command fill enable/disable (92h) this command has two functions. ? enable/disable fill (a[0]) 0 = disable filling of color into rectangle in draw rectangle command. (por) 1 = enable filling of color into rectangle in draw rectangle command. ? enable/disable reverse copy (a[4]) 0 = disable reverse copy (por) 1 = during copy command, the new image colors are swapped such that ?gs0? <-> ?gs63?, ?gs1? <-> ?gs62?, ?. row 3 + row 2, column 3 + column 2 row 1, column 1 row 3, column 3 original image new copied image clear command
solomon systech jul 2005 p 46/59 rev 1.1 ssd1339 horizontal scroll (96h) this command consists of 5 consecutive bytes to set up the horizontal scroll parameters. it determined the scrolling start page, end page and the scrolling speed. before issuing this command, the horizontal scroll must be deactivated (9eh). otherwise, ram content may be corrupted. stop moving (9eh) stop motion of horizontal scrolling. start moving (9fh) start motion of horizontal scrolling. this command should only be issued after horizontal scroll setup parameters are defined. the following actions are prohibited after the horizontal scroll is activated 1. ram access (data write or read) 2. changing horizontal scroll setup parameters the ssd1339 horizontal scroll is designed for 132 columns scrolling
ssd1339 rev 1.1 p 47/59 jul 2005 solomon systech 10. maximum ratings table 6 ? maximum ratings (voltage reference to v ss ) symbol parameter value unit v dd -0.3 to +4 v v cc 0 to 18 v v ref supply voltage 0 to 18 v v comh supply voltage/output voltage 0 to 16 v - seg/com output voltage 0 to 16 v v in input voltage vss-0.3 to vdd+0.3 v t a operating temperature -40 to +90 oc t stg storage temperature range -65 to +150 oc *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the limits in the electrical characteristics tables or pin description.
solomon systech jul 2005 p 48/59 rev 1.1 ssd1339 11. dc characteristics table 7 ? dc characteristics (unless otherwise specified, voltage referenced to v ss , v dd = 2.4 to 3.5v, t a = 25 c) symbol parameter test condition min typ max unit v cc operating voltage 7 11 18 v v dd logic supply voltage 2.4 2.7 3.5 v v ddio power supply for i/o pins 1.5 2.7 3.5 v v oh high logic output level iout =100ua, 3.3mhz 0.9*v ddio - v ddio v v ol low logic output level iout =100ua, 3.3mhz 0 - 0.1*v ddi o v v ih high logic input level iout =100ua, 3.3mhz 0.8*v ddio - v ddio v v il low logic input level iout =100ua, 3.3mhz 0 - 0.2*v ddi o v i sleep sleep mode current vdd=2.7v, display off, no panel attached - - 5 ua i cc v cc supply current vdd=3.0v, vcc=18v, display on contrast =ff, no panel attached - 1.3 - ma i dd v dd supply current vdd=3.0v, vcc=18v, display on contrast =ff, no panel attached - 0.4 - ma contrast = ff - 160 - ua contrast = af 110 ua contrast = 5f - 60 - ua i seg segment output current setting vdd=2.7v, vcc=11v, iref=10ua, all one pattern, display on, segment pin under test is connected with a 20k ? resistive load to vcc. contrast = 00 - 0 - ua dev segment output current uniformity dev = (i seg ? i mid )/i mid i mid = (i max + i min )/2 i s eg [0:395] = segment current at contrast = ff - - 3 % adj. dev adjacent pin output current uniformity (contrast = ff) adj dev = (i[n]-i[n+1]) / (i[n]+i[n+1]) - 2.0 -- % v cc booster output voltage (vcc) vin=3v, l=22uh; r1=450kohm; r2=50kohm; icc = 30ma(soaking) - 12 - v
ssd1339 rev 1.1 p 49/59 jul 2005 solomon systech 12. ac characteristics table 8 ? ac characteristics (unless otherwise specified, voltage referenced to v ss , v dd = 2.4 to 3.5v, t a = 25c.) symbol parameter test condition min typ max unit f osc oscillation frequency of display timing generator vdd = 2.7v - 2.0 - mhz f frm frame frequency for 132 mux mode 132rgb x 132 graphic display mode, display on, internal oscillator enabled - f osc x 1/(d*k*132) - hz d: divide ratio (por =1) k: number of display clocks (por= 136, i.e. phase1 dclk+phase2 dclk+ phase3 dclk=4+7+125) refer to command table for detail description
solomon systech jul 2005 p 50/59 rev 1.1 ssd1339 table 9 ? 6800-series mpu parallel interface timing characteristics (v dd - v ss = 2.4 to 3.5v, t a = 25c) symbol parameter min typ max unit t cycle clock cycle time 300 - - ns t as address setup time 0 - - ns t ah address hold time 0 - - ns t dsw write data setup time 40 - - ns t dhw write data hold time 15 - - ns t dhr read data hold time 20 - - ns t oh output disable time - - 70 ns t acc access time - - 140 ns pw csl chip select low pulse width (read) chip select low pulse width (write) 120 60 - - ns pw csh chip select high pulse width (read) chip select high pulse width (write) 60 60 - - ns t r rise time - - 15 ns t f fall time - - 15 ns d 0 ~d 7 (write) * d 0 ~d 7 (read) * e cs# r/w# pw csl t r t f t dh w t oh t acc t dhr valid data t dsw valid data t cycle pw csh t ah t as d/c# * when 9 bit used: d 0 ~ d 8 instead; when 16 bit used: d 0 ~ d 15 instead; when 18 bit used: d 0 ~ d 17 instead. figure 32 ? 6800-series mpu parallel interface characteristics
ssd1339 rev 1.1 p 51/59 jul 2005 solomon systech table 10 ? 8080-series mpu parallel interface timing characteristics (v dd - v ss = 2.4 to 3.5v, t a = 25c) symbol parameter min typ max unit t cycle clock cycle time 300 - - ns t as address setup time 0 - - ns t ah address hold time 0 - - ns t dsw write data setup time 40 - - ns t dhw write data hold time 15 - - ns t dhr read data hold time 20 - - ns t oh output disable time - - 70 ns t acc access time - - 140 ns pw csl chip select low pulse width (read) chip select low pulse width (write) 120 60 - - ns pw csh chip select high pulse width (read) chip select high pulse width (write) 60 60 - - ns t r rise time - - 15 ns t f fall time - - 15 ns * when 8 bit used: d 0 ~ d 7 instead; when 9 bit used: d 0 ~ d 8 instead; when 16 bit used: d 0 ~ d 15 instead; when 18 bit used: d 0 ~ d 17 instead. figure 33 ? 8080-series mpu parallel interface characteristics t t dhr t a cc valid data valid data t dsw t dhw t r t f pw csl pw csh t cycle t a h t a s d 0 -d 17 * (read data from driver) d 0 -d 17 * (write data to driver) wr # rd# cs# d/c
solomon systech jul 2005 p 52/59 rev 1.1 ssd1339 table 11 ? serial interface timing characteristics (v dd - v ss = 2.4 to 3.5v, t a = 25c) symbol parameter min typ max unit t cycle clock cycle time 250 - - ns t as address setup time 150 - - ns t ah address hold time 150 - - ns t css chip select setup time 120 - - ns t csh chip select hold time 60 - - ns t dsw write data setup time 100 - - ns t dhw write data hold time 100 - - ns t clkl clock low time 100 - - ns t clkh clock high time 100 - - ns t r rise time - - 15 ns t f fall time - - 15 ns t ah t as d/c# valid data t dhw t clk t dsw t clkh t cycle t css t csh t f t r sdin(d 1 ) cs# sclk(d 0 ) d7 sdin ( d 1 ) cs# sclk ( d 0 ) d6 d5 d4 d3 d2 d1 d0 figure 34 ? serial interface characteristics
ssd1339 rev 1.1 p 53/59 jul 2005 solomon systech 13. application example figure 35 ? application example for 8-bit 6800-parallel interface mode color oled panel 132rgb x 132 SSD1339Z com130 . com0 sa0 sb0 sc0 . . . . . . . . . . sa131 sb131 sc131 com1 . com131 nc v cc v comh nc d7~d0 e rw# dc# res# cs# i ref bs2 bs1 v dd v ddio vp_c vp_b vp_a vb ref rese fb vddb gdr v ss nc d7~d0 e rw# dc# res# cs# v ss [gnd] pin connected to mcu interface: d0~d7, e, r/w#, d/c#, res#, cs# pin internally connected to vdd: m/s#, cls pin internally connected to vss: vssb, bggnd pin internally connected to vcc: vref pin externally connected to vdd: bs0,1 pin externally connected to vss: bs2 pin floated: vp_c, vp_b, vp_a, vb ref , rese, fb, vddb, gdr c1~c3: 4.7uf voltage at i ref = vcc ? 3v r1 = (voltage at i ref - vss) / i ref = 910k ? r1 c1 c3 c2 the configuration for 8-bit 6800-parallel interface mode, externally v cc is shown in the following diagram: (v dd = v ddio = 3.0v, external v cc = 12v, i ref = 10ua)
solomon systech jul 2005 p 54/59 rev 1.1 ssd1339 14. package information ssd1339u3 pin assignment figure 36 - ssd1339u3 pin assignment
ssd1339 rev 1.1 p 55/59 jul 2005 solomon systech table 12 - ssd1339u3 pin assignment name pin # name pin # name pin # name pin # name pin # name pin # name pin # name pin # nc 1 nc 40 nc 121 sa101 202 sa74 283 sb47 364 sb20 445 nc 506 vcc 2 nc 41 nc 122 sc100 203 sc73 284 sa47 365 sa20 446 nc 507 comh 3 nc 42 nc 123 sb100 204 sb73 285 sc46 366 sc19 447 nc 508 vddio 4 nc 43 sa127 124 sa100 205 sa73 286 sb46 367 sb19 448 nc 509 vsl 5 com129 44 sc126 125 sc99 206 sc72 287 sa46 368 sa19 449 nc 510 d17 6 com128 45 sb126 126 sb99 207 sb72 288 sc45 369 sc18 450 nc 511 d16 7 com127 46 sa126 127 sa99 208 sa72 289 sb45 370 sb18 451 nc 512 d15 8 com126 47 sc125 128 sc98 209 sc71 290 sa45 371 sa18 452 nc 513 d14 9 com125 48 sb125 129 sb98 210 sb71 291 sc44 372 sc17 453 nc 514 d13 10 com124 49 sa125 130 sa98 211 sa71 292 sb44 373 sb17 454 nc 515 d12 11 com123 50 sc124 131 sc97 212 sc70 293 sa44 374 sa17 455 nc 516 d11 12 com122 51 sb124 132 sb97 213 sb70 294 sc43 375 sc16 456 nc 517 d10 13 com121 52 sa124 133 sa97 214 sa70 295 sb43 376 sb16 457 nc 518 d9 14 com120 53 sc123 134 sc96 215 sc69 296 sa43 377 sa16 458 nc 519 d8 15 com119 54 sb123 135 sb96 216 sb69 297 sc42 378 sc15 459 nc 520 d7 16 com118 55 sa123 136 sa96 217 sa69 298 sb42 379 sb15 460 nc 521 d6 17 com117 56 sc122 137 sc95 218 sc68 299 sa42 380 sa15 461 com0 522 d5 18 com116 57 sb122 138 sb95 219 sb68 300 sc41 381 sc14 462 com1 523 d4 19 com115 58 sa122 139 sa95 220 sa68 301 sb41 382 sb14 463 com2 524 d3 20 com114 59 sc121 140 sc94 221 sc67 302 sa41 383 sa14 464 com3 525 d2 21 com113 60 sb121 141 sb94 222 sb67 303 sc40 384 sc13 465 com4 526 d1 22 com112 61 sa121 142 sa94 223 sa67 304 sb40 385 sb13 466 com5 527 d0 23 com111 62 sc120 143 sc93 224 sc66 305 sa40 386 sa13 467 com6 528 e 24 com110 63 sb120 144 sb93 225 sb66 306 sc39 387 sc12 468 com7 529 r/w# 25 com109 64 sa120 145 sa93 226 sa66 307 sb39 388 sb12 469 com8 530 bs0 26 com108 65 sc119 146 sc92 227 sc65 308 sa39 389 sa12 470 com9 531 bs1 27 com107 66 sb119 147 sb92 228 sb65 309 sc38 390 sc11 471 com10 532 bs2 28 com106 67 sa119 148 sa92 229 sa65 310 sb38 391 sb11 472 com11 533 cs# 29 com105 68 sc118 149 sc91 230 sc64 311 sa38 392 sa11 473 com12 534 d/c# 30 com104 69 sb118 150 sb91 231 sb64 312 sc37 393 sc10 474 com13 535 res# 31 com103 70 sa118 151 sa91 232 sa64 313 sb37 394 sb10 475 com14 536 iref 32 com102 71 sc117 152 sc90 233 nc 314 sa37 395 sa10 476 com15 537 vbref 33 com101 72 sb117 153 sb90 234 sc63 315 sc36 396 sc9 477 com16 538 rese 34 com100 73 sa117 154 sa90 235 sb63 316 sb36 397 sb9 478 com17 539 fb 35 com99 74 sc116 155 sc89 236 sa63 317 sa36 398 sa9 479 com18 540 vddio 36 com98 75 sb116 156 sb89 237 sc62 318 sc35 399 sc8 480 com19 541 gdr 37 com97 76 sa116 157 sa89 238 sb62 319 sb35 400 sb8 481 com20 542 vss 38 com96 77 sc115 158 sc88 239 sa62 320 sa35 401 sa8 482 com21 543 nc 39 com95 78 sb115 159 sb88 240 sc61 321 sc34 402 sc7 483 com22 544 com94 79 sa115 160 sa88 241 sb61 322 sb34 403 sb7 484 com23 545 com93 80 sc114 161 sc87 242 sa61 323 sa34 404 sa7 485 com24 546 com92 81 sb114 162 sb87 243 sc60 324 sc33 405 sc6 486 com25 547 com91 82 sa114 163 sa87 244 sb60 325 sb33 406 sb6 487 com26 548 com90 83 sc113 164 sc86 245 sa60 326 sa33 407 sa6 488 com27 549 com89 84 sb113 165 sb86 246 sc59 327 sc32 408 sc5 489 com28 550 com88 85 sa113 166 sa86 247 sb59 328 sb32 409 sb5 490 com29 551 com87 86 sc112 167 sc85 248 sa59 329 sa32 410 sa5 491 com30 552 com86 87 sb112 168 sb85 249 sc58 330 sc31 411 sc4 492 com31 553 com85 88 sa112 169 sa85 250 sb58 331 sb31 412 sb4 493 com32 554 com84 89 sc111 170 sc84 251 sa58 332 sa31 413 sa4 494 com33 555 com83 90 sb111 171 sb84 252 sc57 333 sc30 414 sc3 495 com34 556 com82 91 sa111 172 sa84 253 sb57 334 sb30 415 sb3 496 com35 557 com81 92 sc110 173 sc83 254 sa57 335 sa30 416 sa3 497 com36 558 com80 93 sb110 174 sb83 255 sc56 336 sc29 417 sc2 498 com37 559 com79 94 sa110 175 sa83 256 sb56 337 sb29 418 sb2 499 com38 560 com78 95 sc109 176 sc82 257 sa56 338 sa29 419 sa2 500 com39 561 com77 96 sb109 177 sb82 258 sc55 339 sc28 420 sc1 501 com40 562 com76 97 sa109 178 sa82 259 sb55 340 sb28 421 sb1 502 com41 563 com75 98 sc108 179 sc81 260 sa55 341 sa28 422 sa1 503 com42 564 com74 99 sb108 180 sb81 261 sc54 342 sc27 423 sc0 504 com43 565 com73 100 sa108 181 sa81 262 sb54 343 sb27 424 sb0 505 com44 566 com72 101 sc107 182 sc80 263 sa54 344 sa27 425 sa0 506 com45 567 com71 102 sb107 183 sb80 264 sc53 345 sc26 426 com46 568 com70 103 sa107 184 sa80 265 sb53 346 sb26 427 com47 569 com69 104 sc106 185 sc79 266 sa53 347 sa26 428 com48 570 com68 105 sb106 186 sb79 267 sc52 348 sc25 429 com49 571 com67 106 sa106 187 sa79 268 sb52 349 sb25 430 com50 572 com66 107 sc105 188 sc78 269 sa52 350 sa25 431 com51 573 nc 108 sb105 189 sb78 270 sc51 351 sc24 432 com52 574 nc 109 sa105 190 sa78 271 sb51 352 sb24 433 com53 575 nc 110 sc104 191 sc77 272 sa51 353 sa24 434 com54 576 nc 111 sb104 192 sb77 273 sc50 354 sc23 435 com55 577 nc 112 sa104 193 sa77 274 sb50 355 sb23 436 com56 578 nc 113 sc103 194 sc76 275 sa50 356 sa23 437 com57 579 nc 114 sb103 195 sb76 276 sc49 357 sc22 438 com58 580 nc 115 sa103 196 sa76 277 sb49 358 sb22 439 com59 581 nc 116 sc102 197 sc75 278 sa49 359 sa22 440 com60 582 nc 117 sb102 198 sb75 279 sc48 360 sc21 441 com61 583 nc 118 sa102 199 sa75 280 sb48 361 sb21 442 com62 584 nc 119 sc101 200 sc74 281 sa48 362 sa21 443 com63 585 nc 120 sb101 201 sb74 282 sc47 363 sc20 444 nc 586 nc 587 nc 588 nc 589
solomon systech jul 2005 p 56/59 rev 1.1 ssd1339 ssd1339u3 cof details dimensions figure 37 - ssd1339u3 detail dimensions 2 1 38 39
ssd1339 rev 1.1 p 57/59 jul 2005 solomon systech contact side jae jacs-10142
solomon systech jul 2005 p 58/59 rev 1.1 ssd1339
ssd1339 rev 1.1 p 59/59 jul 2005 solomon systech http://www.solomon-systech.com solomon systech reserves the right to make changes without further notice to any products herein. solomon systech makes no warr anty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does solomon systech assu me any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without li mitation consequential o r incidental damages. ?typical? parameters can and do vary in different applications. all operating parameters, including ?typica ls? must be validated for each customer application by customer?s technical experts. solomon systech does not convey any license under its patent rig hts nor the rights o f others. solomon systech products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the solom on systech product could create a situation where personal injury or death may occur. should buyer purchase or use solomon systech products for any suc h unintended o r unauthorized application, buyer shall indemnify and hold solomon systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that solomon systech was neglig ent regarding the design or manufacture of the part.

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