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rev. c m112685 dat-15575-pp 071025 page 1 of 12 product features ? single positive supply voltage, +3v ? immune to latch up ? excellent accuracy, 0.1 db typ ? parallel control interface ? low insertion loss ? high ip3, +52 dbm typ ? very low dc power consumption ? excellent return loss, 20 db typ ? small size 4.0 x 4.0 mm typical applications ? base station infrastructure ? portable wireless ? catv & dbs ? mmds & wireless lan ? wireless local loop ? unii & hiper lan ? power ampli?er distortion canceling loops general description the dat-15575-pp is a 75 rf digital step attenuator that offers an attenuation range up to 15.5 db in 0.5 db steps. the control is a 5-bit parallel interface, operating on a single +3 volt supply. the dat- 15575- pp is produced using a unique cmos process on silicon, offering the performance of gaas, with the advantages of conventional cmos devices. digital step attenuator 15.5 db, 0.5 db step 5 bit, parallel control interface, single positive supply voltage, +3v 75 dc-2000 mhz simpli?ed schematic rf input 8db 4db 2db 1db 0.5db parallel control control logic interface latch enable rf out dat-15575-pp+ dat-15575-pp + rohs compliant in accordance with eu directive (2002/95/ec) the +suf?x identi?es rohs compliance. see our web site for rohs compliance methodologies and quali?cations.
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rf electrical speci?cations, dc-2000 mhz, t amb =25c, v dd =+3v absolute maximum ratings parameter freq. range (ghz) min. typ. max. units accuracy @ 0.5 db attenuation setting dc-1.2 0.03 0.17 db 1.2-2.0 0.05 0.18 db accuracy @ 1 db attenuation setting dc-1.2 0.03 0.19 db 1.2-2.0 0.1 0.2 db accuracy @ 2 db attenuation setting dc-1.2 0.07 0.23 db 1.2-2.0 0.15 0.25 db accuracy @ 4 db attenuation setting dc-1.2 0.05 0.25 db 1.2-2.0 0.15 0.35 db accuracy @ 8 db attenuation setting dc-1.2 0.1 0.25 db 1.2-2.0 0.24 0.55 db insertion loss (note1) @ all attenuator set to 0db dc-1.2 1.2 1.8 db 1.2-2.0 1.6 2.1 db input ip3 (note 2) (at min. and max. attenuation) dc-2.0 +52 dbm input power @ 0.2db compression* (at min. and max. attenuation) dc-2.0 +24 dbm vswr dc-1.2 1.6 2.0 1.2-2.0 1.7 2.0 parameter ratings operating temperature -40c to 85c storage temperature -55c to 100c v dd -0.3v min., 4v max. voltage on any input -0.3v min., v dd +0.3v max. esd, hbm 500v esd, mm 100v input power +24dbm parameter min. typ. max. units v dd , supply voltage 2.7 3 3.3 v i dd , supply current 100 a control input low 0.3xv dd v control input high 0.7xv dd v control current 1 a dc electrical speci?cations parameter min. typ. max. units switching speed, 50% control to 0.5db of attenuation value 1.0 sec switching control frequency 25 khz switching speci?cations 2. input ip3 and 1db compression degrades below 1 mhz notes: 1. i. loss values are de-embedded from test board loss (test boards insertion loss: 0.10db @100mhz, 0.40db @1200mhz, 0.55db @2000mhz, 0.75db @4000mhz)
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function pin number description n/c 1 not connected (note 3) rf in 2 rf in port (note 1) n/c 3 not connected (note 3) gnd 4 ground connection le 5 latch enable input (note 2) v dd 6 power supply n/c 7 not connected pup2 8 power up selection bit v dd 9 power supply gnd 10 ground connection gnd 11 ground connection gnd 12 ground connection gnd 13 ground connection rf out 14 rf out port (note 1) c8 15 control for attenuation bit, 8 db c4 16 control for attenuation bit, 4 db c2 17 control for attenuation bit, 2 db gnd 18 ground connection c1 19 control for attenuation bit, 1 db c0.5 20 control for attenuation bit, 0.5 db gnd paddle paddle ground (note 4) notes: 1. both rf ports must be held at 0vdc or dc blocked with an external series capacitor. 2. latch enable (le) has an internal 100k resistor to v dd . 3. place a 10k resistor to gnd. 4. the exposed solder pad on the bottom of the package (see pin con?guration) must be grounded for proper device operation. pin description pin con?guration (top view) gnd gnd gnd gnd gnd vdd vdd pup2 n/c rfout c8 le gnd n/c rfin n/c c4 c2 c1 c0.5 2x2mm paddle ground 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16
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typical performance curves attenuation (0.5db) @ +25c,+85c,-45c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 500 1000 1500 2000 2500 3000 frequency (mhz) (db) -45c +25c +85c attenuation (1db) @ +25c,+85c,-45c 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 0 500 1000 1500 2000 2500 3000 frequency (mhz) (db) -45c +25c +85c attenuation (2db) @ +25c,+85c,-45c 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 0 500 1000 1500 2000 2500 3000 frequency (mhz) (db) -45c +25c +85c attenuation (4db) @ +25c,+85c,-45c 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 0 500 1000 1500 2000 2500 3000 frequency (mhz) (db) -45c +25c +85c attenuation (8db) @ +25c,+85c,-45c 6.6 6.8 7 7.2 7.4 7.6 7.8 8 8.2 8.4 8.6 8.8 0 500 1000 1500 2000 2500 3000 frequency (mhz) (db) -45c +25c +85c insertion loss (ref) @ +25c, +85c, -45c 0 1 2 3 4 5 6 7 0 500 1000 1500 2000 2500 3000 frequency (mhz) (db) +85c +25c -45c
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typical performance curves attenuation (15.5db) @ +25c,+85c,-45c 12 13 14 15 16 17 18 0 500 1000 1500 2000 2500 3000 frequency (mhz) (db) -45c +25c +85c return loss in s11 (ref) @ +25c,+85c,-45c 0 10 20 30 40 50 0 500 1000 1500 2000 2500 3000 frequency (mhz) (db) -45c +25c +85c return loss out s22 (ref) @ +25c,+85c,-45c 0 10 20 30 40 50 0 500 1000 1500 2000 2500 3000 frequency (mhz) (db) -45c +25c +85c return loss in s11 (major attenuation steps) @ +25c 0 10 20 30 40 50 0 500 1000 1500 2000 2500 300 0 frequency (mhz) (db) att=0db att=0.5db att=1db att=2db att=4db att=8db att=15.5db return loss out s22 (major attenuation steps) @ +25c 0 10 20 30 40 50 0 500 1000 1500 2000 2500 3000 frequency (mhz) (db) att=0db att=0.5db att=1db att=2db att=4db att=8db att=15.5db
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typical performance curves ip-3 input (major attenuation steps) @ +25c 0 10 20 30 40 50 60 70 0 200 400 600 800 1000 1200 1400 1600 1800 2000 frequency (mhz) (dbm) att=0db att=0.5db att=1db att=2db att=4db att=8db att=15.5db ip-3 input (major attenuation steps) @ +85c 0 10 20 30 40 50 60 70 0 200 400 600 800 1000 1200 1400 1600 1800 2000 frequency (mhz) (dbm) att=0db att=0.5db att=1db att=2db att=4db att=8db att=15.5db ip-3 input (major attenuation steps) @ -45c 0 10 20 30 40 50 60 70 0 200 400 600 800 1000 1200 1400 1600 1800 2000 frequenc y( mhz ) (dbm) att=0db att=0.5db att=1db att=2db att=4db att=8db att=15.5db compression @input power=+24dbm (+25c) -0.8 -0.6 -0.4 -0.2 0 0.2 0 200 400 600 800 1000 1200 1400 1600 1800 2000 frequency (mhz) (db) att=0db att=0.5db att=1db att=2db att=4db att=8db att=15.5db compression @input power=+24dbm (+85c) -0.8 -0.6 -0.4 -0.2 0 0.2 0 200 400 600 800 1000 1200 1400 1600 1800 2000 frequency (mhz) (db) att=0db att=0.5db att=1db att=2db att=4db att=8db att=15.5db compression @input power=+24dbm (-45c) -0.8 -0.6 -0.4 -0.2 0 0.2 0 200 400 600 800 1000 1200 1400 1600 1800 2000 frequency (mhz) (db) att=0db att=0.5db att=1db att=2db att=4db att=8db att=15.5db
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outline drawing (dg983-1) device marking

15575 outline dimensions ( ) inch mm a bcdefghj k l m n p q r wt. grams .157 .157 .035 .008 .081 .081 .010 .022 .020 .166 .166 .070 .012 .026 .070 .04 4.00 4.00 0.90 0.20 2.06 2.06 0.25 0.56 0.50 4.22 4.22 1.78 0.31 0.66 1.78 suggested layout, tolerance to be within .002 pcb land pattern
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suggested layout for pcb design (pl-201) the suggested layout shows only the footprint area of the dat, and the components located near this area (i.e.: r1, r7). for the complete layout, see photo and schematic diagram on page 11 of 12. notes: 1. trace width is shown for fr4 with dielectric thickness. .025 .002. copper: 1/2 oz. each side. for other materials trace width may need to be modified. 2. 0603, 0402 size chip foot prints shown for reference, values of resistors will vary based on application. 3. bottom side of the pcb is continuous ground plane. denotes pcb copper layout with smobc (solder mask over bare copper) denotes copper land pattern free of soldermask
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the parallel interface timing requirements are de?ned by figure 1 (parallel interface timing diagram) and table 2 (parallel interface ac characteristics), and switching speed. for latched parallel programming the latch enable (le) should be held low while changing attenuation state control values, then pulse le high to low (per figure 1) to latch new attenuation into device. for direct parallel programming, the latch enable (le) line should be pulled high. changing attenuation state control values will change device state to new attenuation. direct mode is ideal for manual control of the device (using hardwire, switches, or jumpers) simpli?ed schematic figure 1: parallel interface timing diagram table 1. truth table attenuation state c8 c4 c2 c1 c0.5 reference 00000 0.5 (db) 00001 1 (db) 00010 2 (db) 00100 4 (db) 01000 8 (db) 10000 15.5 (db) 11111 note: not all 32 possible combinations of c0.5 - c8 are shown in table table 2. parallel interface ac characteristics symbol parameter min. max. units t lepw le minimum pulse width 10 ns t pdsup data set-up time before clock rising edge of le 10 ns t pdhld data hold time after clock falling edge of le 10 ns the dat-15575-pp parallel interface consists of 5 control bits that select the desired attenuation state, as shown in table 1 : truth table t pdsup t pdhld parallel data c8:c0.5 le t lepw rf input 8db 4db 2db 1db 0.5db parallel control control logic interface latch enable rf out
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pin 1 must always be low to prevent the attenuator from entering an unknown state. the dat-15575-pp always assumes a speci?able attenuation setting on power-up, allowing a known at- tenuation state to be established before an initial parallel control word is provided. when the attenuator powers up with le=0, the control bits are automatically set to one of two possible values. these two values are selected by the power-up control bit, pup2, as shown in table 3: (power-up truth table, parallel mode). power-up control settings power-up with le=1 provides normal parallel operation with c0.5-c8, and pup2 is not active. table 3. power-up truth table, parallel mode attenuation state pup2 le reference 0 0 8 (db) 1 0 de?ned by c0.5-c8 (see table 1-truth table) x (note 1) 1 note 1: pup2 connection may be 0, 1, ground, or not connect, without effect on attenuation state.
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TB-337 evaluation schematic diagram dat c0.5 c1 gnd c2 c4 n/c rfin n/c le v dd n/c pup2 v dd gnd c8 rfout gnd gnd r7 rfin rfout c11 r8 c9 c10 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 7 g n d g n d v d d g n d 1234 dc supply j2.1 le control j1.2 c3 r1 c4 c5 c6 c7 c8 r2 r3 r4 r5 r6 gnd ic 1 6 4 2 14 7 13 5 8 10 12 13 11 9 ic 2 6 4 2 14 7 13 5 8 10 12 13 11 9 r10 r11 c2 c4 c8 gnd gnd c16 c0.5 c1 12345678 gnd v dd 12 dc supply j2.2 c2 c1 + gnd le 12 ic3 parallel control j1.1 16 2 5 + r9 gnd TB-337 bill of materials r1 - r8 resistor 0603 10 kohm +/- 1% r10, r11 resistor 0603 470 ohm +/- 1% r9 resistor 0402 10 kohm +/- 1% c2 - c10 npo capacitor 0603 100pf +/- 5% c1, c11 tantalum capacitor 100nf +/- 10% ic1, ic2 hex inverting schmitt trigger mm74hc14 ic3 dual non-inverting schmitt trigger sn74lvc2g17
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tape and reel packaging information table t&r tr no. no. of devices designation letter reel size tape width pitch unit orientation 3000 t 13 inch t-005 multiples of 10, less than full reel of 3k pr 13 inch 12 mm 8 mm multiples of 10, on tape only e not applicable ordering information model no. description packaging designation letter (see table t&r) quantity min. no. of units price $ ea. dat-15575-pp (+) parallel interface, single positive voltage e 10 $3.55 TB-337 test board only not applicable 1 $79.95 how to order example: 3000 pieces of dat-15575-pp+ 3k dat-15575-pp+ t&r=t quantity model no. t&r designation letter (see table t&r) direction of feed tape cavity

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