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9db1933 idt ? nineteen output differential buffer for pcie gen3 1676a ?07/12/10 nineteen output differential buffer for pcie gen3 da t asheet 1 general descriptionoutput features the 9db1933 zero-delay buffer supports pcie gen3requirements, while being backwards compatible to pcie gen2 and gen1. the 9db1933 is dr iv en b y a diff erential src output pair from an idt 932s421, 932sq420, or equivalent, maincloc k gener ator . it atten uates jitter on the input cloc k and has a selectable pll bandwidth to maximize performance in systemswith or without spread-spectrum clocking. ? 19 - 0.7v current mode differential hcsl output pairs functional block diagram ke y specifications ? cycle-to-cycle jitter <50ps ? output-to-output skew < 150 ps ? pcie gen3 phase jitter < 1.0ps rms features/benefits? 8 selectable smbus addresses/mulitple devices can sharethe same smbus segment ? 11 dedicated and 3 group oe# pins/hardware control of theoutputs ? pll or bypass mode/pll can dejitter incoming clock ? selectable pll bandwidth/minimizes jitter peaking indownstream pll's ? spread spectrum compatible/tracks spreading input clockfor low emi ? smbus interface/unused outputs can be disabled ? suppor ts undr iv en diff erential outputs in p ow er do wn mode for power management recommended application19 output pcie gen3 zero-delay/fanout buffer dif_in dif_in# dif(18:0) high_bw# smb_a2_pllbyp# smbdat smbclk ckpwrgd/pd# 19 iref oe(17_18)# oe(15_16)# oe(14:5)#, oe_01234# 13 smb_a0 smb_a1 pll (ss compatible) logic
idt ? nineteen output differential buffer for pcie gen3 9db1933 nineteen output differential buffer for pcie gen3 2 1676a ?07/12/10 pin configuration smb_a2_pllbyp# dif_in# dif_in oe_17_18# dif_18# dif_18 dif_17# dif_17 gnd vdd dif_16# dif_ 16 oe_15_16# dif_15# dif_15 ckpwrgd/pd# dif_14# dif_14 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 iref 1 54 oe14# gnda 2 53 dif_13# vdda 3 52 dif_13 high_bw# 4 51 oe13# vdd 5 50 dif_12# dif_0 6 49 dif_12 dif_0# 7 48 oe12# dif_1 8 47 vdd dif_1# 9 46 gnd gnd 10 45 dif_11# vdd 11 44 dif_11 dif_2 12 43 oe11# dif_2# 13 42 dif_10# dif_3 14 41 dif_10 dif_3# 15 40 oe10# dif_4 16 39 dif_9# dif_4# 17 38 dif_9 oe_01234# 18 37 oe9# 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 smbclk smbdat oe5# dif_5 dif_5# oe6# dif_6 dif_6# vdd gnd oe7# dif_7 dif_7# oe8# dif_8 dif_8# smb_a0 smb_a1 9DB1933AKLF vdd gnd 3 2 pll, analog 5,11,27,47,63 10,28,46,64 dif clocks description pin number po wer gr oups power down functionality outputs ckpwrgd/ pd# dif_in/ dif_in# dif/dif# 1 running running on 0 x hi-z off pll state inputs
idt ? nineteen output differential buffer for pcie gen3 9db1933 nineteen output differential buffer for pcie gen3 3 1676a ?07/12/10 pin description pin # pin name pin type description 1 iref out this pin establishes the reference current for the differential current-mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is t he standard value. 2 gnda pwr ground pin for the pll core. 3 vdda pwr 3.3v power for the pll core. 4 high_bw# in 3.3v input for selecting pll band width 0 = high, 1= low 5 vdd pwr power supply, nominal 3.3v 6 dif_0 out 0.7v differential true clock output 7 dif_0# out 0.7v differential complementary clock out put 8 dif_1 out 0.7v differential true clock output 9 dif_1# out 0.7v differential complementary clock out put 10 gnd pwr ground pin. 11 vdd pwr power supply, nominal 3.3v 12 dif_2 out 0.7v differential true clock output 13 dif_2# out 0.7v differential complementary clock ou tput 14 dif_3 out 0.7v differential true clock output 15 dif_3# out 0.7v differential complementary clock output 16 dif_4 out 0.7v differential true clock output 17 dif_4# out 0.7v differential complementary clock ou tput 18 oe_01234# in active low input for enabling dif pairs 0, 1, 2, 3 and 4. 1 =disable outputs, 0 = enable outputs 19 smbclk in clock pin of smbus circuitry, 5v tolerant 20 smbdat i/o data pin of smbus circuitry, 5v tolerant 21 oe5# in active low input for enabling dif pair 5. 1 =disable outputs, 0 = enable outputs 22 dif_5 out 0.7v differential true clock output 23 dif_5# out 0.7v differential complementary clock ou tput 24 oe6# in active low input for enabling dif pair 6. 1 =disable outputs, 0 = enable outputs 25 dif_6 out 0.7v differential true clock output 26 dif_6# out 0.7v differential complementary clock ou tput 27 vdd pwr power supply, nominal 3.3v 28 gnd pwr ground pin. 29 oe7# in active low input for enabling dif pair 7. 1 =disable outputs, 0 = enable outputs 30 dif_7 out 0.7v differential true clock output 31 dif_7# out 0.7v differential complementary clock ou tput 32 oe8# in active low input for enabling dif pair 8. 1 =disable outputs, 0 = enable outputs 33 dif_8 out 0.7v differential true clock output 34 dif_8# out 0.7v differential complementary clock ou tput 35 smb_a0 in smbus address bit 0 (lsb) 36 smb_a1 in smbus address bit 1
idt ? nineteen output differential buffer for pcie gen3 9db1933 nineteen output differential buffer for pcie gen3 4 1676a ?07/12/10 pin description (cont.) pin # pin name pin type description 37 oe9# in active low input for enabling dif pair 9. 1 =disable outputs, 0 = enable outputs 38 dif_9 out 0.7v differential true clock output 39 dif_9# out 0.7v differential complementary clock ou tput 40 oe10# in active low input for enabling dif pair 10. 1 =disable outputs, 0 = enable outputs 41 dif_10 out 0.7v differential true clock output 42 dif_10# out 0.7v differential complementary clock o utput 43 oe11# in active low input for enabling dif pair 11. 1 =disable outputs, 0 = enable outputs 44 dif_11 out 0.7v differential true clock output 45 dif_11# out 0.7v differential complementary clock o utput 46 gnd pwr ground pin. 47 vdd pwr power supply, nominal 3.3v 48 oe12# in active low input for enabling dif pair 12. 1 =disable outputs, 0 = enable outputs 49 dif_12 out 0.7v differential true clock output 50 dif_12# out 0.7v differential complementary clock o utput 51 oe13# in active low input for enabling dif pair 13. 1 =disable outputs, 0 = enable outputs 52 dif_13 out 0.7v differential true clock output 53 dif_13# out 0.7v differential complementary clock o utput 54 oe14# in active low input for enabling dif pair 14. 1 =disable outputs, 0 = enable outputs 55 dif_14 out 0.7v differential true clock output 56 dif_14# out 0.7v differential complementary clock o utput 57 ckpwrgd/pd# in a rising edge samples latched inputs and release po wer down mode, a low puts the part into power down mode and tristates al l outputs. 58 dif_15 out 0.7v differential true clock output 59 dif_15# out 0.7v differential complementary clock o utput 60 oe_15_16# in active low input for enabling dif pair 15 and 16. 1 = tri-state outputs, 0 = enable outputs 61 dif_ 16 out 0.7v differential true clock output 62 dif_16# out 0.7v differential complementary clock o utput 63 vdd pwr power supply, nominal 3.3v 64 gnd pwr ground pin. 65 dif_17 out 0.7v differential true clock output 66 dif_17# out 0.7v differential complementary clock o utput 67 dif_18 out 0.7v differential true clock output 68 dif_18# out 0.7v differential complementary clock o utput 69 oe_17_18# in active low input for enabling dif pair 17, 18. 1 = tri-state outputs, 0 = enable outputs 70 dif_in in 0.7 v differential true input 71 dif_in# in 0.7 v differential complementary input 72 smb_a2_pllbyp# in smbus address bit 2. when low, the part operates as a fanout buffer with the pll bypassed. when high, the part operates as a zer o-delay buffer (zdb) with the pll operating. 0 = fanout mode (pll bypassed), 1 = zdb mode (pll u sed)
idt ? nineteen output differential buffer for pcie gen3 9db1933 nineteen output differential buffer for pcie gen3 5 1676a ?07/12/10 electrical characteristics - absolute maximum ratin gs parameter symbol conditions min typ max units notes 3.3v core supply voltage vdda 4.6 v 1,2 3.3v logic supply voltage vdd 4.6 v 1,2 input low voltage v il gnd-0.5 v 1 input high voltage v ih except for smbus interface v dd +0.5v v 1 input high voltage v ihsmb smbus clock and data pins 5.5v v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. electrical characteristics - input/supply/common pa rameters ta = t com ; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes ambient operating temperature t com commmercial range 0 70 c 1 input high voltage v ih single-ended inputs, except smbus, low threshold and tri-level inputs 2 v dd + 0.3 v 1 input low voltage v il single-ended inputs, except smbus, low threshold and tri-level inputs gnd - 0.3 0.8 v 1 i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua 1 i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -200 200 ua 1 input frequency f ibyp v dd = 3.3 v, bypass mode 10 166 mhz 2 f ipll v dd = 3.3 v, 100mhz pll mode 90 100 110 mhz 2 pin inductance l pin 7 nh 1 c in logic inputs, except dif_in 1.5 5 pf 1 c indif_in dif_in differential clock inputs 1.5 2.7 pf 1,4 c out output pin capacitance 2.5 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 1.000 1.8 ms 1,2 input ss modulation frequency f modin allowable frequency (triangular modulation) 30 33 khz 1 oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 4 12 cycles 1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 300 us 1,3 tfall t f fall time of control inputs 5 ns 1,2 trise t r rise time of control inputs 5 ns 1,2 smbus input low voltage v ilsmb 0.8 v 1 smbus input high voltage v ihsmb 2.1 v ddsmb v 1 smbus output low voltage v olsmb @ i pullup 0.4 v 1 smbus sink current i pullup @ v ol 4 ma 1 nominal bus voltage v ddsmb 3v to 5v +/- 10% 2.7 5.5 v 1 sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 100 khz 1,5 1 guaranteed by design and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. 5 the differential input clock must be running for th e smbus to be active input current 3 time from deassertion until outputs are >200 mv 4 dif_in input capacitance
idt ? nineteen output differential buffer for pcie gen3 9db1933 nineteen output differential buffer for pcie gen3 6 1676a ?07/12/10 electrical characteristics - clock input parameters ta = t com or t ind; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage - dif_in v ihdif differential inputs (single-ended measurement) 600 800 1150 mv 1 input low voltage - dif_in v ildif differential inputs (single-ended measurement) v ss - 300 0 300 mv 1 input common mode voltage - dif_in v com common mode input voltage 300 1000 mv 1 input amplitude - dif_in v swing peak to peak value 300 1450 mv 1 input slew rate - dif_in dv/dt measured differentially 0.4 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input duty cycle d tin measurement from differential wavefrom 45 55 % 1 input jitter - cycle to cycle j difin differential measurement 0 125 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through +/-75mv window centered around differential zero electrical characteristics - dif 0.7v current mode differential outputs t a = t com; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes slew rate trf scope averaging on 1 2 4 v/ns 1, 2, 3 slew rate matching ? trf slew rate matching, scope averaging on 20 % 1, 2, 4 voltage high vhigh 660 789 850 1 voltage low vlow -150 45 150 1 max voltage vmax 834 1150 1 min voltage vmin -300 17 1 vswing vswing scope averaging off 300 744 mv 1, 2 crossing voltage (abs) vcross_abs scope averaging off 250 380 550 mv 1, 5 crossing voltage (var) ? -vcross scope averaging off 24 140 mv 1, 6 2 measured from differential waveform 6 the total variation of all vcross measurements in any particular system. note that this is a subset o f v_cross_min/max (v_cross absolute) allowed. the intent is to limit vcross induced modu lation by setting v_cross_delta to be smaller than v_cross absolute. mv statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) measurement on single ended signal using absolute value. (scope averaging off) mv 1 guaranteed by design and characterization, not 100% tested in production. iref = vdd/(3xr r ). for r r = 475 (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 (100 differential impedance). 3 slew rate is measured through the vswing voltage ra nge centered around differential 0v. this results in a +/-150mv window around differential 0v. 4 matching applies to rising edge rate of clock / fal ling edge rate of clock#. it is measured in a +/-75 mv window centered on the average cross point where clock rising meets clock# falling . the median cross point is used to calculate the v oltage thresholds the oscilloscope uses for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential rising edge (i.e. clock rising and clock# falling). electrical characteristics - current consumption ta = t com; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes operating supply current i dd3.3op all outputs active @100mhz, c l = full load; 427 500 ma 1 powerdown current i dd3.3pdz all differential pairs tri-stated 32 40 ma 1 1 guaranteed by design and characterization, not 100% tested in production.
idt ? nineteen output differential buffer for pcie gen3 9db1933 nineteen output differential buffer for pcie gen3 7 1676a ?07/12/10 electrical characteristics - output duty cycle, jit ter, skew and pll characterisitics ta = t com; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes -3db point in high bw mode 2 3 4 mhz 1 -3db point in low bw mode 0.7 1 1.4 mhz 1 pll jitter peaking t jpeak peak pass band gain 1.4 2 db 1 duty cycle t dc measured differentially, pll mode 45 49.5 55 % 1,2 duty cycle distortion t dcd measured differentially, bypass mode @100mhz -2 1 2 % 1, 2,5 t pdbyp bypass mode, nominal value @ 25c, 3.3v, v t = 50% 2500 3700 4500 ps 1,2,4 t pdpll pll mode, nominal value @ 25c, 3.3v, v t = 50% 100 300 500 ps 1,2,3 dif_in, dif [x:0] ? t pd_byp input-to-output skew variation in bypass mode (over specified voltage / temperature operating ranges) |500| |600| ps 1,2,4,6, 7,8,9, 13 dif_in, dif [x:0] ? t pd_pll input-to-output skew variation in pll mode (over specified voltage / temperature operating ranges) |250| |350| ps 1,2,3,6, 7,8,9, 13 dif[x:0] t jph differential phase jitter (rms value) 2 10 ps 1,7,10 dif[x:0] t ssterror differential spread spectrum tracking error (peak to peak) 40 80 ps 1,7,12 skew, output to output t sk3 v t = 50% 100 150 ps 1 pll mode 40 50 ps 1,2 additive jitter in bypass mode 25 50 ps 1,2 1 guaranteed by design and characterization, not 100% tested in production. c load = 2pf 5 duty cycle distortion is the difference in duty cy cle between the output and the input clock when the device is operated in bypass mode. 6 vt = 50% of vout 11 t is the period of the input clock pll bandwidth bw 3 pll mode input-to-output skew is measured at the f irst output edge following the corresponding input. 2 measured from differential cross-point to different ial cross-point 4 all bypass mode input-to-output specs refer to the timing between an input edge and the specific outp ut edge created by it. 7 this parameter is deterministic for a given device 13 this parameter is an absolute value. it is not a d ouble-sided figure. skew, input to output jitter, cycle to cycle 9 long-term variation from nominal of input-to-outpu t skew over temperature and voltage for a single de vice. 10 this parameter is measured at the outputs of two s eparate 9db1933 devices driven by a single main clo ck. the 9db1933's must be set to high bandwidth. differential phase jitter is the accumulation of the phase jitter not shared by the outputs (eg. not including the 12 differential spread spectrum tracking error is the difference in spread spectrum tracking between two 9db1933 devices this parameter is measured at the outputs of two separate 9db1933 devices driven by a single main clock in spread spe ctrum mode. the 9db1933's must be set to high bandwidth. the spread spectrum characteristics are: maximum of 0.5%, 30-33khz mod ulation frequency, linear t jcyc-cyc 8 measured with scope averaging on to find mean valu e.
idt ? nineteen output differential buffer for pcie gen3 9db1933 nineteen output differential buffer for pcie gen3 8 1676a ?07/12/10 electrical characteristics - pcie phase jitter para meters ta = t com; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes t jphpcieg1 pcie gen 1 44 86 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 1.4 3 ps (rms) 1,2 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 2.5 3.1 ps (rms) 1,2 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.6 1 ps (rms) 1,2,4 t jphpcieg1 pcie gen 1 3 5 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 0.02 0.1 ps (rms) 1,2 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 0.2 0.3 ps (rms) 1,2 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.04 0.1 ps (rms) 1,2,4 1 applies to all outputs. 4 subject to final radification by pci sig. t jphpcieg2 2 see http://www.pcisig.com for complete specs t jphpcieg2 phase jitter, pll mode additive phase jitter, bypass mode 3 sample size of at least 100k cycles. this figures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1-12.
idt ? nineteen output differential buffer for pcie gen3 9db1933 nineteen output differential buffer for pcie gen3 9 1676a ?07/12/10 clock periods differential outputs with spread spec trum enabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock lg- -ssc -ppm error 0ppm + ppm error +ssc lg+ absolute period short-term average long-term average period long-term average short-term average period minimum absolute period minimum absolute period minimum absolute period nominal maximum maximum maximum dif dif 100 9.87400 9.99900 9.99900 10.00000 10.00100 10.05130 10.176 30 ns 1,2,3 clock periods differential outputs with spread spec trum disabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock lg- -ssc -ppm error 0ppm + ppm error +ssc lg+ absolute period short-term average long-term average period long-term average short-term average period minimum absolute period minimum absolute period minimum absolute period nominal maximum maximum maximum dif dif 100 9.87400 9.99900 10.00000 10.00100 10.17630 ns 1,2,3 1 guaranteed by design and characterization, not 100% tested in production. 3 driven by src output of main clock, pll or bypass mode units measurement window symbol 2 all long term accuracy specifications are guarantee d with the assumption that the input clock complies with ck410b+/ck420bq accuracy requirements. the 9db1933 itself does not contribute to ppm error. notes notes definition measurement window units symbol definition
idt ? nineteen output differential buffer for pcie gen3 9db1933 nineteen output differential buffer for pcie gen3 10 1676a ?07/12/10 common recommendations for differential routing dime nsion or value unit figure l1 length, route as non-coupled 50ohm trace 0.5 max i nch 1 l2 length, route as non-coupled 50ohm trace 0.2 max i nch 1 l3 length, route as non-coupled 50ohm trace 0.2 max i nch 1 rs 33 ohm 1 rt 49.9 ohm 1 down device differential routing l4 length, route as coupled microstrip 100ohm diffe rential trace 2 min to 16 max inch 1 l4 length, route as coupled stripline 100ohm differ ential trace 1.8 min to 14.4 max inch 1 differential routing to pci express connector l4 length, route as coupled microstrip 100ohm diffe rential trace 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100ohm differ ential trace 0.225 min to 12.6 max inch 2 dif reference clock hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express down device ref_clk input figure 1: down device routing hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express add-in board ref_clk input figure 2: pci express connector routing
idt ? nineteen output differential buffer for pcie gen3 9db1933 nineteen output differential buffer for pcie gen3 11 1676a ?07/12/10 vdiff vp-p vcm r1 r2 r3 r4 note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compati ble 0.60 0.3 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 alternative termination for lvds and other common d ifferential signals (figure 3) hcsl output buffer l1 l1' r1b l2 l2' r1a l4' l4 l3 r2a r2b down device ref_clk input figure 3 l3' r3 r4 pcie device ref_clk input figure 4 r5a l4' l4 3.3 volts r5b r6a r6b cc cc component value note r5a, r5b 8.2k 5% r6a, r6b 1k 5% cc 0.1 f vcm 0.350 volts cable connected ac coupled application (figure 4)
idt ? nineteen output differential buffer for pcie gen3 9db1933 nineteen output differential buffer for pcie gen3 12 1676a ?07/12/10 general smbus serial interface information for the 9db1933 ho w to write: ? controller (host) sends a star t bit. ? controller (host) sends the wr ite address dc (h) ? ics cloc k will ac kno wledg e ? controller (host) sends the begining b yte location = n ? ics cloc k will ac kno wledg e ? controller (host) sends the data b yte count = x ? ics cloc k will ac kno wledg e ? controller (host) star ts sending byte n thr ough byte n + x -1 ? ics cloc k will ac kno wledg e each b yte one at a time ? controller (host) sends a stop bit ho w to read: ? controller (host) will send star t bit. ? controller (host) sends the wr ite address dc (h) ? ics cloc k will ac kno wledg e ? controller (host) sends the begining b yte location = n ? ics cloc k will ac kno wledg e ? controller (host) will send a separ ate star t bit. ? controller (host) sends the read address dd (h) ? ics cloc k will ac kno wledg e ? ics cloc k will send the data b yte count = x ? ics cloc k sends byte n + x -1 ? ics cloc k sends byte 0 thr ough b yte x (if x (h) was written to b yte 8) . ? controller (host) will need to ac kno wledge each b yte ? controllor (host) will send a not ac kno wledge bit ? controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address dc (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge p stop bit slave address dd (h) index block read operation slave address dc (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack note: addresses sho w assumes pin 29 is lo w.
idt ? nineteen output differential buffer for pcie gen3 9db1933 nineteen output differential buffer for pcie gen3 13 1676a ?07/12/10 smbustable: reserved register pin # name control function type 0 1 default bit 7 r 1 bit 6 r 1 bit 5 r 1 bit 4 r 1 bit 3 r 1 bit 2 r 0 bit 1 r 1 bit 0 r 1 smbustable: output control register pin # name control function type 0 1 default bit 7 dif_7 output control rw hi-z enable 1 bit 6 dif_6 output control rw hi-z enable 1 bit 5 dif_5 output control rw hi-z enable 1 bit 4 dif_4 output control rw hi-z enable 1 bit 3 dif_3 output control rw hi-z enable 1 bit 2 dif_2 output control rw hi-z enable 1 bit 1 dif_1 output control rw hi-z enable 1 bit 0 dif_0 output control rw hi-z enable 1 smbustable: output and pll bw control register pin # name control function type 0 1 default bit 7 rw high bw low bw 1 bit 6 rw bypass pll 1 bit 5 dif_13 output control rw hi-z enable 1 bit 4 dif_12 output control rw hi-z enable 1 bit 3 dif_11 output control rw hi-z enable 1 bit 2 dif_10 output control rw hi-z enable 1 bit 1 dif_9 output control rw hi-z enable 1 bit 0 dif_8 output control rw hi-z enable 1 note: bit 7 is wired or to the high_bw# input, any 0 selects high bw note: bit 6 is wired or to the smb_a2_pllbyp# input , any 0 selects fanout bypass mode smbustable: output enable readback register pin # name control function type 0 1 default bit 7 r x bit 6 r x bit 5 r x bit 4 r x bit 3 r x bit 2 r x bit 1 r x bit 0 r x 72 see note pll_bw# adjust see note bypass# test mode / pll byte 3 8 byte 1 - - -- byte 0 - - reserved - - reserved reserved readback readback - oe9# input readback - oe8# input readback readback readback - oe7# input readback readback - oe_01234# input readback readback - oe5# input readback - oe6# input readback byte 2 reserved readback - smb_a2_pllbyp# in readback readback - high_bw# in readback reserved reserved reserved reserved
idt ? nineteen output differential buffer for pcie gen3 9db1933 nineteen output differential buffer for pcie gen3 14 1676a ?07/12/10 smbustable: output enable readback register pin # name control function type 0 1 default bit 7 r x bit 6 r x bit 5 0 bit 4 r x bit 3 r x bit 2 r x bit 1 r x bit 0 r x smbustable: vendor & revision id register pin # name control function type 0 1 default bit 7 rid3 r - - 0 bit 6 rid2 r - - 0 bit 5 rid1 r - - 0 bit 4 rid0 r - - 1 bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 smbustable: device id (194 decimal or c2 hex) pin # name control function type 0 1 default bit 7 rw 1 bit 6 rw 1 bit 5 rw 0 bit 4 rw 0 bit 3 rw 0 bit 2 rw 0 bit 1 rw 1 bit 0 rw 0 smbustable: byte count register pin # name control function type 0 1 default bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 0 bit 2 bc2 rw - - 1 bit 1 bc1 rw - - 1 bit 0 bc0 rw - - 1 - - - 54 51 48 43 - - - - - reserved readback readback readback reserved readback reserved reserved reserved reserved device id 1 reserved writing to this register configures how many bytes will be read back. - -- 60 - - 40 - - readback - oe12# input vendor id readback - oe11# input device id 5 device id 6 device id 7 (msb) revision id - byte 5 - byte 6 69 - reserved device id 2 byte 4 readback - oe13# input byte 7 - - -- - - device id 3 device id 4 readback readback - oe10# input readback - oe14# input readback readback reserved device id 0 readback - oe15_16# input readback - oe17_18# input
idt ? nineteen output differential buffer for pcie gen3 9db1933 nineteen output differential buffer for pcie gen3 15 1676a ?07/12/10 smbustable: output control register pin # name control function type 0 1 default bit 7 1 bit 6 x bit 5 x bit 4 dif_18 output control rw hi-z enable 1 bit 3 dif_17 output control rw hi-z enable 1 bit 2 dif_16 output control rw hi-z enable 1 bit 1 dif_15 output control rw hi-z enable 1 bit 0 dif_14 output control rw hi-z enable 1 smbustable: reserved register pin # name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 1 bit 1 0 bit 0 1 reserved reserved reserved byte 8 reserved byte 9 reserved reserved reserved reserved reserved reserved reserved smbus address mapping smbus address (hex) main clock (ckxxx) 9db233 9db433 9db633 9db833 9db1233 9db1933 d0 d2 d4 d6 d8 da dc de note: indicates bypass mode. pll is off.
idt ? nineteen output differential buffer for pcie gen3 9db1933 nineteen output differential buffer for pcie gen3 16 1676a ?07/12/10 top v iew index area d sawn singulation anvil singulation a 0. 08 c c a3 a1 seating plane e2 e2 2 l (n -1)x e (ref.) (ref.) & n n even n e d2 2 d2 (re f.) & odd 1 2 e 2 (t yp.) if n & n are even (n -1)x (ref.) b thermal base n or chamfer 4x0.6 x 0.6 max optional e d n n d d d symbol 72l n 72 a 0.8 1.0 n d 18 a1 0 0.05 n e 18 a3 b 0.18 0.3 e d x e basic d2 min. / max. 5.75 6.15 e2 min. / max. 5.75 6.15 l min. / max. 0.3 0.5 max. 0.25 reference 0.50 basic 10.00 x 10.00 dimensions thermally enhanced, very thin, fine pitch quad flat / no lead plastic package dimensions (mm) symbol min. ordering information part / order number shipping packaging package tempera ture 9DB1933AKLF tubes 72-pin mlf 0 to +70c 9DB1933AKLFt tape and reel 72-pin mlf 0 to +70c ?lf? after the package code denotes the pb-free con figuration, rohs compliant. ?a? is the device revision designator (will not cor relate with the datasheet revision).
9db1933 nineteen output differential buffer for pcie gen3 17 innovate with idt and accelerate your future networks. cont act: www .idt .com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for t ech support 408-284-6578 pcclockhelp@id t.com corporate headquarters integrated device t echnology , inc. 6024 silver creek v alley road san jose, ca 95138 united s t ates 800 345 7015 +408 284 8200 (out side u.s.) asia pacific and japan idt singapore pte. ltd. 1 kallang sector #07-01/06 kolamayer industrial park singapore 349276 phone: 65-6-744-3356 fax: 65-6-744-1764 europe idt europe limited 321 kingston road leatherhead, surrey kt22 7tu england phone: 44-1372-363339 fax: 44-1372-378851 ? 2010 integrated device t echnology , inc. all right s reserved. product specifications subject to change without notice. idt , ics, and the idt logo are trademarks of integrated device t echnology , inc. accelerated thinking is a service mark of integrated device t echnology , inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa revision history rev. issue date who description page # 0.1 7/7/2010 rdw initial release - a 7/12/2010 rdw 1. updated 'pwd' to 'default' in smbus column headi ngs 2. updated electrical tables with char data 3. added smbusaddressing table to page 15 5-8,13-15

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