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freescale semiconductor data sheet: technical data document number: MPC5642A rev. 3.1, 06/2012 ? freescale semiconductor, inc., 2009, 2010, 2012. all rights reserved. MPC5642A 208 mapbga 176 lqfp 324 tepbga (24 24 mm) (23 23 mm) (17 x 17 mm) ? 150 mhz e200z4 power architecture core ? variable length instruction encoding (vle) ? superscalar architectur e with 2 execution units ? up to 2 integer or floating point instructions per cycle ? up to 4 multiply and accumu late operations per cycle ? memory organization ? 2 mb on-chip flash memory with ecc and read-while-write (rww) ? 128 kb on-chip sram with standby functionality (32 kb) and ecc ? 8 kb instruction cache (with line locking), configurable as 2- or 4-way ? 14 + 3 kb etpu code and data ram ?4 ? 4 crossbar switch (xbar) ? 24-entry mmu ? fail safe protection ? 16-entry memory protection unit (mpu) ? crc unit with 3 submodules ? junction temperature sensor ? interrupt ? configurable interrupt controller (intc) with non-maskable interrupt (nmi) ? 64-channel edma ? serial channels ? 3 esci modules ? 3 dspi modules (2 of which support downstream micro second channel [msc]) ? 3 flexcan modules with 64 message buffers each ? 1 flexray module (v2.1) up to 10 mbit/s w/dual or single channel, 128 message objects, ecc ?1 emios ? 24 unified channels ? 1 etpu2 (second generation etpu) ?32 standard channels ? 1 reaction module (6 cha nnels with 3 outputs per channel) ? 2 enhanced queued analog-to-digital converters (eqadcs) ? forty 12-bit input channels (multiplexed on 2 adcs); expandable to 56 channels with external multiplexers ? 6 command queues ? trigger and dma support ? 688 ns minimum conversion time ? on-chip can/sci bootstrap loader with boot assist module (bam) ? nexus: class 3+ for core; class 1 for etpu ? jtag (5-pin) ? development trigger semaphore (dts) ? evto pin for communicati on with external tool ? clock generation ? on-chip 4?40 mhz main oscillator ? on-chip fmpll (frequency-modulated phase-locked loop) ? up to 112 general purpose i/o lines ? individually programmable as input, output or special function ? programmable threshold (hysteresis) ? power reduction modes: slow, stop, and standby ? flexible supply scheme ? 5 v single supply with external ballast ? multiple external supply: 5 v, 3.3 v, and 1.2 v qorivva MPC5642A microcontroller data sheet
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 2 table of contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 document overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.3 device feature summary . . . . . . . . . . . . . . . . . . . . . . . . .3 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.5 feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.5.1 e200z4 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.5.2 crossbar switch (xbar) . . . . . . . . . . . . . . . . . .10 1.5.3 enhanced direct memory access (edma) . . . . .10 1.5.4 interrupt controller (intc) . . . . . . . . . . . . . . . . .11 1.5.5 memory protection unit (mpu). . . . . . . . . . . . . .11 1.5.6 frequency-modulat ed phase-locked loop (fmpll). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.5.7 system integration unit (siu). . . . . . . . . . . . . . .12 1.5.8 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.5.9 static random access memory (sram) . . . . . .14 1.5.10 boot assist module (bam) . . . . . . . . . . . . . . . . .14 1.5.11 enhanced modular input/output system (emios) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 1.5.12 second generation enhanced time processing unit (etpu2) . . . . . . . . . . . . . . . . . . . . . . . . . . .15 1.5.13 reaction module (reacm) . . . . . . . . . . . . . . . .16 1.5.14 enhanced queued analog-to-digital converter (eqadc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.5.15 deserial serial peripheral interface (dspi) . . . .18 1.5.16 enhanced serial communications interface (esci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.5.17 controller area network (flexcan) . . . . . . . . . .19 1.5.18 flexray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.5.19 system timers . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.5.20 software watchdog timer (swt) . . . . . . . . . . . .21 1.5.21 cyclic redundancy check (crc) module . . . . . .21 1.5.22 error correction status module (ecsm). . . . . . .22 1.5.23 peripheral bridge (pbridge) . . . . . . . . . . . . . .22 1.5.24 calibration bus interface . . . . . . . . . . . . . . . . . .22 1.5.25 power management controller (pmc) . . . . . . . .22 1.5.26 nexus port controller (npc) . . . . . . . . . . . . . . .23 1.5.27 jtag controller (jtagc) . . . . . . . . . . . . . . . . . .23 1.5.28 development trigger semaphore (dts). . . . . . .23 2 pinout and signal description . . . . . . . . . . . . . . . . . . . . . . . . .23 2.1 176 lqfp pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 2.2 208 map bga ballmap . . . . . . . . . . . . . . . . . . . . . . . . .25 2.3 324 tepbga ballmap. . . . . . . . . . . . . . . . . . . . . . . . . .26 2.4 signal summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.5 signal details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.1 parameter classification. . . . . . . . . . . . . . . . . . . . . . . . 55 3.2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 58 3.3.1 general notes for specifications at maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.4 emi (electromagnetic interf erence) characteristics . . . 61 3.5 electrostatic discharge (esd) characteristics . . . . . . . 62 3.6 power management control (pmc) and power on reset (por) electrical specificati ons . . . . . . . . . . . . . . 62 3.6.1 regulator example . . . . . . . . . . . . . . . . . . . . . . 65 3.6.2 recommended power transistors. . . . . . . . . . . 66 3.7 power up/down sequencing. . . . . . . . . . . . . . . . . . . . . 66 3.8 dc electrical specifications . . . . . . . . . . . . . . . . . . . . . 67 3.9 i/o pad current specifications . . . . . . . . . . . . . . . . . . . 72 3.9.1 i/o pad v rc33 current specifications . . . . . . . . 73 3.9.2 lvds pad specifications. . . . . . . . . . . . . . . . . . 74 3.10 oscillator and pllmrfm elec trical characteristics . . . 75 3.11 temperature sensor electrical characteristics . . . . . . . 77 3.12 eqadc electrical char acteristics . . . . . . . . . . . . . . . . . 77 3.13 configuring sram wait states. . . . . . . . . . . . . . . . . . . 79 3.14 platform flash controller electrical characteristics . . . . 80 3.15 flash memory electrical charac teristics . . . . . . . . . . . 80 3.16 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.16.1 pad ac specifications. . . . . . . . . . . . . . . . . . . . 82 3.17 ac timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.17.1 reset and configuration pin timing . . . . . . . . . . 86 3.17.2 ieee 1149.1 interface timing . . . . . . . . . . . . . . 86 3.17.3 nexus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 90 3.17.4 calibration bus interface timing . . . . . . . . . . . . 95 3.17.5 external interrupt timing (irq pin) . . . . . . . . . . 99 3.17.6 etpu timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 3.17.7 emios timing . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.17.8 dspi timing . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.17.9 eqadc ssi timing . . . . . . . . . . . . . . . . . . . . . 107 3.17.10flexcan system clock source . . . . . . . . . . . . 108 4 packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 4.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . 109 4.1.1 176 lqfp. . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 4.1.2 208 mapbga. . . . . . . . . . . . . . . . . . . . . . . . . 112 4.1.3 324 tepbga . . . . . . . . . . . . . . . . . . . . . . . . . 114 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 117
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 3 introduction 1 introduction 1.1 document overview this document provides electri cal specifications, pin assignmen ts, and package diagrams fo r the MPC5642A series of microcontroller units (mcus). it also describes the devi ce features and highlights important electrical and physical characteristics. for functiona l characteristics, refer to the device reference manual. 1.2 description this microcontroller is a 32-bit system- on-chip (soc) device intended for use in mid-range engine control and automotive transmission control applications. it is compatible with devices in freescale?s mpc5600 family and offers performance and capabilities beyond the mpc5632m devices. the microcontroller?s e200z4 host processo r core is built on the power architecture ? technology and designed specifically for embedded applications. in addition to the power architecture technology, this core supports instructions for digital signal processing (dsp). the device has two levels of memory hier archy consisting of 8 kb of instructio n cache, backed by a 128 kb on-chip sram and a 2 mb internal flash memory. for development, the device incl udes a calibration bus that is accessible only when using th e freescale vertical calibration system. 1.3 device feature summary table 1 summarizes the MPC5642A f eatures and compares them to those of the mpc5644a. table 1. MPC5642A device feature summary feature MPC5642A mpc5644a process 90 nm core e200z4 simd ye s vle ye s cache 8 kb instruction non-maskable interrupt (nmi) n mi and critical interrupt mmu 24-entry mpu 16-entry crossbar switch 4 ? 45 ? 4 core performance 0?150 mhz windowing software watchdog yes core nexus class 3+ sram 128 kb 192 kb flash 2 mb 4 mb flash fetch accelerator 4 ? 128-bit 4 ? 256-bit
MPC5642A microcontroller data sheet, rev. 3.1 4 freescale semiconductor introduction external bus none 16-bit (incl. 32-bit muxed) calibration bus 16-bit (incl. 32-bit muxed) dma 64 channels dma nexus none serial 3 esci_a yes (msc uplink) esci_b yes (msc uplink) esci_c yes can 3 can_a 64 message buffers can_b 64 message buffers can_c 64 message buffers spi 3 micro second channel (msc) bus downlink yes dspi_a no dspi_b yes (with lvds) dspi_c yes (with lvds) dspi_d yes flexray ye s system timers 5 pit channels 4 stm channels 1 software watchdog emios 24 channels etpu 32-channel etpu2 code memory 14 kb data memory 3 kb reaction module 6 channels interrupt controller 485 channels 1 adc 40 channels adc_0 yes adc_1 yes temperature sensor yes variable gain amplifier yes decimation filter 2 sensor diagnostics yes table 1. MPC5642A device feature summary (continued) feature MPC5642A mpc5644a
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 5 introduction 1.4 block diagram figure 1 shows a top-level block diagram of the MPC5642A series. crc ye s fmpll ye s vrc ye s supplies 5 v, 3.3 v 2 low-power modes stop mode slow mode packages 176 lqfp 3 208 mapbga 3,4 324 tepbga 5 496-pin csp 6 176 lqfp 3 208 mapbga 3,4 324 tepbga 5 496-pin csp 6 1 197 interrupt vectors are reserved. 2 5 v single supply only for 176 lqfp 3 pinout compatible with freescale?s mpc5634m devices 4 pinout compatible with freescale?s mpc5534 5 ballmap upwardly compatible with the standardized pack age ballmap used for various freescale mpc563xm family members 6 for freescale vertical calibration system only table 1. MPC5642A device feature summary (continued) feature MPC5642A mpc5644a
MPC5642A microcontroller data sheet, rev. 3.1 6 freescale semiconductor introduction figure 1. MPC5642A series block diagram table 2 summarizes the functions of the blocks pr esent on the MPC5642A series microcontrollers. adc ? analog to digital converter adci ? adc interface amux ? analog multiplexer bam ? boot assist module crc ? cyclic redundancy check unit dec ? decimation filter dts ? development trigger semaphore dspi ? deserial/serial peripheral interface ecsm ? error correction status module edma ? enhanced direct memory access emios ? enhanced modular input output system esci ? enhanced serial communications interface etpu2 ? second gen. enhanced time processing unit flexcan ? controller area network fmpll ? frequency-modulated phase-locked loop jtag ? ieee 1149.1 test controller mmu ? memory management unit mpu ? memory protection unit pmc ? power management controller pit ? periodic interrupt timer rcosc ? low-speed rc oscillator reacm ? reaction module siu ? system integration unit spe ? signal processing extension sram ? static ram stm ? system timer module swt ? software watchdog timer vga ? variable gain amplifier vle ? variable length (instruction) encoding xosc ? xtal oscillator legend emios 24 channel 3 kb data ram 14 kb code ram etpu2 32 temp sens adci dec x2 vga adc adc amux 2 mb flash 128 kb sram mpu crossbar switch interrupt controller edma 64-channel spe vle mmu 8 kb i-cache power architecture e200z4 jtag nexus ieee-isto 5001-2010 flexray calibration bus interface flexcan x 3 i/o bridge fmpll crc bam pmc stm pit swt siu analog pll rcosc xosc voltage regulator standby regulator with switch dspi x 3 esci x 3 m4 m0 m6 s0 s2 s7 s1 m1 reacm 6 ch dts debug channel ecsm
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 7 introduction table 2. MPC5642A series block summary block function boot assist module (bam) block of read-only memo ry containing executable code that searches for user-supplied boot code and, if n one is found, executes the bam boot code resident in device rom calibration bus interface transfers data across the crossbar switch to/from peripherals attached to the calibration system connector controller area network (flexcan) supports the standard can communications protocol crossbar switch (xbar) internal busmaster cyclic redundancy check (crc) crc checksum generator deserial serial peripheral interface (dspi) provides a synchronous serial interface for communication with external devices e200z4 core executes programs and interrupt handlers enhanced direct memory access (edma) performs comple x data movements with minimal intervention from the core. enhanced modular input-output system (emios) provides the functionality to generate or measure events enhanced queued analog-to-digital converter (eqadc) provides accurate and fast conversions for a wide range of applications enhanced serial communication interface (esci) provides asynchronous serial communication capability with peripheral devices and other microcontroller units enhanced time processor unit (etpu2) second-generatio n co-processor processes real-time input events, performs output waveform generation, and accesses shared data without host intervention error correction status module (ecsm) the error correction status module supports a number of miscellaneous control functions for the platform, and includes registers for capturing information on platform memory errors if error-correcting codes (ecc) are implemented flash memory provides storage for program code, constants, and variables flexray provides high-speed distributed control for advanced automotive applications frequency-modulated phase-locked loop (fmpll) generates high-speed system clocks and supports programmable frequency modulation interrupt controller (intc) provides priority-based preemptive scheduling of interrupt requests jtag controller provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode memory protection unit (mpu) provides hardware access control for all memory references generated nexus port controller (npc) provides real-time development support capabilities in compliance with the ieee-isto 5001-2010 standard periodic interrupt timer (pit) produces periodic interrupts and triggers reaction module (reacm) works in conjunction with the eqadc and etpu2 to increase system performance by removing the cpu from the current control loop.
MPC5642A microcontroller data sheet, rev. 3.1 8 freescale semiconductor introduction system integration unit (siu) controls mcu rese t configuration, pad configuration, external interrupt, general purpose i/o (gpio), internal peripheral multiplexing, and the system reset operation. static random-access memory (sram) provides storage for program code, constants, and variables system timers includes periodic interrupt timer with real-time interrupt; output compare timer and system watchdog timer system watchdog timer (swt) provides protection from runaway code temperature sensor provides the temperat ure of the device as an analog value table 2. MPC5642A series block summary (continued) block function
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 9 introduction 1.5 feature details 1.5.1 e200z4 core MPC5642A devices have a high performance e200z4 core processor: ? 32-bit power architecture technology programmer?s model ? variable length encodi ng (vle) enhancements ? dual issue, 32-bit powe r architecture technology compliant cpu ? 8 kb, 2/4-way set associ ative instruction cache ? thirty-two 64-bit general purpose registers (gprs) ? memory management unit (mmu) with 24-entry fully-associative translation look-aside buffer (tlb) ? harvard architecture: separate in struction bus and load/store bus ? vectored interrupt support ? non-maskable interrupt input ? critical interrupt input ? new ?wait for interrupt? instruction, to be used with new low power modes ? reservation instructions for im plementing read-mod ify-write accesses ? signal processing extension (spe) apu ? single precision floating point (scalar and vector) ? nexus class 3+ debug ? process id manipulation for th e mmu using an external tool ? in-order execution and retirement ? precise exception handling ? branch processing unit ? dedicated branch address calculation adder ? branch target prefetching using 8-entry btb ? supports independent instruction and data accesses to diff erent memory subsystems, such as sram and flash memory via independent instruction and data bius ? load/store unit ? 2-cycle load latency ? fully pipelined ? big and little endian support ? misaligned access support ? signal processing extension (spe1.1) apu supporting simd fixed-point opera tions using the 64-bit general purpose register file ? embedded floating-point (efp2) apu supporting scalar and vector simd single-precision floating-point operations, using the 64-bit general purpose register file ? power management ? low power design ? extensive clock gating ? power saving modes: wait ? dynamic power management of execution units, cache and mmu ? testability ? synthesizeable, muxd scan design ? abist/mbist for arrays ? built-in parallel signature unit
MPC5642A microcontroller data sheet, rev. 3.1 10 freescale semiconductor introduction ? calibration support allowing an external tool to modify address mapping 1.5.2 crossbar switch (xbar) the xbar multiport crossbar switch supports simultaneous connections between four master ports and four slave ports. the crossbar supports a 32-bit address bus width and a 64-bit data bus width. the crossbar allows three concur rent transactions to occur from the master ports to any slav e port but each master must access a different slave. if a slave port is simu ltaneously requested by more than one mast er port, arbitration logic selects the high er priority master and grants it ownership of the slave port. all other masters requesti ng that slave port are stalled until the h igher priority master completes its transactions. requesting masters are treated with equal priority and are granted access to a slav e port in round-robin fashion, based upon the id of the last master to be granted acce ss. the crossbar provides the following features: ? 4 master ports ? cpu instruction bus ? cpu data bus ?edma ?flexray ? 4 slave ports ?flash ? calibration bus interface ?sram ? peripheral bridge ? 32-bit internal address, 64-bit internal data paths 1.5.3 enhanced direct memory access (edma) the enhanced direct memory access (edma) controller is a s econd-generation modul e capable of performing complex data movements via 64 programmable channels, with minimal intervention from the host processor. the hardware micro-architecture includes a dma engine which performs source and destination ad dress calculations, and the actual data movement operations, along with an sram -based memory containing th e transfer control descript ors (tcd) for the channels. this implementation minimizes overall block size. th e edma module provides the following features: ? all data movement via dual-address transfer s: read from source, write to destination ? programmable source and destination a ddresses, transfer size, plus sup port for enhanced addressing modes ? transfer control descriptor organized to s upport two-deep, nested transfer operations ? an inner data transfer loop defined by a ?minor? byte transfer count ? an outer data transfer loop defined by a ?major? iteration count ? channel activation via one of three methods: ? explicit software initiation ? initiation via a channel-to-channel link ing mechanism for co ntinuous transfers ? peripheral-paced hardware requests (one per channel) ? support for fixed-priority and round-robin channel arbitration ? channel completion reported via optional interrupt requests ? 1 interrupt per channel, optionally asserted at completion of major iteration count ? error termination interrupts optionally enabled ? support for scatter/gather dma processing ? ability to suspend channel transfers by a higher priority channel
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 11 introduction 1.5.4 interrupt controller (intc) the intc provides priority-based preemptive scheduling of interrupt requests, suitable for stati cally scheduled hard real-time systems. for high priority interrupt requests, the time from the assertion of the interrupt request from th e peripheral to when the proc essor is executing the interrupt serv ice routine (isr) has been minimized. the intc provides a unique vector for each interrupt request source for quick determination of which isr needs to be ex ecuted. it also provides an ample number of priorities so tha t lower priority isrs do not dela y the execution of higher priority isrs. to allow the approp riate priorities for each source of interrupt request, the priority of each in terrupt request is software configurable. when multiple tasks share a resour ce, coherent accesses to that resource need to be supported. the intc supports the priority ceiling protocol for coherent accesses. by pr oviding a modifiable priority mask, the pr iority can be raised temporarily so that all tasks which share the resource cannot preempt each other. the intc provides the following features: ? 9-bit vector addresses ? unique vector for each interrupt request source ? hardware connection to proce ssor or read from register ? each interrupt source can assigned a specific priority by software ? preemptive prioritized inte rrupt requests to processor ? isr at a higher priority preempts execu ting isrs or tasks at lower priorities ? automatic pushing or popping of preempted priority to or from a lifo ? ability to modify the isr or task priority to implement the priority ceiling protocol for accessing shared resources ? low latency?3 clocks from receipt of interrupt request from periph eral to interrupt request to processor this device also includes a non-maskable interrupt (nmi) pin that bypasses the intc and multiplexing logic. 1.5.5 memory protection unit (mpu) the memory protection unit (mpu) provides hardware access cont rol for all memory references generated in a device. using preprogrammed region descriptor s, which define memory spaces and their a ssociated access rights, the mpu concurrently monitors all system bus transactions and evaluates the appropriateness of each transf er. memory references with sufficient access control rights are allowed to complete; references that are not mapped to an y region descriptor or have insufficient rig hts are terminated with a pr otection error response. the mpu has these major features: ? support for 16 memory region descriptors, each 128 bits in size ? specification of start and end addresses provide gr anularity for region sizes from 32 bytes to 4 gb ? mpu is invalid at reset, thus no access restrictions are enforced ? 2 types of access control definitions: processor core bus master supports the traditional {read, write, execute} permissions with independent definitions for supervis or and user mode accesses; the remaining non-core bus masters (edma, flexray) su pport {read, write} attributes ? automatic hardware maintenance of the region descriptor valid bit removes issues associated with maintaining a coherent image of the descriptor ? alternate memory view of the access control word for each descriptor provides an efficient mechanism to dynamically alter the access ri ghts of a descriptor only ? for overlapping region descriptors, prio rity is given to permission granti ng over access denying as this approach provides more flexibility to system software ? support for two xbar slave port connections (sram and pbridge) ? for each connected xbar slave por t (sram and pbridge), mpu hardware monitors every port access using the preprogrammed memory region descriptors
MPC5642A microcontroller data sheet, rev. 3.1 12 freescale semiconductor introduction ? an access protection error is detected if a memory reference does not hit in any memory region or the reference is flagged as illegal in all memory re gions where it does hit. in the event of an access error, the xbar reference is terminated with an error response and the mpu inhib its the bus cycle being sent to the targeted slave device ? 64-bit error registers, one for each xb ar slave port, capture the last faul ting address, attributes, and detail information 1.5.6 frequency-modulated phase-locked loop (fmpll) the fmpll allows the user to generate hi gh speed system clocks from a 4 mhz to 40 mhz crystal oscillator or external clock generator. further, the fmpll supports programmable frequenc y modulation of the system clock. the pll multiplication factor, output clock divider ratio are all software c onfigurable. the pll has the following major features: ? input clock frequency from 4 mhz to 40 mhz ? reduced frequency divider (rfd) for reduced frequency operation without forcing the pll to relock ? 3 modes of operation ? bypass mode with pll off ? bypass mode with pll running (default mode out of reset) ? pll normal mode ? each of the 3 modes may be run with a crysta l oscillator or an external clock reference ? programmable frequency modulation ? modulation enabled/disabled through software ? triangle wave modulation up to 100 khz modulation frequency ? programmable modulation depth (0% to 2% modulation depth) ? programmable modulation frequency dependent on reference frequency ? lock detect circuitry reports when the pll has achieved fr equency lock and continuously monitors lock status to report loss of lock conditions ? clock quality module ? detects the quality of the crystal clock and causes interrupt request or system reset if error is detected ? detects the quality of the pl l output clock; if error detected, causes system reset or switches system clock to crystal clock and causes interrupt request ? programmable interrupt request or system reset on loss of lock ? self-clocked mode (scm) operation 1.5.7 system integration unit (siu) the MPC5642A siu controls mcu reset configuration, pad configuration, external interrupt, general purpose i/o (gpio), internal peripheral multiplexing , and the system reset operation. the reset conf iguration block contains the external pin boot configuration logic. the pad configuration block controls the static electrical characteristics of i/o pins. the gpio block provides uniform and discrete input/output control of the i/o pins of the mcu. the reset controller performs reset monitoring of internal and external rese t sources, and drives the rstout pin. communication between th e siu and the e200z4 cpu core is via the crossbar switch. the siu provides the following features: ? system configuration ? mcu reset configuration via external pins ? pad configuration control for each pad ? pad configuration control for virtual i/o via dspi serialization ? system reset monitoring and generation ? power-on reset support ? reset status register provides last reset source to software
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 13 introduction ? glitch detection on reset input ? software controlled reset assertion ? external interrupt ? rising or falling edge event detection ? programmable digital filter for glitch rejection ? critical interrupt request ? non-maskable interrupt request ?gpio ? centralized control of i/o and bus pins ? virtual gpio via dspi serialization (r equires external deserialization device) ? dedicated input and output registers fo r setting each gpio and virtual gpio pin ? internal multiplexing ? allows serial and parallel chaining of dspis ? allows flexible selection of eqadc trigger inputs ? allows selection of interrupt requests between external pins and dspi ? from a set of etpu output channels, allows selectio n of source signals for decimation filter integrators 1.5.8 flash memory the MPC5642A provides 2 mb of programma ble, non-volatile, flash memory. the non-volatile memory (nvm) can be used to store instructions or data, or both. the flash module includes a fetch accelerator that opt imizes the performance of the fla sh array to match the cpu architecture. the flash module interfaces the system bus to a dedicated flash memory array controller. for cpu ?loads?, dma transfers and cpu instruction fetch, it supports a 64-bit data bus width at the system bus port, and 128-bit read data interfaces to flash memo ry. the module contains a prefetch contro ller which prefetches sequential lines of data from the flash array into the buffers. prefetch buffer hits allow no-wait responses. the flash memory provides the following features: ? supports a 64-bit data bus for instruction fetch, cpu loads and dma access. byte, halfword, word and doubleword reads are supported. only aligned word and doubleword writes are supported. ? fetch accelerator ? architected to optimize th e performance of the flash ? configurable read buffering and line prefetch support ? 4-entry 128-bit wide line read buffer ? prefetch controller ? hardware and software configur able read and write access prot ections on a per-master basis ? interface to the flash array controller pi pelined with a depth of one, allowing ov erlapped accesses to proceed in parallel for pipelined flash array designs ? configurable access timing usable in a wide range of system frequencies ? multiple-mapping support and mapping- based block access timing (0 ?31 additional cycles) us able for emulation of other memory types ? software programmable block progr am/erase restriction control ? erase of selected block(s) ? read page size of 128 bits (4 words) ? ecc with single-bit correction, double-bit detection ? program page size of 128 bits (4 words) to accelerate programming ? ecc single-bit error correcti ons are visible to software ? minimum program size is 2 consecutive 32-bit words, aligned on a 0-modulo-8 byte address, due to ecc
MPC5642A microcontroller data sheet, rev. 3.1 14 freescale semiconductor introduction ? embedded hardware program and erase algorithm ? erase suspend, program suspe nd and erase-suspended program ? shadow information stored in non-volatile shadow block ? independent program/erase of the shadow block 1.5.9 static random access memory (sram) the sram provides 128 kb of general purpose system sram. th e first 32 kb block of the sram is powered by its own power supply pin only during standby operation. the sram controller includes these features: ? 128 kb data ram implemented as eight 16 kb (2048 ? 78 bits) blocks ? each 16 kb block has 2 rows repairable (rams with internal repair feature) ? supports read/write accesses mapped to the sram memory from any master ? 32 kb block powered by separate supply for standby operation ? byte, halfword, word and doubleword addressable ? ecc performs single bit correction, double bit detection 1.5.10 boot assist module (bam) the bam is a block of read-only memory that is programm ed once by freescale and is id entical for all MPC5642A mcus. the bam program is executed every time the mcu is powered on or reset in normal mode. the bam supports different modes of booting. they are: ? booting from internal flash memory ? serial boot loading (boot code is downloaded into ram via esci or the fl excan and then executed) the bam also reads the reset configuratio n half word (rchw) from internal flash memory and configures the MPC5642A hardware accordingly. the bam pr ovides the following features: ? sets up mmu to cover all resources and mapping of all phy sical addresses to logical a ddresses with minimum address translation ? sets up mmu to allow user boot code to execute as either power architecture t echnology code (default) or as freescale vle code ? location and detection of user boot code ? automatic switch to serial boot mode if internal flash is blank or invalid ? supports user programmable 64-bit password protection for serial boot mode ? supports serial bootloading via flexcan bus and esci using freescale protocol ? supports serial bootloading via flexcan bus and esci with auto baud rate sensing ? supports serial bootloading of either power archit ecture technology code (def ault) or freescale vle code ? supports booting from calibration bus interface ? supports censorship protection for internal flash memory ? provides an option to enable the core watchdog timer ? provides an option to disable the system watchdog timer 1.5.11 enhanced modular inpu t/output system (emios) the emios timer module provides the capability to generate or measure events in hardware. the emios module features include: ? twenty-four 24-bit wide channels
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 15 introduction ? 3 channels? internal timebases sharable between channels ? 1 timebase from etpu2 can be im ported and used by the channels ? global enable feature for all emios and etpu timebases ? dedicated pin for each channel (n ot available on all package types) ? each channel (0?23) supports the following functions: ? general purpose input/output (gpio) ? single action input capture (saic) ? single action outp ut compare (saoc) ? output pulse width modulation buffered (opwmb) ? input period measurement (ipm) ? input pulse width measurement (ipwm) ? double action output compare (doac) ? modulus counter buffered (mcb) ? output pulse width & frequency modulation buffered (opwfmb) ? each channel has its own pin (not available on all package types) 1.5.12 second generation enhanced time processing unit (etpu2) the etpu2 is an enhanced co-processor de signed for timing control. operating in parallel with the host cpu, the etpu2 processes instructions and real-t ime input events, performs output waveform ge neration, and accesses shar ed data without host intervention. conseque ntly, for each timer event, the host cpu setup and service times are mi nimized or eliminated. a powerful timer subsystem is formed by combining the etpu2 with its ow n instruction and data ram. hi gh-level assembler/compiler and documentation allows customers to de velop their own functions on the etpu2. MPC5642A devices feature the second generation of the etpu, cal led etpu2. enhancements of the etpu2 over the standard etpu include: ? the timer counter (tcr1), channel logic and digital filters (both channel and the external timer clock input [tcrclk]) now have an option to run at full system clock speed or system clock / 2. ? channels support unordered transitions: transition 2 can now be detected befo re transition 1. related to this enhancement, the transition detectio n latches (tdl1 and tdl2) can now be independently negated by microcode. ? a new user programmable channel mode has been added: the blocking, enabling, service request and capture characteristics of this channel mode can be programmed via microcode. ? microinstructions now provide an option to issue interrupt and data transfer requests se lected by channel. they can also be requested simultaneously at the same instruction. ? channel flags 0 and 1 can now be tested for bran ching, in addition to selecting the entry point. ? channel digital filters can be bypassed. the etpu2 includes these distinctive features: ? 32 channels; each channel associated with one input and one output signal ? enhanced input digital filters on the input pins for improved noise immunity ? identical, orthogonal channels: each channel can perform an y time function. each time function can be assigned to more than one channel at a given time, so each signal can have any functionality. ? each channel has an event mechanism which supports single and double action functionality in various combinations. it includes two 24-bi t capture registers, two 24-bit matc h registers, 24-bit greater-equal and equal-only comparators. ? input and output signal states visible from the host ? 2 independent 24-bit time bases for channel synchronization: ? first time base clocked by system clock with programmable prescale division from 2 to 512 (in steps of 2), or by output of second time base prescaler
MPC5642A microcontroller data sheet, rev. 3.1 16 freescale semiconductor introduction ? second time base counter can work as a continuous angle counter, enabling angle based applications to match angle instead of time ? both time bases can be exported to the emios timer module ? both time bases visible from the host ? event-triggered microengine: ? fixed-length instruction execution in two-system-clock microcycle ? 14 kb of code memory (scm) ? 3 kb of parameter (data) ram (spram) ? parallel execution of data memory, alu, channel control and flow control sub-instructions in selected combinations ? 32-bit microengine registers and 24-bit wide alu, with 1 microcycle addition and subt raction, absolute value, bitwise logical operations on 24-bit, 16-bit, or byte op erands, single-bit manipulation, shift operations, sign extension and conditional execution ? additional 24-bit multiply/mac/divide unit which supports all signed/unsigned multiply/mac combinations, and unsigned 24-bit divide. the mac/divide unit works in parallel with the regular microcode commands. ? resource sharing features support ch annel use of common channel register s, memory and microengine time: ? hardware scheduler works as a ?task management? unit, dispatching event service routines by predefined, host-configured priority ? automatic channel context switch when a ?task switch? occurs, that is, one function thread ends and another begins to service a request from othe r channel: channel-specific registers, flags and parameter base address are automatically loaded for th e next serviced channel ? spram shared between host cpu and etpu2, supporting communication either between channels and host or inter-channel ? hardware implementation of 4 semaphores support cohe rent parameter sharing between both etpu engines ? dual-parameter coherency hardware support a llows atomic access to 2 parameters by host ? test and development support features: ? nexus class 1 debug, supporting single-step executi on, arbitrary microinstruction execution, hardware breakpoints and watchpoints on several conditions ? software breakpoints ? scm continuous signature-check built-in self test misc (multiple input signature calculator), runs concurrently with etpu2 normal operation 1.5.13 reaction module (reacm) the reacm provides the ability to modulate output signals to manage closed loop control without cpu assistance. it works in conjunction with the eqadc and etpu2 to increase system pe rformance by removing the cpu from the current control loop. the reacm has the following features: ? 6 reaction channels with peak and hold control blocks ? each channel output is a bus of 3 signals, providing ability to control 3 inputs. ? each channel can implement a peak and hold waveform, making it possible to implement up to six independent peak and hold control channels target applications include solenoid control for direct injection systems and valve control in automatic transmissions.
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 17 introduction 1.5.14 enhanced queued analog -to-digital con verter (eqadc) the eqadc block provides accurate and fast conversions for a wide range of appl ications. the eqadc provides a parallel interface to two on-chip an alog-to-digital converters (adc), a nd a single master to single slav e serial interface to an off-chi p external device. both on-chip adcs ha ve access to all the analog channels. the eqadc prioritizes and transf ers commands from six command conversion comm and ?queues? to the on-chip adcs or to the external device. the block can also r eceive data from the on-chip adcs or from an off-chip external device into the six result queues, in parallel, independently of the command queue s. the six command queues are prio ritized with queue_0 having the highest priority and queue_5 the lowest . queue_0 also has the added ability to bypass all buffering and queuing and abort a currently running conversion on either ad c and start a queue_0 conver sion. this means that queu e_0 will always have a deterministic time from trigger to start of conversion, irresp ective of what tasks the adcs were performing when the trigger occurred. the eqadc supports software and external hardware tr iggers from other blocks to initiate transfers of commands from the queues to the on-chip adcs or to the external device. it also monitors the fullness of command queues and result queues, and accordingly generates dma or interrupt requests to control data movement between the queues and the system memory, which is external to the eqadc. the adcs also support features designed to allow the direct connection of high imp edance acoustic sensors that might be used in a system for detecting engine knock. th ese features include differen tial inputs; integrated variable gain amplifiers for increasing the dynamic range; programmable pull-up and pul l-down resistors for biasing and sensor diagnostics. the eqadc also integrates a programmable decimation filter capable of taking in adc conversion results at a high rate, passing them through a hardware low pass filter, then down-samplin g the output of the filter and feeding the lower sample rate results to the result fifos. this allows the adcs to sample th e sensor at a rate high enough to avoid aliasing of out-of-band noise; while providing a reduced sample rate output to minimize the amount dsp processing bandwidth required to fully process the digitized waveform. the eqadc provides the following features: ? dual on-chip adcs ?2 ? 12-bit adc resolution ? programmable resolution for increased conversion speed (12-bit, 10-bit, 8-bit) ? 12-bit conversion time ? 938 ns (1m sample/s) ? 10-bit conversion time ? 813 ns (1.2m sample/s) ? 8-bit conversion time ? 688 ns (1.4m sample/s) ? up to 10-bit accuracy at 500k sample/s and 8-bit accuracy at 1m sample/s ? differential conversions ? single-ended signal range from 0 to 5 v ? sample times of 2 (d efault), 8, 64, or 128 adc clock cycles ? provides time stamp info rmation when requested ? allows time stamp information relative to et pu clock sources, such as an angle clock ? parallel interface to eqadc command fi fos (cfifos) and re sult fifos (rfifos) ? supports both right-justified unsigned and signed formats for conversion results ? 40 single-ended input channels, expandable to 56 channels with external multiplexers (supports 4 external 8-to-1 muxes) ? 8 channels can be used as 4 pairs of differential analog input channels ? differential channels include variable gain amplifier for improved dynamic range ( ? 1, ? 2, ? 4) ? differential channels include programmable pull-up and pull-down resistors for biasing and sensor diagnostics (200 k ??? 100 k ??? 5k ?? ? additional internal channels for monitoring voltages (such as core voltage, i/o voltage, lvi voltages, etc.) inside the device ? an internal bandgap reference to allow absolute voltage measurements ? silicon die temperature sensor
MPC5642A microcontroller data sheet, rev. 3.1 18 freescale semiconductor introduction ? provides temperature of silicon as an analog value ? read using an internal adc analog channel ? may be read with either adc ? 2 decimation filters ? programmable decimation factor (1 to 16) ? selectable iir or fir filter ? up to 4th order iir or 8th order fir ? programmable coefficients ? saturated or non-saturated modes ? programmable rounding (convergent; two?s complement; truncated) ? prefill mode to precondition the filter before the sample window opens ? supports multiple cascading decimation filters to implement more complex filter designs ? optional absolute integrators on the output of decimation filters ? full duplex synchronous serial in terface (ssi) to an external device ? free-running clock for us e by an external device ? supports a 26-bit message length ? priority based queues ? supports 6 queues with fixed priority. when commands of distinct queues are bound for the same adc, the higher priority queue is always served first ? queue_0 can bypass all prioritization, buffering and abor t current conversions to st art a queue_0 conversion a deterministic time after the queue trigger ? supports software and hardware trigger modes to arm a particular queue ? generates interrupt when comm and coherency is not achieved ? external hardware triggers ? supports rising edge, falling edge, high level and low level triggers ? supports configurable digital filter 1.5.15 deserial serial pe ripheral interface (dspi) the dspi block provides a synchronous serial interface for communication betw een the MPC5642A mcu and external devices. the dspi supports pin count reduction through seria lization and deserialization of etpu and emios channels and memory-mapped registers. the channels and register content are transmitted using a sp i-like protocol. this spi-like protocol is completely configurable for baud rate, po larity and phase, frame length, chip select assertion, et c. each bit in the frame m ay be configured to serialize either etpu channels, emios channels or gpio signals. the ds pi can be configured to serialize data to an external device that implements the microsecond bus protocol. there are thre e identical dspi blocks on the MPC5642A mcu. the dspi pins support 5 v logic levels or low voltage differential signalling (lvds) to improve high speed operation. dspi module features include: ? selectable lvds pads working at 40 mhz for sout and sck pins for dspi_b and dspi_c ? support for downstream micro second channel (msc) with timed serial bus (tsb) configuration on dspi_b and dspi_c ? 3 sources of serialized data: etpu_a, emios output channels, and memory-map ped register in the dspi ? 4 destinations for deserialized data: etpu_a and emio s input channels, siu external interrupt input request, memory-mapped register in the dspi ? 32-bit dsi and tsb modes require 32 pcr registers, 32 gpo an d gpi registers in the siu to select either gpio, etpu or emios bits for serialization ? the dspi module can generate an d check parity in a serial frame
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 19 introduction 1.5.16 enhanced serial commun ications interface (esci) three esci modules provide asynchronous serial communicatio ns with peripheral devices and other mcus, and include support to interface to local interconnect network (lin) slave devices. each esci block provides the following features: ? full-duplex operation ? standard mark/space non-ret urn-to-zero (n rz) format ? 13-bit baud rate selection ? programmable 8-bit or 9-bit data format ? programmable 12-bit or 13-bit data format for timed seri al bus (tsb) configuration to support the microsecond bus standard ? automatic parity generation ? lin support ? compatible with lin slaves from revisions 1.x and 2.0 of the lin standard ? autonomous transmission of entire frames ? configurable to support all revisions of the lin standard ? automatic parity bit generation ? double stop bit after bit error ? 10- or 13-bit break support ? separately enabled tr ansmitter and receiver ? programmable transmitter output parity ? 2 receiver wake-up methods: ? idle line wake-up ? address mark wake-up ? interrupt-driven operation with flags ? receiver framing error detection ? hardware parity checking ? 1/16 bit-time noise detection ? dma support for both transmit and receive data ? global error bit stored with r eceive data in system ram to al low post processing of errors 1.5.17 controller area network (flexcan) the MPC5642A mcu includes three flexcan blocks. the flexcan module is a communication controller implementing the can protocol according to bosch specification vers ion 2.0b. the can protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requi rements of this field: real-time processing, reliable operation in the emi environme nt of a vehicle, cost-effectiveness an d required bandwidth. each flexcan module contains 64 message buffers. the flexcan modules provide the following features: ? based on and including all existing feat ures of the freescale toucan module ? full implementation of the can protocol specification, version 2.0b ? standard data and remote frames ? extended data and remote frames ? zero to eight bytes data length ? programmable bit rate up to 1 mbit/s ? content-related addressing ? 64 message buffers of 0 to 8 bytes data length ? individual rx mask register per message buffer
MPC5642A microcontroller data sheet, rev. 3.1 20 freescale semiconductor introduction ? each message buffer configurable as rx or tx , all supporting standard and extended messages ? includes 1088 bytes of embedded memory for message buffer storage ? includes 256-byte memory for storing individual rx mask registers ? full-featured rx fifo with storage capacity for 6 frames and internal pointer handling ? powerful rx fifo id filterin g, capable of matching incoming ids against 8 extended, 16 standard or 32 partial (8 bits) ids, with individual masking capability ? selectable backwards compatibility with previous flexcan versions ? programmable clock source to the can protocol interface, either system clock or oscillator clock ? listen only mode capability ? programmable loop-back mode supporting self-test operation ? 3 programmable mask registers ? programmable transmit-first scheme: lowest id , lowest buffer number or highest priority ? time stamp based on 16-bit free-running timer ? global network time, synchronized by a specific message ? maskable interrupts ? warning interrupts when the rx and tx error counters reach 96 ? independent of the transmission medium (an external transceiver is assumed) ? multi-master concept ? high immunity to emi ? short latency time due to an arbitr ation scheme for high-priority messages ? low power mode, with programmable wakeup on bus activity 1.5.18 flexray the MPC5642A includes one dual-channel flexray module that implements the flexray communications system protocol specification, version 2.1 rev a. features include: ? single channel support ? flexray bus data rates of 10 mbit/s, 8 mbit/s, 5 mbit/s, and 2.5 mbit/s supported ? 128 message buffers, each configurable as: ? receive message buffer ? single-buffered transmit message buffer ? double-buffered transmit message buffer (combines two single-buffered message buffers) ? 2 independent receive fifos ? 1 receive fifo per channel ? up to 255 entries for each fifo ? ecc support 1.5.19 system timers the system timers include two distinct types of system timer: ? periodic interrupts/triggers using the periodic interrupt timer (pit) ? operating system task monitors using the system timer module (stm) 1.5.19.1 periodic interrupt timer (pit) the pit provides five independent timer channels, capable of producing periodic interrupts and periodic triggers. the pit has no external input or output pins and is intended to provide syst em ?tick? signals to the operating system, as well as periodic
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 21 introduction triggers for eqadc queues. of the five ch annels in the pit, four are clocked by th e system clock and one is clocked by the crystal clock. this one channel is also referred to as real-tim e interrupt (rti) and is used to wake up the device from low pow er stop mode. the following features ar e implemented in the pit: ? 5 independent timer channels ? each channel includes 32-bit wide down counter with automatic reload ? 4 channels clocked from system clock ? 1 channel clocked from cr ystal clock (wake-up timer) ? wake-up timer remains active when system stop mode is entered; used to restart system cl ock after predefined time-out period ? each channel optionally able to generate an interrupt requ est or a trigger event (to trigger eqadc queues) when timer reaches zero 1.5.19.2 system timer module (stm) the stm is designed to implement the software task monitor as defined by autosar 1 . it consists of a single 32-bit counter, clocked by the system clock, and four independent timer comp arators. these comparators prod uce a cpu interrupt when the timer exceeds the programmed value. the following features ar e implemented in the stm: ? one 32-bit up counter with 8-bit prescaler ? four 32-bit compare channels ? independent interrupt source for each channel ? counter can be stopped in debug mode 1.5.20 software watchdog timer (swt) the swt is a second watchdog module to complement the standard power architecture watchdog integrated in the cpu core. the swt is a 32-bit modulus counter, clocked by the system cloc k or the crystal clock, that can provide a system reset or interrupt request when the correct software key is not written within the required time window. the following featur es are implemented: ? 32-bit modulus counter ? clocked by system clock or crystal clock ? optional programmable watchdog window mode ? can optionally cause system reset or interrupt request on timeout ? reset by writing a software key to memory mapped register ? enabled out of reset ? configuration is protected by a software key or a write-once register 1.5.21 cyclic redundancy check (crc) module the crc computing unit is dedicated to the computatio n of crc off-loading the cp u. the crc module features: ? support for crc-16-ccitt ( x 25 protocol): ? x 16 + x 12 + x 5 + 1 ? support for crc-32 (e thernet protocol): ? x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 1. autosar: automotive open system architecture (see http://www.autosar.org)
MPC5642A microcontroller data sheet, rev. 3.1 22 freescale semiconductor introduction ? zero wait states for each write/read operations to th e crc_cfg and crc_inp register s at the maximum frequency 1.5.22 error correction status module (ecsm) the ecsm provides a myriad of miscellaneous control functions regarding program-visible information about the platform configuration and revision levels, a reset status register, a so ftware watchdog timer, wakeup control for exiting sleep modes, and information on platform me mory errors reported by error-correcting code s and/or generic access error information for certain processor cores. the error correction status module supports a number of miscellaneous control functio ns for the platform. the ecsm includes these features: ? registers for capturing information on platform memory errors if error-correcting codes (ecc) are implemented ? for test purposes, optional registers to specify the ge neration of double-bit memory errors are enabled on the MPC5642A. the sources of the ecc errors are: ? flash memory ?sram ? peripheral ram (flexray, can, etpu2 parameter ram) 1.5.23 peripheral bridge (pbridge) the pbridge implements the following features: ? duplicated periphery ? master access privilege level per peripheral (per master: read access enable; write access enable) ? write buffering for peripherals ? checker applied on pbridge output toward periphery ? byte endianess swap capability 1.5.24 calibration bus interface the calibration bus interface controls data tr ansfer across the crossbar sw itch to/from memories or peripherals attached to the vertical connector in the calibration addr ess space. the calibration bus interface is only available in the vertical calibratio n system. features include: ? 3.3 v 10% i/o (3.0 v to 3.6 v) ? memory controller supports various memory types ? 16-bit data bus, up to 22-bit address bus ? pin muxing supports 32-bit muxed bus ? selectable drive strength ? configurable bus speed modes ? bus monitor ? configurable wait states 1.5.25 power management controller (pmc) the pmc contains circuitry to generate the internal 3.3 v supply and to control the regulation of 1.2 v supply with an external npn ballast transistor. it also contains low voltage inhibit (l vi) and power-on reset (por) circuits for the 1.2 v supply, the 3.3 v supply, the 3.3 v/5 v supply of the closest i/o segm ent (vddeh1), and the 5 v supply of the regulators (vddreg).
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 23 pinout and signal description 1.5.26 nexus port controller (npc) the npc block provides real-time nexus class3+ development support capabilities for the MPC5642A power architecture technology-based mcu in compliance with the ieee-isto 5001-2 010 standard. mdo port widths of 4 pins and 12 pins are available in all packages. 1.5.27 jtag controller (jtagc) the jtag controller (jtagc) block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in te st mode. testing is performed vi a a boundary scan technique, as defined in the ieee 1149.1-2001 standard. all data input to and output from the jtagc block is communicated in serial format. the jtagc block is compliant with the ieee 1149.1-2001 standard an d supports the following features: ? ieee 1149.1-2001 test access port (tap) in terface 4 pins (tdi, tms, tck, and tdo) ? a 5-bit instruction register th at supports the following ieee 1149.1-2001 define d instructions: ? bypass, idcode, extest, sample, sample/preload, highz, clamp ? a 5-bit instruction register that supports the additional following public instructions: ? access_aux_tap_npc ? access_aux_tap_once ? access_aux_tap_etpu ? access_censor ? 3 test data registers to support jtag boundary scan mode ? bypass register ? boundary scan register ? device identification register ? a tap controller state machine that cont rols the operation of the data register s, instruction register and associated circuitry ? censorship inhibit register ? 64-bit censorship password register ? if the external tool writes a 64-bit password that matches the serial boot password stored in the internal flash shadow row, censorship is disabled until the next system reset. 1.5.28 development trigger semaphore (dts) MPC5642A devices include a system development feature, the development trigger semaphore (dts) module, that enables user software to signal to an external tool?by driving a persis tent (affected only by reset or an external tool) signal on an external device pin?that data is available. the dts includes a register of semaphores (32-bits) and an identification register. there are a variety of ways this module can be used, including as a component of an external real-time data acquisition system. 2 pinout and signal description this section contains the pinouts for all production packages for the MPC5642A device. for pin signal descriptions, please refe r to table 3 note any pins labeled ?nc? are to be left unconnect ed. any connection to an external circuit or voltage may cause unpredictable device behavior or damage.
MPC5642A microcontroller data sheet, rev. 3.1 24 freescale semiconductor pinout and signal description 2.1 176 lqfp pinout figure 2. 176-pin lqfp pinout (top view) 176-pin lqfp vdd an[37] an[36] an[21] an[0] (dan0+) an[1] (dan0-) an[2] (dan1+) an[3] (dan1-) an[4] (dan2+) an[5] (dan2-) an[6] (dan3+) an[7] (dan3-) refbypc vrh vrl an[22] an[23] an[24] an[25] an[27] an[28] an[30] an[31] an[32] an[33] an[34] an[35] vdd an[12] / ma[0] / etpua19_o / sds an[13] / ma[1] / etpua21_o / sdo an[14] / ma[2] / etpua27_o / sdi an[15] / fck / etpua29_o gpio[207] / etrig1 gpio[206] / etrig0 dspi_a_pcs[3] / dspi_d_sin / gpio[99] dspi_a_pcs[2] / dspi_d_sck / gpio[98] vss mdo9 / etpua25_o / gpio[80] vddeh7b mdo8 / etpua21_o / gpio[79] mdo7 / etpua19_o / gpio[78] mdo6 / etpua13_o / gpio[77] mdo10 / etpua27_o / gpio[81] vss vdd etpua13 / dspi_b_pcs[3] / gpio[127] etpua12 / dspi_b_pcs[1] / rch4_c / gpio[126] etpua11 / etpua23_o / rch4_b / gpio[125] etpua10 / etpua22_o / rch1_c / gpio[124] etpua9 / etpua21_o / rch1_b / gpio[123] etpua8 / etpua20_o / dspi_b_sout_lvds+ / gpio[122] etpua7 / etpua19_o / dspi_b_sout_lvds- / etpua6_o / gpio[121] etpua6 / etpua18_o / dspi_b_sck_lvds+ / fr_b_rx / gpio[120] etpua5 / etpua17_o / dspi_b_sck_lvds- / fr_b_tx_en / gpio[119] vddeh4a etpua4 / etpua16_o / fr_b_tx / gpio[118] vss etpua3 / etpua15_o / gpio[117] etpua2 / etpua14_o / gpio[116] etpua1 / etpua13_o / gpio[115] etpua0 / etpua12_o / etpua19_o / gpio[114] vdd emios0 / etpua0 / etpua25_o / gpio[179] emios1 / etpua1_o / gpio[180] emios2 / etpua2_o / rch2_b / gpio[181] emios3 / etpua3_o / gpio[182] emios4 / etpua4_o / rch2_c / gpio[183] emios6 / etpua6_o / gpio[185] emios7 / etpua7_o / gpio[186] emios8 / etpua8_o / sci_b_tx / gpio[187] emios9 / etpua9_o / sci_b_rx / gpio[188] vss emios10 / dspi_b_pcs[3] / rch3_b / gpio[189] vddeh4b emios11 / dspi_d_pcs[4] / rch3_c / gpio[190] emios12 / dspi_c_sout / etpua27_o / gpio[191] emios13 / dspi_d_sout / gpio[192] emios14 / irq [0] / etpua29_o / gpio[193] emios15 / irq [1] / gpio[194] emios23 / etpub7_o / gpio[202] can_a_tx / sci_a_tx / gpio[83] can_a_rx / sci_a_rx / gpio[84] pllref / irq [4] / etrig[2] / gpio[208] sci_b_rx / dspi_d_pcs[5] / gpio[92] bootcfg1 / irq [3] / etrig[3] / gpio[212] wkpcfg / nmi / dspi_b_sout / gpio[213] sci_b_tx / dspi_d_pcs[1] / gpio[91] can_b_tx / dspi_c_pcs[3] / sci_c_tx / gpio[85] vdd tms tdi mdo5 / etpua4_o / gpio[76] tck vss mdo4 / etpua2_o / gpio[75] vddeh7a mdo11 / etpua29_o / gpio[82] tdo gpio[219] jcomp evto nc mseo [0] mseo[1] evti vss dspi_b_pcs[3] / dspi_c_sin / gpio[108] dspi_b_sout / dspi_c_pcs[5] / gpio[104] dspi_b_sin / dspi_c_pcs[2] / gpio[103] dspi_b_pcs[0] / dspi_d_pcs[2] / gpio[105] vddeh6b dspi_b_pcs[1] / dspi_d_pcs[0] / gpio[106] vss dspi_b_pcs[2] / dspi_c_sout / gpio[107] dspi_b_sck / dspi_c_pcs[1] / gpio[102] dspi_b_pcs[4] / dspi_c_sck / gpio[109] dspi_b_pcs[5] / dspi_c_pcs[0] / gpio[110] vddf rstout can_c_tx / dspi_d_pcs[3] / gpio[87] sci_a_tx / emios13 / gpio[89] sci_a_rx / emios15 / gpio[90] can_c_rx / dspi_d_pcs[4] / gpio[88] reset vss vddeh6a vss xtal extal vddpll vss can_b_rx / dspi_c_pcs[4] / sci_c_rx / gpio[86] an[18] an[17] an[16] an[11] / anz an[9] / anx vdda vssa an[39] an[8] / anw vddreg vrcctl vstby vrc33 mcko vss nc mdo[0] mdo[1] mdo[2] mdo[3] (see signal details, pin 21) (see signal details, pin 22) (see signal details, pin 23) (see signal details, pin 24) (see signal details, pin 25) (see signal details, pin 26) (see signal details, pin 27) (see signal details, pin 28) vss (see signal details, pin 30) vddeh1a (see signal details, pin 32) vdd (see signal details, pin 34) (see signal details, pin 35) (see signal details, pin 36) (see signal details, pin 37) (see signal details, pin 38) (see signal details, pin 39) (see signal details, pin 40) vddeh1b (see signal details, pin 42) vss nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 signal details: pin 21: etpua31 / dspi_c_pcs[4] / etpua13_o / gpio[145] pin 22: etpua30 / dspi_c_pcs[3] / etpua11_o / gpio[144] pin 23: etpua29 / dspi_c_pcs[2] / rch5_c / gpio[143] pin 24: etpua28 / dspi_c_pcs[1] / rch5_b / gpio[142] pin 25: etpua27 / irq [15] / dspi_c_sout_lvds+ / dspi_b_sout / gpio[141] pin 26: etpua26 / irq [14] / dspi_c_sout_lvds- / gpio[140] pin 27: etpua25 / irq [13] / dspi_c_sck_lvds+ / gpio[139] pin 28: etpua24 / irq [12] / dspi_c_sck_lvds- / gpio[138] pin 30: etpua23 / irq [11] / etpua21_o / fr_a_tx_en / gpio[137] pin 32: etpua22 / irq [10] / etpua17_o / gpio[136] pin 34: etpua21 / irq[9] / rch0_c / fr_a_rx / gpio[135] pin 35: etpua20 / irq[8] / rch0_b / fr_a_tx / gpio[134] pin 36: etpua19 / dspi_d_pcs[4] / rch5_a / gpio[133] pin 37: etpua18 / dspi_d_pcs[3] / rch4_a / gpio[132] pin 38: etpua17 / dspi_d_pcs[2] / rch3_a / gpio[131] pin 39: etpua16 / dspi_d_pcs[1] / rch2_a / gpio[130] pin 40: etpua15 / dspi_b_pcs[5] / rch1_a / gpio[129] pin 42: etpua14 / dspi_b_pcs[4] / etpua9_o / rch0_a / gpio[128] note: pin 96 (vss) should be tied low.
pinout and signal description MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 25 2.2 208 map bga ballmap figure 3. 208-pin mapbga package ballmap (viewed from above) 12345678910111213141516 a vss an9 an11 vdda1 vssa1 an1 an5 vrh vrl an27 vssa0 an12-sds mdo2 mdo0 vrc33 vss a b vdd vss an8 an21 an0 an4 refbypc an22 an25 an28 vdda0 an13-sdo mdo3 mdo1 vss vdd b c vstby vdd vss an17 an34 an16 an3 an7 an23 an32 an33 an14-sdi an15-fck vss mseo0 tck c d vrc33 an39 vdd vss an18 an2 an6 an24 an30 an31 an35 vddeh7 vss tms evto nc d e etpua30 etpua31 an37 vdd nc tdi evti mseo1 e f etpua28 etpua29 etpua26 an36 vddeh6ab tdo mcko jcomp f g etpua24 etpua27 etpua25 etpua21 vss vss vss vss dspi_b_ sout dspi_b_ pcs[3] dspi_b_sin dspi_b_ pcs[0] g h etpua23 etpua22 etpua17 etpua18 vss vss vss vss gpio[99] dspi_b_ pcs[4] dspi_b_ pcs[2] dspi_b_ pcs[1] h j etpua20 etpua19 etpua14 etpua13 vss vss vss vss dspi_b_ pcs[5] sci_a_tx gpio[98] dspi_b_ sck j k etpua16 etpua15 etpua7 vddeh1ab vss vss vss vss can_c_tx sci_a_rx rstout vddreg k l etpua12 etpua11 etpua6 tcrclka sci_b_tx can_c_rx wkpcfg reset l m etpua10 etpua9 etpua1 etpua5 sci_b_rx pllref bootcfg1 vss m n etpua8 etpua4 etpua0 vss vdd vrc33 emios2 emios10 vddeh4ab emios12 mdo7_ etpua19_o vrc33 vss vrcctl nc extal n p etpua3 etpua2 vss vdd gpio[207] nc emios6 emios8 mdo11_ etpua29_o mdo4_ etpua2_o mdo8_ etpua21_o can_a_tx vdd vss nc xtal p r nc vss vdd gpio[206] emios4 emios3 emios9 emios11 emios14 mdo10_ etpua27_o emios23 can_a_rx can_b_rx vdd vss vddpll r t vss vdd nc emios0 emios1 gpio[219] mdo9_ etpua25_o emios13 emios15 mdo5_ etpua4_o mdo6_ etpua13_o can_b_tx vdde12 engclk vdd vss t 12345678910111213141516
MPC5642A microcontroller data sheet, rev. 3.1 26 freescale semiconductor pinout and signal description 2.3 324 tepbga ballmap figure 4. 324-pin tepbga package ballmap (northwest, viewed from above) 1234567891011 a vss vdd an16 an17 an37 vdda1 vssa1 an23 an25 vrh vrl b vrc33 vss vdd an18 an36 an21 an4 an5 an24 refbypc an30 c an11 an9 vss vdd an20 an0 an1 an6 an7 an27 an29 d an10 an39 an38 vss vdd an19 an2 an3 an22 an26 an28 e an8 vssa0 vdda0 vstby f mcko vrcctl mdo0 vddreg g nc mdo1 mdo2 mdo3 h nc nc nc nc j nc nc nc nc vss vss vss k etpua31 nc nc vddeh1ab vss vss vss l etpua27 etpua26 etpua29 etpua30 vss vss vss
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 27 pinout and signal description figure 5. 324-pin tepbga package ballmap (southwest, viewed from above) m etpua23 etpua24 etpua25 etpua28 nc nc vss n nc nc etpua22 etpua21 vss vss vdde12 p nc nc gpio[12] gpio[13] vss vss vrc33 r gpio[14] gpio[15] vdde-eh gpio[16] t gpio[17] nc nc nc u nc nc nc nc v nc vdde-eh nc nc w etpua20 etpua19 etpua18 vss vdde12 nc nc vdde12 nc engclk etpua4 y etpua17 etpua16 vss vdd nc nc nc nc nc etpua8 etpua3 aa etpua15 etpua14 vdd etpua10 nc nc nc nc etpua9 etpua7 etpua2 ab vss etpua13 etpua12 etpua11 nc nc nc nc clkout etpua6 etpua5 1234567891011
MPC5642A microcontroller data sheet, rev. 3.1 28 freescale semiconductor pinout and signal description figure 6. 324-pin tepbga package ballmap (northeast, viewed from above) 12 13 14 15 16 17 18 19 20 21 22 an34 an14-sdi an15-fck gpio[203] dspi_a_ pcs[5] dspi_a_ sout mdo8_ etpua21_o mdo10_ etpua27_o vdd vdd vss a an33 an13-sdo gpio[207] gpio[99] dspi_a_ pcs[4] dspi_a_sin mdo7_ etpua19_o mdo4_ etpua2_o mdo5_ etpua4_o vss vddeh7 b an32 an12-sds gpio[206] gpio[98] dspi_a_ pcs[1] dspi_a_sck mdo6_ etpua13_o mdo11_ etpua29_o vss vddeh7 vdd c an31 an35 gpio[204] vddeh7 dspi_a_ pcs[0] vss mdo9_ etpua25_o vss vddeh7 tck tdi d vddeh7 tms tdo nc e vddeh7 jcomp vss nc f rdy evto mseo0 mseo1 g vddeh7 evti vss dspi_b_sin h vss vss vddeh7 dspi_b_ sout dspi_b_ pcs[3] dspi_b_ pcs[0] dspi_b_ pcs[1] j vss vss vss nc dspi_b_ pcs[4] dspi_b_sck dspi_b_ pcs[2] k vss vss vss dspi_b_ pcs[5] nc vss nc l
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 29 pinout and signal description figure 7. 324-pin tepbga package ballmap (southeast, viewed from above) vss vss vss vrc33 nc nc vddeh6ab m vss vss vss nc sci_a_tx vss nc n vss vss vss can_c_tx sci_a_rx rstout rstcfg p nc nc nc reset r vss bootcfg0 vss vss t vddeh6ab pllcfg1 bootcfg1 extal u sci_c_rx can_c_rx pllref xtal v etpua1 emios1 vddeh4ab emios8 emios15 emios16 emios23 sci_c_tx vdd can_b_rx vddpll w etpua0 emios2 emios5 emios9 emios14 emios17 emios22 can_a_rx vss vdd can_b_tx y emios0 emios3 emios6 emios10 emios13 emios18 emios21 vddeh4ab wkpcfg vss vdd aa tcrclka emios4 emios7 emios11 emios12 emios19 emios20 can_a_tx sci_b_rx sci_b_tx vss ab 12 13 14 15 16 17 18 19 20 21 22
MPC5642A microcontroller data sheet, rev. 3.1 pinout and signal description freescale semiconductor 30 2.4 signal summary table 3. MPC5642A signal properties name 1 function 2 p / a / g 3 pcr pa field 4 pcr 5 i/o type voltage 6 / pad type 7 status 8 package pin no. during reset after reset 176 208 324 gpio fr_a_tx gpio[12] flexray transmit data channel a gpio a1 g 010 000 12 o i/o vdde-eh / medium ? / up ? / up ? ? p3 fr_a_tx_en gpio[13] flexray ch. a tx data enable gpio a1 g 010 000 13 o i/o vdde-eh / medium ? / up ? / up ? ? p4 fr_a_rx gpio[14] flexray receive data ch. a gpio a1 g 010 000 14 i i/o vdde-eh / medium ? / up ? / up ? ? r1 fr_b_tx gpio[15] flexray transmit data ch. b gpio a1 g 010 000 15 o i/o vdde-eh / medium ? / up ? / up ? ? r2 fr_b_tx_en gpio[16] flexray tx data enable for ch. b gpio a1 g 010 000 16 o i/o vdde-eh / medium ? / up ? / up ? ? r4 fr_b_rx gpio[17] flexray receive data channel b gpio a1 g 010 000 17 i i/o vdde-eh / medium ? / up ? / up ? ? t1 gpio[206] etrig0 gpio / eqadc trigger input g 00 206 i/o 9 vddeh7 / slow 10 ? / up ? / up 143 r4 c14 gpio[207] etrig1 gpio / eqadc trigger input g 00 207 i/o 9 vddeh7 / slow ? / up ? / up 144 p5 b14 gpio[219] gpio g 000 219 11 i/o vddeh7 / multv ? / up ? / up 122 t6 ? reset / configuration reset external reset input p ? ? i vddeh6 / slow reset / up reset / up 97 l16 r22 rstout external reset output p 01 230 o vddeh6 / slow rstout / down rstout / down 102 k15 p21 pllref irq[4] etrig2 gpio[208] fmpll mode selection external interrupt request eqadc trigger input gpio p a1 a2 g 001 010 100 000 208 i i i i/o vddeh6 / slow ? / up pllref / up 83 m14 v21 pllcfg1 12 irq[5] dspi_d_sout gpio[209] ? external interrupt request dspi d data output gpio ? a1 a2 g ? 010 100 000 209 ? i o i/o vddeh6 / medium ? / up ? / up ? ? u20 rstcfg gpio[210] rstcfg gpio p g 01 00 210 i i/o vddeh6 / slow ? / down ? ? ? p22
pinout and signal description MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 31 bootcfg[0] irq[2] gpio[211] boot config. input external interrupt request gpio p a1 g 01 10 00 211 i i i/o vddeh6 / slow ? / down bootcfg[0] / down ??t20 bootcfg[1] irq[3] etrig3 gpio[212] boot config. input external interrupt request eqadc trigger input gpio p a1 a2 g 001 010 100 000 212 i i i i/o vddeh6 / slow ? / down bootcfg[1] / down 85 m15 u21 wkpcfg nmi dspi_b_sout gpio[213] weak pull config. input non-maskable interrupt dspi b data output gpio p a1 a2 g 001 010 100 000 213 i i o i/o vddeh6 / medium ? / up wkpcfg / up 86 l15 aa20 calibration bus cal_cs0 calibration chip select p 01 336 o vdde12 / fast ?/? ??? cal_cs2 cal_addr[10] cal_we[2]/be[2] calibration chip select calibration address bus calibration write/byte enable p a1 a2 001 010 100 338 o i/o o vdde12 / fast ?/? ??? cal_cs3 cal_addr[11] cal_we [3]/be [3] calibration chip select calibration address bus calibration write/byte enable p a1 a2 001 010 100 339 o i/o o vdde12 / fast ?/? ??? cal_addr[12] cal_we [2]/be [2] calibration address bus calibration write/byte enable p a1 01 10 340 i/o o vdde12 / fast ?/? ??? cal_addr[13] cal_we [3]/be [3] calibration address bus calibration write/byte enable p a1 01 10 340 i/o o vdde12 / fast ?/? ??? cal_addr[14] cal_data[31] calibration address bus calibration data bus p a1 01 10 340 i/o i/o vdde12 / fast ?/? ??? cal_addr[15] cal_ale calibration address bus calibration address latch enable p a1 01 10 340 i/o o vdde12 / fast ?/? ??? cal_addr[16] cal_data[16] calibration address bus calibration data bus p a1 01 10 345 i/o i/o vdde12 / fast ?/? ??? cal_addr[17] cal_data[17] calibration address bus calibration data bus p a1 01 10 345 i/o i/o vdde12 / fast ?/? ??? cal_addr[18] cal_data[18] calibration address bus calibration data bus p a1 01 10 345 i/o i/o vdde12 / fast ?/? ??? cal_addr[19] cal_data[19] calibration address bus calibration data bus p a1 01 10 345 i/o i/o vdde12 / fast ?/? ??? cal_addr[20] cal_data[20] calibration address bus calibration data bus p a1 01 10 345 i/o i/o vdde12 / fast ?/? ??? cal_addr[21] cal_data[21] calibration address bus calibration data bus p a1 01 10 345 i/o i/o vdde12 / fast ?/? ??? table 3. MPC5642A signal properties (continued) name 1 function 2 p / a / g 3 pcr pa field 4 pcr 5 i/o type voltage 6 / pad type 7 status 8 package pin no. during reset after reset 176 208 324
MPC5642A microcontroller data sheet, rev. 3.1 pinout and signal description freescale semiconductor 32 cal_addr[22] cal_data[22] calibration address bus calibration data bus p a1 01 10 345 i/o i/o vdde12 / fast ?/? ??? cal_addr[23] cal_data[23] calibration address bus calibration data bus p a1 01 10 345 i/o i/o vdde12 / fast ?/? ??? cal_addr[24] cal_data[24] calibration address bus calibration data bus p a1 01 10 345 i/o i/o vdde12 / fast ?/? ??? cal_addr[25] cal_data[25] calibration address bus calibration data bus p a1 01 10 345 i/o i/o vdde12 / fast ?/? ??? cal_addr[26] cal_data[26] calibration address bus calibration data bus p a1 01 10 345 i/o i/o vdde12 / fast ?/? ??? cal_addr[27] cal_data[27] calibration address bus calibration data bus p a1 01 10 345 i/o i/o vdde12 / fast ?/? ??? cal_addr[28] cal_data[28] calibration address bus calibration data bus p a1 01 10 345 i/o i/o vdde12 / fast ?/? ??? cal_addr[29] cal_data[29] calibration address bus calibration data bus p a1 01 10 345 i/o i/o vdde12 / fast ?/? ??? cal_addr[30] cal_data[30] calibration address bus calibration data bus p a1 01 10 345 i/o i/o vdde12 / fast ?/? ??? cal_data[0] calibration data bus p 01 341 i/o vdde12 / fast ? / up ? / up ? ? ? cal_data[1] calibration data bus p 01 341 i/o vdde12 / fast ? / up ? / up ? ? ? cal_data[2] calibration data bus p 01 341 i/o vdde12 / fast ? / up ? / up ? ? ? cal_data[3] calibration data bus p 01 341 i/o vdde12 / fast ? / up ? / up ? ? ? cal_data[4] calibration data bus p 01 341 i/o vdde12 / fast ? / up ? / up ? ? ? cal_data[5] calibration data bus p 01 341 i/o vdde12 / fast ? / up ? / up ? ? ? cal_data[6] calibration data bus p 01 341 i/o vdde12 / fast ? / up ? / up ? ? ? cal_data[7] calibration data bus p 01 341 i/o vdde12 / fast ? / up ? / up ? ? ? cal_data[8] calibration data bus p 01 341 i/o vdde12 / fast ? / up ? / up ? ? ? cal_data[9] calibration data bus p 01 341 i/o vdde12 / fast ? / up ? / up ? ? ? table 3. MPC5642A signal properties (continued) name 1 function 2 p / a / g 3 pcr pa field 4 pcr 5 i/o type voltage 6 / pad type 7 status 8 package pin no. during reset after reset 176 208 324
pinout and signal description MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 33 cal_data[10] calibration data bus p 01 341 i/o vdde12 / fast ? / up ? / up ? ? ? cal_data[11] calibration data bus p 01 341 i/o vdde12 / fast ? / up ? / up ? ? ? cal_data[12] calibration data bus p 01 341 i/o vdde12 / fast ? / up ? / up ? ? ? cal_data[13] calibration data bus p 01 341 i/o vdde12 / fast ? / up ? / up ? ? ? cal_data[14] calibration data bus p 01 341 i/o vdde12 / fast ? / up ? / up ? ? ? cal_data[15] calibration data bus p 01 341 i/o vdde12 / fast ? / up ? / up ? ? ? cal_rd_wr calibration data bus p 01 342 o vdde12 / fast ?/? ??? cal_we[0] calibration write enable p 01 342 o vdde12 / fast ?/? ??? cal_we[1] calibration write enable p 01 342 o vdde12 / fast ?/? ??? cal_oe calibration output enable p 01 342 o vdde12 / fast ?/? ??? cal_ts cal_ale calibration transfer start address latch enable p a1 01 10 343 o o vdde12 / fast ?/? ??? cal_mdo[4] calibration nexus message data out p 01 ? o vdde12 / fast ? cal_mdo[4] / ? ? ? ? cal_mdo[5] calibration nexus message data out p 01 ? o vdde12 / fast ? cal_mdo[5] / ? ? ? ? cal_mdo[6] calibration nexus message data out p 01 ? o vdde12 / fast ? cal_mdo[6] / ? ? ? ? cal_mdo[7] calibration nexus message data out p 01 ? o vdde12 / fast ? cal_mdo[7] / ? ? ? ? cal_mdo[8] calibration nexus message data out p 01 ? o vdde12 / fast ? cal_mdo[8] / ? ? ? ? cal_mdo[9] calibration nexus message data out p 01 ? o vdde12 / fast ? cal_mdo[9] / ? ? ? ? cal_mdo[10] calibration nexus message data out p 01 ? o vdde12 / fast ? cal_mdo[10] / ? ? ? ? cal_mdo[11] calibration nexus message data out p 01 ? o vdde12 / fast ? cal_mdo[11] / ? ? ? ? table 3. MPC5642A signal properties (continued) name 1 function 2 p / a / g 3 pcr pa field 4 pcr 5 i/o type voltage 6 / pad type 7 status 8 package pin no. during reset after reset 176 208 324
MPC5642A microcontroller data sheet, rev. 3.1 pinout and signal description freescale semiconductor 34 nexus 13 evti nexus event in p 01 231 i vddeh7 / multiv ? / up evti / up 116 e15 h20 evto 14 nexus event out p 01 227 o vddeh7 / multiv abr/up evto / ? 120 d15 g20 mcko nexus message clock out p ? 219 11 ovrc33 / fast ?mcko / ?14f15f1 mdo[0] nexus message data out p 01 220 o vrc33 / fast ? mdo[0] / ? 17 a14 f3 mdo[1] nexus message data out p 01 221 o vrc33 / fast ? mdo[1] / ? 18 b14 g2 mdo[2] nexus message data out p 01 222 o vrc33 / fast ? mdo[2] / ? 19 a13 g3 mdo[3] nexus message data out p 01 223 o vrc33 / fast ? mdo[3] / ? 20 b13 g4 mdo[4] etpua2_o gpio[75] nexus message data out etpu a channel (output only) gpio p a1 g 01 10 00 75 o o i/o vddeh7 / multiv ?? / ?126p10b19 mdo[5] etpua4_o gpio[76] nexus message data out etpu a channel (output only) gpio p a1 g 01 10 00 76 o o i/o vddeh7 / multiv ?? / ?129t10b20 mdo[6] etpua13_o gpio[77] nexus message data out etpu a channel (output only) gpio p a1 g 01 10 00 77 o o i/o vddeh7 / multiv ?? / ?135t11c18 mdo[7] etpua19_o gpio[78] nexus message data out etpu a channel (output only) gpio p a1 g 01 10 00 78 o o i/o vddeh7 / multiv ?? / ?136n11b18 mdo[8] etpua21_o gpio[79] nexus message data out etpu a channel (output only) gpio p a1 g 01 10 00 79 o o i/o vddeh7 / multiv ?? / ?137p11a18 mdo[9] etpua25_o pio[80] nexus message data out etpu a channel (output only) gpio p a1 g 01 10 00 80 o o i/o vddeh7 / multiv ?? / ?139t7d18 mdo[10] etpua27_o gpio[81] nexus message data out etpu a channel (output only) gpio p a1 g 01 10 00 81 o o i/o vddeh7 / multiv ?? / ?134r10a19 mdo[11] etpua29_o gpio[82] nexus message data out etpu a channel (output only) gpio[82] p a1 g 01 10 00 82 o o i/o vddeh7 / multiv ?? / ?124p9c19 table 3. MPC5642A signal properties (continued) name 1 function 2 p / a / g 3 pcr pa field 4 pcr 5 i/o type voltage 6 / pad type 7 status 8 package pin no. during reset after reset 176 208 324
pinout and signal description MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 35 mseo[0] nexus message start/end out p 01 224 o vddeh7 / multiv ? mseo[0] / ? 118 c15 g21 mseo[1] nexus message start/end out p 01 225 o vddeh7 / multiv ? mseo[1] / ? 117 e16 g22 rdy nexus ready output p 01 226 o vddeh7 / multiv ????g19 jtag tck jtag test clock input p 01 ? i vddeh7 / multiv tck / down tck / down 128 c16 d21 tdi jtag test data input p 01 232 i vddeh7 / multiv tdi / up tdi / up 130 e14 d22 tdo jtag test data output p 01 228 o vddeh7 / multiv tdo / up tdo / up 123 f14 e21 tms jtag test mode select input p 01 ? i vddeh7 / multiv tms / up tms / up 131 d14 e20 jcomp jtag tap controller enable p 01 ? i vddeh7 / multiv jcomp / down jcomp / down 121 f16 f20 flexcan can_a_tx sci_a_tx gpio[83] flexcan a transmit esci a transmit gpio p a1 g 01 10 00 83 o o i/o vddeh6 / slow ? / up ? / up 81 p12 ab19 can_a_rx sci_a_rx gpio[84] flexcan a receive esci a receive gpio p a1 g 01 10 00 84 i i i/o vddeh6 / slow ? / up ? / up 82 r12 y19 can_b_tx dspi_c_pcs[3] sci_c_tx gpio[85] flexcan b transmit dspi c peripheral chip select esci c transmit gpio p a1 a2 g 001 010 100 000 85 o o o i/o vddeh6 / slow ? / up ? / up 88 t12 y22 can_b_rx dspi_c_pcs[4] sci_c_rx gpio[86] flexcan b receive dspi c peripheral chip select esci c receive gpio p a1 a2 g 001 010 100 000 86 i o i i/o vddeh6 / slow ? / up ? / up 89 r13 w21 can_c_tx dspi_d_pcs[3] gpio[87] flexcan c transmit dspi d peripheral chip select gpio p a1 g 01 10 00 87 o o i/o vddeh6 / medium ? / up ? / up 101 k13 p19 can_c_rx dspi_d_pcs[4] gpio[88] flexcan c receive dspi d peripheral chip select gpio p a1 g 01 10 00 88 i o i/o vddeh6 / slow ? / up ? / up 98 l14 v20 esci table 3. MPC5642A signal properties (continued) name 1 function 2 p / a / g 3 pcr pa field 4 pcr 5 i/o type voltage 6 / pad type 7 status 8 package pin no. during reset after reset 176 208 324
MPC5642A microcontroller data sheet, rev. 3.1 pinout and signal description freescale semiconductor 36 sci_a_tx emios13 15 gpio[89] esci a transmit emios channel gpio p a1 g 01 10 00 89 o o i/o vddeh6 / medium ? / up ? / up 100 j14 n20 sci_a_rx emios15 15 gpio[90] esci a receive emios channel gpio p a1 g 01 10 00 90 i o i/o vddeh6 / medium ? / up ? / up 99 k14 p20 sci_b_tx dspi_d_pcs[1] gpio[91] esci b transmit dspi d peripheral chip select gpio p a1 g 01 10 00 91 o o i/o vddeh6 / medium ? / up ? / up 87 l13 ab21 sci_b_rx dspi_d_pcs[5] gpio[92] esci b receive dspi d peripheral chip select gpio p a1 g 01 10 00 92 i o i/o vddeh6 / medium ? / up ? / up 84 m13 ab20 sci_c_tx gpio[244] esci c transmit gpio p g 01 00 244 o i/o vddeh6 / medium ? / up ? / up ? ? w19 sci_c_rx gpio[245] esci c receive gpio p g 01 00 245 i i/o vddeh6 / medium ? / up ? / up ? ? v19 dspi dspi_a_sck 16 dspi_c_pcs[1] gpio[93] ? dspi c peripheral chip select gpio ? a1 g ? 10 00 93 ? o i/o vddeh7 / medium ? / up ? / up ? ? c17 dspi_a_sin 16 dspi_c_pcs[2] gpio[94] ? dspi c peripheral chip select gpio ? a1 g ? 10 00 94 ? o i/o vddeh7 / medium ? / up ? / up ? ? b17 dspi_a_sout 16 dspi_c_pcs[5] gpio[95] ? dspi c peripheral chip select gpio ? a1 g ? 10 00 95 ? o i/o vddeh7 / medium ? / up ? / up ? ? a17 dspi_a_pcs[0] 16 dspi_d_pcs[2] gpio[96] ? dspi c peripheral chip select gpio ? a1 g ? 10 00 96 ? o i/o vddeh7 / medium ? / up ? / up ? ? d16 dspi_a_pcs[1] 16 dspi_b_pcs[2] gpio[97] ? dspi c peripheral chip select gpio ? a1 g ? 10 00 97 ? o i/o vddeh7 / medium ? / up ? / up ? ? c16 dspi_a_pcs[2] 16 dspi_d_sck gpio[98] ? spi clock pin for dspi module gpio ? a1 g ? 10 00 98 ? i/o i/o vddeh7 / medium ? / up ? / up 141 j15 c15 dspi_a_pcs[3] 16 dspi_d_sin gpio[99] ? dspi d data input gpio ? a1 g ? 10 00 99 ? i i/o vddeh7 / medium ? / up ? / up 142 h13 b15 dspi_a_pcs[4] 16 dspi_d_sout gpio[100] ? dspi d data output gpio ? a1 g ? 10 00 100 ? o i/o vddeh7 / medium ? / up ? / up ? ? b16 table 3. MPC5642A signal properties (continued) name 1 function 2 p / a / g 3 pcr pa field 4 pcr 5 i/o type voltage 6 / pad type 7 status 8 package pin no. during reset after reset 176 208 324
pinout and signal description MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 37 dspi_a_pcs[5] 16 dspi_b_pcs[3] gpio[101] ? dspi b peripheral chip select gpio ? a1 g ? 10 00 101 ? o i/o vddeh7 / medium ? / up ? / up ? ? a16 dspi_b_sck dspi_c_pcs[1] gpio[102] spi clock pin for dspi module dspi b peripheral chip select gpio p a1 g 01 10 00 102 i/o o i/o vddeh6 / medium ? / up ? / up 106 j16 k21 dspi_b_sin dspi_c_pcs[2] gpio[103] dspi b data input dspi c peripheral chip select gpio p a1 g 01 10 00 103 i o i/o vddeh6 / medium ? / up ? / up 112 g15 h22 dspi_b_sout dspi_c_pcs[5] gpio[104] dspi b data output dspi c peripheral chip select gpio p a1 g 01 10 00 104 o o i/o vddeh6 / medium ? / up ? / up 113 g13 j19 dspi_b_pcs[0] dspi_d_pcs[2] gpio[105] dspi b peripheral chip select dspi d peripheral chip select gpio p a1 g 01 10 00 105 i/o o i/o vddeh6 / medium ? / up ? / up 111 g16 j21 dspi_b_pcs[1] dspi_d_pcs[0] gpio[106] dspi b peripheral chip select dspi d peripheral chip select gpio p a1 g 01 10 00 106 o i/o i/o vddeh6 / medium ? / up ? / up 109 h16 j22 dspi_b_pcs[2] dspi_c_sout gpio[107] dspi b peripheral chip select dspi c data output gpio p a1 g 01 10 00 107 o o i/o vddeh6 / medium ? / up ? / up 107 h15 k22 dspi_b_pcs[3] dspi_c_sin gpio[108] dspi b peripheral chip select dspi c data input gpio p a1 g 01 10 00 108 o i i/o vddeh6 / medium ? / up ? / up 114 g14 j20 dspi_b_pcs[4] dspi_c_sck gpio[109] dspi b peripheral chip select spi clock pin for dspi module gpio p a1 g 01 10 00 109 o i/o i/o vddeh6 / medium ? / up ? / up 105 h14 k20 dspi_b_pcs[5] dspi_c_pcs[0] gpio[110] dspi b peripheral chip select dspi c peripheral chip select gpio p a1 g 01 10 00 110 o i/o i/o vddeh6 / medium ? / up ? / up 104 j13 l19 eqadc an0 dan0+ single ended analog input positive terminal differential input p??ivdda / analog pull-up/down i / ? an[0] / ? 172 b5 c6 an1 dan0 ? single ended analog input negative terminal differential input p??ivdda / analog pull-up/down i / ? an[1] / ? 171 a6 c7 an2 dan1+ single ended analog input positive terminal differential input p??ivdda / analog pull-up/down i / ? an[2] / ? 170 d6 d7 table 3. MPC5642A signal properties (continued) name 1 function 2 p / a / g 3 pcr pa field 4 pcr 5 i/o type voltage 6 / pad type 7 status 8 package pin no. during reset after reset 176 208 324
MPC5642A microcontroller data sheet, rev. 3.1 pinout and signal description freescale semiconductor 38 an3 dan1 ? single ended analog input negative terminal differential input p??ivdda / analog pull-up/down i / ? an[3] / ? 169 c7 d8 an4 dan2+ single ended analog input positive terminal differential input p??ivdda / analog pull-up/down i / ? an[4] / ? 168 b6 b7 an5 dan2 ? single ended analog input negative terminal differential input p??ivdda / analog pull-up/down i / ? an[5] / ? 167 a7 b8 an6 dan3+ single ended analog input positive terminal differential input p??ivdda / analog pull-up/down i / ? an[6] / ? 166 d7 c8 an7 dan3 ? single ended analog input negative terminal differential input p??ivdda / analog pull-up/down i / ? an[7] / ? 165 c8 c9 an8 anw single-ended analog input multiplexed analog input p01?ivdda / analog i / ? an[8] / ? 9 b3 e1 an9 anx single-ended analog input external multiplexed analog input p01?ivdda / analog i / ? an[9] / ? 5 a2 c2 an10 any single-ended analog input multiplexed analog input p01?ivdda / analog i / ? an[10] / ? ? ? d1 an11 anz single-ended analog input multiplexed analog input p01?ivdda / analog i / ? an[11] / ? 4 a3 c1 an12 - sds ma0 etpua19_o sds single-ended analog input mux address 0 etpu a channel (output only) eqadc serial data select p a1 a2 g 001 010 100 000 215 i o o i/o vddeh7 / medium i / ? an[12] / ? 148 a12 c13 an13 - sdo ma1 etpua21_o sdo single-ended analog input mux address 1 etpu a channel (output only) eqadc serial data out p a1 a2 g 001 010 100 000 216 i o o o vddeh7 / medium i / ? an[13] / ? 147 b12 b13 an14 - sdi ma2 etpua27_o sdi single-ended analog input mux address 2 etpu a channel (output only) eqadc serial data in p a1 a2 g 001 010 100 000 217 i o o i vddeh7 / medium i / ? an[14] / ? 146 c12 a13 an15 - fck fck etpua29_o single-ended analog input eqadc free running clock etpu a channel (output only) p a1 a2 001 010 100 218 i o o vddeh7 / medium i / ? an[15] / ? 145 c13 a14 an16 single-ended analog input p ? ? i vdda / analog i / ? an[16] / ? 3 c6 a3 an17 single-ended analog input p ? ? i vdda / analog i / ? an[17] / ? 2 c4 a4 table 3. MPC5642A signal properties (continued) name 1 function 2 p / a / g 3 pcr pa field 4 pcr 5 i/o type voltage 6 / pad type 7 status 8 package pin no. during reset after reset 176 208 324
pinout and signal description MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 39 an18 single-ended analog input p ? ? i vdda / analog i / ? an[18] / ? 1 d5 b4 an19 single-ended analog input p ? ? i vdda / analog i / ? an[19] / ? ? ? d6 an20 single-ended analog input p ? ? i vdda / analog i / ? an[20] / ? ? ? c5 an21 single-ended analog input p ? ? i vdda / analog i / ? an[21] / ? 173 b4 b6 an22 single-ended analog input p ? ? i vdda / analog i / ? an[22] / ? 161 b8 d9 an23 single-ended analog input p ? ? i vdda / analog i / ? an[23] / ? 160 c9 a8 an24 single-ended analog input p ? ? i vdda / analog i / ? an[24] / ? 159 d8 b9 an25 single-ended analog input p ? ? i vdda / analog i / ? an[25] / ? 158 b9 a9 an26 single-ended analog input p ? ? i vdda / analog i / ? an[26] / ? ? ? d10 an27 single-ended analog input p ? ? i vdda / analog i / ? an[27] / ? 157 a10 c10 an28 single-ended analog input p ? ? i vdda / analog i / ? an[28] / ? 156 b10 d11 an29 single-ended analog input p ? ? i vdda / analog i / ? an[29] / ? ? ? c11 an30 single-ended analog input p ? ? i vdda / analog i / ? an[30] / ? 155 d9 b11 an31 single-ended analog input p ? ? i vdda / analog i / ? an[31] / ? 154 d10 d12 an32 single-ended analog input p ? ? i vdda / analog i / ? an[32] / ? 153 c10 c12 an33 single-ended analog input p ? ? i vdda / analog i / ? an[33] / ? 152 c11 b12 an34 single-ended analog input p ? ? i vdda / analog i / ? an[34] / ? 151 c5 a12 an35 single-ended analog input p ? ? i vdda / analog i / ? an[35] / ? 150 d11 d13 an36 single-ended analog input p ? ? i vdda / analog i / ? an[36] / ? 174 f4 b5 table 3. MPC5642A signal properties (continued) name 1 function 2 p / a / g 3 pcr pa field 4 pcr 5 i/o type voltage 6 / pad type 7 status 8 package pin no. during reset after reset 176 208 324
MPC5642A microcontroller data sheet, rev. 3.1 pinout and signal description freescale semiconductor 40 an37 single-ended analog input p ? ? i vdda / analog i / ? an[37] / ? 175 e3 a5 an38 single-ended analog input p ? ? i vdda / analog i / ? an[38] / ? ? ? d3 an39 single-ended analog input p ? ? i vdda / analog i / ? an[39] / ? 8 d2 d2 vrh voltage reference high p ? ? i vdda / ? i / ? ? 163 a8 a10 vrl voltage reference low p ? ? i vdda / ? i / ? ? 162 a9 a11 refbybc reference bypass capacitor input p??ivdda / analog i / ? ? 164 b7 b10 etpu2 tcrclka irq[7] gpio[113] etpu a tcr clock external interrupt request gpio p a1 g 01 10 00 113 i i i/o vddeh4 / slow ? / up ? / up ? l4 ab12 etpua0 etpua12_o etpua19_o gpio[114] etpu a channel etpu a channel (output only) etpu a channel (output only) gpio p a1 a2 g 001 010 100 000 114 i/o o o i/o vddeh4 / slow ? / wkpcfg ? / wkpcfg 61 n3 y12 etpua1 etpua13_o gpio[115] etpu a channel etpu a channel (output only) gpio p a1 g 01 10 00 115 i/o o i/o vddeh4 / slow ? / wkpcfg ? / wkpcfg 60 m3 w12 etpua2 etpua14_o gpio[116] etpu a channel etpu a channel (output only) gpio p a1 g 01 10 00 116 i/o o i/o vddeh4 / slow ? / wkpcfg ? / wkpcfg 59 p2 aa11 etpua3 etpua15_o gpio[117] etpu a channel etpu a channel (output only) gpio p a1 g 01 10 00 117 i/o o i/o vddeh4 / slow ? / wkpcfg gpio / wkpcfg 58 p1 y11 etpua4 etpua16_o ? fr_b_tx gpio[118] etpu a channel etpu a channel (output only) ? flexray transmit data channel b gpio p a1 a2 a3 g 0001 0010 ? 1000 0000 118 i/o o ? o i/o vddeh4 / slow ? / wkpcfg ? / wkpcfg 56 n2 w11 etpua5 etpua17_o dspi_b_sck_lvds ? fr_b_tx_en gpio[119] etpu a channel etpu a channel (output only) lvds negative dspi clock flexray tx data enable for ch. b gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 119 i/o o o o i/o vddeh4 / slow + lv d s ? / wkpcfg ? / wkpcfg 54 m4 ab11 table 3. MPC5642A signal properties (continued) name 1 function 2 p / a / g 3 pcr pa field 4 pcr 5 i/o type voltage 6 / pad type 7 status 8 package pin no. during reset after reset 176 208 324
pinout and signal description MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 41 etpua6 etpua18_o dspi_b_sck_lvds+ fr_b_rx gpio[120] etpu a channel etpu a channel (output only) lvds positive dspi clock flexray receive data channel b gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 120 i/o o o i i/o vddeh4 / medium + lv d s ? / wkpcfg ? / wkpcfg 53 l3 ab10 etpua7 etpua19_o dspi_b_sout_lvds ? etpua6_o gpio[121] etpu a channel etpu a channel (output only) lvds negative dspi data out etpu a channel (output only) gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 121 i/o o o o i/o vddeh4 / slow + lv d s ? / wkpcfg ? / wkpcfg 52 k3 aa10 etpua8 etpua20_o dspi_b_sout_lvds+ gpio[122] etpu a channel etpu a channel (output only) lvds positive dspi data out gpio p a1 a2 g 001 010 100 000 122 i/o o o i/o vddeh4 / slow + lv d s ? / wkpcfg ? / wkpcfg 51 n1 y10 etpua9 etpua21_o rch1_b gpio[123] etpu a channel etpu a channel (output only) reaction channel 1b gpio p a1 a2 g 001 010 100 000 123 i/o o o i/o vddeh4 / slow ? / wkpcfg ? / wkpcfg 50 m2 aa9 etpua10 etpua22_o rch1_c gpio[124] etpu a channel etpu a channel (output only) reaction channel 1c gpio p a1 a2 g 001 010 100 000 124 i/o o o i/o vddeh1 / slow ? / wkpcfg ? / wkpcfg 49 m1 aa4 etpua11 etpua23_o rch4_b gpio[125] etpu a channel etpu a channel (output only) reaction channel 4b gpio p a1 a2 g 001 010 100 000 125 i/o o o i/o vddeh1 / slow ? / wkpcfg ? / wkpcfg 48 l2 ab4 etpua12 dspi_b_pcs[1] rch4_c gpio[126] etpu a channel dspi b peripheral chip select reaction channel 4c gpio p a1 a2 g 001 010 100 000 126 i/o o o i/o vddeh1 / medium ? / wkpcfg ? / wkpcfg 47 l1 ab3 etpua13 dspi_b_pcs[3] gpio[127] etpu a channel dspi b peripheral chip select gpio p a1 g 01 10 00 127 i/o o i/o vddeh1 / medium ? / wkpcfg ? / wkpcfg 46 j4 ab2 etpua14 dspi_b_pcs[4] etpua9_o rch0_a gpio[128] etpu a channel dspi b peripheral chip select etpu a channel (output only) reaction channel 0a gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 128 i/o o o o i/o vddeh1 / medium ? / wkpcfg ? / wkpcfg 42 j3 aa2 etpua15 dspi_b_pcs[5] rch1_a gpio[129] etpu a channel dspi b peripheral chip select reaction channel 1a gpio p a1 a2 g 001 010 100 000 129 i/o o o i/o vddeh1 / medium ? / wkpcfg ? / wkpcfg 40 k2 aa1 etpua16 dspi_d_pcs[1] rch2_a gpio[130] etpu a channel dspi d peripheral chip select reaction channel 2a gpio p a1 a2 g 001 010 100 000 130 i/o o o i/o vddeh1 / slow ? / wkpcfg ? / wkpcfg 39 k1 y2 table 3. MPC5642A signal properties (continued) name 1 function 2 p / a / g 3 pcr pa field 4 pcr 5 i/o type voltage 6 / pad type 7 status 8 package pin no. during reset after reset 176 208 324
MPC5642A microcontroller data sheet, rev. 3.1 pinout and signal description freescale semiconductor 42 etpua17 dspi_d_pcs[2] rch3_a gpio[131] etpu a channel dspi d peripheral chip select reaction channel 3a gpio p a1 a2 g 001 010 100 000 131 i/o o o i/o vddeh1 / slow ? / wkpcfg ? / wkpcfg 38 h3 y1 etpua18 dspi_d_pcs[3] rch4_a gpio[132] etpu a channel dspi d peripheral chip select reaction channel 4a gpio p a1 a2 g 001 010 100 000 132 i/o o o i/o vddeh1 / slow ? / wkpcfg ? / wkpcfg 37 h4 w3 etpua19 dspi_d_pcs[4] rch5_a gpio[133] etpu a channel dspi d peripheral chip select reaction channel 5a gpio p a1 a2 g 001 010 100 000 133 i/o o o i/o vddeh1 / slow ? / wkpcfg ? / wkpcfg 36 j2 w2 etpua20 irq[8] rch0_b fr_a_tx gpio[134] etpu a channel external interrupt request reaction channel 0b flexray transmit data channel a gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 134 i/o i o o i/o vddeh1 / slow ? / wkpcfg ? / wkpcfg 35 j1 w1 etpua21 irq[9] rch0_c fr_a_rx gpio[135] etpu a channel external interrupt request reaction channel 0c flexray receive channel a gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 135 i/o i o i i/o vddeh1 / slow ? / wkpcfg ? / wkpcfg 34 g4 n4 etpua22 irq[10] etpua17_o gpio[136] etpu a channel external interrupt request etpu a channel (output only) gpio p a1 a2 g 001 010 100 000 136 i/o i o i/o vddeh1 / slow ? / wkpcfg ? / wkpcfg 32 h2 n3 etpua23 irq[11] etpua21_o fr_a_tx_en gpio[137] etpu a channel external interrupt request etpu a channel (output only) flexray ch. a transmit enable gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 137 i/o i o o i/o vddeh1 / slow ? / wkpcfg ? / wkpcfg 30 h1 m1 etpua24 irq[12] dspi_c_sck_lvds ? gpio[138] etpu a channel external interrupt request lvds negative dspi clock gpio p a1 a2 g 001 010 100 000 138 i/o i o i/o vddeh1 / slow + lv d s ? / wkpcfg ? / wkpcfg 28 g1 m2 etpua25 irq[13] dspi_c_sck_lvds+ gpio[139] etpu a channel external interrupt request lvds positive dspi clock gpio p a1 a2 g 001 010 100 000 139 i/o i o i/o vddeh1 / medium + lv d s ? / wkpcfg ? / wkpcfg 27 g3 m3 etpua26 irq[14] dspi_c_sout_lvds ? gpio[140] etpu a channel external interrupt request lvds negative dspi data out gpio p a1 a2 g 001 010 100 000 140 i/o i o i/o vddeh1 / slow + lv d s ? / wkpcfg ? / wkpcfg 26 f3 l2 table 3. MPC5642A signal properties (continued) name 1 function 2 p / a / g 3 pcr pa field 4 pcr 5 i/o type voltage 6 / pad type 7 status 8 package pin no. during reset after reset 176 208 324
pinout and signal description MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 43 etpua27 irq[15] dspi_c_sout_lvds+ dspi_b_sout gpio[141] etpu a channel external interrupt request lvds positive dspi data out dspi b data output gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 141 i/o i o o i/o vddeh1 / slow + lv d s ? / wkpcfg ? / wkpcfg 25 g2 l1 etpua28 dspi_c_pcs[1] rch5_b gpio[142] etpu a channel dspi c peripheral chip select reaction channel 5b gpio p a1 a2 g 001 010 100 000 142 i/o o o i/o vddeh1 / medium ? / wkpcfg ? / wkpcfg 24 f1 m4 etpua29 dspi_c_pcs[2] rch5_c gpio[143] etpu a channel dspi c peripheral chip select reaction channel 5c gpio p a1 a2 g 001 010 100 000 143 i/o o o i/o vddeh1 / medium ? / wkpcfg ? / wkpcfg 23 f2 l3 etpua30 dspi_c_pcs[3] etpua11_o gpio[144] etpu a channel dspi c peripheral chip select etpu a channel (output only) gpio p a1 a2 g 001 010 100 000 144 i/o o o i/o vddeh1 / medium ? / wkpcfg ? / wkpcfg 22 e1 l4 etpua31 dspi_c_pcs[4] etpua13_o gpio[145] etpu a channel dspi c peripheral chip select etpu a channel (output only) gpio p a1 a2 g 001 010 100 000 145 i/o o o i/o vddeh1 / medium ? / wkpcfg ? / wkpcfg 21 e2 k1 emios emios0 etpua0_o etpua25_o gpio[179] emios channel etpu a channel (output only) etpu a channel (output only) gpio p a1 a2 g 001 010 100 000 179 i/o o o i/o vddeh4 / slow ? / up ? / up 63 t4 aa12 emios1 etpua1_o gpio[180] emios channel etpu a channel (output only) gpio p a1 g 01 10 00 180 i/o o i/o vddeh4 / slow ? / up ? / up 64 t5 w13 emios2 etpua2_o rch2_b gpio[181] emios channel etpu a channel (output only) reaction channel 2b gpio p a1 a2 g 001 010 100 000 181 i/o o o i/o vddeh4 / slow ? / up ? / up 65 n7 y13 emios3 etpua3_o gpio[182] emios channel etpu a channel (output only) gpio p a1 g 01 10 00 182 i/o o i/o vddeh4 / slow ? / wkpcfg ? / wkpcfg 66 r6 aa13 emios4 etpua4_o rch2_c gpio[183] emios channel etpu a channel (output only) reaction channel 2c gpio p a1 a2 g 001 010 100 000 183 i/o o o i/o vddeh4 / slow ? / wkpcfg ? / wkpcfg 67 r5 ab13 emios5 etpua5_o gpio[184] emios channel etpu a channel (output only) gpio p a1 g 01 10 00 184 i/o o i/o vddeh4 / slow ? / wkpcfg ? / wkpcfg ??y14 table 3. MPC5642A signal properties (continued) name 1 function 2 p / a / g 3 pcr pa field 4 pcr 5 i/o type voltage 6 / pad type 7 status 8 package pin no. during reset after reset 176 208 324
MPC5642A microcontroller data sheet, rev. 3.1 pinout and signal description freescale semiconductor 44 emios6 etpua6_o gpio[185] emios channel etpu a channel (output only) gpio p a1 g 01 10 00 185 i/o o i/o vddeh4 / slow ? / down ? / down 68 p7 aa14 emios7 etpua7_o gpio[186] emios channel etpu a channel (output only) gpio p a1 g 01 10 00 186 i/o o i/o vddeh4 / slow ? / down ? / down 69 ? ab14 emios8 etpua8_o sci_b_tx gpio[187] emios channel etpu a channel (output only) esci b transmit gpio p a1 a2 g 001 010 100 000 187 i/o o o i/o vddeh4 / slow ? / up ? / up 70 p8 w15 emios9 etpua9_o sci_b_rx gpio[188] emios channel etpu a channel (output only) esci b receive gpio p a1 a2 g 001 010 100 000 188 i/o o i i/o vddeh4 / slow ? / up ? / up 71 r7 y15 emios10 dspi_d_pcs[3] rch3_b gpio[189] emios channel dspi d peripheral chip select reaction channel 3b gpio p a1 a2 g 001 010 100 000 189 i/o o o i/o vddeh4 / medium ? / wkpcfg ? / wkpcfg 73 n8 aa15 emios11 dspi_d_pcs[4] rch3_c gpio[190] emios channel dspi d peripheral chip select reaction channel 3c gpio p a1 a2 g 001 010 100 000 190 i/o o o i/o vddeh4 / medium ? / wkpcfg ? / wkpcfg 75 r8 ab15 emios12 dspi_c_sout etpua27_o gpio[191] emios channel dspi c data output etpu a channel (output only) gpio p a1 a2 g 001 010 100 000 191 i/o o o i/o vddeh4 / medium ? / wkpcfg ? / wkpcfg 76 n10 ab16 emios13 dspi_d_sout gpio[192] emios channel dspi d data output gpio p a1 g 01 10 00 192 i/o o i/o vddeh4 / medium ? / wkpcfg ? / wkpcfg 77 t8 aa16 emios14 irq[0] etpua29_o gpio[193] emios channel external interrupt request etpu a channel (output only) gpio p a1 a2 g 001 010 100 000 193 i/o i o i/o vddeh4 / slow ? / down ? / down 78 r9 y16 emios15 irq[1] gpio[194] emios channel external interrupt request gpio p a1 g 01 10 00 194 i/o i i/o vddeh4 / slow ? / down ? / down 79 t9 w16 emios16 gpio[195] emios channel gpio p g 01 00 195 i/o i/o vddeh4 / slow ? / up ? / up ? ? w17 emios17 gpio[196] emios channel gpio p g 01 00 196 i/o i/o vddeh4 / slow ? / up ? / up ? ? y17 emios18 gpio[197] emios channel gpio p g 01 00 197 i/o i/o vddeh4 / slow ? / up ? / up ? ? aa17 emios19 gpio[198] emios channel gpio p g 01 00 198 i/o i/o vddeh4 / slow ? / wkpcfg ? / wkpcfg ??ab17 table 3. MPC5642A signal properties (continued) name 1 function 2 p / a / g 3 pcr pa field 4 pcr 5 i/o type voltage 6 / pad type 7 status 8 package pin no. during reset after reset 176 208 324
pinout and signal description MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 45 emios20 gpio[199] emios channel gpio p g 01 00 199 i/o i/o vddeh4 / slow ? / wkpcfg ? / wkpcfg ??ab18 emios21 gpio[200] emios channel gpio p g 01 00 200 i/o i/o vddeh4 / slow ? / wkpcfg ? / wkpcfg ??aa18 emios22 gpio[201] emios channel gpio p g 01 00 201 i/o i/o vddeh4 / slow ? / down ? / down ? ? y18 emios23 gpio[202] emios channel gpio p g 01 00 202 i/o i/o vddeh4 / slow ? / down ? / down 80 r11 w18 emios14 15 gpio[203] emios channel gpio p g 01 00 203 o i/o vddeh7 / slow ? / down ? / down ? ? a15 emios15 15 gpio[204] emios channel gpio p g 01 00 204 o i/o vddeh7 / slow ? / down ? / down ? ? d14 clock synthesizer xtal crystal oscillator output p 01 ? o vddeh6 / analog ? ? 93 p16 v22 extal crystal oscillator input p 01 ? i vddeh6 / analog ? ? 92 n16 u22 clkout system clock output p 01 229 o vdde12 / fast ?clkout??ab9 engclk engineering clock output p 01 214 o vdde12 / fast ? engclk ? t14 w10 power / ground vddreg voltage regulator supply ? ? i 5 v i / ? vddreg 10 k16 f4 vrcctl voltage regulator control output ? ? o ? o / ? vrcctl 11 n14 f2 vrc33 17 internal regulator output ? ? o 3.3 v i/o / ? vrc33 13 a15, d1, n6, n12 b1, m19, p11 input for external 3.3 v supply ? ? i 3.3 v vdda eqadc high reference voltage ? ? i 5 v i / ? vdda 6 a4, b11 e3, a6 vssa eqadc ground/low reference voltage ? ? i ? i / ? vssa 7 a5, a11 a7, e2 vddpll fmpll supply voltage ? ? i 1.2 v i / ? vddpll 91 r16 w22 vstby power supply for standby ram ? ? i 0.9 v ? 6 v i / ? vstby 12 c1 e4 table 3. MPC5642A signal properties (continued) name 1 function 2 p / a / g 3 pcr pa field 4 pcr 5 i/o type voltage 6 / pad type 7 status 8 package pin no. during reset after reset 176 208 324
MPC5642A microcontroller data sheet, rev. 3.1 pinout and signal description freescale semiconductor 46 vdd core supply for input or decoupling ? ? i 1.2 v i / ? vdd 33, 45, 62, 103, 132, 149, 176 b1, b16, c2, d3, e4, n5, p4, p13, r3, r14, t2, t15 a2, a20, a21, b3, c4, c22, d5, w20, y4, y21, aa3, aa22 vdde12 external supply input for calibration bus interfaces ? ? i 3.0 v ? 3.6 v i / ? vdde12 ? ? ? vdde5 external supply input for engclk and clkout ? ? i 3.0 v ? 3.6 v i / ? vdde5 ? t13 n11, w5, w8 vdde-eh external supply for ebi interfaces ? ? i 3.0 v ? 5.0 v i / ? vdde-eh ? ? r3, v2 vddeh1a 18 i/o supply input ? ? i 3.3 v ? 5.0 v i / ? vddeh1a 18 31 ? ? vddeh1b 18 i/o supply input ? ? i 3.3 v ? 5.0 v i / ? vddeh1b 18 41 ? ? vddeh1ab 18 i/o supply input ? ? i 3.3 v ? 5.0 v i / ? vddeh1ab 18 ?k4k4 vddeh4 19 i/o supply input ? ? i 3.3 v ? 5.0 v i / ? vddeh4 19 ??? vddeh4a 19 i/o supply input ? ? i 3.3 v ? 5.0 v i / ? vddeh4a 19 55 ? ? vddeh4b 19 i/o supply input ? ? i 3.3 v ? 5.0 v i / ? vddeh4b 19 74 ? ? vddeh4ab 19 i/o supply input ? ? i 3.3 v ? 5.0 v i / ? vddeh4ab 19 ? n9 w14, aa19 vddeh6 20 i/o supply input ? ? i 3.3 v ? 5.0 v i / ? vddeh6 20 ??? vddeh6a 20 i/o supply input ? ? i 3.3 v ? 5.0 v i / ? vddeh6a 20 95 ? ? vddeh6b 20 i/o supply input ? ? i 3.3 v ? 5.0 v i / ? vddeh6b 20 110 ? ? vddeh6ab 20 i/o supply input ? ? i 3.3 v ? 5.0 v i / ? vddeh6ab 20 ? f13 m22, u19 table 3. MPC5642A signal properties (continued) name 1 function 2 p / a / g 3 pcr pa field 4 pcr 5 i/o type voltage 6 / pad type 7 status 8 package pin no. during reset after reset 176 208 324
pinout and signal description MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 47 vddeh7 21 i/o supply input ? ? i 3.3 v ? 5.0 v i / ? vddeh7 ? d12 b22, c21, d15, d20, e19, f19, h19, j14 vddeh7a 21 i/o supply input ? ? i 3.3 v ? 5.0 v i / ? vddeh7a 125 ? ? vddeh7b 21 i/o supply input ? ? i 3.3 v ? 5.0 v i / ? vddeh7b 138 ? ? vss ground ? ? i ? i / ? vss 15, 29, 43, 57, 72, 90, 94, 96, 108, 115, 127, 133, 140 a1, a16, b2, b15, c3, c14, d4, d13, g7, g8, g9, g10, h7, h8, h9, h10, j7, j8, j9, j10, k7, k8, k9, k10, m16, n4, n13, p3, p14, r2, r15, t1, t16 a1, a22, b2, b21, c3, c20, d4, d17, d19, f21, h21, j9, j10, j11, j12, j13, k9, k10, k11, k12, k13, k14, l9, l10, l11, l12, l13, l14, l21, m11, m12, m13, m14, n9, n10, n12, n13, n14, n21, p9, p10, p12, p13, p14, t19, t21, t22, w4, y3, y20, aa21, ab1, ab22 1 the suffix ?_o? identifies an output-only etpu channel 2 for each pin in the table, each line in the function column is a separate function of the pin. for all i/o pins the selection o f primary pin function or secondary function or gpio is done in the siu except where explicitly noted. see the signal details table for a description of each signa l. 3 the p/a/g column indicates the position a signal occupies in the muxing order for a pin?primary, alternate 1, alternate 2, alte rnate 3, or gpio. signals are selected by setting the pa field value in the appropriate pcr re gister in the siu module. the pa field values are as follows: p - 0b0001, a1 - 0b0010, a2 - 0b0100, a3 - 0b1000, or g - 0b0000. depending on the register, the pa field size can vary in length. for pa fields having fewer than four bits, remove the appropriate number of leading zeroes from these values. 4 the pad configuration register (pcr) pa field is used by software to select pin function. 5 values in the pcr column refer to registers in the system integr ation unit (siu). the actual register name is ?siu_pcr? suffixe d by the pcr number. for example, pcr[190] refers to t he siu register named siu_pcr190. 6 the vdde and vddeh supply inputs are broken into segments. each segment of slow i/o pins (vddeh) may have a separate supply in the 3.3 v to 5.0 v range ( ? 10%/+5%). each segment of fast i/o (vdde) may have a separate supply in the 1.8 v to 3.3 v range (+/ ? 10%). table 3. MPC5642A signal properties (continued) name 1 function 2 p / a / g 3 pcr pa field 4 pcr 5 i/o type voltage 6 / pad type 7 status 8 package pin no. during reset after reset 176 208 324
MPC5642A microcontroller data sheet, rev. 3.1 pinout and signal description freescale semiconductor 48 7 see ta bl e 4 for details on pad types. 8 the status during reset pin is sampled after the internal por is negated. prior to exiting por, the signal has a high impedance . terminology is o (output), i (input), up (weak pull up enabled), down (weak pull down enabl ed), low (output driven low), high (output driven high). a dash for the function in this column denotes that both the input and output buffer are turned off. th e signal name to the left or ri ght of the slash indicates the p in is enabled. 9 when used as etrig, this pin must be configured as an input. for gpio it can be configured either as an input or output. 10 maximum frequency is 50 khz 11 pcr219 controls two different pins: mcko and gpio[219]. please refer to pad configuration register 219 section in siu chapter o f device reference manual for details. 12 on 176 lqfp and 208 mapbga packages, this pin is tied low internally. 13 these pins are selected by asserting jcomp and configuring the np c. siu values have no effect on the function of this pin once enabled. 14 the bam uses this pin to select if auto baud rate is on or off. 15 output only 16 this signal name is used to support legacy naming. 17 do not use vrc33 to drive external circuits. 18 vddeh1a, vddeh1b and vddeh1ab are shorted together in all production packages. the se paration of the signal names is present to support legacy naming, however they should be considered as the same signal in this document. 19 vddeh4, vddeh4a, vddeh4b and vddeh4ab are shorted together in a ll production packages. the separat ion of the signal names is pr esent to support legacy naming, however they should be considered as the same signal in this document. 20 vddeh6, vddeh6a, vddeh6b and vddeh6ab are shorted together in a ll production packages. the separat ion of the signal names is pr esent to support legacy naming, however they should be considered as the same signal in this document. 21 vddeh7, vddeh7a and vdde7b are shorted toge ther in all production packages. the separation of the signal names is present to su pport legacy naming, however they should be considered as the same signal in this document.
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 49 pinout and signal description 2.5 signal details table 4. pad types pad type name i/o voltage range slow pad_ssr_hv 3.0v - 5.5 v medium pad_msr_hv 3.0 v - 5.5 v fast pad_fc 3.0 v - 3.6 v multiv 1,2 1 multivoltage pads are automatically configured in low swing mode when a jtag or nexus function is selected, otherwise they are high swing. 2 vddeh7 supply cannot be below 4.5 v when in low-swing mode. pad_multv_hv 3.0 v - 5.5 v (high swing mode) 3.0 v - 3.6 v (low swing mode) analog pad_ae_hv 0.0 - 5.5 v lvds pad_lo_lv ? table 5. signal details signal module or function description clkout clock generation MPC5642A clock output for the calibration bus interface engclk clock generation clock for external asic devices extal clock generation input pin for an external crystal oscillator or an external clock source based on the value driven on the pllref pin at reset pllref clock generation reset/configuration pllref is used to select wh ether the oscillator operates in xtal mode or external reference mode from reset. pllref = 0 selects external reference mode. on the 324 tepbga package, pllref is bonded to the ball used for pllcfg[0] for compatibility with mpc55xx devices. for the 176-pin qfp and 208-ball bga packages: 0: external reference clock is selected 1: xtal oscillator mode is selected for the 324-ball bga package: if rstcfg is 0: 0: external reference clock is selected 1: xtal oscillator mode is selected if rstcfg is 1, xtal oscillator mode is selected. xtal clock generation crystal oscillator input dspi_b_sck_lvds ? dspi_b_sck_lvds+ dspi lvds pair used for dspi_b tsb mode transmission dspi_b_sout_lvds ? dspi_b_sout_lvds+ dspi lvds pair used for dspi_b tsb mode transmission
MPC5642A microcontroller data sheet, rev. 3.1 50 freescale semiconductor pinout and signal description dspi_c_sck_lvds ? dspi_c_sck_lvds+ dspi lvds pair used for dspi_c tsb mode transmission dspi_c_sout_lvds ? dspi_c_sout_lvds+ dspi lvds pair used for dspi_c tsb mode transmission dspi_b_pcs[0] dspi_c_pcs[0] dspi_d_pcs[0] dspi_b ? dspi_d peripheral chip select when device is in master mode?slave select when used in slave mode dspi_b_pcs[1:5] dspi_c_pcs[1:5] dspi_d_pcs[1:5] dspi_b ? dspi_d peripheral chip select when device is in master mode?not used in slave mode dspi_b_sck dspi_c_sck dspi_d_sck dspi_b ? dspi_d dspi clock?output when device is in master mode; input when in slave mode dspi_b_sin dspi_c_sin dspi_d_sin dspi_b ? dspi_d dspi data in dspi_b_sout dspi_c_sout dspi_d_sout dspi_b ? dspi_d dspi data out emios[0:23] emios emios i/o channels an[0:39] eqadc single-ended analog inputs for analog-to-digital converter an[0:7]/dan+ eqadc differential analog input pair for analog-to-digital converter with pull-up/pull-down functionality an[0:7]/dan ? eqadc differential analog input pair for analog-to-digital converter with pull-up/pull-down functionality fck eqadc eqadc free running clock for eqadc ssi ma[0:2] eqadc these three control bits are output to enable the selection for an external analog mux for expansion channels. refbypc eqadc bypass capacitor input sdi eqadc serial data in sdo eqadc serial data out sds eqadc serial data select vrh eqadc voltage reference high input vrl eqadc voltage reference low input sci_a_rx sci_b_rx sci_c_rx esci_a ? esci_c esci receive sci_a_tx sci_b_tx sci_c_tx esci_a ? esci_c esci transmit etpu_a[0:31] etpu etpu i/o channel table 5. signal details (continued) signal module or function description
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 51 pinout and signal description rch0_[a:c] rch1_[a:c] rch2_[a:c] rch3_[a:c] rch4_[a:c] rch5_[a:c] etpu2 reaction module etpu2 reaction channels. used to control external actuators, e.g., solenoid control for dire ct injection systems and valve control in automatic transmissions tcrclka etpu2 input clock for tcr time base can_a_tx can_b_tx can_c_tx flexcan_a ? flexcan_c flexcan transmit can_a_rx can_b_rx can_c_rx flexcan_a ? flexcan_c flexcan receive fr_a_rx fr_b_rx flexray flexray receive (channels a, b) fr_a_tx_en fr_b_tx_en flexray flexray transmit enable (channels a, b) fr_a_tx fr_b_tx flexray flexray transmit (channels a, b) jcomp jtag enables the jtag tap controller tck jtag clock input for the on-chip test logic tdi jtag serial test instruction and data input for the on-chip test logic tdo jtag serial test data output for the on-chip test logic tms jtag controls test mode operations for the on-chip test logic evti nexus evti is an input that is read on the negation of reset to enable or disable the nexus debug port. after reset, the evti pin is used to initiate program synchronization messages or generate a breakpoint. evto nexus output that provides timing to a development tool for a single watchpoint or breakpoint occurrence mcko nexus mcko is a free running cl ock output to the development tools which is used for timing of the mdo and mseo signals. mdo[0:11] nexus trace message output to development tools. this pin also indicates the status of the cryst al oscillator clock following a power-on reset, when mdo[0] is driven high until the crystal oscillator clock achieves stability and is then negated. mseo [0:1] nexus output pin?indicates the start or end of the variable length message on the mdo pins rdy nexus nexus ready output (rdy)?indicates to the development tools that data is ready to be re ad from or written to the nexus read/write access registers. table 5. signal details (continued) signal module or function description
MPC5642A microcontroller data sheet, rev. 3.1 52 freescale semiconductor pinout and signal description bootcfg[0:1] siu ? c onfiguration two bootcfg signal s are implemented in MPC5642A mcus. the bam program uses the bootcfg0 bit to determine where to read the reset confi guration word, and whether to initiate a flexcan or esci boot. the bootcfg1 pin is sampled during the assertion of the rstout signal, and the value is used to update the rsr and the bam boot mode. see reference manual section ?reset configuration half word (rchw)? for details on the rchw. the table ?boot modes? in reference manual section ?bam program operation? defines the boot modes specified by the bootcfg1 pin. the following values are for bootcfg[0:1}: 00: boot from internal flash memory 01: flexcan/esci boot 10: boot from external memory using calibration bus 11: reserved note: for the 176-pin qfp and 208-ball bga packages bootcfg[0] is always 0 sinc e the ebi interface is not available. wkpcfg siu ? configuration the wkpcfg pin is applied at the assertion of the internal reset signal (assertion of rstout ), and is sampled four clock cycles before the negation of the rstout pin. the value is used to configure whether the etpu and emios pins are connected to internal weak pull up or weak pull down devices after reset. the value latched on the wkpcfg pin at reset is stored in the reset status register (rsr), and is updated for all reset sources except the debug port reset and software external reset. 0: weak pulldown applied to etpu and emios pins at reset 1: weak pullup applied to etpu and emios pins at reset etrig[2:3] siu ? eqadc triggers external signal etrigx triggers eqadc cfifox gpio[206] etrig0 (input) siu ? eqadc triggers external signal etrigx triggers eqadc cfifox gpio[207] etrig1 (input) siu ? eqadc triggers external signal etrigx triggers eqadc cfifox irq[0:5] irq[7:15] siu ? external interrupts the irq[0:15] pins connect to the siu irq inputs. imux select register 1 is used to sele ct the irq[0:15] pins as inputs to the irqs. see reference manual section ?external irq input select register (siu_eiisr)? for more information. nmi siu ? external interrupts non-maskable interrupt table 5. signal details (continued) signal module or function description
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 53 pinout and signal description gpio[12:17] gpio[75:110] gpio[113:145] gpio[179:204] gpio[206:213] gpio[219] gpio[244:245] siu ? gpio configurable general purpose i/o pins. each gpio input and output is separately controlled by an 8-bit input (gpdi) or output (gpdo) register. additionally, each gpio pin is configured using a dedicated siu_pcr register. the gpio pins are generally multiplexed with other i/o pin functions. see the following reference manual sections for more information: ? ?pad configuration registers (siu_pcr)? ? ?gpio pin data output registers (siu_gpdo0_3 ? siu_gpdo412_413)? ? ?gpio pin data input registers (siu_gpdi0_3 ? siu_gpdi_232)? reset siu ? reset the reset pin is an active low input. the reset pin is asserted by an external device during a power-on or external reset. the internal reset si gnal asserts only if the reset pin asserts for 10 clock cycles. assertion of the reset pin while the device is in reset causes the reset cycle to start over. the reset pin has a glitch detector which detects spikes greater than two clock cycles in duration that fall below the switch point of the input buffer logic of the vddeh input pins. the switch point lies between the maximum vil and minimum vih specifications for the vddeh input pins. rstcfg siu ? reset used to enable or disable the pllref and the bootcfg[0:1] conf iguration signals. 0: get configuration informat ion from bootcfg[0:1] and pllref 1: use default configuration of booting from internal flash with crystal clock source note: for the 176-pin qfp and 208-ball bga packages rstcfg is always 0, so pllref and bootcfg signals are used. rstout siu ? reset the rstout pin is an active low output that uses a push/pull configuration. the rstout pin is driven to the low state by the mcu for all internal and external reset sources. there is a delay between initiation of the reset and the assertion of the rstout pin. see reference manual section ?rstout? for details. table 5. signal details (continued) signal module or function description
MPC5642A microcontroller data sheet, rev. 3.1 54 freescale semiconductor pinout and signal description table 6. power/ground segmentation power segment voltage i/o pins powered by segment vdde5 3.0 v ? 3.6 v data[0:15], clkout, engclk vdde12 3.0 v ? 3.6 v cal_cs0, cal_cs2, cal_ cs3, cal_addr[12:3 0], cal_data[0:15], cal_rd_wr, cal_we0, cal_we1, cal_oe, cal_ts vdde-eh 3.0 v ? 5.5 v fr_a_tx, fr_a_tx_en, fr_a_rx, fr_b_tx, fr_b_tx_en, fr_b_rx vddeh1 3.3 v ? 5.5 v etpua[10:31] vddeh4 3.3 v ? 5.5 v emios[0:23], tcrclka, etpua[0:9] vddeh6 3.3 v ? 5.5 v reset , rstout , pllref, pllcfg1, rstcfg, bootcfg0, bootcfg1, wkpcfg, can_a_tx, can_a_rx, ca n_b_tx, can_b_rx, can_c_tx, can_c_rx, sci_a_tx, sci_a_rx, sci_b_tx, sci_b_rx, sci_c_tx, sci_c_rx, dspi_b_sck, dspi_b_sin, dspi_b_sout, dspi_b_pcs[0:5], extal, xtal vddeh7 3.3 v ? 5.5 v emios14, emios15, gpio[98:9 9], gpio[203:204], gpio [206], gpio[207], gpio[219], evti, evto, mdo[4:11], m seo0, mseo1, rdy, tck, tdi, tdo, tms, jcomp, dspi_a_sck, dspi_a_sin , dspi_a_sout, dspi_a_pcs[0:1], dspi_a_pcs[4:5], an12-sds, an13-sdo, an14-sdi, an15-fck vdda 5.0 v an[0:11], an[16: 39], vrh, vrl, refbybc vrc33 3.3 v mcko, mdo[0:3] other power segments vddreg 5.0 v ? vrcctl ? ? vddpll 1.2 v ? vstby 0.9 v ? 6.0 v ? vss ? ?
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 55 electrical characteristics 3 electrical characteristics this section contains detailed information on power cons iderations, dc/ac electrical ch aracteristics, and ac timing specifications for the MPC5642A series of mcus. the electrical specifications are preliminary and are from prev ious designs, design simulations, or initial evaluation. these specifications may not be fully tested or guaranteed at this early stage of the pro duct life cycle, however for production sili con these specifications will be met. finali zed specifications will be published afte r complete characterization and device qualifications have been completed. in the tables where the device lo gic provides signals with their respective timing characteristics, the symbol ?cc? for control ler characteristics is included in the symbol column. in the tables where the external system mu st provide signals with their respective timing characteristics to the device, the sy mbol ?sr? for system requirement is included in the symbol column. 3.1 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding, the classifications listed in table 7 are used and the parameters are ta gged accordingly in the tables where appropriate. note the classification is shown in the column labeled ?c? in the parameter tables where appropriate. table 7. paramete r classifications classification ta g tag description p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations.
MPC5642A microcontroller data sheet, rev. 3.1 56 freescale semiconductor electrical characteristics 3.2 maximum ratings table 8. absolute maximum ratings 1 1 functional operating conditions are given in the dc electr ical specifications. absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. symbol parameter conditions value unit min max v dd sr 1.2 v core supply voltage 2 2 allowed 2 v for 10 hours cumulative time, remaining time at 1.2 v + 10% ?0.3 1.32 v v flash sr flash core voltage 3,4 3 the v flash supply is connected to v rc33 in the package substrate. this specification applies to calibration package devices only. 4 allowed 5.3 v for 10 hours cumulative time, remaining time at 3.3 v + 10% ?0.3 3.6 v v stby sr sram standby voltage 5 5 allowed 5.9 v for 10 hours cumulative time, remaining time at 5 v + 10% ?0.3 6.0 v v ddpll sr clock synthesizer voltage 3 ?0.3 1.32 v v rc33 sr voltage regulator control input voltage 4 ?0.3 3.6 v v dda sr analog supply voltage 5 reference to v ssa ?0.3 5.5 v v dde sr i/o supply voltage 4,6 ?0.3 3.6 v v ddeh sr i/o supply voltage 5,7 ?0.3 5.5 v v in sr dc input voltage 8 v ddeh powered i/o pads ?1.0 10 v ddeh + 0.3 v 9 v v dde powered i/o pads ?1.0 14 v dde + 0.3 v 10 v dda powered i/o pads ?1.0 5.5 v ddreg sr voltage regulator supply voltage ?0.3 5.5 v v rh sr analog reference high voltage reference to vrl ?0.3 5.5 v v ss ? v ssa sr v ss differential voltage ?0.1 0.1 v v rh ? v rl sr v ref differential voltage ?0.3 5.5 v v rl ? v ssa sr v rl to v ssa differential voltage ?0.3 0.3 v v sspll ? v ss sr v sspll to v ss differential voltage ?0.1 0.1 v i maxd sr maximum dc digital input current 11 per pin, applies to all digital pins ?3 3 ma i maxa sr maximum dc analog input current 12 per pin, applies to all analog pins ?5 13 ma t j sr maximum operating temperature range ? die junction temperature ?40.0 150.0 o c t stg sr storage temperature range ?55 150 c t sdr sr maximum solder temperature 14 ? 260 c msl sr moisture sensitivity level 15 ?3?
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 57 electrical characteristics 6 all functional non-supply i/o pins are clamped to v ss and v dde , or v ddeh . 7 internal structures hold the voltage greater than ?1 .0 v if the injection current limit of 2 ma is met. 8 ac signal overshoot and undershoot of up to 2.0 v of the in put voltages is permitted for an accumulative duration of 60 hours over the complete lifetime of the device (injection current not limited for this duration). 9 internal structures hold the input voltage less than the maximum voltage on all pads powered by v ddeh supplies, if the maximum injection current specificat ion is met (2 ma for all pins) and v ddeh is within the operating voltage specifications. 10 internal structures hold the input voltage less than the maximum voltage on all pads powered by v dde supplies, if the maximum injection current specificat ion is met (2 ma for all pins) and v dde is within the operating voltage specifications. 11 total injection current for all pins (including both digital and analog) must not exceed 25 ma. 12 total injection current for all analog input pins must not exceed 15 ma. 13 lifetime operation at these specif ication limits is not guaranteed. 14 solder profile per ipc/jedec j-std-020d 15 moisture sensitivity per jedec test method a112
MPC5642A microcontroller data sheet, rev. 3.1 58 freescale semiconductor electrical characteristics 3.3 thermal characteristics table 9. thermal characteristics for 176-pin lqfp 1 1 thermal characteristics are targets based on simulation th at are subject to change per device characterization. symbol c parameter conditions value unit r ? ja cc d junction-to-ambient, natural convection 2 2 junction-to-ambient thermal resistance determined per jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. single-layer board ? 1s 38 c/w r ? ja cc d junction-to-ambient, natural convection 2 four-layer board ? 2s2p 31 c/w r ? jma cc d junction-to-moving-air, ambient 2 at 200 ft./min., single-layer board ? 1s 30 c/w cc d at 200 ft./min., four-layer board ? 2s2p 25 c/w r ? jb cc d junction-to-board 3 3 junction-to-board thermal resistanc e determined per jedec jesd51-8. thermal test board meets jedec specification for the specified package. 20 c/w r ? jctop cc d junction-to-case 4 4 junction-to-case at the top of the package determi ned using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported va lue includes the thermal resistance of the interface layer. 5c/w ? jt cc d junction-to-package top, natural convection 5 5 thermal characterization parameter indicating the te mperature difference between the package top and the junction temperature per jedec jesd51-2. when greek le tters are not available, the thermal characterization parameter is written as psi-jt. 2c/w table 10. thermal characteristics for 208-pin mapbga 1, 1 thermal characteristics are targets based on simulation th at are subject to change per device characterization. symbol c parameter conditions value unit r ? ja cc d junction-to-ambient, natural convection 2 2 junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. single layer board ? 1s 3 3 per semi g38-87 and jedec jesd51-2 with the single-layer board horizontal 39 c/w cc d four layer board ? 2s2p 4 4 per jedec jesd51-6 with the board horizontal 24 c/w r ? jma cc d junction-to-moving-air, ambient 2 at 200 ft./min., single-layer board ? 1s 4 31 c/w cc d at 200 ft./min., four-layer board ? 2s2p 20 c/w r ? jb cc d junction-to-board 5 5 thermal resistance between the die and the printed circ uit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. four-layer board ? 2s2p 13 c/w r ? jc cc d junction-to-case 6 6 indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1) with the cold plate temperature used for the case temperature. 6c/w ? jt cc d junction-to-package top natural convection 7 2c/w
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 59 electrical characteristics 3.3.1 general notes for specification s at maximum junction temperature an estimation of the chip junction temperature, t j , can be obtained from equation 1 : t j = t a + (r ? ja * p d ) eqn. 1 where: t a = ambient temperature for the package (c) r ? ja = junction-to-ambient thermal resistance (c/w) p d = power dissipation in the package (w) the thermal resistance values used are based on the jedec jesd 51 series of standards to provide consistent values for estimations and comparisons. th e difference between the values determined fo r the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a grou nd plane (2s2p), demonstrate that the effective thermal resistan ce is not a constant. the therma l resistance depends on the: ? construction of the application board (number of planes) ? effective size of the boar d which cools the component ? quality of the thermal and elect rical connections to the planes ? power dissipated by adjacent components connect all the ground and power balls to the respective planes with one via per ball. using fewer vias to connect the package to the planes reduces the thermal perfor mance. thinner planes also reduce the thermal performance. when the clearance between the vias leave the planes virtually disconnected, the thermal pe rformance is also greatly reduced. 7 thermal characterization parameter indicating the temper ature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt. table 11. thermal characteristics for 324-pin tepbga 1 1 thermal characteristics are targets based on simulation th at are subject to change per device characterization. symbol c parameter conditions value unit r ? ja cc d junction-to-ambient, natural convection 2 2 junction-to-ambient thermal resistance determined per jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. single-layer board ? 1s 29 c/w cc d four-layer board ? 2s2p 19 c/w r ? jma cc d junction-to-moving-air, ambient 2 at 200 ft./min., single-layer board ? 1s 23 c/w cc d at 200 ft./min., four-layer board ? 2s2p 16 c/w r ? jb cc d junction-to-board 3 3 junction-to-board thermal resistanc e determined per jedec jesd51-8. thermal test board meets jedec specification for the specified package. 10 c/w r ? jctop cc d junction-to-case 4 4 junction-to-case at the top of the package determi ned using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported va lue includes the thermal resistance of the interface layer. 7c/w ? jt cc d junction-to-package top, natural convection 5 5 thermal characterization parameter indicating the te mperature difference between the package top and the junction temperature per jedec jesd51-2. when greek le tters are not available, the thermal characterization parameter is written as psi-jt. 2c/w
MPC5642A microcontroller data sheet, rev. 3.1 60 freescale semiconductor electrical characteristics as a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. the value obtained on a board with the internal planes is usually within the normal range if the application board has: ? one oz. (35 micron nominal thickness) internal planes ? components that are well separated ? overall power dissipation on the board is less than 0.02 w/cm 2 the thermal performance of any component depends on the power dissipation of the surrounding components. in addition, the ambient temperature varies widely within the application. for many natural co nvection and especially closed-box applications, the board temperature at the perimeter (edge ) of the package is approxim ately the same as the loca l air temperature near the device. specifying the local ambi ent conditions explicitly as th e board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. at a known board temperature, the junction temperature is estimated using equation 2 : t j = t b + (r ? jb * p d ) eqn. 2 where: t b = board temperature for th e package perimeter (c) r ? jb = junction-to-board thermal re sistance (c/w) per jesd51-8s p d = power dissipation in the package (w) when the heat loss from the package case to the air does not factor in to the calculation, an accep table value for the junction temperature is predictable. ensure the appl ication board is similar to the thermal te st condition, with the component soldered to a board with internal planes. the thermal resistance is expressed as the sum of a junctio n-to-case thermal resistance pl us a case-to-ambient thermal resistance: r ? ja = r ? jc + r ? ca eqn. 3 where: r ? ja = junction-to-ambient thermal resistance (c/w) r ? jc = junction-to-case thermal resistance (c/w) r ? ca = case to ambient thermal resistance (c/w) r ? jc is device-related and is not affected by other factors. the thermal environment can be controlled to change the case-to-ambient thermal resistance, r ? ca . for example, change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. this description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient. for most pack ages, a better model is required. a more accurate two-resistor thermal model can be construc ted from the junction-to-board thermal resistance and the junction-to-case thermal resistance. the junction-to-case thermal resistance descri bes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. the junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the pr inted circuit board. this model can be used to generate simple estimations and for computational fluid dynamics (cfd) thermal models. to determine the junction temperature of th e device in the application on a prototyp e board, use the thermal characterization parameter ( ? jt ) to determine the junction temperature by measuring the temperature at the top cente r of the package case using equation 4 : t j = t t + ( ? jt x p d ) eqn. 4 where: t t = thermocouple temperature on top of the package (c)
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 61 electrical characteristics ? jt = thermal characterization parameter (c/w) p d = power dissipation in the package (w) the thermal characterization parameter is measured in compli ance with the jesd51-2 specificat ion using a 40-gauge type t thermocouple epoxied to the top center of the package case. positio n the thermocouple so that the thermocouple junction rests on the package. place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. place the thermocoup le wire flat against the package case to avoi d measurement errors caused by the cooling effects of the thermocouple wire. references: ? semiconductor equipment and materials international 3081 zanker road san jose, ca 95134 usa phone (+1) 408-943-6900 ? mil-spec and eia/jesd (jedec) speci fications available from global engineering documents (phone (+1) 800-854-7179 or (+1) 303-397-7956) ? jedec specifications available on the web at http://www.jedec.org ? c.e. triplett and b. joiner, ? an experimental characterization of a 272 pbga within an automotive engine controller module ,? proceedings of semitherm, san diego, 1998, pp. 47-54. ? g. kromann, s. shidore, and s. addison, ? thermal modeling of a pbga for air-cooled applications ?, electronic packaging and production, pp. 53-58, march 1998. ? b. joiner and v. adams, ? measurement and simulation of junction to board thermal resistance and its application in thermal modeling ,? proceedings of semitherm, san diego, 19 99, pp. 212-220. 3.4 emi (electromagnetic interference) characteristics table 12. emi testing specifications 1 1 emi testing and i/o port waveforms per standard iec 61967-2. symbol parameter conditions f osc /f bus frequency level (max) unit v re_tem radiated emissions, electric field v dd =5.25v; t a =+25c 150 khz?30 mhz ? rbw 9 khz, step size 5khz 30 mhz?1 ghz ? rbw 120 khz, step size 80 khz 16 mhz crystal 40 mhz bus no pll frequency modulation 150 khz?50 mhz 20 dbv 50?150 mhz 20 150?500 mhz 26 500?1000 mhz 26 iec level k ? sae level 3 ? 16 mhz crystal 40 mhz bus 2% pll frequency modulation 150 khz?50 mhz 13 dbv 50?150 mhz 13 150?500 mhz 11 500?1000 mhz 13 iec level l ? sae level 2 ?
MPC5642A microcontroller data sheet, rev. 3.1 62 freescale semiconductor electrical characteristics 3.5 electrostatic discharge (esd) characteristics 3.6 power management control (pmc) and power on reset (por) electrical specifications table 13. esd ratings 1,2 1 all esd testing is in conformity with cdf-aec-q100 stre ss test qualification for au tomotive grade integrated circuits. 2 device failure is defined as: ?if after exposure to esd pulses, the device does not meet the device specification requirements, which includes the complete dc parametric and functional testing at room temperature and hot temperature.? symbol parameter conditions value unit ? sr esd for human body model (hbm) ? 2000 v r1 sr hbm circuit description ? 1500 ? csr ? 100 pf ? sr esd for field induced charge model (fdcm) all pins 500 v corner pins 750 ? sr number of pulses per pin positive pulses (hbm) 1 ? negative pulses (hbm) 1 ? ? sr number of pulses ? 1 ? table 14. pmc operating conditions and external regulators supply voltage id name c parameter value unit min typ max 1t j sr ? junction temperature ?40 27 150 c 2v ddreg sr ? pmc 5 v supply voltage vddreg 4.75 5 5.25 v 3v dd cc c core supply voltage 1.2 v vdd when external regulator is used without disabling the internal regulator (pmc unit turned on, lvi monitor active) 1 1 an internal regulator controller can be used to regulate the core supply. 1.26 2 2 the minimum supply required for the part to ex it reset and enter in normal run mode is 1.28 v. 1.3 1.32 v 3a ? cc c core supply voltage 1.2 v vdd when external regulator is used with a disabled internal regulator (pmc unit turned-off, lvi monitor disabled) 1.14 1.2 1.32 v 4i vdd cc c voltage regulator core supply maximum required dc output current 400 ? ? ma 5v dd33 cc c regulated 3.3 v supply voltage when external regulator is used without disabling the internal regulator (pmc unit turned-on, internal 3.3v regulator enabled, lvi monitor active) 3 3 an internal regulator can be used to regulate the 3.3 v supply. 3.3 3.45 3.6 v 5a ? cc c regulated 3.3 v supply voltage when external regulator is used with a disabled internal regulator (pmc unit turned-off, lvi monitor disabled) 33.33.6v 6 ? cc c voltage regulator 3.3 v supply maximum required dc output current 80 ? ? ma
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 63 electrical characteristics table 15. pmc electrical characteristics id name c parameter value unit min typ max 1v bg cc c nominal bandgap voltage reference ? 1.219 ? v 1a ? cc c untrimmed bandgap reference voltage v bg ?? ? %v bg v bg +6% v 1b ? cc c trimmed bandgap reference voltage (5 v, 27 c) v bg ? ? 10mv v bg v bg + 10mv v 1c ? cc c bandgap reference tem perature variation ? 100 ? ppm/c 1d ? cc c bandgap reference supply voltage variation ? 3000 ? ppm/v 2v dd cc c nominal v dd core supply internal regulator target dc output voltage 1 ?1.28?v 2a ? cc c nominal v dd core supply internal regulator target dc output voltage variation at power-on reset v dd ?? 6% v dd v dd + 10% v 2b ? cc c nominal v dd core supply internal regulator target dc output voltage variation after power-on reset v dd ? 10% 2 v dd v dd +3% v 2c ? cc c trimming step v dd ?20?mv 2d i vrcctl cc c voltage regulator controller for core supply maximum dc output current 20 ? ? ma 3 lvi1p2 cc c nominal lvi for rising core supply 3 ? 1.160 ? v 3a ? cc c variation of lvi for rising core supply at power-on reset 4 1.120 1.200 1.280 v 3b ? cc c variation of lvi for rising core supply after power-on reset 4 lvi1p2 ? 3% lvi1p2 lvi1p2 +3% v 3c ? cc c trimming step lvi core supply ? 20 ? mv 3d lvi1p2_h cc c lvi core supply hysteresis ? 40 ? mv 4 por1.2v_r cc c por 1.2 v rising ? 0.709 ? v 4a ? cc c por 1.2 v rising variation por1.2v_r ? 35% por1.2v_r por1.2v_r +35% v 4b por1.2v_f cc c por 1.2 v falling ? 0.638 ? v 4c ? cc c por 1.2 v falling variation por1.2v_f ? 35% por1.2v_f por1.2v_f +35% v 5v dd33 cc c nominal 3.3 v supply internal regulator dc output voltage ?3.39?v 5a ? cc c nominal 3.3 v supply internal regulator dc output voltage variation at power-on reset v dd33 ? ? 8.5% v dd33 v dd33 +7% v 5b ? cc c nominal 3.3 v supply internal regulator dc output voltage variation after power-on reset 5 v dd33 ? ? 7.5% v dd33 v dd33 +7% v 5c ? cc c voltage regulator 3.3 v output impedance at maximum dc load ?? 2 ?
MPC5642A microcontroller data sheet, rev. 3.1 64 freescale semiconductor electrical characteristics 5d idd3p3 cc c voltage regulator 3.3 v maximum dc output current 80 ? ? ma 5e vdd33 ilim cc c voltage regulator 3.3 v dc current limit ? 130 ? ma 6 lvi3p3 cc c nominal lvi for rising 3.3 v supply 6 ? 3.090 ? v 6a ? cc c variation of lvi for rising 3.3 v supply at power-on reset 7 lvi3p3 ? 6% lvi3p3 lvi3p3 +6% v 6b ? cc c variation of lvi for rising 3.3 v supply after power-on reset 7 lvi3p3 ? ? 3% lvi3p3 lvi3p3 +3% v 6c ? cc c trimming step lvi 3.3 v ? 20 ? mv 6d lvi3p3_h cc c lvi 3.3 v hysteresis ? 60 ? mv 7 por3.3v_r cc c nominal por for rising 3.3 v supply 8 ?2.07?v 7a ? cc c variation of por for rising 3.3 v supply por3.3v_r ? 35% por3.3v_r por3.3v_r +35% v 7b por3.3v_f cc c nominal por for falling 3.3 v supply ? 1.95 ? v 7c ? cc c variation of por for falling 3.3 v supply por3.3v_f ? 35% por3.3v_f por3.3v_f +35% v 8 lvi5p0 cc c nominal lvi for rising 5 v vddreg supply ? 4.290 ? v 8a ? cc c variation of lvi for rising 5 v vddreg supply at power-on reset lvi5p0 ? 6% lvi5p0 lvi5p0 +6% v 8b ? cc c variation of lvi for rising 5 v vddreg supply power-on reset lvi5p0 ? 3% lvi5p0 lvi5p0 +3% v 8c ? cc c trimming step lvi 5 v ? 20 ? mv 8d lvi5p0_h cc c lvi 5 v hysteresis ? 60 ? mv 9 por5v_r cc c nominal por for rising 5 v vddreg supply ? 2.67 ? v 9a ? cc c variation of por for rising 5 v vddreg supply por5v_r ? 35% por5v_r por5v_r +35% v 9b por5v_f cc c nominal por for falling 5 v vddreg supply ?2.47?v 9c ? cc c variation of por for falling 5 v vddreg supply por5v_f ? 35% por5v_f por5v_f +35% v 1 using external ballast transistor. 2 min range is extended to 10% since lvi1p2 is reprog rammed from 1.2 v to 1.16 v after power-on reset. 3 lvi for falling supply is calculated as lvi rising ? lvi hysteresis. 4 lvi1p2 tracks dc target variation of internal v dd regulator. minimum and maximum lvi1p2 correspond to minimum and maximum v dd dc target respectively. 5 with internal load up to idd3p3 6 the lvi3p3 specs are also valid for the v ddeh lv i 7 lvi3p3 tracks dc target variation of internal v dd33 regulator. minimum and maximum lvi3p3 correspond to minimum and maximum v dd33 dc target respectively. table 15. pmc electrical characteristics (continued) id name c parameter value unit min typ max
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 65 electrical characteristics 3.6.1 regulator example in designs where the MPC5642A microcontroller?s internal regulators are used, a ballast is required for generation of the 1.2 v internal supply. no ballast is required when an external 1.2 v supply is used. figure 8. core voltage regulator controller external components preferred configuration 8 the 3.3v por specs are also valid for the v ddeh por table 16. MPC5642A external network specification external network parameter min typ max comment t1 ? ? ? njd2873 or bcp68 only cb 1.1 ? f2.2 ? f2.97 ? f x7r,-50%/+35% ce 3*2.35 ? f+5 ? f3*4.7 ? f+10 ? f3*6.35 ? f+13.5 ? f x7r, -50%/+35% equivalent esr of ce capacitors 5m ? 50m ? cd 4*50nf 4*100nf 4*135nf x7r, -50%/+35% rb 9 10 11 +/-10% mcu the bypass transistor must be operated out of saturation region. mandatory decoupling capacitor network v ddreg v rcctl v dd v ss vrcctl capacitor and resistor is required ce cd cb rb cc creg rc the resistor may or may not be required. this depends on the allowable power dissipation of the npn bypass transistor device. the resistor may be used to limit the in-rush current at power on. re keep parasitic inductance under 20nh t 1 ? ? ? ? ?
MPC5642A microcontroller data sheet, rev. 3.1 66 freescale semiconductor electrical characteristics 3.6.2 recommended power transistors the following npn transistors are recommen ded for use with the on-chip voltage regulator controller: on semiconductor? bcp68t1 or njd2873 as well as philips se miconductor? bcp68. the collector of th e external transist or is preferably connected to the same voltage supply sour ce as the output stage of the regulator. 3.7 power up/down sequencing there is no power sequencing required among power sources dur ing power up and power down, in order to operate within specification. although there are no power up/down sequencing requirements to pr event issues such as latch-up or excessive current spikes, the state of the i/o pins during power up/down varies according to table 18 for all pins with pad type fast, and table 19 for all pins with pad type medium, slow, and multi-voltage. re 0.252 0.280 0.308 +/-10% creg ? 10 ? f ? it depends on external vreg. cc 5 ? f10 ? f13.5 ? f x7r, -50%/+35% rc 1.1 ? 5.6 may or may not be required. it depends on the allowable power dissipation of t1. table 17. transistor recommended operating characteristics symbol parameter value unit h fe ( ? ) dc current gain (beta) 60?550 ? p d absolute minimum power dissipation >1.0 (1.5 preferred) w i cmaxdc minimum peak collector current 1.0 a vce sat collector-to-emitter saturation voltage 200?600 1 1 adjust resistor at bipola r transistor collector for 3.3 v/5.0 v to avoid vce < vce sat mv v be base-to-emitter voltage 0.4?1.0 v table 18. power sequence pin states?fast type pads v dde v rc33 v dd pin state low x x low v dde low x high v dde v rc33 low high impedance v dde v rc33 v dd functional table 16. MPC5642A external network specification (continued) external network parameter min typ max comment ? ? ? ? ?
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 67 electrical characteristics 3.8 dc electrical specifications table 19. power sequence pin states?medium, slow and multi-voltage type pads v ddeh v dd pin state low x low v ddeh low high impedance v ddeh v dd functional table 20. dc electrical specifications 1 symbol c parameter conditions value unit min typ max v dd sr p core supply voltage ? 1.14 ? 1.32 v v dde sr p i/o supply voltage ? 3.0 ? 3.6 v v ddeh sr p i/o supply voltage ? 3.0 ? 5.25 v v dde-eh sr p i/o supply voltage ? 3.0 ? 5.25 v v rc33 sr p 3.3 v regulated voltage 2 ?3.0?3.6v v dda sr p analog supply voltage ? 4.75 3 ?5.25v v indc sr c analog input voltage ? v ssa ? 0.3 ? v dda +0.3 v v ss ? v ssa sr d v ss differential voltage ? ?100 ? 100 mv v rl sr d analog reference low voltage ?v ssa ?v ssa +0.1 v v rl ? v ssa sr d v rl differential voltage ? ?100 ? 100 mv v rh sr d analog reference high voltage ?v dda ? 0.1 ? v dda v v rh ? v rl sr p v ref differential voltage ? 4.75 ? 5.25 v v ddf sr p flash operating voltage 4 ? 1.14 ? 1.32 v v flash 5 sr p flash read voltage ? 3.0 ? 3.6 v v stby sr c sram standby voltage unregulated mode 0.95 ? 1.2 v regulated mode 2.0 ? 5.5 v ddreg sr p voltage regulator supply voltage 6 ? 4.75 ? 5.25 v v ddpll sr p clock synthesizer operating voltage ? 1.14 ? 1.32 v v sspll ? v ss sr d v sspll to v ss differential voltage ? ?100 ? 100 mv v il_s sr p slow/medium i/o input low voltage hysteresis enabled v ss ? 0.3 ? 0.35 * v ddeh v p hysteresis disabled v ss ? 0.3 ? 0.40 * v ddeh v il_f sr p fast i/o input low voltage hysteresis enabled v ss ? 0.3 ? 0.35 * v dde v p hysteresis disabled v ss ? 0.3 ? 0.40 * v dde
MPC5642A microcontroller data sheet, rev. 3.1 68 freescale semiconductor electrical characteristics v il_ls sr p multi-voltage i/o pad input low voltage in low-swing-mode 7,8,9,10 hysteresis enabled v ss ? 0.3 ? 0.8 v p hysteresis disabled v ss ? 0.3 ? 0.9 v il_hs sr p multi-voltage pad i/o input low voltage in high-swing-mode hysteresis enabled v ss ? 0.3 ? 0.35 v ddeh v p hysteresis disabled v ss ? 0.3 ? 0.4 v ddeh v ih_s sr p slow/medium pad i/o input high voltage hysteresis enabled 0.65 v ddeh ?v ddeh +0.3 v p hysteresis disabled 0.55 v ddeh ?v ddeh +0.3 v ih_f sr p fast i/o input high volt age hysteresis enabled 0.65 v dde ?v dde +0.3 v p hysteresis disabled 0.58 v dde ?v dde +0.3 v ih_ls sr p multi-voltage pad i/o input high voltage in low-swing-mode 7,8,9,10 hysteresis enabled 2.5 ? v dde +0.3 v p hysteresis disabled 2.2 ? v dde +0.3 v ih_hs sr p multi-voltage i/o input high voltage in high-swing-mode hysteresis enabled 0.65 v ddeh ?v ddeh +0.3 v p hysteresis disabled 0.55 v ddeh ?v ddeh +0.3 v ol_s cc p slow/medium pad i/o output low voltage 11 ???0.2*v ddeh v v ol_f cc p fast i/o output low voltage 11 ???0.2*v dde v v ol_ls cc p multi-voltage pad i/o output low voltage in low-swing mode 7,8,9,10,11 ???0.6v v ol_hs cc p multi-voltage pad i/o output low voltage in high-swing mode 11 ???0.2v ddeh v v oh_s cc p slow/medium i/o output high voltage 11 ?0.8v ddeh ??v v oh_f cc p fast pad i/o output high voltage 11 ?0.8v dde ??v v oh_ls cc p multi-voltage pad i/o output high voltage in low-swing mode 7,8,9,10,11 ?2.33.13.7v v oh_hs cc p multi-voltage pad i/o output high voltage in high-swing mode 11 ?0.8v ddeh ??v v hys_s cc p slow/medium/multi-voltage i/o input hysteresis ?0.1 * v ddeh ??v v hys_f cc p fast i/o input hysteresis ? 0.1 * v dde ??v v hys_ls cc c low-swing-mode multi-voltage i/o input hysteresis hysteresis enabled 0.25 ? ? v table 20. dc electrical specifications 1 (continued) symbol c parameter conditions value unit min typ max
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 69 electrical characteristics i dd +i ddpll cc p operating current 1.2 v supplies v dd @1.32 v @80mhz ? ? 300 ma pv dd @ 1.32 v @ 120 mhz ? ? 360 ma pv dd @ 1.32 v @ 150 mhz ? ? 400 ma i ddstby cc t operating current 0.95-1.2 v v stby at 55 o c ? 35 100 ? a t operating current 2?5.5 v v stby at 55 o c ? 45 110 ? a i ddstby27 cc p operating current 0.95-1.2 v v stby 27 o c ? 25 90 ? a p operating current 2-5.5 v v stby 27 o c ? 35 100 ? a i ddstby150 cc p operating current 0.95-1.2 v v stby 150 o c ? 790 2000 ? a p operating current 2?5.5 v v stby at 150 o c ? 760 2000 ? a i ddpll cc p operating current 1.2 v supplies v ddpll , 80 mhz, v dd =1.2 v ? ? 15 ma i ddslow i ddstop cc c v dd low-power mode operating current @ 1.32 v slow mode 12 ? ? 191 ma c stop mode 13 ? ? 190 i dd33 cc p operating current 3.3 v supplies v rc33 2 ??60ma i dda i ref i ddreg cc p operating current 5.0 v supplies v dda ? ? 30.0 ma p analog reference supply current (transient) ??1.0 pv ddreg ??70 14 i ddh1 i ddh4 i ddh6 i ddh7 i dd7 i ddh9 i dd12 cc p operating current v dde 15 supplies v ddeh1 ? ? see note 15 ma pv ddeh4 ?? pv ddeh6 ?? pv ddeh7 ?? pv dde7 ?? pv ddeh9 ?? pv dde12 ?? table 20. dc electrical specifications 1 (continued) symbol c parameter conditions value unit min typ max
MPC5642A microcontroller data sheet, rev. 3.1 70 freescale semiconductor electrical characteristics i act_s cc p slow/medium i/o weak pull-up/down current 16 3.0 v ? 3.6 v 15 ? 95 a p4.75v ? 5.25 v 35 ? 200 i act_f cc p fast i/o weak pull-up/down current 16 1.62 v ? 1.98 v 36 ? 120 a p2.25v ? 2.75 v 34 ? 139 p3.0v ? 3.6 v 42 ? 158 i act_mv_pu cc c multi-voltage pad weak pull-up current v dde =3.0?3.6v 7 , multi-voltage, high swing mode only 10 ? 75 a c4.75v ? 5.25 v 25 ? 175 i act_mv_pd cc c multi-voltage pad weak pull-down current v dde =3.0?3.6v 7 , multi-voltage, all process corners, high swing mode only 10 ? 60 a c4.75v ? 5.25 v 25 ? 200 i inact_d cc p i/o input leakage current 17 ? ?2.5 ? 2.5 a i ic sr t dc injection current (per pin) ? ?1.0 ? 1.0 ma i inact_a sr p analog input current, channel off, an[0:7] 18 ? ?250 ? 250 na p analog input current, channel off, all other analog pins 18 ? ?150 ? 150 c l cc d load capacitance (fast i/o) 19 dsc(pcr[8:9]) = 0b00 ? ? 10 pf d dsc(pcr[8:9]) = 0b01 ??20 d dsc(pcr[8:9]) = 0b10 ??30 d dsc(pcr[8:9]) = 0b11 ??50 c in cc d input capacitance (digital pins) ???7pf c in_a cc d input capacitance (analog pins) ???10pf c in_m cc d input capacitance (digital and analog pins 20 ) ???12pf r pupd200k sr c weak pull-up/down resistance 21 , 200 k ? option ? 130 ? 280 k ? table 20. dc electrical specifications 1 (continued) symbol c parameter conditions value unit min typ max
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 71 electrical characteristics r pupd100k sr c weak pull-up/down resistance 21 , 100 k ? option ? 65 ? 140 k ? r pupd5k sr c weak pull-up/down resistance 21 , 5 k ? option 5 v 10% supply 1.4 ? 5.2 k ? c 3.3 v 10% supply 1.7 ? 7.7 r pupd5k sr c weak pull-up/down resistance 21 , 5k ? option 5 v 5% supply 1.4 ? 7.5 k ? r pupdmtch cc c pull-up/down resistance matching ratios (100k/200k) pull-up and pull-down resistances both enabled and settings are equal. ?2.5 ? 2.5 % t a (t l to t h ) sr p operating temperature range - ambient (packaged) ? ?40.0 ? 125.0 c ? sr d slew rate on power supply pins ???25v/ms 1 these specifications are design targets and s ubject to change per device characterization. 2 these specifications apply when v rc33 is supplied externally, after disabling the internal regulator (v ddreg =0). 3 adc is functional with 4 v ? v dda ? 4.75 v but with derated accuracy. this means the adc will continue to function at full speed with no undesirable behavior, but the accuracy will be degraded. 4 the v ddf supply is connected to v dd in the package substrate. this specification applies to calibration package devices only. 5 v flash is available in the calibration package only. 6 regulator is functional, with derated per formance, with supply voltage down to 4.0 v 7 multi-voltage power supply cannot be below 4.5 v when in low-swing mode 8 the slew rate (src) setting must be 0b11 when in low-swing mode. 9 while in low-swing mode there are no restri ctions in transitioning to high-swing mode. 10 pin in low-swing mode can accept a 5 v input 11 all v ol /v oh values 100% tested with 2 ma load except where otherwise noted 12 bypass mode, system clock @ 1 mhz (usi ng system clock divider), pll shut down, cpu running simple executive code, 4 x adc conversion every 10 ms, 2 x pwm channels @ 1 khz, all other modules stopped. 13 bypass mode, system clock @ 1 mhz (using system clock divider), cpu stopped, pit running, all other modules stopped 14 if 1.2v and 3.3v internal regulators are on,then iddreg=70ma if supply is external that is 3.3v internal regulator is off, then iddreg=15ma 15 power requirements for each i/o segment are dependent on t he frequency of operation and load of the i/o pins on a particular i/o segment, and the vo ltage of the i/o segment. see ta b l e 2 1 for values to calculate power dissipation for specific operation. the total power consumption of an i/o segment is the sum of the individual power consumptions for each pin on the segment. 16 absolute value of current, measured at v il and v ih 17 weak pull-up/down inactive. measured at v dde = 3.6 v and v ddeh = 5.25 v. applies to all digital pad types. table 20. dc electrical specifications 1 (continued) symbol c parameter conditions value unit min typ max
MPC5642A microcontroller data sheet, rev. 3.1 72 freescale semiconductor electrical characteristics 3.9 i/o pad current specifications the power consumption of an i/o segment depends on the usage of the pins on a particular segment. the power consumption is the sum of all output pin currents for a particular segment. the output pin curr ent can be calculated from table 21 based on the voltage, frequency, and load on the pin. use linear scaling to calculate pin cu rrents for voltage, frequency, and load parameters that fall outside the values given in table 21 . 18 maximum leakage occurs at maximum operating temper ature. leakage current decreases by approximately one-half for each 8 to 12 o c, in the ambient temperature range of 50 to 125 o c. applies to analog pads. 19 applies to clkout, external bus pins, and nexus pins 20 applies to the fck, sdi, sdo, and sds pins 21 this programmable option applies only to eqadc differenti al input channels and is used for biasing and sensor diagnostics. table 21. i/o pad average i dde specifications 1 1 numbers from simulations at best case process, 150 c pad type symbol c period (ns) load 2 (pf) 2 all loads are lumped. v dde (v) drive/slew rate select i dde avg (ma) 3 3 average current is for pad configured as output only i dde rms (ma) slow i drv_ssr_hv cc d 37 50 5.25 11 9 ? cc d 130 50 5.25 01 2.5 ? cc d 650 50 5.25 00 0.5 ? cc d 840 200 5.25 00 1.5 ? medium i drv_msr_hv cc d 24 50 5.25 11 14 ? cc d 62 50 5.25 01 5.3 ? cc d 317 50 5.25 00 1.1 ? cc d 425 200 5.25 00 3 ? fast i drv_fc cc d 10 50 3.6 11 22.7 68.3 cc d 10 30 3.6 10 12.1 41.1 cc d 10 20 3.6 01 8.3 27.7 cc d 10 10 3.6 00 4.44 14.3 cc d 10 50 1.98 11 12.5 31 cc d 10 30 1.98 10 7.3 18.6 cc d 10 20 1.98 01 5.42 12.6 cc d 10 10 1.98 00 2.84 6.4 multiv (high swing mode) i drv_multv_hv cc d 20 50 5.25 11 9 ? cc d 30 50 5.25 01 6.1 ? cc d 117 50 5.25 00 2.3 ? cc d 212 200 5.25 00 5.8 ? multiv (low swing mode) i drv_multv_hv cc d 30 30 5.25 11 3.4 ?
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 73 electrical characteristics 3.9.1 i/o pad v rc33 current specifications the power consumption of the v rc33 supply is dependent on the usage of the pins on all i/o segments. the power consumption is the sum of all input and output pin v rc33 currents for all i/o se gments. the output pin v rc33 current can be calculated from table 22 based on the voltage, frequency, and load on all fast pins. the input pin v rc33 current can be calculated from table 22 based on the voltage, frequency, and load on all medium pins. us e linear scaling to calculate pi n currents for voltage, frequen cy, and load parameters that fall outside the values given in table 22 . table 22. i/o pad v rc33 average i dde specifications 1 1 these are typical values that are esti mated from simulation and not tested. currents apply to output pins only. pad type symbol c period (ns) load 2 (pf) 2 all loads are lumped. drive select i dd33 avg (a) i dd33 rms (a) slow i drv_ssr_hv cc d 100 50 11 0.8 235.7 cc d 200 50 01 0.04 87.4 cc d 800 50 00 0.06 47.4 cc d 800 200 00 0.009 47 medium i drv_msr_hv ccd4050112.75258 cc d 100 50 01 0.11 76.5 cc d 500 50 00 0.02 56.2 cc d 500 200 00 0.01 56.2 multiv 3 (high swing mode) 3 average current is for pad configured as output only i drv_multv_hv cc d 20 50 11 33.4 35.4 cc d 30 50 01 33.4 34.8 cc d 117 50 00 33.4 33.8 cc d 212 200 00 33.4 33.7 multiv 4 (low swing mode) 4 in low swing mode, multi-voltage pads must operate in highest slew rate setting, ipp_sre0 = 1, ipp_sre1 = 1. i drv_multv_hv cc d 30 30 11 33.4 33.7
MPC5642A microcontroller data sheet, rev. 3.1 74 freescale semiconductor electrical characteristics 3.9.2 lvds pad specifications lvds pads are implemented to support th e msc (microsecond channel) protocol whic h is an enhanced fe ature of the dspi module. the lvds pads are compliant with lvds specifications and support data rates up to 50 mhz. table 23. v rc33 pad average dc current 1 1 these are typical values that are esti mated from simulation and not tested. currents apply to output pins only. pad type symbol c period (ns) load 2 (pf) 2 all loads are lumped. v rc33 (v) v dde (v) drive select i dd33 avg (a) i dd33 rms (a) fast i drv_fc ccd10 503.63.611 2.35 6.12 ccd10 303.63.610 1.75 4.3 ccd10 203.63.601 1.41 3.43 ccd10 103.63.600 1.06 2.9 cc d 10 50 3.6 1.98 11 1.75 4.56 cc d 10 30 3.6 1.98 10 1.32 3.44 cc d 10 20 3.6 1.98 01 1.14 2.95 cc d 10 10 3.6 1.98 00 0.95 2.62 table 24. dspi lvds pad specification symbol c parameter condition value unit min typ max data rate f lv d s c l k cc d data frequency ? ? 50 ? mhz driver specifications v od cc p differential output voltage src = 0b00 or 0b11 150 ? 400 mv cc p src = 0b01 90 ? 320 cc p src = 0b10 160 ? 480 v oc cc p common mode voltage (lvds), vos ? 1.06 1.2 1.39 v t r /t f cc d rise/fall time ? ? 2 ? ns t plh cc d propagation delay (low to high) ? ? 4 ? ns t phl cc d propagation delay (high to low) ? ? 4 ? ns t pdsync cc d delay (h/l), sync mode ? ? 4 ? ns t dz cc d delay, z to normal (high/low) ? ? 500 ? ns
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 75 electrical characteristics 3.10 oscillator and pllmrf m electrical characteristics t skew cc d differential skew itphla-tplhbi or itplhb-tphlai ???0.5ns termination cc d transmission line (differential zo) ? 95 100 105 w cc d temperature ? ?40 ? 150 ? c table 25. pllmrfm electrical specifications 1 (v ddpll = 1.08 v to 3.6 v, v ss = v sspll = 0 v, t a = t l to t h ) symbol c parameter conditions value unit min max f ref_crystal f ref_ext cc p pll reference frequency range 2 crystal reference 4 40 mhz p external reference 4 80 f pll_in cc d phase detector input frequency range (after pre-divider) ?416mhz f vco cc d vco frequency range ? 256 512 mhz f sys cc t on-chip pll frequency 2 ?16150mhz f sys cc t system frequency in bypass mode 3 crystal reference 4 40 mhz t external reference 0 80 t cyc cc d system clock period ? ? 1 / f sys ns f lorl f lorh cc d loss of reference frequency window 4 lower limit 1.6 3.7 mhz d upper limit 24 56 f scm cc p self-clocked mode frequency 5,6 ? 1.2 72.25 mhz c jitter cc c clkout period jitter 7,8,9,10 peak-to-peak (clock edge to clock edge) f sys maximum ?5 5 % f clkout c long-term jitter (avg. over 2 ms interval) ?6 6 ns t cst cc t crystal start-up time 11,12 ??10ms v ihext cc d extal input high voltage crystal mode 13 vxtal +0.4 ?v texternal reference 13,14 v rc33 /2 + 0.4 v rc33 table 24. dspi lvds pad specification (continued) symbol c parameter condition value unit min typ max
MPC5642A microcontroller data sheet, rev. 3.1 76 freescale semiconductor electrical characteristics v ilext cc d extal input low voltage crystal mode 13 ?vxtal ? 0.4 v texternal reference 13,14 0v rc33 /2 ? 0.4 ? cc t xtal load capacitance ? 5 30 pf ? cc c xtal load capacitance 11 4mhz 5 30 pf 8mhz 5 26 12 mhz 5 23 16 mhz 5 19 20 mhz 5 16 40 mhz 5 8 t lpll cc p pll lock time 11,15 ??200s t dc cc d duty cycle of reference ? 40 60 % f lck cc d frequency lock range ? ?6 6 % f sys f ul cc d frequency un-lock range ? ?18 18 % f sys f cs f ds cc d modulation depth center spread 0.25 4.0 % f sys d down spread ?0.5 ?8.0 f mod cc d modulation frequency 16 ??100khz 1 all values given are initial design targets and subject to change. 2 considering operation with pll not bypassed 3 all internal registers retain data at 0 hz. 4 ?loss of reference frequency? window is the reference freq uency range outside of which the pll is in self clocked mode. 5 self clocked mode frequency is the frequency that the pl l operates at when the refere nce frequency falls outside the f lor window. 6 f vco self clock range is 20?150 mhz. f scm represents f sys after pll output divider (erfd) of 2 through 16 in enhanced mode. 7 this value is determined by the cr ystal manufacturer and board design. 8 jitter is the average deviation from the programmed frequ ency measured over the specified interval at maximum f sys . measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v ddpll and v sspll and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. 9 proper pc board layout procedures must be followed to achieve specifications. 10 values are with frequency modulation disabled. if frequ ency modulation is enabled, jitter is the sum of c jitter and either f cs or f ds (depending on whether center spread or down spread modulation is enabled). 11 this value is determined by the crystal manufacturer and board design. for 4 mhz to 40 mhz crystals specified for this pll, load capacitors s hould not exceed these limits. 12 proper pc board layout procedures must be followed to achieve specifications. 13 this parameter is guaranteed by design rather than 100% tested. table 25. pllmrfm electrical specifications 1 (v ddpll = 1.08 v to 3.6 v, v ss = v sspll = 0 v, t a = t l to t h ) (continued) symbol c parameter conditions value unit min max
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 77 electrical characteristics 3.11 temperature sensor electrical characteristics 3.12 eqadc electrical characteristics 14 v ihext cannot exceed v rc33 in external reference mode. 15 this specification applies to the period required for the pl l to relock after changing the mfd frequency control bits in the synthesizer control register (syncr). 16 modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 khz. table 26. temperature sensor electrical characteristics symbol c parameter conditions value unit min typ max ? cc c temperature monitoring range ?40 ? 150 c ? cc c sensitivity ? 6.3 ? mv/c ? cc c accuracy t j = ?40 to 150 c ?10 ? 10 c table 27. eqadc conversion specifications (operating) symbol c parameter value unit min max f adclk sr ? adc clock (adclk) frequency 2 16 mhz cc cc d conversion cycles 2+ 13 128+14 adclk cycles t sr cc c stop mode recovery time 1 1 stop mode recovery time is the time from the setting of either of the enable bits in the adc control register to the time that the adc is ready to perform conversions.delay from power up to full accuracy = 8 ms. ?10 ? s f adclk sr ? adc clock (adclk) frequency 2 16 mv table 28. eqadc single ended conversion specifications (operating) symbol c parameter value unit min max offnc cc c offset error without calibration 0 160 counts offwc cc c offset error with calibration ?4 4 counts gainnc cc c full scale gain error without calibration ?160 0 counts gainwc cc c full scale gain error with calibration ?4 4 counts i inj cc t disruptive input injection current 1, 2, 3, 4 ?3 3 ma e inj cc t incremental error due to injection current 5,6 ?4 4 counts tue8 cc c total unadjusted error (tue) at 8 mhz ?4 4 6 counts tue16 cc c total unadjusted error at 16 mhz ?8 8 counts
MPC5642A microcontroller data sheet, rev. 3.1 78 freescale semiconductor electrical characteristics 1 below disruptive current conditions, the channel bein g stressed has conversion values of 0x3ff for analog inputs greater then v rh and 0x0 for values less then v rl . other channels are not af fected by non-disruptive conditions. 2 exceeding limit may cause conversion error on stresse d channels and on unstressed channels. transitions within the limit do not affect device reliability or cause permanent damage. 3 input must be current limited to th e value specified. to determine the value of the required current-limiting resistor, calculate resistance values using v posclamp = v dda + 0.5 v and v negclamp = ? 0.3 v, then use the larger of the calculated values. 4 condition applies to two adjacent pins at injection limits. 5 performance expected with production silicon. 6 all channels have same 10 k ? MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 79 electrical characteristics 3.13 configuring sram wait states use the swsc field in the ecsm_mudcr regi ster to specify an additio nal wait state for the devi ce sram. by default, no wait state is added. please see the device reference manual for details. diff max cc c maximum differential voltage (danx+ - danx-) or (danx- - danx+) 5 pregain set to 1x setting ? (vrh - vrl)/2 v diff max2 cc c pregain set to 2x setting ? (vrh - vrl)/4 v diff max4 cc c pregain set to 4x setting ? (vrh - vrl)/8 v diff cmv cc c differential input common mode voltage (danx- + danx+)/2 5 ?(v rh + v rl )/2 - 5% (v rh + v rl )/2 + 5% v 1 applies only to differential channels. 2 variable gain is controlled by setting the pre_gain bits in the adc_acr1-8 registers to select a gain factor of ? 1, ? 2, or ? 4. settings are for differential input only. tested at ? 1 gain. values for other settings are guaranteed by as indicated. 3 at v rh ? v rl = 5.12 v, one lsb = 1.25 mv. 4 guaranteed 10-bit mono tonicity. 5 voltages between vrl and vrh will not cause damage to the pins . however, they may not be converted accurately if the differential voltage is above the maximum differential voltage. in addition, conversion errors may occur if the common mode voltage of the differential signal violates the dif ferential input common mo de voltage specification. table 30. cutoff frequency for additional sram wait state 1 1 max frequencies including 2% pll fm. swsc value 98 0 153 1 table 29. eqadc differential ended conversion specifications (operating) (continued) symbol c parameter value unit min max
MPC5642A microcontroller data sheet, rev. 3.1 80 freescale semiconductor electrical characteristics 3.14 platform flash controll er electrical characteristics 3.15 flash memory electrical characteristics table 31. apc, rwsc, wwsc settings vs. frequency of operation 1 1 apc, rwsc and wwsc are fields in the flash memory biucr register used to specify wait states for address pipe lining and read/write accesses. illegal combinations exist?all entries must be taken from the same row. max. flash operating frequency (mhz) 2 2 max frequencies including 2% pll fm. apc 3 3 apc must be equal to rwsc. rwsc 3 wwsc 20 mhz 0b000 0b000 0b01 61 mhz 0b001 0b001 0b01 90 mhz 0b010 0b010 0b01 123 mhz 0b011 0b011 0b01 153 mhz 0b100 0b100 0b01 table 32. flash program and erase specifications 1 1 typical program and erase times assume nominal supply values and operation at 25 c. all times are subject to change pending device characterization. # symbol c parameter value unit min typ initial max 2 2 initial factory condition: < 100 program/erase cycles, 25 c, typical supply voltage, 80 mhz minimum system frequency. max 3 3 the maximum erase time occurs after the specified nu mber of program/erase cycles. this maximum value is characterized but not guaranteed. 1t dwprogram cc c double word (64 bits) program time ? 30 ? 500 s 2t pprogram cc c page program time 4 4 page size is 128 bits (4 words) ? 40 160 500 s 3t 16kpperase cc c 16 kb block pre-program and erase time ? 250 1,000 5,000 ms 5t 64kpperase cc c 64 kb block pre-program and erase time ? 450 1,800 5,000 ms 6t 128kpperase cc c 128 kb block pre-program and erase time ? 800 2,600 7,500 ms 7t 256kpperase cc c 256 kb block pre-program and erase time ? 1,400 5,200 15,000 ms 8t psrt sr ? program suspend request rate 5 5 time between program suspend resume and the next program suspend request. 100??? ? s 9t esrt sr ? erase suspend request rate 6 6 time between erase suspend resume and the next erase suspend request. 10 ms
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 81 electrical characteristics table 33. flash eeprom module life symbol c parameter conditions value unit min typ p/e cc d number of program/erase cycles per block for 16 kb, 48 kb, and 64 kb blocks over the operating temperature range (t j ) ? 100,000 ? cycles p/e cc d number of program/erase cycles per block for 128 kb and 256 kb blocks over the operating temperature range (t j ) ? 1,000 100,000 cycles retention cc d minimum data retention at 85 c blocks with 0 ? 1,000 p/e cycles 20 ? years d blocks with 10,000 p/e cycles 10 ? d blocks with 100,000 p/e cycles 5?
MPC5642A microcontroller data sheet, rev. 3.1 82 freescale semiconductor electrical characteristics 3.16 ac specifications 3.16.1 pad ac specifications table 34. pad ac specifications (v dde = 4.75 v) 1 1 these are worst case values that are estimated from si mulation and not tested. the values in the table are simulated at v dd = 1.14 v to 1.32 v, v ddeh = 4.75 v to 5.25 v, t a = t l to t h . name c output delay (ns) 2,3 low-to-high / high-to-low 2 this parameter is supplied for reference and is not guaranteed by design and not tested. 3 delay and rise/fall are measured to 20% or 80% of the respective signal. rise/fall edge (ns) 3,4 4 this parameter is guaranteed by characteriza tion before qualification ra ther than 100% tested. drive load (pf) src/dsc min max min max msb, lsb medium 5,6,7 5 in high swing mode, high/low swing pad v ol and v oh values are the same as those of the slew controlled output pads. 6 medium slew-rate controlled output buffer. cont ains an input buffer and weak pull-up/pull-down. 7 output delay is shown in figure 9 and figure 10 . add a maximum of one system cloc k to the output delay for delay with respect to system clock. cc d 4.6/3.7 12/12 2.2/2.2 12/12 50 11 8 8 can be used on the tester ?10 9 9 this drive select value is not supported. if selected, it will be approximately equal to 11. cc d 12/13 28/34 5.6/6 15/15 50 01 cc d 69/71 152/165 34/35 74/74 50 00 slow 7,10 10 slow slew-rate controlled output buffer. cont ains an input buffer and weak pull-up/pull-down. cc d 7.3/5.7 19/18 4.4/4.3 20/20 50 11 8 ?10 9 cc d 26/27 61/69 13/13 34/34 50 01 cc d 137/142 320/330 72/74 164/164 50 00 multiv 11 (high swing mode) 11 selectable high/low swing i/o pad with selectable slew in high swing mode only cc d 4.1/3.6 10.3/8.9 3.28/2.98 8/8 50 11 8 ?10 9 cc d 8.38/6.11 16/12.9 5 .48/4.81 11/11 50 01 cc d 61.7/10.4 92.2/24 .3 42.0/12.2 63/63 50 00 multiv (low swing mode) cc d 2.31/2.34 7.62/6.33 1 .26/1.67 6.5/4.4 30 11 8 fast 12 12 fast pads are 3.3 v pads. ? standalone input buffer 13 13 also has weak pull-up/pull-down. cc d 0.5/0.5 1.9/1.9 0.3/0.3 1.5/1.5 0.5 ?
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 83 electrical characteristics table 35. pad ac specifications (v dde = 3.0 v) 1 1 these are worst case values that are estimated from si mulation and not tested. the values in the table are simulated at v dd = 1.14 v to 1.32 v, v dde = 3 v to 3.6 v, v ddeh = 3v to 3.6v, t a = t l to t h . pad type c output delay (ns) 2,3 low-to-high / high-to-low 2 this parameter is supplied for reference and is not guaranteed by design and not tested. 3 delay and rise/fall are measured to 20% or 80% of the respective signal. rise/fall edge (ns) 3,4 4 this parameter is guaranteed by characteriza tion before qualification ra ther than 100% tested. drive load (pf) src/dsc min max min max msb,lsb medium 5,6,7 cc d 5.8/4.4 18/17 2.7/2.1 10/10 50 11 8 cc d 16/13 46/49 11.2/8.6 34/34 200 ?10 9 cc d 14/16 37/45 6.5/6.7 19/19 50 01 cc d 27/27 69/82 15/13 43/43 200 cc d 83/86 200/210 38/38 86/86 50 00 cc d 113/109 270/285 53/46 120/120 200 slow 7,10 cc d 9.2/6.9 27/28 5.5/4.1 20/20 50 11 cc d 30/23 81/87 21/16 63/63 200 ?10 9 cc d 31/31 80/90 15.4/15.4 42/42 50 01 cc d 58/52 144/155 32/26 82/85 200 cc d 162/168 415/415 80/82 190/190 50 00 cc d 216/205 533/540 106/95 250/250 200 multiv 7,11 (high swing mode) cc d ? 3.7/3.1 ? 10/10 30 11 8 cc d ? 46/49 ? 42/42 200 ?10 9 cc d ? 32 ? 15/15 50 01 cc d ? 72 ? 46/46 200 cc d ? 210 ? 100/100 50 00 cc d ? 295 ? 134/134 200 multiv (low swing mode) not a valid operational mode fast cc d ? 2.5/2.5 ? 1.2/1.2 10 00 cc d ? 2.5/2.5 ? 1.2/1.2 20 01 cc d ? 2.5/2.5 ? 1.2/1.2 30 10 cc d ? 2.5/2.5 ? 1.2/1.2 50 11 8 standalone input buffer 12 cc d 0.5/0.5 3/3 0.4/0.4 1.5/1.5 0.5 ?
MPC5642A microcontroller data sheet, rev. 3.1 84 freescale semiconductor electrical characteristics figure 9. pad output delay?fast pads 5 in high swing mode, high/low swing pad v ol and v oh values are the same as those of the slew controlled output pads. 6 medium slew-rate controlled output buffer. cont ains an input buffer and weak pull-up/pull-down. 7 output delay is shown in figure 9 and figure 10 . add a maximum of one system cloc k to the output delay for delay with respect to system clock. 8 can be used on the tester. 9 this drive select value is not supported. if selected, it will be approximately equal to 11. 10 slow slew-rate controlled output buffer. cont ains an input buffer and weak pull-up/pull-down. 11 selectable high/low swing i/o pad with selectable slew in high swing mode only. 12 also has weak pull-up/pull-down. v dde /2 v oh v ol rising edge output delay falling edge output delay pad data input pad output
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 85 electrical characteristics figure 10. pad output delay?slew rate controlled fast, medium, and slow pads v dde /2 v oh v ol rising edge output delay falling edge output delay pad data input pad output
MPC5642A microcontroller data sheet, rev. 3.1 86 freescale semiconductor electrical characteristics 3.17 ac timing 3.17.1 reset and configuration pin timing figure 11. reset and c onfiguration pin timing 3.17.2 ieee 1149.1 interface timing table 36. reset and configuration pin timing 1 1 reset timing specified at: v ddeh = 3.0 v to 5.25 v, v dd = 1.14 v to 1.32 v, t a =t l to t h . # symbol characteristic value unit min max 1t rpw reset pulse width 10 ? t cyc 2t gpw reset glitch detect pulse width 2 ? t cyc 3t rcsu pllref, bootcfg, wkpcfg setup time to rstout valid 10 ? t cyc 4t rch pllref, bootcfg, wkpcfg hold time to rstout valid 0 ? t cyc table 37. jtag pin ac electrical characteristics 1 # symbol c characteristic value unit min max 1t jcyc cc d tck cycle time 100 ? ns 2t jdc cc d tck clock pulse width 40 60 ns 3t tckrise cc d tck rise and fall times (40%?70%) ? 3 ns 1 2 reset rstout wkpcfg 3 4 bootcfg
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 87 electrical characteristics note the nexus/jtag read/write access control/status register (rwcs) write (to begin a read access) or the write to the read/write access data register (rwd) (to begin a write access) does not actually begin its action until 1 jtag clock (tck) after leaving the jtag update-dr state. this prevents the access fr om being performed a nd therefore will not signal its completion via the ready (rdy) output unless the jtag controller receives an additional tck. in addition, evti is not latched into the device unless there are clock transitions on tck. the tool/debugger must provide at least one tck clock for the evti signal to be recognized by the mcu. when using the r dy signal to indicate the end of a nexus read/write access, ensure that tck continues to run for at l east one tck after leaving the update-dr state. this can be just a tck with tms low while in the run-test/idle state or by continuing with the next nexus/jtag command. expect the effect of evti and rdy to be delayed by edges of tck. rdy is not available in all device packages. 4t tmss, t tdis cc d tms, tdi data setup time 10 ? ns 5t tmsh, t tdih cc d tms, tdi data hold time 25 ? ns 6t tdov cc d tck low to tdo data valid ? 22 2 ns 7t tdoi cc d tck low to tdo data invalid 0 ? ns 8t tdohz cc d tck low to tdo high impedance ? 22 ns 9t jcmppw cc d jcomp assertion time 100 ? ns 10 t jcmps cc d jcomp setup time to tck low 40 ? ns 11 t bsdv cc d tck falling edge to output valid ? 50 ns 12 t bsdvz cc d tck falling edge to output valid out of high impedance ? 50 ns 13 t bsdhz cc d tck falling edge to output high impedance ? 50 ns 14 t bsdst cc d boundary scan input valid to tck rising edge 25 3 ?ns 15 t bsdht cc d tck rising edge to boundary scan input invalid 25 3 ?ns 1 jtag timing specified at v dd = 1.14 v to 1.32 v, v ddeh = 4.75 v to 5.25 v with multi-voltage pads programmed to low-swing mode, t a = t l to t h , c l = 30 pf, src = 0b11. these specifications apply to jtag boundary scan only. see ta bl e 3 8 for functional specifications. 2 pad delay is 8?10 ns. remainder includes tck pad delay, clock tree delay logic delay and tdo output pad delay. 3 for 20 mhz tck. table 37. jtag pin ac electrical characteristics 1 (continued) # symbol c characteristic value unit min max
MPC5642A microcontroller data sheet, rev. 3.1 88 freescale semiconductor electrical characteristics figure 12. jtag test clock input timing figure 13. jtag test access port timing tck 1 2 2 3 3 tck 4 5 6 7 8 tms, tdi tdo
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 89 electrical characteristics figure 14. jtag jcomp timing tck jcomp 9 10
MPC5642A microcontroller data sheet, rev. 3.1 90 freescale semiconductor electrical characteristics figure 15. jtag boundary scan timing 3.17.3 nexus timing table 38. nexus debug port timing 1 # symbol c characteristic value unit min max 1t mcyc cc d mcko cycle time 2 2,3 8t cyc 1a t mcyc cc d absolute minimum mcko cycle time 25 4 ?ns 2t mdc cc d mcko duty cycle 40 60 % 3t mdov cc d mcko low to mdo data valid 5 ? 0.1 0.35 t mcyc 4t mseov cc d mcko low to mseo data valid 5 ? 0.1 0.35 t mcyc 6t evtov cc d mcko low to evto data valid 5 ? 0.1 0.35 t mcyc 7t evtipw cc d evti pulse width 4.0 ? t tcyc tck output signals input signals output signals 11 12 13 14 15
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 91 electrical characteristics 8t evtopw cc d evto pulse width 1 ? t mcyc 9t tcyc cc d tck cycle time 4 6,7 ?t cyc 9a t tcyc cc d absolute minimum tck cycle time 100 8 ?ns 10 t tdc cc d tck duty cycle 40 60 % 11 t ntdis cc d tdi data setup time 10 ? ns 12 t ntdih cc d tdi data hold time 25 ? ns 13 t ntmss cc d tms data setup time 10 ? ns 14 t ntmsh cc d tms data hold time 25 ? ns 15 ? cc d tdo propagation delay from falling edge of tck ? 19.5 ns 16 ? cc d tdo hold time wrt tck falling edge (minimum tdo propagation delay) 5.25 ? ns 1 all nexus timing relative to mcko is measured from 50% of mcko and 50% of the respective signal. nexus timing specified at v dd = 1.14 v to 1.32 v, v ddeh = 4.75 v to 5.25 v with multi-voltag e pads programmed to low-swing mode, t a =t l to t h , and c l = 30 pf with dsc = 0b10. 2 achieving the absolute minimum mcko cycle time may requ ire setting the mcko divider to more than its minimum setting (npc_pcr[mcko_div] depending on the actual system frequency being used. 3 this is a functionally allowable feature. however, this may be limited by the maximum frequency specified by the absolute minimum mcko period specification. 4 this may require setting the mco divider to more t han its minimum setting (npc_pcr[mcko_div]) depending on the actual system frequency being used. 5 mdo, mseo , and evto data is held valid until next mcko low cycle. 6 achieving the absol ute minimum tck cycle time may require a maximu m clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system frequency being used. 7 this is a functionally allowable feature. however, this may be limited by the maximum frequency specified by the absolute minimum tck period specification. 8 this may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system frequency being used. table 38. nexus debug port timing 1 (continued) # symbol c characteristic value unit min max
MPC5642A microcontroller data sheet, rev. 3.1 92 freescale semiconductor electrical characteristics figure 16. nexus output timing figure 17. nexus event trigger and test clock timings 1 2 4 6 mcko mdo mseo evto output data valid 3 tck 9 7 8 evti evto 8 7
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 93 electrical characteristics figure 18. nexus tdi, tms, tdo timing n table 39. nexus debug port operating frequency package nexus width nexus routing nexus pin usage max. operating frequency mdo[0:3] mdo[4:11] cal_mdo[4:1 1] 176 lqfp 208 bga 324 bga reduced port mode 1 1 npc_pcr[fpm] = 0 route to mdo 2 2 npc_pcr[nexcfg] = 0 nexus data out [0:3] gpio gpio 40 mhz 3 full port mode 4 route to mdo 2 nexus data out [0:3] nexus data out [4:11] gpio 40 mhz 5,6 496 csp reduced port mode 1 route to mdo 2 nexus data out [0:3] gpio gpio 40 mhz 3 full port mode 4 route to mdo 2 nexus data out [0:3] nexus data out [4:11] gpio 40 mhz 5,6 route to cal_mdo 7 cal nexus data out [0:3] gpio cal nexus data out [4:11] 40 mhz 3 tck 11 12 15 tms, tdi tdo 13 14 16
MPC5642A microcontroller data sheet, rev. 3.1 94 freescale semiconductor electrical characteristics 3 the nexus aux port runs up to 40 mhz. set npc_pcr[mc ko_div] to divide-by-two if the system frequency is greater than 40 mhz. 4 npc_pcr[fpm] = 1 5 set the npc_pcr[mcko_div] to divide by two if the system frequency is between 40 mhz and 80 mhz inclusive. set the npc_pcr[mcko_div] to divide by four if the system frequency is greater than 80 mhz. 6 pad restrictions limit the maximum oper ation frequency in these configurations 7 npc_pcr[nexcfg] = 1
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 95 electrical characteristics 3.17.4 calibration bus interface timing table 40. calibration bus interface maximum operating frequency port width multiplexed mode pin usage max. operating frequency cal_addr[12:15] cal_addr[16:30] cal_data[0:15] 16-bit yes gpio gpio cal_addr[12:30] cal_data[0:15] 66 mhz 1 1 set siu_eccr[ebdf] to either divide by two or divide by four if the system frequency is greater than 66 mhz. 16-bit no cal_addr[12:15] cal_addr[16:30] cal_data[0:15] 66 mhz 1 32-bit yes cal_we/be[2:3] cal_data[31] cal_addr[16:30] cal_data[16:30] cal_addr[0:15] cal_data[0:15] 66 mhz 1 table 41. calibration bus operation timing 1 # symbol c characteristic 66 mhz 2 unit min max 1t c cc p clkout period 3 15.2 ? ns 2t cdc cc t clkout duty cycle 45% 55% t c 3t crt cc t clkout rise time ? 4 ns 4t cft cc t clkout fall time ? 4 ns 5t coh cc p clkout posedge to output signal invalid or high z (hold time) cal_addr[12:30] cal_cs[0], cal_cs[2:3] cal_data[0:15] cal_oe cal_rd_wr cal_ts cal_we [0:3]/be [0:3] 1.3 ? ns 6t cov cc p clkout posedge to output signal valid (output delay) cal_addr[12:30] cal_cs[0], cal_cs[2:3] cal_data[0:15] cal_oe cal_rd_wr cal_ts cal_we [0:3]/be [0:3] ?9ns 7t cis cc p input signal valid to clkout posedge (setup time) data[0:31] 6.0 ? ns 8t cih cc p clkout posedge to input signal invalid (hold time) data[0:31] 1.0 ? ns 9t apw cc p ale pulse width 5 6.5 ? ns 10 t aai cc p ale negated to address invalid 5 1.5 6 ?ns
MPC5642A microcontroller data sheet, rev. 3.1 96 freescale semiconductor electrical characteristics figure 19. clkout timing 1 calibration bus timing specified at f sys = 150 mhz and 100 mhz, v dd = 1.14 v to 1.32 v, v dde =3vto3.6v (unless stated otherwise), t a =t l to t h , and c l = 30 pf with dsc = 0b10. 2 the calibration bus is limited to half the speed of the in ternal bus. the maximum calibration bus frequency is 66 mhz. the bus division factor should be set accordingly based on the internal frequency being used. 3 signals are measured at 50% v dde 4 refer to fast pad timing in ta b l e 3 4 and ta b l e 3 5 (different values for 1.8 v vs. 3.3 v). 5 measured at 50% of ale 6 when cal_ts pad is used for cal_ale function the hold time is 1 ns instead of 1.5 ns. 1 2 2 3 4 clkout vdde/2 v ol_f v oh_f
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 97 electrical characteristics figure 20. synchronous output timing 6 5 5 clkout bus 5 output signal output vdde/2 vdde/2 vdde/2 vdde/2 6 5 output signal vdde/2 6
MPC5642A microcontroller data sheet, rev. 3.1 98 freescale semiconductor electrical characteristics figure 21. synchronous input timing figure 22. ale signal timing 7 8 clkout input bus 7 8 input signal vdde/2 vdde/2 vdde/2 system clock clkout ale ts addr data a/d 9 10
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 99 electrical characteristics 3.17.5 external interrupt timing (irq pin) figure 23. external interrupt timing 3.17.6 etpu timing table 42. external interrupt timing 1 1 irq timing specified at v dd = 1.14 v to 1.32 v, v ddeh = 3.0 v to 5.25 v, v dd33 and v ddsyn = 3.0 v to 3.6 v, t a =t l to t h . # symbol characteristic value unit min max 1t ipwl irq pulse width low 3 ? t cyc 2t ipwh irq pulse width high 3 ? t cyc 3t icyc irq edge to edge time 2 2 applies when irq pins are configured for rising edge or falling edge events, but not both. 6?t cyc table 43. etpu timing 1 1 etpu timing specified at v dd = 1.14 v to 1.32 v, v ddeh = 3.0 v to 5.25 v, v dd33 and v ddsyn = 3.0 v to 3.6 v, t a =t l to t h , and c l = 50 pf with src = 0b00. # symbol characteristic value unit min max 1t icpw etpu input channel pulse width 4 ? t cyc 2t ocpw etpu output channel pulse width 2 2 this specification does not include the rise and fall times. when calculating the minimum etpu pulse width, include the rise and fall times defined in the slew rate contro l fields (src) of the pad co nfiguration registers (pcr). 2?t cyc irq 1 2 3
MPC5642A microcontroller data sheet, rev. 3.1 100 freescale semiconductor electrical characteristics 3.17.7 emios timing 3.17.8 dspi timing dspi channel frequency support fo r the MPC5642A mcu is shown in table 45 . timing specifications are in table 46 . table 44. emios timing 1 1 emios timing specified at v dd = 1.14 v to 1.32 v, v ddeh = 4.75 v to 5.25 v, t a = t l to t h , and c l =50pf with src = 0b00. # symbol c characteristic value unit min max 1t mipw cc d emios input pulse width 4 ? t cyc 2t mopw cc d emios output pulse width 1 ? t cyc table 45. dspi channel frequency support system clock (mhz) dspi use mode maximum usable frequency (mhz) notes 150 lvds 37.5 use sysclock /4 divide ratio non-lvds 18.75 use sysclock /8 divide ratio 120 lvds 40 use sysclock /3 divide ratio. gives 33/66 duty cycle. use dspi configuration dbr = 0b1 (double baud rate), br = 0b0000 (scaler value 2) and pbr = 0b01 (prescaler value 3). non-lvds 20 use sysclock /6 divide ratio 80 lvds 40 use sysclock /2 divide ratio non-lvds 20 use sysclock /4 divide ratio table 46. dspi timing 1,2 # symbol c characteristic condition min. max. unit 1t sck cc d sck cycle time 3,4,5 24.4 ns 2.9 ms ? 2t csc cc d pcs to sck delay 6 22 7 ?ns 3t asc cc d after sck delay 8 21 9 ?ns 4t sdc cc d sck duty cycle ( ? t sc ) ? 2( ? t sc ) + 2 ns 5t a cc d slave access time (ss active to sout driven) ?25ns 6t dis cc d slave sout disable time (ss inactive to sout high-z or invalid) ?25ns 7t pcsc cc d pcsx to pcss time 4 10 ?ns 8t pasc cc d pcss to pcsx time 5 11 ?ns
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 101 electrical characteristics 9t sui cc data setup time for inputs d master (mtfe = 0) v ddeh =4.75?5.25 v 20 ? ns d v ddeh =3?3.6 v 22 ? dslave 2 ? d master (mtfe = 1, cpha = 0) 12 8? d master (mtfe = 1, cpha = 1) v ddeh =4.75?5.25 v 20 ? d v ddeh =3?3.6 v 22 ? 10 t hi cc data hold time for inputs d master (mtfe = 0) ? 4?ns dslave 7 ? d master (mtfe = 1, cpha = 0) 12 21 ? d master (mtfe = 1, cpha = 1) ? 4? 11 t suo cc data valid (after sck edge) d master (mtfe = 0) v ddeh =4.75?5.25 v ? 5 ns d v ddeh =3?3.6 v ? 6.3 dslave v ddeh =4.75?5.25 v ? 25 d v ddeh =3?3.6 v ? 25.7 d master (mtfe = 1, cpha = 0) ? 21 d master (mtfe = 1, cpha = 1) v ddeh =4.75?5.25 v ? 5 d v ddeh =3?3.6 v ? 6.3 12 t ho cc data hold time for outputs d master (mtfe = 0) v ddeh =4.75?5.25 v ? 5?ns d v ddeh =3?3.6 v ? 6.3 ? dslave 5.5 ? d master (mtfe = 1, cpha = 0) 3 ? d master (mtfe = 1, cpha = 1) v ddeh =4.75?5.25 v ? 5? d v ddeh =3?3.6 v ? 6.3 ? 1 all dspi timing specifications use the fastest slew rate (src = 0b11) on pad type pad_msr. dspi signals using pad type of pad_ssr have an additional delay based on the slew rate. dspi timing is specified at v ddeh = 3.0 to 3.6 v, t a =t l to t h , and c l = 50 pf with src = 0b11. 2 data is verified at f sys = 102 mhz and 153 mhz (100 mhz and 150 mhz + 2% frequency modulation). 3 the minimum dspi cycle time restricts the baud rate selectio n for given system clock rate. these numbers are calculated based on two MPC5642A devices communicating over a dspi link. 4 the actual minimum sck cycle time is limited by pad performance. 5 for dspi channels using lvds output operation, up to 40 mhz sck cycle time is supported. for non-lvds output, maximum sck frequency is 20 mhz. appropriate clock division must be applied. 6 the maximum value is programmable in dspi_ctarx[pssck] and dspi_ctarx[cssck]. table 46. dspi timing 1,2 (continued) # symbol c characteristic condition min. max. unit
MPC5642A microcontroller data sheet, rev. 3.1 102 freescale semiconductor electrical characteristics figure 24. dspi classic spi timing (master, cpha = 0) 7 timing met when pcssck = 3 (01), and cssck = 2 (0000) 8 the maximum value is programmable in dspi_ctarx[pasc] and dspi_ctarx[asc]. 9 timing met when asc = 2 (0000), and pasc = 3 (01) 10 timing met when pcssck = 3 11 timing met when asc = 3 12 this number is calculated assuming the sm pl_pt bitfield in dspi_mcr is set to 0b10. data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol = 0) (cpol = 1) 3 2
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 103 electrical characteristics figure 25. dspi classic spi timing (master, cpha = 1) figure 26. dspi classic spi timing (slave, cpha = 0) data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol = 0) (cpol = 1) last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol = 0) (cpol = 1)
MPC5642A microcontroller data sheet, rev. 3.1 104 freescale semiconductor electrical characteristics figure 27. dspi classic spi timing (slave, cpha = 1) figure 28. dspi modified transfer format timing (master, cpha = 0) 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1) pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol = 0) (cpol = 1)
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 105 electrical characteristics figure 29. dspi modified transfer format timing (master, cpha = 1) figure 30. dspi modified transfer format timing (slave, cpha = 0) pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol = 0) (cpol = 1) last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) 12
MPC5642A microcontroller data sheet, rev. 3.1 106 freescale semiconductor electrical characteristics figure 31. dspi modified transfer format timing (slave, cpha = 1) figure 32. dspi pcs strobe (pcss ) timing 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1) pcsx 7 8 pcss
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 107 electrical characteristics 3.17.9 eqadc ssi timing figure 33. eqadc ssi timing table 47. eqadc ssi timing characteristics (pads at 3.3 v or at 5.0 v) 1 1 ssi timing specified at f sys = 80 mhz, v dd = 1.14 v to 1.32 v, v ddeh = 4.75 v to 5.25 v, t a = t l to t h , and c l = 50 pf with src = 0b00. cload = 25 pf on all outputs. pa d drive strength set to maximum. # symbol c rating value unit min typ max 1f fck cc d fck frequency 2,3 2 maximum operating frequency is highly dependent on track delays, master pad delays, and slave pad delays. 3 fck duty is not 50% when it is generated through the division of the system clock by an odd number. 1/17 1 ? 2f sys_clk 1t fck cc d fck period (t fck = 1/ f fck ) 2 17 t sys_clk 2t fckht cc d clock (fck) high time t sys_clk ? 6.5 9 * t sys_clk + 6.5 ns 3t fcklt cc d clock (fck) low time t sys_clk ? 6.5 8 * t sys_clk + 6.5 ns 4t sds_ll cc d sds lead/lag time ? 7.5 7.5 ns 5t sdo_ll cc d sdo lead/lag time ? 7.5 7.5 ns 6t dvfe cc d data valid from fck falling edge (t fcklt +t sdo_ll ) 1ns 7t eq _ su cc d eqadc data setup time (inputs) 22 ns 8t eq_ho cc d eqadc data hold time (inputs) 1 ns 1st (msb) 2nd 25th 26th 1st (msb) 2nd 25th 26th 8 7 5 6 5 4 4 3 1 3 2 1 2 fck sds sdo external device data sample at sdi eqadc data sample at fck falling edge fck rising edge
MPC5642A microcontroller data sheet, rev. 3.1 108 freescale semiconductor electrical characteristics 3.17.10 flexcan system clock source table 48. flexcan engine syst em clock divider threshold # symbol characteristic value unit 1f can_th flexcan engine system clock threshold 100 mhz table 49. flexcan engine system clock divider system frequency required siu_sysdiv[can_src] value ? f can_th 0 1,2 1 divides system clock source for flexcan engine by 1 2 system clock is only selected for flexcan when can_cr[clk_src] = 1 > f can_th 1 2,3 3 divides system clock source for flexcan engine by 2
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 109 packages 4 packages 4.1 package mechanical data 4.1.1 176 lqfp
MPC5642A microcontroller data sheet, rev. 3.1 110 freescale semiconductor packages figure 34. 176 lqfp package mechanical drawing (part 1) figure 35. 176 lqfp package mechanical drawing (part 2)
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 111 packages figure 36. 176 lqfp package mechanical drawing (part 3)
MPC5642A microcontroller data sheet, rev. 3.1 112 freescale semiconductor packages 4.1.2 208 mapbga figure 37. 208 mapbga package mechanical drawing (part 1)
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 113 packages figure 38. 208 mapbga package mechanical drawing (part 2)
MPC5642A microcontroller data sheet, rev. 3.1 114 freescale semiconductor packages 4.1.3 324 tepbga figure 39. 324 bga package mechanical drawing (part 1)
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 115 packages figure 40. 324 bga package mechanical drawing (part 2)
MPC5642A microcontroller data sheet, rev. 3.1 116 freescale semiconductor ordering information 5 ordering information table 50 shows the orderable part numbers for the MPC5642A series. figure 41. product code structure table 50. orderable part number summary part number flash/sram package speed (mhz) spc5642af2mlu1 2 mb/128 kb 176 lqfp (pb free) 150 sc667201mmg1 2 mb/128 kb 208 mapbga (pb free) spc5642af2mvz1 2 mb/128 kb 324 tepbga spc5642af2mlu2 2 mb/128 kb 176 lqfp (pb free) 120 sc667201mmg2 2 mb/128 kb 208 mapbga (pb free) spc5642af2mvz2 2 mb/128 kb 324 tepbga spc5642af2mlu3 2 mb/128 kb 176 lqfp (pb free) 80 sc667201mmg3 2 mb/128 kb 208 mapbga (pb free) spc5642af2mvz3 2 mb/128 kb 324 tepbga qualification status product family atmc fab and mask revision temperature range package maximum frequency mpc 5642a 1 example code: m vz qualification status mpc = industrial qualified spc = automotive qualified pc = prototype product 5642a = MPC5642A family fab and mask revision f = atmc 0 = revision temperature spec. m = ?40 c to 125 c package code lu = 176 lqfp mg = 208 mapbga vz = 324 tepbga maximum frequency 1 = 150 mhz 2 = 120 mhz 3 = 80 mhz f0
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 117 document revision history 6 document revision history table 51 summarizes customer facing re visions to this document. table 51. revision history date revision substantive changes 05 oct 2010 1 initial release 26 mar 2012 2 figure 1 (MPC5642A series block diagram) , added ecsm block and its definition in the elegend. table 2 (MPC5642A series block summary) , added the following blocks: reacn, siu, ecsm, fmpll, pit and swt. updated table 8 (absolute maximum ratings) in 3, electrical characteristics , deleted the ?recommend ed operating conditions? subsection. table 14 (pmc operating conditions and external regulators supply voltage) , removed minimum value of v ddreg and its footnote. updated table 15 (pmc electrical characteristics) updated section 3.6.1, regulator example updated table 20 (dc electrical specifications) figure 8 (core voltage regulator controller external components preferred configuration) , added ?t1? label to indicate the transistor. table 20 (dc electrical specifications) , changed maximum value of v il_ls to 0.9, was 1.1 table 21 (i/o pad average i dde specifications) , in the v dde column changed all 5.5 to 5.25 table 24 (dspi lvds pad specification) : renamed v oc , was v od updated minimum and maximum value of v oc deleted all footnote table 26 (temperature sensor electrical characteristics) , updated minimum and maximum value of accuracy updated section 3.12, eqadc electrical characteristics added section 3.13, configuring sram wait states updated table 31 (apc, rwsc, wwsc settings vs. frequency of operation) updated table 32 (flash program and erase specifications) table 31 (apc, rwsc, wwsc settings vs. frequency of operation) , changed all values in the wwsc column to 0b01. updated table 32 (flash program and erase specifications) table 33 (flash eeprom module life) : updated temperature value in the retention description (was 150 ? c, is 85 ? c) added values for retention table 34 (pad ac specifications (v dde =4.75 v)) : changed maximum value of medium to 12/12 changed maximum value of slow to 20/20 updated table 35 (pad ac specifications (v dde = 3.0 v)) table 37 (jtag pin ac electrical characteristics) : changed all parameter classification to d changed minumum value of t tmss , t tdis to 10 updated table 38 (nexus debug port timing) added table 39 (nexus debug port operating frequency) table 39 (nexus debug port operating frequency) , added a footnote near the value of t aai table 44 (emios timing) : changed minumum value of t mopw to 1 removed the footnote of t mopw
MPC5642A microcontroller data sheet, rev. 3.1 118 freescale semiconductor document revision history 26 mar 2012 2 (cont?d) merged ?dspi timing (v ddeh = 3.0 to 3.6 v)? and ?dspi timing (v ddeh = 4.5 to 5.5v)? tables into table 46 (dspi timing , ) and changed all parameter classification to d table 47 (eqadc ssi timing characteristics (pads at 3.3 v or at 5.0 v)) changed all parameter classification to d 04 may 2012 3 minor editorial changes and improvements throughout. in section 2.4, signal summary , table 3 (MPC5642A signal properties) , updated the following properties for the nexus pins: ? added a footnote to the ?nexus? title for this pin group. ? added a footnote to the ?name? entry for evto . ? updated the ?status during reset? entry for evto . in section 3.2, maximum ratings , table 8 (absolute maximum ratings) , removed the ?tbd - to be defined? footnote. in section 3.6, power management control (pmc) and power on reset (por) electrical specifications , removed the ?voltage regulator controller (vrc) electrical specifications? subsection. in section 3.8, dc electrical specifications , table 20 (dc electrical specifications) , removed the ?tbd - to be defined? footnote. in section 3.9, i/o pad current specifications , table 21 (i/o pad average i dde specifications) : ? updated values and replaced tbds with numerical data. ? removed the ?tbd - to be defined? footnote. in section 3.9.1, i/o pad v rc33 current specifications , table 22 (i/o pad v rc33 average i dde specifications) : ? updated values and replaced tbds with numerical data. ? removed the ?tbd - to be defined? footnote. in section 3.14, platform flash controller electrical characteristics , table 31 (apc, rwsc, wwsc settings vs. frequency of operation) , removed the ?tbd - to be defined? footnote. in section 5, ordering information , table 50 (orderable part number summary) : ? changed all part numbers from ?MPC5642Af0...? to ?spc5642af2...?. ? changed ?MPC5642Af0mmg1? to ?sc667201mmg1?. ? changed ?MPC5642Af0mmg2? to ?sc667201mmg2?. ? changed ?MPC5642Af0mmg3? to ?sc667201mmg3?. in table 51 (revision history) , removed several erroneous items from the revision 2 entry. 29 jun 2012 3.1 no content changes, technical or editorial, were made in this revision. removed the ?preliminary? footers throughout. changed ?data sheet: advance information? to ?data sheet: technical data? on page 1. removed the ?product under development? disclaimer on page 1. table 51. revision history (continued) date revision substantive changes
MPC5642A microcontroller data sheet, rev. 3.1 freescale semiconductor 119 document revision history
MPC5642A microcontroller data sheet, rev. 3.1 120 freescale semiconductor document revision history document number: MPC5642A rev. 3.1 06/2012 information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fabr icate any integrated circuits based on the information in this document. freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the app lication or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s technical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.reg.net/v2/webservices/freescale/docs/termsandconditions.htm how to reach us: home page: freescale.com web support: freescale.com/support freescale, the freescale logo, altivec, c-5, codetest, codewarrior, coldfire, c-ware, energy efficient solutions logo, kinetis, mobilegt, powerquicc, processor expert, qoriq, qorivva, starcore, symphony, and vortiqa are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. airfast, beekit, beestack, coldfire+, corenet, flexis, magniv, mxc, platform in a package, qoriq qonverge, quicc engine, ready play, safeassure, smartmos, turbolink, vybrid, and xtrinsic are trademarks of freescale semiconductor, in c. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. ? 2009, 2010, 2012 freescale semiconductor, inc.

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