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4.7 f 4.7 f d in c in1 c in2 b240a v bat 3.3 v npor cp2 vcp vin ton lx isen? isen+ vreg clv33 g33 v33 cp1 cpor enbats enbat enb v5 v5p 3.3 v 0.22 f0.22 f 0.22 f A4405 d buck b240a d1 b240a vin(pin1) d2 b240a gnd r sense 300 m 1 / 4 w r cl 390 m 1 / 4 w r drop 1.2 1 / 2 w l1 10 h, 1.3 a 65 m max 3.3 v, 400 ma (500 ma max) 40 c/w 175c max 1 to 4.7 f 1 to 2.2 f 1 to 2.2 f 5 v enable 100 nf 1 k 100 pad v ign 5 v protected 10 f c vreg c v33 c v5 c v5p 0.47 f q v33 r ton 412 k 4.7 k 4.7 k c cpor protec ? on diodes d1 and d2 are required when the v5p pin is driving a wiring harness (or excessively long pcb trace) where parasi ? c inductance will cause the voltage at the v5p to momentarily transi ? on above vin or below ground during a fault condi ? on. a a description the A4405 is an automotive power management ic that uses a high frequency constant on-time 5.45 v pre-regulator to supply two internal 5 v linear regulators and a 3.3 v linear dmos driver. designed to supply can and microprocessor power supplies in high temperature environments, the A4405 is ideal for under hood applications. efficient operation is achieved by using a buck pre-regulator to efficiently drop the input voltage before supplying the linear regulators; this reduces power dissipation and increases overall regulator efficiency. the switching regulator is capable of operating at a nominal switching frequency of 2.2 mhz. the high switching frequency enables the customer to select low value inductors and ceramic capacitors while avoiding emi in the am frequency band. protection features include undervoltage lockout and thermal shutdown. the v5p output is protected from short-to-battery events. in case of a shorted load, all regulators feature A4405-ds, rev. 1 features and benefits ? aec q100 grade 0 qualified ? internal buck pre-regulator followed by ldo outputs ? 5.5 to 36 v vin operating range (50 v maximum); for start/stop, cold crank, and load dump requirements ? 2.2 mhz constant on-time buck regulator ? valley current sensing achieves shortest buck on-times ? 50 v absolute maximum input voltage for surges ? 5.5 to 46 v input voltage range ? ? 40oc to 150oc junction temperature range ? power-on reset (npor pin) with adjustable rising delay ? 5 v (v5p pin) internal low dropout tracking linear regulator with both overcurrent foldback and short-to-battery protection constant on-time buck regulator with one external and two internal linear regulators package: 20-pin tssop with exposed thermal pad (suffix lp) typical application circuit not to scale A4405 continued on the next page? continued on the next page? applications: automotive control modules, such as: ? electronic power steering (eps) ? transmission control (tcu) ? antilock braking (abs) ? emissions control
constant on-time buck regulator with one external and two internal linear regulators A4405 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings 1 characteristic symbol notes rating unit vin pin v in ?0.3 to 50 v lx pin v lx ?0.3 to 50 v t < 250 ns ?1.5 v vcp, cp1, and cp2 pins v vcp , v cpx ?0.3 to 60 v isen ? pin v isen ? ?0.5 to 1 v isen+ pin v isen+ ?0.5 to 0.5 v enbat pin 2 v enbat ?0.3 v enbat pin current i enbat ?50 to 50 ma vreg pin v vreg ?0.3 to 8 v v33 pin v v33 ?0.3 to 7 v g33 pin 3 v g33 ?0.3 v clv33 pin v clv33 ?0.3 to 10 v v5p pin v v5p ?0.3 to v in +0.5 v v5 pin v v5 ?0.3 to 7 v ton pin v ton ?0.3 to 50 v npor and cpor pins v xpor ?0.3 to 7 v enb and enbats pins v en , v enbats ?0.3 to 7 v operating ambient temperature t a range k ?40 to 135 c junction temperature t j (max) ?40 to 150 c storage temperature range t stg ?40 to 150 c 1 absolute maximum ratings are limiting values that should not be exceeded under worst case operating conditions or damage may oc cur. 2 the enbat pin is internally clamped to approximately 8.5 v due to an esd protection device. 3 the g33 pin is internally clamped by an esd protection device. clamp voltages range from 10 v (min) to 15 v (max). thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value unit package thermal resistance r ja estimated on 4-layer pcb based on jedec standard 32 oc/w *additional thermal information available on the allegro website. overcurrent protection. the A4405 also features power-on-reset with adjustable delay for the microprocessor output. the A4405 is supplied in a low profile (1.2 mm max) 20-pin tssop package with exposed thermal pad (suffix lp). the package is lead (pb) free with 100% matte-tin leadframe plating ? 5 v (v5 pin) internal low dropout linear regulator with overcurrent foldback protection ? 3.3 v (v33 pin) external linear regulator dmos driver with a programmable current limit (up to 500 ma) and overcurrent foldback protection ? logic enable input (enb pin) ? ignition enable input (enbat pin) ? ignition status indicator (enbats pin) ? buck pulse-by-pulse overcurrent protection ? buck lx short circuit protection (latched) ? missing asynchronous diode protection (latched) ? switcher (vreg pin), 3.3 v (v33 pin), and charge pump (vcp pin) undervoltage lockout protection (uvlo) ? thermal shutdown protection (tsd) features and benefits (continued) description (continued) selection guide part number packing A4405klptr-t 4000 pieces per 13-in. reel
constant on-time buck regulator with one external and two internal linear regulators A4405 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com table of contents specifications 2 functional block diagram 4 pin-out diagram and terminal list 5 electrical characteristics 6 characteristic performance 9 functional description 11 basic operation 11 overcurrent protection 11 dropout mode 11 soft start 11 buck pulse width ( t on ) 11 isen+ and isen? 11 switcher overcurrent protection 12 lx short circuit protection 12 missing asynchronous diode protection 13 thermal shutdown 13 power-on reset (npor) 13 v5 regulator 14 v5p tracking regulator 14 3.3 v linear regulator 15 charge pump 15 enbat 15 enbats 15 enb 15 timing diagrams 16 application information 18 switcher on-time and switching frequency 18 low voltage operation 18 inductor selection 18 output capacitor 19 input capacitor 19 rectification diode 19 external mosfet selection 19 3.3 v dropping resistor (r drop ) 20 pcb layout 21 application circuit performance 23 package outline drawing 26
constant on-time buck regulator with one external and two internal linear regulators A4405 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional block diagram + ? + ? + ? 3.3 v (from v33) 3.3 v (from v33) v reg v 33 enb 0.22 f 0.22 f charge pump fault v reg uvlo v 33 uvlo 0.22 f v ign b240a d buck d1 b240a r sense 300 m 1 / 4 w r cl 390 m 1 / 4 w r drop 1.2 1 / 2 w l1 10 h, 1.3 a 65 m max 3.3 v, 400 ma (500 ma max) 1 to 4.7 f v ref v ref v ref v ref v ref v reg 1 to 2.2 f 5 v 1 to 2.2 f 100 nf 4.0 v h 2.2 v l 8.5 v 100 tsd switch disable pwm control soft start ramp generator regulator v33 fet driver v5 regulator v5 control and v33 to v5p tracking control short to supply protection 5 v protected 10 f 0.47 f r ton 412 k 4.7 k 4.7 k microcontroller reset microcontroller enable 1 k c v33 c vreg c cpor npor cpor enbats enbat enb v5p gnd pad cp2 vcp vin ton cp1 lx isen? isen+ vreg clv33 g33 v33 v5 q v33 c v5 c v5p 4.7 f 4.7 f d in c in1 c in2 b240a v bat vin(pin1) d2 b240a protec ? on diodes d1 and d2 are required when the v5p pin is driving a wiring harness (or excessively long pcb trace) where parasi ? c inductance will cause the voltage at the v5p to momentarily transi ? on above vin or below ground during a fault condi ? on. a a
constant on-time buck regulator with one external and two internal linear regulators A4405 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pin-out diagram pad 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 vin gnd ton enbat enb enbats npor cpor v5 v5p vcp cp2 cp1 lx isen+ isen? vreg clv33 g33 v33 terminal list table name number function clv33 13 3.3 v current sense and limit input cp1 18 charge pump capacitor terminal 1 cp2 19 charge pump capacitor terminal 2 cpor 8 npor delay programming pin enb 5 logic enable input from the microcontroller enbat 4 ignition enable input from the key or switch via a 1 k resistor enbats 6 open drain ignition status output g33 12 gate driver to the external mosfet for 3.3 v regulation gnd 2 ground terminal isen? 15 buck negative current sense pin, sense resistor and diode node isen+ 16 buck positive current sense pin, sense resistor and ground node lx 17 buck regulator switching node npor 7 active low, open-drain fault indication output pad ? exposed pad for enhanced thermal dissipation ton 3 buck regulator on-time programming pin v33 11 3.3 v regulator output v5 9 5 v regulator output v5p 10 5 v tracking, protected regulator output vcp 20 charge pump reservoir capacitor terminal vin 1 input voltage vreg 14 buck regulator dc output, and input to the 3.3 v external regulator
constant on-time buck regulator with one external and two internal linear regulators A4405 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics valid at ?40c t j 150c, 5.5 v v in 36 v; unless otherwise specified characteristic symbol test conditions min. typ. max. unit general function input voltage v in(f) device functional, parameters not guaranteed 5.5 ? 46 v operating input voltage v in(op) 5.5 13.5 36 v supply quiescent current 1 i q v in = 13.5 v, v ign > v ign(h) or v enb > v enb(h) , no load on vreg ?10?ma i q(sleep) v in = 13.5 v, v ign < v ign(l) , v enb < v enb(l) , no load on vreg ??10 a buck regulator switcher output v vreg enb = high , v insw(l) < v in < 27 v, 25 ma < i vreg < 600 ma 5.25 5.45 5.60 v enb = high , v insw(nom) < v in < 27 v, 25 ma < i vreg < 750 ma 5.30 5.45 5.60 v enb = high , 5.5 v < v in < 6.5 v, lx 100% on, 100 ma < i vreg < 600 ma 5.15 ? 6.46 v switcher period 2 t sw(l) v insw(l) < v in < v insw(nom) , r ton = 412 k ? 1.6 ? s t sw(nom) v insw(nom) < v in < v insw(h) , r ton = 412 k ? 450 ? ns t sw(h) v insw(h) < v in < 36 v, r ton = 412 k ? 1.6 ? s switcher on-time t on v in = 7 v, r ton = 412 k 1070 1335 1600 ns v in = 13.5 v, r ton = 412 k 160 200 240 ns v in = 27 v, r ton = 412 k 80 118 135 ns v in = 35 v, r ton = 412 k 220 275 330 ns switcher period v in threshold v insw(l) v in falling, t sw changes from t sw(l) to 100% duty cycle 5.9 6.2 6.5 v v insw(nom) v in falling, t sw changes from t sw(nom) to t sw(l) 7.7 8.3 8.9 v v insw(h) v in rising, t sw changes from t sw(nom) to t sw(h) 28 31 34 v switcher period v in hysteresis v insw(hys) v insw(l) and v insw(nom) comparators, relative to the v in voltage that initially caused the switcher period to change ? 250 ? mv v insw(h) comparator, relative to the v in voltage that initially caused the switcher period to change ? 700 ? mv buck switch on-resistance r ds(on) t j = 25c, i ds = 0.1 a ? 275 300 m t j = 150c, i ds = 0.1 a ? 400 470 m minimum on-time t on(min) v in = 13.5 v, r ton = 49.9 k ?6590ns minimum off-time t off(min) v in = 13.5 v 85 110 140 ns isen voltage threshold v isen v isen+ ? v isen? 175 220 265 mv vreg valley current limit i lim(valley) r sense = 300 m , v in > v insw(l) ? 733 ? ma vreg peak current limit i lim(peak) 2.5 5.0 ? a continued on the next page?
constant on-time buck regulator with one external and two internal linear regulators A4405 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics (continued) valid at ?40c t j 150c, 5.5 v v in 36 v; unless otherwise specified characteristic symbol test conditions min. typ. max. unit continued on the next page? 5 v linear regulators v5 accuracy and load regulation v v5 10 ma < i v5 < 215 ma, v vreg 5.25 v 4.9 5.0 5.1 v v5p accuracy and load regulation v v5p 10 ma < i v5p < 270 ma, v vreg 5.25 v 4.9 5.0 5.1 v v5p/v33 tracking ratio v5p track v v5p / v v33 1.507 1.515 1.523 ? v5p/v33 tracking accuracy err v5ptrack 2.69 v < v v33 < 3.37 v, i v5p = 75 ma, 5.5 v < v in < 27 v ? 0.5 ? +0.5 % linear regulator and fet driver v33 accuracy err v33 10 ma < i v33 < 500 ma 3.23 3.30 3.37 v g33 source current 1 i g33(src) v v33 = 3.0 v, v g33 = v g33(max) ? 1 v ? 175 ? 250 ? 400 a g33 sink current 1 i g33(sink) v v33 = 3.6 v, v g33 = 6 v 0.5 3 ? ma g33 maximum voltage v g33(max) v v33 = 3.0 v 9 ? 15 v g33 minimum voltage v g33(min) v v33 = 3.6 v ? 0.7 1.0 v g33 output impedance 2 r out ? 175 ? external fet gate capacitance 2 c iss 250 ? 5200 pf charge pump (vcp pin) output voltage v vcp v vcp ? v in 4.1 6.6 ? v switching frequency f sw(cp) ? 100 ? khz logic enable input (enb pin) enb logic input threshold v enb(h) v enb rising ? ? 2.0 v v enb(l) v enb falling 0.8 ? ? v enb logic input current 1 i enb(in) v enb = 3.3 v ? ? 100 a enb pull-down resistance r enb ?60?k ignition enable input (enbat and enbats pins) enbat and enbats thresholds v ign(h) v ign rising via a 1 k series resistance, measure v ign when i q occurs ? ? 4.0 v v ign(l) v ign falling via a 1 k series resistance, measure v ign when i q(sleep) occurs 2.2 ? ? v enbat input current 1 i enbat(in) v ign = 5.5 v via a 1 k series resistance ? 50 100 a v ign = 0.8 v via a 1 k series resistance 0.5 ? 5 a enbat input resistance r enbat ? 650 ? k ignition status output (enbats pin) enbats output voltage v enbats(l) i enbats = 4 ma ? ? 400 mv enbats leakage current 1 i enbats v enbats = 3.3 v ? ? 1 a enbats turn-on delay t enbats sleep mode to v enbats = 3.3 v ? 11 ? ms
constant on-time buck regulator with one external and two internal linear regulators A4405 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics (continued) valid at ?40c t j 150c, 5.5 v v in 36 v; unless otherwise specified characteristic symbol test conditions min. typ. max. unit npor pin output and timing npor power-up delay t npor c por = 0.22 f ? 20 ? ms npor output voltage v npor(l) enb = high or enbat = high, v vreg < v regnpor(l) or v v33 < v 33npor(l) , i npor 4 ma ? ? 400 mv enbat = low, enb transitioning to low, v vreg = 5.45 v, i npor 0.3 ma, 0.8 v < v v33 < err v33 , 0c t j 150c ? 350 800 mv enbat = low, enb transitioning to low, v vreg = 5.45 v, i npor 0.3 ma, 1.0 v < v v33 < err v33 , ? 40c t j 150c ? ? 800 mv npor leakage current 1 i npor(leak) v npor = 3.3 v ? ? 1 a cpor pin characteristics cpor charge current 1 i cpor(src) ? ? 13 ? a cpor threshold v cpor(h) v cpor rising 1.0 1.2 1.4 v vreg pin soft start timing soft start t ss ?10?ms protection circuitry vreg pin npor thresholds v regnpor(h) v vreg rising, npor transitioning to high 4.80 5.00 5.20 v v regnpor(l) v vreg falling, npor transitioning to low 4.75 4.94 5.14 v vreg pin npor hysteresis v reg(hys) ?60?mv v33 regulator npor thresholds v 33npor(h) v v33 rising, npor transitioning to high 2.80 2.95 3.10 v v 33npor(l) v v33 falling, npor transitioning to low 2.69 2.83 2.97 v v33 regulator npor hysteresis v 33(hys) ? 125 ? mv v33 regulator overcurrent threshold v 33ocp v vreg ? v clv33 175 200 245 mv v33 regulator current limit i v33ilim r cl = 620 m ? 323 ? ma v33 regulator foldback threshold v 33ifb v v33 = 0 v, v vreg ? v clv33 35 55 75 mv v33 regulator foldback current limit i v33ifb r cl = 620 m ?89?ma v5p pin current limit 1 i v5pilim v v5p = 5 v ? 300 ? 405 ? ma v5p pin foldback current 1 i v5pifb v v5p = 0 v ? 70 ? 110 ? 150 ma v5 pin current limit 1 i v5ilim v v5 = 5 v ? 230 ? 315 ? ma v5 pin foldback current 1 i v5ifb v v5 = 0 v ? 84 ? 105 ? 163 ma thermal shutdown threshold t jtsd t j rising 155 170 ? oc thermal shutdown hysteresis t jtsd(hys) ?20?oc 1 for input and output current specifications, negative current is defined as coming out of (sourcing) the specified pin. 2 determined by design and systems characterization. not production tested.
constant on-time buck regulator with one external and two internal linear regulators A4405 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 3.27 3.28 3.29 3.30 3.31 3.32 3.33 -40 -20 0 20 40 60 80 100 120 140 v33 output voltage (v) temperature (c) 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 -40 -20 0 20 40 60 80 100 120 140 v5p output voltage (v) temperature (c) 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 -40-20 0 20406080100120140 v5 output voltage (v) temperature (c) 0 100 200 300 400 500 600 700 800 900 1,000 1,100 1,200 1,300 1,400 -40 -20 0 20 40 60 80 100 120 140 t on pulse width (ns) temperature (c) 5.40 5.41 5.42 5.43 5.44 5.45 5.46 5.47 5.48 5.49 5.50 -40 -20 0 20 40 60 80 100 120 140 vreg output voltage (v) temperature (c) v5 output versus temperature vreg output versus temperature v5p output versus temperature t on versus temperature v33 output versus temperature v in = 7.5 v v in = 35 v v in = 13.5 v v in = 27 v characteristic performance
constant on-time buck regulator with one external and two internal linear regulators A4405 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 210 205 200 195 190 185 -40 -20 0 20 40 60 80 100 120 140 v33 over current threshold (mv) temperature ( c) 0 50 100 150 200 250 300 -40 -20 0 20 40 60 80 100 120 140 vreg valley limit (mv) temperature ( c) 0 50 100 150 200 250 300 350 400 -40-20 0 20406080100120140 enbats voltage (mv) temperature (c) i enbats = 4 ma 10 11 12 13 14 15 16 -40-20 0 20406080100120140 cpor charging current (ua) temperature (c) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -40-20 0 20406080100120140 enb threshold (v) temperature (c) 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 -40 -20 0 20 40 60 80 100 120 140 enbat threshold (v) temperature (c) cpor charging current versus temperature enbat start / stop thresholds versus temperature enbats (low) voltage versus temperature enb start / stop thresholds versus temperature vreg valley current limit versus temperature v33 overcurrent threshold versus temperature start stop start stop
constant on-time buck regulator with one external and two internal linear regulators A4405 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional description basic operation the A4405 contains a fixed on-time, buck switching pre-regu- lator with valley sensing current mode control, two integrated 5 v linear regulators, and an n-channel fet driver for a 3.3 v linear regulator. the constant on-time (cot) converter maintains a constant output frequency because the on-time is inversely proportional to the supply voltage. as the input voltage decreases the on-time is increased, which maintains a relatively constant period. valley mode current control allows the converter to achieve very short on-times because current is measured during the off-time. with very low input voltages the buck switch maintains a 100% duty cycle. this turns the buck switch on 100% of the time (no switching) and allows the regulator to operate in dropout mode. the device is enabled via logic level enb or high voltage igni- tion enbat input. when the device is enabled the converter starts up under the control of an internal soft start routine. the two enable inputs are logically ored together internally so either of the inputs can be used to enable the device. under light load conditions the switch enters pulse-skipping mode to ensure regulation is maintained. in order to maintain a wide input voltage range the switcher period is extended when the minimum on- or off-time is reached, or when the input supply is at either end of its range. overcurrent protection the A4405 features overcurrent protection on all regulators including the vreg pre-regulator. the buck switch current limit is determined by the selection of the sense resistor at the isenx pins. output current is also monitored on the 5vp and 5v linear regulators, and if shorted the outputs fold back. the external fet driver has a current limit tap that can be used with a sense resistor to trigger a current limit based on an external resistor and trip voltage. dropout mode the topology of a cot timer is ideal for systems that have high input voltages. because current is measured during the off-time, very short on-times can be achieved. with low input voltages the switcher must maintain very short off-times. to prevent the switcher from reaching its minimum off-time, the switcher is designed to enter a 100% duty cycle mode. this causes the switcher to stop acting as a buck switch. the voltage at vreg then becomes the simply the supply voltage minus the drop across the buck switch and inductor. in this mode the maximum available current may be lower, depending on ambient tempera- ture and supply voltage, while in dropout mode. soft start an internal ramp generator and counter allow the output voltage to ramp-up. this limits the maximum demand on the external power supply by controlling the inrush current required to charge the external capacitor and any dc load at startup. internally, the ramp is set to 10 ms nominal. the following conditions are required to trigger a soft start: ? enbat or enb transition to high, and ? there is no thermal shutdown, and ? v33 voltage is below its uvlo threshold, and ? vreg voltage is below its uvlo threshold. buck pulse width ( t on ) a resistor from the ton input to vin sets the on-time of the converter for a given input voltage. when the supply voltage is between 8.3 and 31 v, the switcher period remains constant based on the selected value of r ton . at voltages lower than 6.5 v the switch is in dropout mode. for reasonable input voltage ranges the period of the converter is held constant resulting in a constant operating frequency over the input supply range. more informa- tion on how to choose r ton can be found in the application information section. the formula to calculate the value for the on-time resistor is: t on = ( r ton / v in ) 6.36 10 ?12 + 5 10 ?9 (ns). (1) isen+ and isen? the sense inputs are used to sense the current in the buck, free- wheeling diode during the off-time cycle. the value for r sense is obtained by the formula: r sense = 220 (mv) / i valley , (2) where i valley is the lowest current measured through the induc- tor during the off-time cycle. it is recommended that the current sense resistor be sized so that, at peak output current, the voltage
constant on-time buck regulator with one external and two internal linear regulators A4405 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com at the isen? pin does not exceed ?0.75 v during pwm opera- tion (that is, a transient condition). because the diode current is measured when the inductor current is at the valley, the average output current is greater than the i valley value. the value for i valley should be: i valley = i out(avg) ? 0.5 i ripple + k , (3) where: i out(avg) is the average of the output currents of all the regulators, i ripple is the inductor ripple current, and k is a design margin allowing for component tolerances. the peak current in the switch is simply: i peak = i valley + i ripple . (4) information on how to calculate the ripple current is included in the application information section. switcher overcurrent protection the converter utilizes pulse-by-pulse valley current limiting, which is activated when the current through the sense resistor (that is, the buck output current) is high enough to create 220 mv between the isen pins. during an overload condition, the switch is turned on for a period determined by the constant on-time circuitry. the switch off-time is extended until the current decays to the current limit value set by the selection of the sense resistor, at which point the switch is allowed to turn on again. because no slope compensation is required in this control scheme, the current limit is maintained at a reasonably constant level across the input voltage range. figure 1 illustrates how the current is limited during an overload condition. the current decay (period with switch off) is propor- tional to the output voltage. as the overload is increased, the out- put voltage tends to decrease and the switching period increases. lx short circuit protection if the lx node is shorted to ground there will be a relatively high peak current in the buck mosfet within a very short time. the A4405 protects itself by detecting the unusually high current, turning off the buck mosfet, and latching itself off. to avoid false tripping, the current required to activate the peak current protection (i lim(peak) , nominally 5 a) is set well above the normal range of currents. when the peak current limit is acti- vated the A4405 is latched off until either v in is cycled below its uvlo threshold or the A4405 is disabled (both enbat and enb must be brought low) and re-enabled. npor is not directly activated (pulled low) by the peak current protection circuitry. however, npor will certainly be in the correct state depending on vreg and v33. time current limit level inductor current, operating at maximum load inductor current, operating a soft overload current limit level current current constant on-time constant period extended period maximum load overload time constant on-time figure 1. current limiting during overload conditions
constant on-time buck regulator with one external and two internal linear regulators A4405 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com missing asynchronous diode protection in most high voltage asynchronous buck regulators, if the asyn- chronous diode is missing or damaged the lx pin will transition to a very high negative voltage when the upper mosfet turns off, resulting in damage to the regulator. the A4405 includes pro- tection circuitry to detect when the asynchronous diode is missing or damaged. if the lx pin becomes more negative than 1.2 v at 25c for more than 200 ns, the A4405 will latch itself in the off state to prevent damage. after a missing diode fault occurs, the latch must be reset by either cycling vin or enbat or enb. see figure 2 for the missing diode voltage threshold and time filtering versus temperature. thermal shutdown if the A4405 junction temperature becomes too high, a thermal shutdown circuit disables the vreg output, thus protecting the A4405 from damage. when a thermal shutdown occurs, the buck regulator stops switching and the vreg voltage will decay. when v vreg crosses its uvlo threshold, the npor signal is pulled low. thermal shutdown is not a latched condition so, when the junction temperature cools to an acceptable level, the A4405 will automatically restart. power-on reset (npor) the npor output is an open drain pin that can be used to signal a reset event to a dsp or microcontroller. the npor function actively monitors enbat, enb, v33, and vreg. during power- up, npor is held low for a programmable amount of time, t npor , after both vreg and v33 transition above their upper uvlo thresholds. the rising edge delay allows time for the regulators to be within specification when the dsp or microcontroller begins processing. the amount of the rising edge delay is determined by the value of the external capacitor from the cpor pin to ground. the rising delay can be calculated from the following formula: t npor = 92.3 10 3 c cpor (seconds). (5) any of the following conditions will force npor to transition to low immediately (within a few microseconds): ? v33 voltage falls below its uvlo threshold, or ? vreg voltage falls below its uvlo threshold, or ? enbat and enb are both low, or ? charge pump voltage is too low. or ? internal ic regulation (v rail ) is too low. if thermal shutdown occurs, pwm switching will terminate, v vreg and/or v v33 will decay below the uvlo threshold, and npor will transition to low. thus, a thermal shutdown event indirectly causes npor to transition to low. when the A4405 is disabled (either both enb and enbat are low, or v in is removed) the npor output is held low until the voltage from the 3.3 v regulator (v v33 ) falls below 1.0 v. this assumes maximum initial current (4 ma) in the npor open drain dmos. the npor voltages would be somewhat lower for lower values of i npor . see figure 3. enb, enbat v v33 i npor v npor 3.3 v 1.0 v 0.3 ma 800 mv 4ma 350 mv (typ) 400 mv figure 3. npor and v33 characteristics when the A4405 is disabled figure 2. missing diode protection versus device junction temperature 170 175 180 185 190 195 200 205 210 215 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 -50 -25 0 25 50 75 100 125 150 time filtering (ns) nega ? ve voltage threshold (v) junc ? on temperature (c) voltage threshold time filtering
constant on-time buck regulator with one external and two internal linear regulators A4405 14 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com v5 regulator the 5 v linear regulator is provided to supply local circuitry. this regulator can deliver 300 ma (typ), 215 ma (min). when a direct short is applied to this regulator the output the current folds back to 0 v at approximately 100 ma (typ) (figure 4). v5p tracking regulator the 5vp linear tracking regulator is provided to supply remote circuitry such as off-board sensors. the v5p pin is monitored and if a short to ground or a short to battery occurs the v5p output is disabled and/or disconnected and the other outputs (vreg, v5, and v33) remain active until the short is removed. the regulator can deliver 375 ma (typ), 270 ma (min). when a direct short is applied to this regulator the output the current folds back to 0 v at approximately 112 ma (typ) (figure 5). the v5p regulator is designed to track the v33 output during power-up and when the device is completing a soft start ramp. the v5p regulator tracks the 3.3 v output to within 0.5% under normal steady state operating conditions. if the v33 regulator is decreasing, the v5p regulator accurately tracks the v33 output down to the point at which a v33 undervoltage fault (2.825 v nominally: 2.95 v ? 125 mv) results in the npor output going active. the figures 6 and 7 show A4405 operation when the v5p pin is shorted to ground and vin (battery). in both cases, the v5p output is disabled and/or disconnected while the other outputs (vreg, v5, and v33) remain active. figure 6. v5p is shorted to ground in 5 s (d v5p is populated); shows v vreg (ch1, 2 v/div.), v v33 (ch2, 1 v/div.), v v5 (ch3, 2 v/div.), v v5p (ch4, 2 v /div.), t = 10 s/div. t v v33 v v5 v v5p v vreg c1 c3 c4 c2 figure 7. v5p is shorted to a 25 v battery; shows v vreg (ch1, 2 v/div.), v v33 (ch2, 2 v/div.), vin pin (ch3, 5 v/div.), v v5p (ch4, 5 v /div.), t = 10 s/div. 6 5 4 3 2 1 0 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 output voltage (v) output current (ma) typical minimum minimum maximum 6 5 4 3 2 1 0 50 100 150 200 250 300 350 output voltage (v) output current (ma) 400 450 500 typical minimum minimum maximum figure 4. foldback current limit of the 5v regulator figure 5. foldback current limit of the 5vp regulator t v v33 v reg v v5p 5 v 25 v 30 v vin pin ringing due to parasitics from a long wire v5p is clamped to a safe level above vin by d2 (see application schematic) all
constant on-time buck regulator with one external and two internal linear regulators A4405 15 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 3.3 v linear regulator an additional 3.3v linear regulator can be implemented using an external mosfet. in the event the 3.3v regulator output is shorted to ground, the A4405 protects the external mosfet by folding back when the programmed current limit, i cl , is exceeded. the current limit is determined by the voltage devel- oped across the external sense resistor, r cl , shown in the typical application circuit schematic. the 3.3v current limit can be calculated using the following formula: i cl = v clv33 / r cl , (6) where v clv33 is as documented in the electrical characteris- tics table, nominally 200 mv. typically r cl will be a fairly low value so it will not dissipate significant power, 1 / 4 w should be adequate, but the tolerance should be 1% or less. when i cl is exceeded, the maximum load current through the external mosfet is typically folded back to 48% of i cl as shown in figure 8. charge pump the charge pump is used to generate a supply above v in . a 0.22 f ceramic monolithic capacitor should be connected between vcp and vin to act as a reservoir to run the dmos switch. the vcp voltage is internally monitored to ensure that the charge pump is disabled in the case of a fault condition. a 0.22 f ceramic monolithic capacitor should be connected between cp1 and cp2. enbat this is a level-triggered enable input, use for enabling the device based on a high voltage ignition or battery switch (via a 1 k resistor). the enbat comparator thresholds are v ign(l) = 2.2 v(min)and v ign(h) = 4.0 v (max). enbat is used only as a momentary switch to enable or wake up the A4405. after enbat is removed, enb must be high to keep the A4405 enabled. the enb and enbat signals are logically ored together internally so either one may wake up the A4405 and both must be low to disable the A4405. only one of the two inputs must be pulled high in order to enable the part. if there is no requirement for an ignition switch, then enbat can be pulled low, which makes enb a single reset control. if an external resistor and capacitor are used to form a low-pass filter to the enbat pin, then a 100 resistor must be used to prevent the external capacitor from discharging into and damag- ing the enbat pin. see the typical application circuit sche- matic for connection of these 3 components. enbats when a logic high is sensed on the enbat input, the enbats output will go high, signaling to the user that the ignition input is high. when a logic low is sensed on the enbat input, then enbats will also transition to low. the enbats input logic levels are identical to the enbat input logic levels. enb this pin can be used as an enable input from either a dsp or from a microcontroller. this input has an internal pull-down resistor so it may be left unconnected if not used. 3.5 3.0 2.5 2.0 1.5 1.0 05 0 50 10 20 30 40 50 60 120 90 100 110 80 70 output voltage (v) percentage of normal current se ng (%) typical minimum maximum figure 8. foldback current limit of the v33 regulator
constant on-time buck regulator with one external and two internal linear regulators A4405 16 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com timing diagrams typical power-up and power-down by enbat and enb with v in = 13.5 v; enbats is assumed to be connected to v33 via a pull-up resistor vin npor cpor enbats enbat enb v5 v5p 3 v3 internal v rail or vcp vreg v h =4.0v v l =2.2v 10 ms 20 ms 1. 2 v 13.5 v v h =5.00v v h =2.95 v clamped at 8.5v via 1k v l =4.94v v l =2.83v v h =2v v l =0.8v internal uvlo 1.0 v 0.8 v max internal uvlo vreg > 5.00 v and v33 > 2.95 v enb < 0.8v or vreg < 4.94v or v33 < 2.83v or vcp low or internal v rail low npor is open-drain, pulled up to v33 decay rates of vreg, v5, v5p, and v33 depend on output capacitances and loading enbats is open-drain, pulled up to v33 v5, v5p, and v33 ramp at approximately the same rate as vreg
constant on-time buck regulator with one external and two internal linear regulators A4405 17 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com vin npor cpor enbats enbat enb v5 v5p 3 v3 internal v rail or vcp vreg 10 ms 20 ms 1. 2 v 13.5 v v h =5.00v v h =2.95v v l =4.94v v l =2.83v 6.5 v internal uvlo 5.2 v 5.5 v 4. 9 v v enbat = 0v enbats is not connected 100 % duty cycle internal regulators collapse 0.8 v max 1.0 v internal uvlo v enb 2v prior to v in ramping up vreg > 5.00 v and v33 > 2.95 v enb < 0.8v or vreg < 4.94v or v33 < 2.83v vcp low or internal v rail low v5p tracks v33 until v v33npor(l) or v in < 5.5 v v5, v5p, and v33 ramp at approximately the same rate as vreg npor is open-drain, pulled up to v33 decay rates of vreg, v5, v5p, and v33 depend on output capacitances and loading typical power-up and power-down via vin with enb always logic high; enbat and enbats are not used
constant on-time buck regulator with one external and two internal linear regulators A4405 18 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com application information switcher on-time and switching frequency in order for the switcher to maintain regulation, the energy that is transferred to the inductor during the on-time must be transferred to the capacitor during the off-time. because of this relation- ship, the load current and ir drops, as well as input and output voltages, affect the on-time of the converter. the formula that governs switcher on-time is shown below: = t on v in ? r ds(on) i peak + v f t sw { v vreg + [( r l + r sense ) i peak ] + v f } . (7) where v f is the forward voltage on the diode d buck in the typi- cal application circuit schematic. the effects of the voltage drop on the inductor and trace resis- tance will affect the switching frequency. however, the frequency variation due to these factors is small and is covered in the varia- tion of the switcher period, which is 25% of the target. remov- ing these current dependant terms simplifies the formula: = t on v in ? r ds(on) i peak + v f (1/ f sw ) ( v vreg + r sense i peak ) + v f . (8) be sure to use the worst-case sense voltage and forward voltage of the diode d buck , including any effects due to temperature. for an example: assume a 1 a converter with a supply voltage of 13.5 v. the output voltage is 5.45 v, v f is 0.45 v, r sense i peak is 0.20 v, r ds(on) i peak is 0.15 v, and the required frequency is 2.2 mhz. substituting into equation 8, we can solve for t on : t on = 1 / 2.2 (mhz) [(5.45+0.20+0.45) / (13.5 ? 0.15 + 0.45)] = 201 (ns) . the formulas above describe how t on changes based on input and load conditions. because load changes are minimal and the output voltage is fixed, the only factor that will affect the on-time is the input voltage. the converter is able to maintain a constant period over a varying supply voltage because the on-time changes based on the input voltage. the current into the ton terminal is derived from a resistor tied to vin, which sets the on-time pro- portional to the supply voltage. selecting the resistor value based on the t on calculated above is done using the following formula: r ton = [v in ( t on ? 5 (ns) )] / 6.36 10 ?12 . (9) after the resistor is selected and a suitable t on is found, it must be demonstrated that t on does not, under worst-case condi- tions, exceed the minimum on-time or minimum off-time of the converter. the minimum on-time occurs at maximum input voltage and minimum load. the maximum off-time occurs at minimum supply voltage and maximum load. for supply voltages below 8.3 v and above 6.5 v, refer to the low voltage opera- tion section. low voltage operation the converter can run at very low input voltages; with a 5.25 v output the minimum input supply can be as low as 5.5 v. when operating at high frequencies the on-time of the converter must be very short because the available period is short. at high input voltages the converter should not violate the minimum on-time, t on (min), while at low input voltages the converter should not violate the minimum off-time, t off (min). rather than limit the supply voltage range, the converter solves this problem by automatically increasing the period. with the period extended the converter will not violate the minimum on-time or off-time specifications. if the input voltage is between 8.3 and 31 v, the converter maintains a constant period. when calculating worst case on-times and off-times, make sure to use the highest switch- ing frequency if the supply voltage is in that range. when operating at voltages below 8.3 v, additional care must be taken when selecting the inductor and diode. at low voltages the maximum current may be limited due to the ir drops in the current path. when selecting external components for low volt- age operation, the ir drops must be considered for determining on-time, so the complete equation (formula 8) should be used to make sure the converter does not violate the timing specification. inductor selection choosing the right inductor is critical to the correct operation of the switcher. the converter is capable of running at frequencies above 2 mhz, this makes it possible to use small inductor values, which reduces cost and board area. the inductor value is what determines the ripple current. it is important to size the inductor so that under worst-case condi- tions i trip equals i av g , minus half of the ripple current, plus a reasonable margin. if the ripple current is too large, the converter will activate the current limit function. typically peak-to-peak
constant on-time buck regulator with one external and two internal linear regulators A4405 19 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com ripple current should be limited to a range of 20% to 25% of the maximum average load current. worst-case ripple current occurs at maximum supply voltage. after calculating the duty cycle for this condition, the ripple cur- rent can be calculated: = d v in (max)? r ds(on) i peak + v f v vreg + ( r sense i peak ) + v f . (10) using the duty cycle, a ripple current can be calculated using the formula below: = l d i ripple v in ? v vreg f sw (min) 1 , (11) where i ripple is 25% of the maximum load current, and f sw (min) is the minimum switching frequency, nominal frequency minus 25%. for the example used above, a 1 a converter with a supply voltage of 13.5 v was the design objective. the supply voltage can vary by 10%. the output voltage is 5.45 v, v f is 0.5 v, v sense is 0.20 v and the required frequency is 2.2 mhz. the duty cycle is calculated to be 36.45%. the worst-case frequency is 1.76 mhz, 2.2 mhz minus 20%. using these numbers in formula 11 shows that the minimum inductance for this converter is 9.6 h. output capacitor the converter is designed to operate with a low value ceramic output capacitor on vreg (c vreg ). when choosing a ceramic capacitor make sure the rated voltage is at least 3 times the maximum output voltage of the converter. this is because the capacitance of a ceramic decreases as it operates closer to the capacitor rated voltage. it is recommended that the vreg output be decoupled with a 10 f x7r ceramic capacitor. greater capacitance may be required on the output if load surges dramati- cally influence the output voltage. output ripple is determined by the output capacitance and the effects of esr and esl can be ignored assuming recommended layout techniques are followed. the output voltage ripple is approximated by: v ripple = i ripple / (8 f sw c vreg ) (12) input capacitor the value of the input capacitance affects the amount of cur- rent ripple on the input. this current ripple is usually the source of supply-side emi. the amount of interference will depend on the impedance from the input capacitor and the bulk capacitance located on the supply bus. placing a 0.1 f ceramic capacitor very close to the input supply pin will help reduce emi effects. the small capacitor will help reduce high frequency transient cur- rents on the supply line. if further filtering is needed it is recom- mended that two ceramic capacitors be used in parallel to further reduce emissions. rectification diode the diode conducts the current during the off cycle. a schottky diode is required to minimize the forward drop and switching losses. in order to size the diode correctly it is necessary to find the average diode conduction current using the formula below : i diode(avg) = i load (1 ? d( min )) (13) where d(min) is the minimum duty cycle, defined as: d( min ) = (v vreg + v f ) / (v in + v f ) (14) where v in is the maximum input voltage and v f is the maximum forward voltage of the diode. the average power dissipation in the diode is: p d diode(avg) = i avg d( min ) v f (15) the power dissipation in the sense resistor must also be consid- ered using i 2 r and the minimum duty cycle. external mosfet selection to choose an external mosfet for the 3.3 v linear regulator consider the maximum of: drain-to-source voltage (v ds ), contin- uous drain current (i d ), threshold voltage (v gsth ), on-resistance (r ds(on) ), and thermal resistance (r jc ). the buck switcher pre-regulates the voltage to the external mosfet, so even under worst case conditions, the mosfet will not have to support more than 7 v from drain to source. also, the 3.3 v current limit will usually be set from 200 to 500 ma using the external current setting resistor, r cl . numerous mosfets are available with v ds ratings of at least 20 v that can support much more than 1 a. these two goals should not be difficult to achieve.
constant on-time buck regulator with one external and two internal linear regulators A4405 20 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the A4405 gate drive circuitry is guaranteed to pull the g33 voltage down to 1 v, maximum. therefore, allegro recommends using a mosfet with a v gs threshold (v gsth ) higher than 1 v. do not use a mosfet that will conduct significant current when v gs is at 1 v and the system is at the highest expected ambient temperature. one of the more critical specifications is the mosfet on- resistance, r ds(on) . if the on-resistance is too high, then the 3.3 v regulator will not be able to maintain 3.3 v at the maximum required load current, i lim(v33) . calculate the typical r ds(on) (at 25c) using the following formula: r ds(on)25c < 0.6 1.56 (v) / ( i lim(v33) ? r drop ) (16) where i lim(v33) is the maximum required 3.3 v output current, and r drop is the value of the resistor connected from the clv33 pin to the drain of the mosfet. the multiplier of 0.6 in the following formula allows a 66% increase in r ds(on) when the mosfet is very hot: < r ds(on)25c 0.6 ? r drop i lim(v33) 1.56 (v) . (17) where i lim(v33) is the maximum required 3.3 v output current. the necessity and value of r drop is closely related to the thermal resistance (r jc ) of the mosfet. for a medium size mosfet (such as an sot-223) including r drop in the pcb layout is highly recommended. for a large size mosfet with a very low thermal resistance (such as a dpak) r drop is probably not necessary. mosfet thermal resistance is a function of die size, package size, and cost. so, choosing r drop and r jc together should result in optimal performance, minimal component sizes, and lowest system cost. determining the value and power dissipated by the series dropping resistor and mosfet thermal resistance are addressed in detail in the 3.3 v dropping resistor section. 3.3 v dropping resistor (r drop ) in the typical application circuit schematic, there are two resis- tors, r cl and r drop , from the output of the buck regulator to the drain of the external mosfet. r cl must always be pres- ent because it sets the 3.3 v regulator current limit threshold. however, r drop , if used, prevents the external mosfet from dissipating too much power during certain conditions. in particu- lar, when the battery voltage is extremely low (v bat 6.5 v) and the buck regulator transitions to dropout mode (100% duty cycle) then v vreg will be approximately 1 v higher than normal. in this situation, without r drop , the mosfet could dissipate too much power. the value of r drop depends on the maximum pcb temperature, the maximum current load on the 3.3 v regulator, i lim(v33) , the maximum allowable junction temperature of the mosfet, and the thermal resistance of the mosfet. as the thermal resistance of the mosfet decreases, the required value of r drop will also decrease. if the mosfet is relatively large and has a very low thermal resistance, then r drop is not required (0 ). figure 9 shows recommended values of r drop versus mosfet thermal resistance at various 3.3 v regulator maximum current settings ( i lim(v33) ). this graph assumes a pcb temperature of 135c, a maximum mosfet junction temperature of 145c, v bat of 6.5 v, and 3.23 v from the linear regulator. this graph takes into account the voltage drop across the 3.3 v current limit resistor, r cl . 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 10 15 20 25 30 35 40 45 50 55 60 r drop ( ) mosfet thermal resistance ( c/w) 140 ma 230 ma 320 ma 410 ma 500 ma figure 9. value of r drop versus mosfet thermal resistance at various v33 regulator maximum current settings, i lim(v33)
constant on-time buck regulator with one external and two internal linear regulators A4405 21 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com after a value for r drop is determined, the designer should calcu- late its maximum power dissipation (i 2 r) and select an appro- priate component, allowing adequate design margin. assuming the r drop value was chosen referencing figure 9, then figure 10 can be used to determine the power dissipated by r drop versus mosfet thermal resistance at various 3.3v regulator current settings. the exact value of r drop is not critical, so a component with 1% or 5% tolerance could be used. pcb layout the board layout will have a large impact on the performance of the device. it is important to isolate high current ground returns to minimize ground bounce that could produce reference errors in the device. the method used to isolate power ground from noise sensitive circuitry is to use a star ground. this approach ensures that the high current components such as the input capacitor, out- put capacitor, and diode have very low impedance paths to each other. figure 11 illustrates the technique. the ground connections from each of the components should be very close to each other and be connected on the same surface as the components. internal ground planes should not be used for the star ground connection, because vias add impedance to the current path. in order to further reduce noise effects on the pcb, noise sensi- tive traces should not be connected to internal ground planes. the feedback network from the switcher output should have an independent ground trace that goes directly to the exposed pad underneath the device. the exposed pad should be connected to internal ground plans and any exposed copper used for heat dissipation. if the ground connections from the device are also connected directly to the exposed pad, the ground reference from the feedback network will be less susceptible to noise injection or ground bounce. 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 10 15 20 25 30 35 40 45 50 55 60 p rdrop (w) mosfet thermal resistance ( c/w) 140 ma 230 ma 320 ma 410 ma 500 ma figure 10. r drop dissipation versus mosfet thermal resistance at various v33 regulator maximum current settings, i v33ilim figure 11. illustration of star ground connection star ground lx q1 A4405 d buck current path (off-cycle) current path (on-cycle) r sense l1 vin c in r load c vreg
constant on-time buck regulator with one external and two internal linear regulators A4405 22 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com to reduce radiated emissions from the high frequency switching nodes, it is important to have an internal ground plane directly under the lx node. the plane should not be broken directly under the node because the lowest impedance path back to the star ground would then be directly under the signal trace. if another trace does break the return path, the energy will have to find another path, which is through radiated emissions. for accurate current sensing, the current sense pins, isen+ and isen?, and the internal differential amplifier comprise a dif- ferential signal receiver, and a balanced pair of traces should be routed from the pins of the buck current sense resistor, r sense , as shown in figure 12 (upper panel). the isen+ pin and the sense resistor ground should not be separated by simply using local via connections to the ground plane (figure 12 lower panel). incorrect routing of the isen+ pin would likely add an offset error to the buck current sense signal. lx isen ? isen + A4405 differential amplifier d buck (asynchronous) r sense l1 + ? lx isen ? isen + ground plane A4405 differential amplifier d buck (asynchronous) r sense l1 + ? figure 12. comparison of routing paths for the traces between the A4405 isen+ and isen? traces and the sense resistor, r sense correct routing of isen+ and isen? traces (direct on same plane) incorrect routing of isen+ and isen? traces (using vias to a ground plane)
constant on-time buck regulator with one external and two internal linear regulators A4405 23 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com application circuit performance (refer to typical application circuit diagram.) frequency (khz) phase () gain (db) 10 3 100 10 1 10 ?1 60 48 36 24 12 0 -12 -24 -36 -48 -60 200 160 120 80 40 0 -40 -80 -120 -160 -200 gain 215 ma gain 0.8 a gain margin 12 db phase 215 ma phase margin 215 ma (55) phase margin 0.8 a (59) phase 0.8 a gain 0 db (215 ma: at 106 khz 0.8 ma: at 104 khz) -0.50 -0.45 -0.40 -0.35 -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 v out percentage drop (%) v out percentage drop (%) output current, i out (a) -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.000 0.050 0.100 0.150 0.200 0.250 0.300 output current, i out (a) v5 v5p v33 50 55 60 65 70 75 80 85 90 95 100 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 e ? ciency (%) output current, i out (a) buck regulator bode plots at i load = 215 ma and 0.8 a e ? ciency (%) output current, i out (a) - - - output current, i out (a) buck regulator (vreg) efficiency buck regulator (vreg) load regulation linear regulator load regulation v in = 8 v v in = 12 v v in = 16 v v in = 8 v v in = 12 v v in = 16 v bill of materials for critical components this design is capable of full load, 135c ambient, and 5.5 v bat indefinitely with an adequate thermal solution component description package manufacturer part number q v33 mosfet, 40 v, 90 a, 4.3 m , t j 175c dpak infineon ipd90n04s3-04 r sense resistor, 0.300 , 1 / 4 w, 1% 1206 r cl resistor, 0.390 , 1 / 4 w, 1% 1206 r drop resistor, 1.2 total, 1 / 2 w, 1% 1210 c in1 , c in2 capacitor, ceramic, 4.7 f, 50 v, 10%, x7r 1210 murata gcm32er71h475ka55l c vreg capacitor, ceramic, 10 f, 16 v, 10%, x7r 1206 kemet c1206c106k4ractu c v33 , c v5 , c v5p capacitor, ceramic, 2.2 f, 16 v, 10%, x7r 1206 murata grm31mr71c225ka35l d buck , d in , d v5p diode, schottky, 2 a, 40 v sma diodes, inc. b240a-13-f l1 inductor, 10 h, 64 m , 2.39 a sat , 165c 7.6 x 7.6 mm cooper/bussman dra73-100-r
constant on-time buck regulator with one external and two internal linear regulators A4405 24 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com startup at v in = 13.5 v; shows v vreg (ch1, 2 v/div.), v v33 (ch2, 2 v/div.), npor (ch3, 2 v /div.), t = 5 ms/div. t v v33 npor v vreg c1 c3 c2 pwm at v bat = 12 v with a vreg 0.8 a load; shows v vreg (ch1, 5 v/div.), v lx (ch2, 5 v/div.), i l (ch3, 500 ma/div.), t = 500 ns/div. t v reg v lx i l c1 c3 c2 startup at v in = 13.5 v; shows v vreg (ch1, 2 v/div.), v v5 (ch2, 2 v/div.), v v5p (ch3, 2 v/div.), npor (ch4, 2 v /div.), t = 5 ms/div. c1 c3 c4 c2 t v v5 v v5p npor v vreg startup at v in = 6.5 v; shows v vreg (ch1, 2 v/div.), v v5 (ch2, 2 v/div.), v v5p (ch3, 2 v/div.), npor (ch4, 2 v /div.), t = 5 ms/div. c1 c3 c4 c2 t v v5 v v5p npor v vreg startup at v in = 6.5 v; shows v vreg (ch1, 2 v/div.), v v33 (ch2, 2 v/div.), npor (ch3, 2 v /div.), t = 5 ms/div. t v v33 npor v vreg c1 c3 c2 pwm at v bat = 12 v with a vreg 25 ma load; shows v vreg (ch1, 5 v/div.), v lx (ch2, 5 v/div.), i l (ch3, 100 ma/div.), t = 2 s/div. t v vreg i l c1 c3 c2 v lx
constant on-time buck regulator with one external and two internal linear regulators A4405 25 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com v v33 transient response: 125 ma to 250 ma; shows v v33 (ch1, 50 mv/div.), i v33 (ch2, 100 ma/div.), t = 50 s/div. t v v33 i v33 c1 c2 v v5 transient response: 100 ma to 200 ma; shows v v5 (ch1, 50 mv/div.), i v5 (ch2, 100 ma/div.), t = 50 s/div. c1 c2 t v v5 i v5 vreg short circuit operation, v in = 12 v; shows v vreg (ch1, 2 v/div.), i l (ch2, 500 ma/div.), t = 5 s/div. c1 c2 t i l v vreg v v5p transient response: 125 ma to 250 ma; shows v v5p (ch1, 50 mv/div.), i v5p (ch2, 100 ma/div.), t = 50 s/div. t v v5p i v5p c1 c2 vreg normal and overloaded operation, v in = 12 v; shows i l (ch1, 250 ma/div.), v vreg (ch2, 2 v/div.) t i l i l v vreg v vreg before overcurrent after overcurrent c1 c2 c1 c2
constant on-time buck regulator with one external and two internal linear regulators A4405 26 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package lp, 20-pin tssop with exposed thermal pad a 1.20 max 0.15 0.00 0.30 0.19 0.20 0.09 8o 0o 0.60 0.15 1.00 ref c seating plane c 0.10 20x 0.65 bsc 0.25 bsc 2 1 20 6.500.10 4.400.10 3.00 3.00 4.20 4.20 6.400.20 gauge plane seating plane a terminal #1 mark area for reference only; not for tooling use (reference mo-153 act) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown b 0.45 1.70 20 2 1 pcb layout reference view b 6.10 0.65 c exposed thermal pad (bottom surface) reference land pattern layout (reference ipc7351 sop65p640x110-21m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) c
constant on-time buck regulator with one external and two internal linear regulators A4405 27 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com revision history revision revision date description of revision rev. 1 december 21, 2012 change in absolute maximums copyright ?2012, allegro microsystems, inc. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com

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