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s3c9424/c9428/p9428 product overview 1 - 1 1 product overview sam87r i product family samsung ? s sam87ri family of 8-bit single-chip cmos microcontrollers offers a fast and efficient cpu, a wide range of integrated peripherals, and various mask-programmable rom sizes. a address/data bus architecture and a large number of bit- configurable i/o ports provide a flexible programming environment for applications with varied memory and i/o requirements. timer/counters with selectable operating modes are included to support real-time operations. s3c9424/c9428/p9428 microcontroller the s3c9424/c9428/p9428 single-chip 8-bit microcontroller is fabricated using an advanced cmos process. it is built around the powerful sam87ri cpu core. the s3c9424/c9428/p9428 is a versatile microcontroller , with its a/d converter, sio, iic and a zero-crossing detection capability it can be used in a wide range of general purpose applications. stop and idle power-down modes were implemented to reduce power consumption. to increase on-chip register space, the size of the internal register file was logically expanded. the s3c9424/c9428/p9428 have 4k-byte or 8k-byte of program memory on-chip (rom) and 208-bytes of general purpose register area ram . using the sam87ri design approach, the following peripherals were integrated with the sam87ri core: ? four configurable i/o ports (24 pins ) ? nine interrupt s ources with one vector and one interrupt level ? two 8-bit timer/counter with various operating modes ? analog to digital converter with 12 input channels and 10-bit resolution ? one synchronous sio module ? one iic module ? two 12-bit pwm output the s3c9424/c9428/p9428 microcontroller is ideal for use in a wide range of electronic applications requiring simple timer/counter, pwm, adc, sio, iic, zcd and capture functions. s3c9424/c9428/p9428 is available in a 28/32- pin sop and a 30-pin sdip package. otp the S3P9428 is an otp (one time programmable) version of the s3c9424/c9428 microcontroller. the S3P9428 has on-chip 8-k-byte one-time-programmable eprom instead of masked rom. the S3P9428 is fully compatible with the s3c9424/c9428, in function, in d.c. electrical characteristics and in pin configuration.
product overview s3c9424/c9428/p942 8 1 - 2 features cpu ? sam87ri cpu core memory ? 208-byte general purpose register area (ram) ? 4k/8k byte internal program memory (rom) instruction set ? 41 instructions ? the sam87ri core provides all the sam87 core instruction except the word-oriented instruction, multiplication, division, and some one-byte instruction instruction execution time ? 375 n s at 16 mhz fosc(minimum) interrupts ? 9 interrupt sources and 1 vector ? one interrupt level general i/o ? four i/o ports (total 24 pins ) ? bit programmable ports serial i/o ? one synchronous serial i/o module ? selectable transmit and receive rates multi-master iic-bus ? serial peripheral interface zero-crossing detection circuit ? zero crossing detection circuit that generates a digital signal in synchronism with an ac signal input built-in reset circuit (lvd) ? low voltage detector for safe reset timer/counters ? one 8-bit basic timer for watchdog function ? one 8-bit timer/counter with three operating mode ? one 8-bit timer/counter pwm module ? 12-bit pwm 2-ch (max: 250khz) ? 6-bit base + 6-bit extension frame ? one 8-bit timer/counter a/d converter ? 12 analog input pins ? 10-bit conversion resolution buzzer frequency range ? 200 hz to 20 khz signal can be generated oscillator freqeuncy ? 1-mhz to 16-mhz external crystal oscillator maximum 16-mhz cpu clock ? rc: 4mhz(typ) operating temperature range ? ? 4 0 c to + 85 c operating voltage range ? 3.0 v to 5.5 v (lvd) ? 1.8 v to 5.5 v (no lvd) otp interface protocol spec ? serial otp package types ? s3c9424/c9428 32-pin sop-450 (3v lvd) 30-pin sdip-400 (3v lvd) 28-pin sop-375
s3c9424/c9428/p9428 product overview 1 - 3 block diagram port 0 4k/8k rom 208-byte register file port 1 timer 1 basic timer timer 0 osc adc buz pwm p0.0-p0.7 sck,so, si, ad8-ad11 port 2 port 3 zcd iic sio p1.0-p1.3 t0, buz, int0, int1 port i/o and interrupt control sam87ri cpu x in x out t0 (cap) t0(pwm) ad0-ad11 p1.1/buz p0.7/pwm0 p1.3/pwm1 p2.0-p2.7 ad0-ad7 p3.0-p3.3 zcd p2.7/sclk p2.6/sdat p0.0/sck p0.1/so p0.2/si figure 1 -1 . block diagram
product overview s3c9424/c9428/p942 8 1 - 4 pin assignments s3c9424/c9428 32-sop (top view) v ss x in x out test p0.1/so p0.0/sck reset p3.0 p3.2 p2.0/ad0 p2.1/ad1 p2.2/ad2 p2.3/ad3 p2.4/ad4 p2.5/ad5 av ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd p0.2/si p0.3/clo p0.4/ad8 p0.5/ad9 p0.6/ad10 p0.7/ad11/pwm0 p3.1 p3.3 p1.0/t0/zcd p1.1/buz p1.2/int0 p1.3/int1/pwm1 p2.7/ad7/sclk p2.6/ad6/sdat av ref 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 figure 1 -2 . pin assignment diagram ( 32 -pin so p package)
s3c9424/c9428/p9428 product overview 1 - 5 pin assignments (continued) v ss x in x out test p0.1/so p0.0/sck reset reset p3.0 p2.0/ad0 p2.1/ad1 p2.2/ad2 p2.3/ad3 p2.4/ad4 p2.5/ad5 av ss v d d p0.2/si p0.3/clo p0.4/ad8 p0.5/ad9 p0.6/ad10 p0.7/ad11/pwm0 p3.1 p1.0/t0/zcd p1.1/buz p1.2/int0 p1.3/int1/pwm1 p2.7/ad7/sclk p2.6/ad6/sdat av ref s3c9424/c9428 30-sdip (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 figure 1 -3 . pin assignment diagram ( 30 -pin sdip package) s3c9424/c9428 28-sop (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v ss x in x out test p0.1/so p0.0/sck reset reset p2.0/ad0 p2.1/ad1 p2.2/ad2 p2.3/ad3 p2.4/ad4 p2.5/ad5 av ss v d d p0.2/si p0.3/clo p0.4/ad8 p0.5/ad9 p0.6/ad10 p0.7/ad11/pwm0 p1.0/t0/zcd p1.1/buz p1.2/int0 p1.3/int1/pwm1 p2.7/ad7/sclk p2.6/ad6/sdat av ref figure 1 -4 . pin assignment diagram ( 28 -pin sop package)
product overview s3c9424/c9428/p942 8 1 - 6 pin descriptions table 1 - 1. s3c9424/c9428/p9428 pin descriptions pin names pin type pin description pin type share pins p0.0-p0.7 i/o bit-programmable i/o port for schmitt trigger input or push- pull, open-drain output. pull-up resistors are assignable by software. e e-1 sck,so,si , clo, ad8-ad11 p1.0-p1.3 i/o bit-programmable i/o port for schmitt trigger input or push- pull output. pull-up resistors are assignable by software. port 1 pins can also be used as alternative functions. d t0/zcd buz int0 int1 p2.0-p2.7 i/o bit-programmable i/o port for schmitt trigger input or push- pull , open drain output. pull up resistors are assignable by software. port 2 can also be used as external interrupt, a/d input . e-1 ad0-ad7 p3.0-p3.3 o push-pull or open-drain output port. pull-up resistors are assignable by software. e-2 ? x in , x out ? crystal/ceramic, or rc oscillator signal for system clock. ? ? reset i system reset signal input pin. b ? test i test signal input pin (for factory use only: must be connected to v ss ) ? ? av ref , a v ss ? a/d converter reference voltage input and ground ? ? v dd , v ss ? voltage input pin and ground ? ? sck i/o serial interface clock input or output e p0.0 so o serial data output e p0.1 si i serial data output e p0.2 clo o system clock output port e p0.3 sclk sdat i/o iic clock iic data e-1 p2.7 p2.6 buz o 200 hz-20 khz frequency output for buzzer sound. d p1.1 zcd i zero crossing detector input d p1.0 t0 i/o timer 0 capture input or 10-bit pwm output d p1.0 int0 int1 i external interrupt input d p1.2 p1.3 pwm0 pwm1 o 12-bit pwm output e-1 d p0.7 p1.3 ad0-ad11 i a/d converter input e-1 p2.0-p2.7 p0.4-p0.7
s3c9424/c9428/p9428 product overview 1 - 7 pin circuits p-channel n-channel in v dd figure 1 -5 . pin circuit type a last developing: 99.02.02 in v dd pull-up resistor figure 1 -6 . pin circuit type b p-channel n-channel v dd out output disable data figure 1 -7 . pin circuit type c i/o output disable data circuit type c resistor enable v dd data p-channel pull-up resistor figure 1-8. pin circuit type d
product overview s3c9424/c9428/p942 8 1 - 8 v dd pull-up enable v dd i/o pne output disable data p-ch pull-up resistor input n-ch figure 1 -9 . pin circuit type e v dd pull-up enable v dd i/o pne output disable data p-ch pull-up resistor input n-ch analog input figure 1 -10 . pin circuit type e-1 v dd pull-up enable v dd out pne data 47k output disable figure 1 -11 . pin circuit type e-2
s3c9424/c9428/p9428 address spaces 2 - 1 2 address spaces overview the s3c9424/c9428/p9428 microcontroller has two kinds of address space: ? internal p rogram memory (rom ) ? internal register file a 13 -bit address bus supports program memory operations. a separate 8 -bit register bus carries addresses and data between the cpu and the internal register file. the s3c9424/c9428/p9428 have 4 k - bytes or 8k-bytes of mask-progr ammable on-chip program memory: which is configured as the internal rom mode, all of the 4 k-byte internal program memory is used. the s3c9424/c9428/p9428 microcontroller has 208 general-purpose registers in its internal register file. forty- four bytes in the register file are mapped for system and peripheral control functions.
address spaces s3c9424/c9428/p9428 2 - 2 program memory (rom) normal operating mode the s3c9424/c9428/p9428 ha ve 4 k-byte s (locations 0h - 0fffh) or 8k-bytes (locations 0h-1fffh) of internal mask-programmable program memory. the first 2 - bytes of the rom (0000h? 0001h) are interrupt vector address. unused locations (0002h ? 00ffh) can be used as normal program memory. the program reset address in the rom is 0100h. 8-kbyte program memory area (hex) 1fffh (decimal) 8,181 4-kbyte program memory area 4,095 256 2 1 0 0100h 0002h 0001h 0000h program start interrupt vector (hex) 0fffh figure 2 - 1. program memory address space
s3c9424/c9428/p9428 address spaces 2 - 3 register architecture the upper 64 - bytes of the s3c9424/c9428/p9428 's internal register file are addressed as working registers, system cont rol regi ste r s and periphe r al control registers. the lower 192 - bytes of internal register file(00h - bfh) is called the general purpose register space . the total addressable registe r space is thereby 256-bytes. 252 registers in this space can be accesse d; 208 are available for gener al-purpose use. for many sam87ri microcontrollers, the addressable area of the internal register file is further expanded by additional register pages at the general purpose register space (00h - bfh). this register file expansion is not implemented in the s3c9424/c9428/p9428 , however. the specific register types and the area (in bytes) that they occupy in the internal register file are summarized in table 2 - 1. table 2 - 1. register type summary register type number of bytes cpu and system control registers 12 peripheral, i/o, and clock control and data registers 32 general-purpose registers (including the 16-bit common working register area) 208 total addressable bytes 252
address spaces s3c9424/c9428/p9428 2 - 4 general pupose registers or stack area (page 0) ffh e0h dfh d0h cfh c0h bfh working registers 64 bytes of common area 192 bytes (page 0) system registers peripheral control registers 00h figure 2 - 2. internal register file organization
s3c9424/c9428/p9428 address spaces 2 - 5 common working register area (c0h - cfh) the sam87r i register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. this 16-byte address range is called common area. that is, locations in this area can be used as working registers by operations that address any location on any page in the register file. typically, these working registers serve as temporary buffers for data operations between different pages. however, because the s3c9424/c9428/p9428 uses only page 0, you can use the common area for any internal data operation. the register (r) addressing mode can be used to access this area registers are addressed either as a single 8-bit register or as a paired 16-bit register. in 16-bit register pairs, the address of the first 8-bit register is always an even number and the address of the next register is an odd number. the most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in the next (+ 1) odd-numbered register. msb n= even address rn lsb rn + 1 figure 2 - 3. 16-bit register pairs + + programming tip ? addressing the common working register area as the following examples show, you should access working registers in the common area, locations c0h - cfh, using working register addressing mode only. example s : 1 . ld 0c2h,40h ; invalid addressing mode! use working register addressing instead: ld r2,40h ; r2 (c2h) ? the value in location 40h 2 . add 0c3h,#45h ; invalid addressing mode! use working register addressing instead: add r3,#45h ; r3 (c3h) ? r3 + 45h
address spaces s3c9424/c9428/p9428 2 - 6 system stack s3c9 -series microcontrollers use the system stack for subroutine calls and returns and to store data. the push and pop instructions are used to control system stack operations. the s3c9424/c9428/p9428 architecture supports stack operations in the internal register file. stack operations return addresses for procedure calls and interrupts and data are stored on the stack. the contents of the pc are saved to stack by a call instruction and restored by the ret instruction. when an interrupt occurs, the contents of the pc and the flags register are pushed to the stack. the iret instruction then pops these values back to their original locations. the stack address is always decremented before a push operation and incremented after a pop operation. the stack pointer (sp) always points to the stack frame stored on the top of the stack, as shown in figure 2 -4 . pcl stack contents after a call instruction low address pch pcl pch flags high address top of stack top of stack stack contents after an interrupt figure 2 - 4. stack operations stack pointer (sp) register location d9h contains the 8-bit stack pointer (sp) that is used for system stack operations. after a reset, the sp value is undetermined. because only internal memory space is implemented in the s3c9424/c9428/p9428 , the sp must be initialized to an 8-bit value in the range 00h -0c0h . note in case a stack pointer is initialized to 00h, it is decre as ed to ffh when stack operation starts. this means that a stack pointer access invalid stack area.
s3c9424/c9428/p9428 address spaces 2 - 7 + + programming tip ? standard stack operations using push and pop the following example shows you how to perform stack operations in the internal register file using push and pop instructions: ld sp,#0c0h ; sp ? c0h (normally, the sp is set to 0c0h by the ; initialization routine) ? ? ? push sym ; stack address 0bfh ? sym push r15 ; stack address 0beh ? r15 push 20h ; stack add ress 0bdh ? 20h push r3 ; stack address 0bch ? r3 ? ? ? pop r3 ; r3 ? stack address 0bch pop 20h ; 20h ? stack address 0bdh pop r15 ; r15 ? stack address 0beh pop sym ; sym ? stack address 0bfh
s3c9424/c9428/p9428 addressing modes 3 - 1 3 addressing modes overview instructions that are stored in program memory are fetched for execution using the program counter. instructions indicate the operation to be performed and the data to be operated on. addressing mode is the method used to determine the location of the data operand. the operands specified in sam87ri instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. the sam87ri instruction set supports six explicit addressing modes. not all of these addressing modes are available for each instruction. the addressing modes and their symbols are as follows: ? register (r) ? indirect register (ir) ? indexed (x) ? direct address (da) ? relative address (ra) ? immediate (im)
addressing modes s3c9424/c9428/p9428 3 - 2 register addressing mode (r) in register addressing mode, the operand is the content of a specified register (see figure 3 - 1). working register addressing differs from register addressing because it uses an 16 -byte working register space in the register file and an 4-bit register within that space (see figure 3 - 2). dst value used in instruction execution opcode operand 8-bit register file address point to one rigister in register file one-operand instruction (example) sample instruction: dec cntr ; where cntr is the label of an 8-bit register address program memory register file figure 3 - 1. register addressing dst opcode operand 4-bit working register point to the woking register (1 of 16) two-operand instruction (example) sample instruction: add r1, r2 ; where r1 = c1h and r2 = c2h program memory register file src 4 lsbs cfh c0h figure 3 - 2. working register addressing
s3c9424/c9428/p9428 addressing modes 3 - 3 indirect register addressing mode (ir) in indirect register (ir) addressing mode, the content of the specified register or register pair is the address of the operand. depending on the instruction used, the actual address may point to a register in the register file, to program memory (rom), or to an external memory space (see figures 3 - 3 through 3 - 6). you can use any 8-bit register to indirectly address another register. any 16-bit register pair can be used to indirectly address another memory location. dst address of operand used by instruction opcode address 8-bit register file address point to one rigister in register file one-operand instruction (example) sample instruction: rl @shift ; where shift is the label of an 8-bit register address program memory register file value used in instruction execution operand figure 3 - 3. indirect register addressing to register file
addressing modes s3c9424/c9428/p9428 3 - 4 indirect register addressing mode (c ontinued ) dst opcode pair point to rigister pair example instruction references program memory sample instructions: call @rr2 jp @rr2 program memory register file value used in instruction operand register program memory 16-bit address point to program memory figure 3 - 4. indirect register addressing to program memory
s3c9424/c9428/p9428 addressing modes 3 - 5 indirect register addressing mode (c ontinued ) dst opcode operand 4-bit working register address point to the woking register (1 of 16) sample instruction: or r6, @r2 program memory register file src 4 lsbs cfh c0h value used in instruction operand figure 3 - 5. indirect working register addressing to register file
addressing modes s3c9424/c9428/p9428 3 - 6 indirect register addressing mode (c oncluded ) dst opcode 4-bit working register address next 3-bit point to working register pair (1 of 8) sample instructions: lcd r5,@rr2 ; program memory access lde r3,@rr14 ; external data memory access lde @rr4, r8 ; external data memory access program memory register file src cfh c0h value used in instruction operand register pair example instruction references either program memory or data memory program memory or data memory figure 3 - 6. indirect working register addressing to program or data memory
s3c9424/c9428/p9428 addressing modes 3 - 7 indexed addressing mode (x) indexed (x) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see figure 3 - 7). you can use indexed addressing mode to access locations in the internal register file or in external memory. in short offset indexed addressing mode, the 8 -bit displacement is treated as a signed integer in the range ? 128 to + 127. this applies to external memory accesses only (see figure 3 - 8). for register file addressing, an 8 -bit base address provided by the instruction is added to an 8-bit offset contained in a working register. for external memory accesses, the base address is stored in the working register pair designated in the instruction. the 8-bit or 16-bit offset given in the instruction is then added to the base address (see figure 3 - 9). the only instruction that supports indexed addressing mode for the internal register file is the load instruction (ld). the ldc and lde instructions support indexed addressing mode for internal program memory, external program memory, and for external data memory, when implemented. dst opcode two-operand instruction example point to one of the woking register (1 of 16) sample instruction: ld r0, #base[r1] ; where base is an 8-bit immediate value program memory register file src 4 lsbs value used in instruction operand index x(offset) + ~ ~ ~ ~ figure 3 - 7. indexed addressing to register file
addressing modes s3c9424/c9428/p9428 3 - 8 indexed addressing mode (c ontinued ) dst opcode point to woking register pair sample instructions: ldc r4, #04h[rr2] ; the values in the program address (rr2 + #04h) are loaded into register r4. lde r4,#04h[rr2] ; identical operation to ldc example, except that external program memory is accessed. program memory register file src next 3 bits value used in instruction operand x(offset) register pair 16-bit address added to offset + lsb selects program memory or data memory 4-bit working register address 16 bits 8 bits 16 bits figure 3 - 8. indexed addressing to program or data memory with short offset
s3c9424/c9428/p9428 addressing modes 3 - 9 indexed addressing mode (c oncluded ) dst opcode point to woking register pair (1 of 8) sample instructions: ldc r4, #1000h[rr2] ; the values in the program address (rr2 + #1000h) are loaded into register r4. lde r4,#1000h[rr2] ; identical operation to ldc example, except that external program memory is accessed. program memory register file src next 3 bits value used in instruction operand xl l (offset) register pair 16-bit address added to offset + lsb selects program memory or data memory 4-bit working register address 16 bits 8 bits 16 bits xl h (offset) figure 3 - 9. indexed addressing to program or data memory with long offset
addressing modes s3c9424/c9428/p9428 3 - 10 direct address mode (da) in direct address (da) mode, the instruction provides the operand's 16-bit memory address. jump (jp) and call (call) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the pc whenever a jp or call instruction is executed. the ldc and lde instructions can use direct address mode to specify the source or destination address for load operations to program memory (ldc) or to external data memory (lde), if implemented. dst/src opcode program memory "0" or "1" lower addr byte lsb selects program memory or data memory: "0" = program memory "1" = data memory memory address used upper addr byte program or data memory sample instructions: ldc r5,1234h ; the values in the program address (1234h) are loaded into register r5. lde r5,1234h ; identical operation to ldc example, except that external program memory is accessed. figure 3 - 10. direct addressing for load instructions
s3c9424/c9428/p9428 addressing modes 3 - 11 direct address mode (c ontinued ) opcode program memory lower addr byte memory address used upper addr byte sample instructions: jp c,job1 ; where job1 is a 16-bit immediate address call display ; where display is a 16-bit immediate address next opcode figure 3 - 11. direct addressing for call and jump instructions
addressing modes s3c9424/c9428/p9428 3 - 12 relative address mode (ra) in relative address (ra) mode, a two's-complement signed displacement between ? 128 and + 127 is specified in the instruction. the displacement value is then added to the current pc value. the result is the address of the next instruction to be executed. before this addition occurs, the pc contains the address of the instruction immediately following the current instruction. the instructions that support ra addressing is jr. opcode program memory displacement program memory address used sample instructions: jr ult,$+offset ; where offset is a value in the range +127 to -128 next opcode + signed displacement value current instruction current pc value figure 3 - 12. relative addressing immediate mode (im) in immediate (im) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. immediate addressing mode is useful for loading constant values into registers. (the operand value is in the instruction) opcode sample instruction: ld r0,#0aah program memory operand figure 3 - 13. immediate addressing
s3c9424/c9428/p9428 control registers 4 - 1 4 control registers overview in this section, detailed descriptions of the s3c9424/c9428/p9428 control registers are presented in an easy-to- read format. these descriptions will help familiarize you with the mapped locations in the register file. you can also use them as a quick-reference source when writing application programs. system and peripheral registers are summarized in table 4 - 1. figure 4 - 1 illustrates the important features of the standard register description format. control register descriptions are arranged in alphabetical order according to register mnemonic. more information about control registers is presented in the context of the various peripheral hardware descriptions in part ii of this manual.
control registers s3c9424/c9428/p9428 4 - 2 table 4 - 1. register map and r eset status register name mnemonic address & location reset value (bit) address r/w 7 6 5 4 3 2 1 0 timer 0 counter register t0cnt d0h r 0 0 0 0 0 0 0 0 timer 0 data register t0data d1h r/w 1 1 1 1 1 1 1 1 timer 0 control register (high) t0conh d2h r/w ? ? ? ? ? ? ? 0 timer 0 control register (low) t0conl d3h r/w 0 0 0 0 0 0 0 0 clock control register clkcon d4h r/w 0 0 0 0 0 0 0 0 system flags register flags d5h r/w x x x x ? ? ? ? locations d6h-d8h are not mapped. stack pointer register sp d9h r/w x x x x x x x x locations dah is reserved. mds special register mdsreg dbh r/w 0 0 0 0 0 0 0 0 basic timer control register btcon dch r/w 0 0 0 0 0 0 0 0 basic timer counter btcnt ddh r 0 0 0 0 0 0 0 0 test mode control register ftstcon deh w ? ? 0 0 0 0 0 0 system mode register sym dfh r/w ? ? ? ? ? 0 0 0 note: ??? is not mapped, ?x?is undefined
s3c9424/c9428/p9428 control registers 4 - 3 table 4 -1. register map and r eset status (continued) register name mnemonic address r/w reset value (bit) hex 7 6 5 4 3 2 1 0 port 0 data register p0 e0h r/w 0 0 0 0 0 0 0 0 port 1 data register p1 e1h r/w ? ? ? ? 0 0 0 0 port 2 data register p2 e2h r/w 0 0 0 0 0 0 0 0 port 3 data register p3 e3h r/w ? ? ? ? 0 0 0 0 timer 1 control register t1con e 4 h r/w 0 0 0 0 0 0 0 0 timer 1 data register t1data e 5 h r/w 1 1 1 1 1 1 1 1 port 0 control register (high) p0conh e6h r/w 0 0 0 0 0 0 0 0 port 0 control register (low) p0conl e 7 h r/w 0 0 0 0 0 0 0 0 port 0 pull-up resistor enable register p0pur e8h r/w 0 0 0 0 0 0 0 0 po rt 1 control register p1con e9h r/w 0 0 0 0 0 0 0 0 por t 1 pull-up, pending register p1pnd eah r/w 0 0 0 0 0 0 0 0 port 2 control register (high) p2conh ebh r/w 0 0 0 0 0 0 0 0 port 2 control register (low) p2conl ech r/w 0 0 0 0 0 0 0 0 port 2 pull-up resistor enable register p2pur e d h r/w 0 0 0 0 0 0 0 0 port 3 control register p3 con ee h r/w 0 0 0 0 0 0 0 0 sio data register siodata efh r/w 0 0 0 0 0 0 0 0 sio control register siocon f0h r/w 0 0 0 0 0 0 0 0 sio prescaler siops f1h r/w 0 0 0 0 0 0 0 0 iic-bus clock control register iccr f2h r/w 0 0 0 0 0 0 0 0 iic-bus clock/status register icsr f3h r/w 0 0 0 0 0 0 0 0 iic-bus address register iar f4h r/w x x x x x x x ? iic-bus tx/rx data shift register idsr f5h r/w x x x x x x x x 8-bit prescaler for buzzer output buzps f6h r/w 0 0 0 0 0 0 0 0 a/d control register adcon f7h r/w 0 0 0 0 0 0 0 0 a/d converter data register (high) addatah f8h r x x x x x x x x a/d converter data register (low) addatal f9h r 0 0 0 0 0 0 x x pwm 0 data register pwm0 fah r/w ? ? 0 0 0 0 0 0 pwm 0 extension data register pwm0ex fbh r/w 0 0 0 0 0 0 ? ? pwm 1 data register pwm1 fch r/w ? ? 0 0 0 0 0 0 pwm 1 extension data register pwm1ex fdh r/w 0 0 0 0 0 0 ? ? pwm control register pwmcon feh r/w 0 0 0 0 0 0 0 0 zero crossing detection control register zcmod ffh r/w ? ? ? 0 0 0 0 0 note: ??? is not mapped, ?x?is undefined
control registers s3c9424/c9428/p9428 4 - 4 flags - system flags register .7 .6 .5 bit identifier reset reset value read/write r = read-only w = write-only r/w = read/write ' - ' = not used bit number: msb = bit 7 lsb = bit 0 addressing mode or modes you can use to modify register values description of the effect of specific bit settings reset value notation: '-' = not used 'x' = undetermind value '0' = logic zero '1' = logic one bit number(s) that is/are appended to the register name for bit addressing d5h register address (hexadecimal) full register name register mnemonic name of individual bit or bit function .7 .6 .5 .4 .2 .3 .1 .0 x r/w x r/w x r/w x r/w 0 r/w x r/w 0 r/w x r/w carry flag (c) 0 operation dose not generate a carry or borrow condition 1 operation generates carry-out or borrow into high-order bit7 zero flag 0 operation result is a non-zero value 1 operation result is zero sign flag 0 operation generates positive number (msb = "0") 1 operation generates negative number (msb = "1") figure 4 - 1. register description format
s3c9424/c9428/p9428 control registers 4 - 5 ad con ? a/d converter control register f7 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7?.4 a/d converter input pin selection bits 0 0 0 0 ad0 (p2.0) 0 0 0 1 ad1 (p2.1) 0 0 1 0 ad2 (p2.2) 0 0 1 1 ad3 (p2.3) 0 1 0 0 ad4 (p2.4) 0 1 0 1 ad5 (p2.5) 0 1 1 0 ad6 (p2.6) 0 1 1 1 ad7 (p2.7) 1 0 0 0 ad8 (p0.4) 1 0 0 1 ad9 (p0.5) 1 0 1 0 ad10 (p0.6) 1 0 1 1 ad11 (p0.7) 1 1 0 0 internally connected to gnd 1 1 0 1 internally connected to gnd 1 1 1 0 internally connected to gnd 1 1 1 1 internally connected to av ref .3 end-of-conversion status bit 0 a/d conversion is in progress 1 a/d conversion complete .2?.1 clock source selection bit 0 0 f osc / 16 0 1 f osc / 8 1 0 f osc / 4 1 1 fosc/1 .0 conversion start bit 0 no meaning 1 a/d conversion start
control registers s3c9424/c9428/p9428 4 - 6 btcon ? basic timer control register dch bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7?.4 watchdog timer function enable bit 1 0 1 0 disable watchdog timer function o ther s enable watchdog timer function .3 ? .2 basic timer input clock selection bits 0 0 f osc /4096 0 1 f osc /1024 1 0 f osc /128 1 1 invalid setting .1 basic timer 8-bit counter clear bit ( n ote) 0 no effect 1 clear basic timer counter value .0 basic timer divider clear bit ( n ote) 0 no effect 1 clear both dividers note: when you write a "1" to btcon.0 (or btcon.1), the basic timer counter (or basic timer divider) is cleared. the bit is then cleared automatically to "0".
s3c9424/c9428/p9428 control registers 4 - 7 buzps ? 6-bit prescaler for buzzer output f6h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 buzzer output enable bit 0 disable buzzer output (buzzer off) 1 enable buzzer output (buzzer on) .6 buzzer clock selection bit 0 divided by 256 (fx/256) 1 divided by 64 (fx/64) .5?.0 6-bit prescaler 0 0 0 0 0 0 divided by 2 [fx/(256 or 64)] 0 0 0 0 0 1 divided by 4 [fx/(256 or 64)] 0 0 0 0 1 0 divided by 6 [fx/(256 or 64)] 0 0 0 0 1 1 divided by 8 [fx/(256 or 64)] divided by 2x(n+1) [fx/(256 or 64)] 1 1 1 1 1 1 divided by 128 [fx/(256 or 64)]
control registers s3c9424/c9428/p9428 4 - 8 clkcon ? system clock control register d4h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 ? ? 0 0 ? ? ? read/write r/w ? ? r/w r/w ? ? ? .7 oscillator irq wake-up function enable bit 0 enable irq for main system oscillator wake-up function 1 disable irq for main system oscillator wake-up function .6 and .5 not used for s3c9424/c9428/p9428 .4 and .3 cpu clock (system clock) selection bits (1) 0 0 divide by 16 (f osc /16) 0 1 divide by 8 ( fosc/ 8) 1 0 divide by 2 (f osc /2) 1 1 non-divided clock (f osc ) (2) .2?.0 not used for s3c9424/c9428/p9428 notes: 1. after a reset, the slowest clock (divided by 16) is selected as the system clock. to select faster clock speeds, load the appropriate values to clkcon.3 and clkcon.4. 2. f osc means oscillator frequency
s3c9424/c9428/p9428 control registers 4 - 9 flags ? system flags register d5h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 carry flag (c) 0 operation does not generate a carry or borrow condition 1 operation generates a carry-out or borrow into high-order bit 7 .6 zero flag (z) 0 operation result is a non-zero value 1 operation result is zero .5 sign flag (s) 0 operation generates a positive number (msb = "0") 1 operation generates a negative number (msb = "1") .4 overflow flag (v) 0 operation result is + 127 or 3 ? 128 1 operation result is > + 127 or < ? 128 .3? .0 not used for s3c9424/c9428/p9428
control registers s3c9424/c9428/p9428 4 - 10 iccr ? multi-master iic-bus clock control register f2h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 acknowledgement enable bit 0 acknowledgement disable mode 1 acknowledgement enable mode .6 tx clock selection bit 0 fosc/16 1 fosc/512 .5 multi-master iic-bus tx/rx interrupt enable bit 0 disable interrupt 1 enable interrupt .4 multi-master iic-bus tx/rx interrupt pending bit 0 when write ?0? to this bit or when icsr.4 is ?0? 1 when 1-byte transmit/receive is terminated, general call or slave address match occurred, or arbitration lost .3?.0 iccr.3-0: transmit clock 4-bit prescaler bits scl clock = iiclk/ccr<3:0> + 1 where, iiclk = fosc/16 when iicr.6 is ?0?, iiclk = fosc/512 when iccr.6 is ?1?
s3c9424/c9428/p9428 control registers 4 - 11 icsr ? multi-master iic-bus control/status register f3h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7?.6 master/slave tx/rx mode selection bits 0 0 slave receiver mode (default mode) 0 1 slave transmitter mode 1 0 master receiver mode 1 1 master transmitter mode .5 iic-bus busy bit 0 iic-bus is not busy 0 stop condition generation 1 iic-bus is busy (when read) 1 stop condition generation (when write) .4 iic-bus interface module enable bit 0 disable iic-bus data transmit/receive 1 enable iic-bus data transmit/receive .3 arbitration lost bit this bit is set by h/w when the serial i/o interface, in master transmit mode, loses a bus arbitration procedure. in slave mode this flag is set to ?1? when iccr.5 is ?1? and icsr.2 is ?0? .2 address match bit 0 when start or stop or reset 1 when received slave address matches to iar register or general call .1 general call bit 0 when start/stop condition is generated 1 when received slave address is ?00000000? (general call) .0 received acknowledge bit 0 ack is received 1 ack is not received
control registers s3c9424/c9428/p9428 4 - 12 p0conh ? port 0 control register (high byte) e6h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7?.6 port 0, p0.7/ad11/pwm0 configuration bits 0 0 schmitt trigger input 0 1 a/d converter input (ad11) ; schmitt trigger input off 1 0 push-pull output 1 1 alternative function (pwm0 output) .5?.4 port 0, p0.6/ad10 configuration bits 0 0 schmitt trigger input 0 1 a/d converter input (ad10) ; schmitt trigger input off 1 0 push-pull output 1 1 open-drain output .3?.2 port 0, p0.5/ad9 configuration bits 0 0 schmitt trigger input 0 1 a/d converter input (ad9) ; schmitt trigger input off 1 0 push-pull output 1 1 open-drain output .1?.0 port 0, p0.4/ad10 configuration bits 0 0 schmitt trigger input 0 1 a/d converter input (ad8) ; schmitt trigger input off 1 0 push-pull output 1 1 open-drain output
s3c9424/c9428/p9428 control registers 4 - 13 p0conl ? port 0 control register (low byte) e 7 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7?.6 port 0, p0.3/clo configuration bits 0 0 schmitt trigger input 0 1 alternative function; clo ouput 1 0 push-pull output 1 1 open-drain output .5?.4 port 0, p0.2/si configuration bits 0 0 schmitt trigger input; si input 0 1 schmitt trigger input; si input 1 0 push-pull output 1 1 open-drain output .3?.2 port 0, p0.1/so configuration bits 0 0 schmitt trigger input 0 1 alternative function; so output 1 0 push-pull output 1 1 open-drain output .1?.0 port 0, p0.0/sck configuration bits 0 0 schmitt trigger input; sck input 0 1 alternative function; sck output 1 0 push-pull output 1 1 open-drain output
control registers s3c9424/c9428/p9428 4 - 14 p0pur ? port 0 pull-up resistor enable register e8 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 port 0, p0.7 pull-up resistor enable bit 0 disable pull-up 1 enable pull-up .6 port 0, p0.6 pull-up resistor enable bit 0 disable pull-up 1 enable pull-up .5 port 0, p0.5 pull-up resistor enable bit 0 disable pull-up 1 enable pull-up .4 port 0, p0.4 pull-up resistor enable bit 0 disable pull-up 1 enable pull-up .3 port 0, p0.3 pull-up resistor enable bit 0 disable pull-up 1 enable pull-up .2 port 0, p0.2 pull-up resistor enable bit 0 disable pull-up 1 enable pull-up .1 port 0, p0.1 pull-up resistor enable bit 0 disable pull-up 1 enable pull-up .0 port 0, p0.0 pull-up resistor enable bit 0 disable pull-up 1 enable pull-up
s3c9424/c9428/p9428 control registers 4 - 15 p1con ? port 1 control register e9h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 port 1, p1.3/int1/pwm1 configuration bits 0 0 schmitt trigger input ; int1 interrupt disabled 0 1 schmitt trigger input ; interrupt on falling edge 1 0 push-pull output 1 1 alternative function (pwm1 output) .5 and .4 port 1, p1.2/int0 configuration bits 0 0 schmitt trigger input ; int0 interrupt disabled 0 1 schmitt trigger input ; interrupt on falling edge 1 0 push-pull output 1 1 schmitt trigger input ; interrupt on rising edge .3 and .2 port 1, p1.1/buz configuration bits 0 0 schmitt trigger 0 1 schmitt trigger input 1 0 push-pull output 1 1 alternative function (buz output) .1 and .0 port 1, p1.0 /zcd configuration bits 0 0 schmitt trigger input (or t0 capture input) 0 1 zcd input; zcd enable 1 0 push-pull output 1 1 alternative function (t0 output; match or pwm)
control registers s3c9424/c9428/p9428 4 - 16 p1pnd ? port 1 interrupt pending register ea h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 port 1, p1.3/int1/pwm1 pull-up resistor enable bit 0 disable pull-up 1 enable pull-up .6 port 1, p1.2/int0 pull-up resistor enable bit 0 disable pull-up 1 enable pull-up .5 port 1, p1.1/buz pull-up resistor enable bit 0 disable pull-up 1 enable pull-up .4 port 1, p1.0/t0/zcd pull-up resistor enable bit 0 disable pull-up 1 enable pull-up .3 port 1,p1.3/int1/pwm1 open-drain enable bit 0 push pull output mode 1 open-drain output .2 port 1, p1.1/buz open-drain enable bit 0 push pull output mode 1 open-drain output .1 port 1, p1.3/int1 interrupt pending bit 0 no interrupt pending (when read) 0 clear pending bit (when write) 1 interrupt is pending (when read)/no effect (when write) .0 port 1, p1.2/int0 interrupt pending bit 0 no interrupt pending (when read) 0 clear pending bit (when write) 1 interrupt is pending (when read)/no effect (when write)
s3c9424/c9428/p9428 control registers 4 - 17 p2con h ? port 2 control register (high byte) e b h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 port 2, p2. 7 / ad7/sclk configuration bits 0 0 schmitt trigger input 0 1 a/d converter input (ad7); schmitt trigger input off 1 0 push-pull output 1 1 alternative function (iic clock pin); open-drain type .5 and .4 port 2, p2.6/ad 6 /sdat configuration bits 0 0 schmitt trigger input 0 1 a/d converter input (ad6); schmitt trigger input off 1 0 push-pull output 1 1 alternative function (iic data pin); open-drain type .3 and .2 port 2, p2.5/ad5 configuration bits 0 0 schmitt trigger input 0 1 a/d converter input (ad5); schmitt trigger input off 1 0 push-pull output 1 1 open-drain output .1 and .0 port 2, p2.4 / ad4 configuration bits 0 0 schmitt trigger input 0 1 a/d converter input (ad4); schmitt trigger input off 1 0 push-pull output 1 1 open-drain output
control registers s3c9424/c9428/p9428 4 - 18 p2con l ? port 2 control register (low byte) e c h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 port 2, p2. 3 / ad3 configuration bits 0 0 schmitt trigger input 0 1 a/d converter input (ad3); schmitt trigger input off 1 0 push-pull output 1 1 open-drain output .5 and .4 port 2, p2.2/ad2 configuration bits 0 0 schmitt trigger input 0 1 a/d converter input (ad2); schmitt trigger input off 1 0 push-pull output 1 1 open-drain output .3 and .2 port 2, p2.1/ad1 configuration bits 0 0 schmitt trigger input 0 1 a/d converter input (ad1); schmitt trigger input off 1 0 push-pull output 1 1 open-drain output .1 and .0 port 2, p2.0 / ad0 configuration bits 0 0 schmitt trigger input 0 1 a/d converter input (ad0); schmitt trigger input off 1 0 push-pull output 1 1 open-drain output
s3c9424/c9428/p9428 control registers 4 - 19 p2 pur ? port 2 pull-up resistor enable register ed h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 port 2.7 pull-up resistor enable bit 0 disable pull-up 1 enable pull-up .6 port 2.6 pull-up resistor enable bit 0 disable pull-up 1 enable pull-up .5 port 2.5 pull-up resistor enable bit 0 disable pull-up 1 enable pull-up .4 port 2.4 pull-up resistor enable bit 0 disable pull-up 1 enable pull-up .3 port 2.3 pull-up resistor enable bit 0 disable pull-up 1 enable pull-up .2 port 2.2 pull-up resistor enable bit 0 disable pull-up 1 enable pull-up .1 port 2.1 pull-up resistor enable bit 0 disable pull-up 1 enable pull-up .0 port 2.0 pull-up resistor enable bit 0 disable pull-up 1 enable pull-up
control registers s3c9424/c9428/p9428 4 - 20 p3con ? port 3 control register ee h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w .7 and .6 port 3, p3.3 configuration bits 0 0 push-pull output 0 1 push-pull output 1 0 open-drain output; pull-up resistor disable 1 1 open-drain output; pull-up resistor enable . 5 and . 4 port 3, p3.2 configuration bits 0 0 push-pull output 0 1 push-pull output 1 0 open-drain output; pull-up resistor disable 1 1 open-drain output; pull-up resistor enable . 3 and . 2 port 3, p3.1 configuration bits 0 0 push-pull output 0 1 push-pull output 1 0 open-drain output; pull-up resistor disable 1 1 open-drain output; pull-up resistor enable . 1 and . 0 port 3, p3.0 configuration bits 0 0 push-pull output 0 1 push-pull output 1 0 open-drain output; pull-up resistor disable 1 1 open-drain output; pull-up resistor enable
s3c9424/c9428/p9428 control registers 4 - 21 pwmcon ? pwm control register fe h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 ?.6 pwm input clock slection bit 0 0 fosc/256 0 1 fosc/64 1 0 fosc/8 1 1 fosc/1 . 5 pwm 1 data reload interval selection bit 0 reload from 12-bit up counter overflow 1 reload from 6-bit up counter overflow . 4 pwm 0 data reload interval selection bit 0 reload from 12-bit up counter overflow 1 reload from 6-bit up counter overflow .3 pwm counter clear bit 0 no effect 1 clear 12-bit up counter (when write) .2 pwm counter enable bit 0 stop counter 1 start (resume counting) .1 pwm overflow interrupt enable bit (12-bit counter overflow) 0 disable interrupt 1 enable interrupt .0 pwm 12-bit counter overflow interrupt pending bit 0 no interrupt pending 0 clear pending bit (when write) 1 interrupt is pending
control registers s3c9424/c9428/p9428 4 - 22 siocon ? serial i/o module control registers f0h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 sio shift clock selection bit 0 interval clock (p.s clock) 1 external clock (sck) .6 data direction control bit 0 msb-first mode 1 lsb-first mode .5 sio mode selection bit 0 receive-only mode 1 transmit/receive mode .4 shift clock edge selection bit 0 tx at falling edges, rx at rising edges. 1 tx at rising edges, rx at falling edges. .3 sio counter clear and shift start bit 0 no action 1 clear 3-bit counter and start shifting .2 sio shift operation enable bit 0 disable shift and clock counter 1 enable shift and clock counter .1 sio interrupt enable bit 0 disable sio interrupt 1 enable sio interrupt .0 sio interrupt pending bit 0 no interrupt pending 0 clear pending condition (when write) 1 interrupt is pending
s3c9424/c9428/p9428 control registers 4 - 23 sym ? system mode register dfh bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? ? 0 0 0 read/write ? ? ? ? ? r/w r/w r/w .7? .3 not used for s3c9424/c9428/p9428 .2 global interrupt enable bit (note) 0 disable all interrupt (di instruction) 1 enable all interrupt (ei instruction) .1 and .0 page selection bits 0 0 page 0 0 1 page 1 (not used for s3c9424/c9428/p9428) 1 0 page 2 (not used for s3c9424/c9428/p9428) 1 1 page 3 (not used for s3c9424/c9428/p9428) note: following a reset, you enable global interrupt processing by executing an ei instruction (not by writing a ?1? to sym.2).
control registers s3c9424/c9428/p9428 4 - 24 t0conh ? timer 0 control register (high byte) d2h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 (8) reset reset value ? ? ? ? ? ? ? 0 read/write ? ? ? ? ? ? ? r/w .7?.1 not used for s3c9424/c9428/p9428 .0 (8) timer 0 overflow interrupt pending bit (overflow interrupt) 0 no interrupt pending (when read) 0 clear pending bit (when write) 1 interrupt is pending (when read)
s3c9424/c9428/p9428 control registers 4 - 25 t0conl ? timer 0 control register (low byte) d3 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 and .6 timer 0 input clock selection bits 0 0 f osc /4096 0 1 f osc /256 1 0 f osc /8 1 1 f osc /1 .5 and .4 timer 0 operating mode selection bits 0 0 interval mode 0 1 capture mode (capture on rising edge, counter running, ovf) 1 0 capture mode (capture on falling edge, counter running, ovf) 1 1 pwm mode (ovf interrupt can occur) .3 timer 0 counter clear bit 0 no effect 1 clear the timer 0 counter (when write) .2 timer 0 overflow interrupt enable bit 0 disable overflow interrupt 1 enable overflow interrupt .1 timer 0 interrupt enable bit 0 disable interrupt 1 enable interrupt .0 timer 0 interrupt pending bit (capture or match interrupt) 0 no interrupt pending (when read) 0 clear pending bit (when write) 1 interrupt is pending (when read) note: when you write a ?1? to t0conl.3 the timer 0 counter is cleared. the bit is then cleared automatically to ?0?.
control registers s3c9424/c9428/p9428 4 - 26 t 1 con ? timer 1 control register e4 h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w . 7 timer 1 counter control bit 0 disable operation 1 enable counter operation . 6 and .4 timer 1 input clock selection bits 0 0 0 fosc/4096 0 0 1 fosc/1024 0 1 0 fosc/512 0 1 1 fosc/256 1 0 0 fosc/128 1 0 1 fosc/32 .3 timer 1 counter automatic clear enable bit 0 disable 1 enable zcd clear signal to clear the timer 1 counter .2 timer 1 counter clear enable bit 0 no effect 1 clear the timer 1 counter (when write) .1 timer 1 interrupt enable bit 0 disable interrupt 1 enable interrupt .0 timer 1 interrupt pending bit 0 no interrupt pending 0 clear pending bit (when write) 1 interrupt is pending
s3c9424/c9428/p9428 control registers 4 - 27 zcmod ? zero crossing detection control register ff h bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? 0 0 0 0 0 read/write ? ? ? r/w r/w r/w r/w r/w .7-.5 not used for s3c9424/c9428/p9428 .4 zcd operation enable bit 0 disable operation 1 enable operation .3 and .2 interrupt mode selection bits 0 0 interrupt on falling edge 0 1 interrupt on rising edge 1 0 interrupt on both edge 1 1 not used .1 zcd interrupt enable bit 0 disable interrupt 1 enable interrupt .0 zcd interrupt pending bit 0 no interrupt pending (when read) 0 clear pending bit (when write) 1 interrupt is pending (when read)
s3c9424/c9428/p9428 interrupt structure 5 - 1 5 interrupt structure overview the sam87ri interrupt structure has two basic components: a vector, and sources. the number of interrupt sources can be serviced through a n interrupt vector which is assigned in rom address 0000h. sources vector s1 s2 s3 sn 0000h 0001h notes: 1. the sam87ri interrupt has only one vector address (0000h-0001h). 2. the number of sn value is expandable. figure 5 - 1. s3c9 -series interrupt type interrupt processing control points interrupt processing can be controlled in two ways: either globally, or by specific interrupt level and source. the system-level control points in the interrupt structure are therefore: ? global interrupt enable and disable (by ei and di instructions) ? interrupt source en able and disable settings in the corresponding peripheral control register(s) enable/disable interrupt instructions (ei, di) the system mode register, sym (dfh), is used to enable and disable interrupt processing. sym.2 is the enable and disable bit for global interrupt processing respectively, by modifying sym.2. an enable interrupt (ei) instruction must be included in the initialization routine that follows a reset operation in order to enable interrupt processing. although you can manipulate sym.2 directly to enable and disable interrupts during normal operation, we recommend that you use the ei and di instructions for this purpose.
interrupt structure s3c9424/c9428/p9428 5 - 2 interrupt pending function types when the interrupt service routine has executed, the application program's service routine must clear the appropriate pending bit before the return from interrupt subroutine (iret) occurs. interrupt priority because there is not a interrupt priority register in sam87ri, the order of service is determined by a sequence of source which is executed in interrupt service routine. s r q interrupt pending register global interrupt control (ei, di instruction) vector interrupt cycle interrpt priority is determind by software polling method "ei" instruction execution reset source interrupts source interrupts enable figure 5 - 2. interrupt function diagram
s3c9424/c9428/p9428 interrupt structure 5 - 3 interrupt source service sequence the interrupt request polling and servicing sequence is as follows: 1. a source generates an interrupt request by setting the interrupt request pending bit to "1". 2. the cpu generates an interrupt ac knowledge signal. 3. the service routine starts and the source's pending flag is cleared to "0" by software. 4. interrupt priority must be determined by software polling method. interrupt service routines before an interrupt request can be serviced, the following conditions must be met: ? interrupt processing must be enabled (ei, sym.2 = "1") ? interrupt must be enabled at the interrupt's source (peripheral control register) if all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. the cpu then initiates an interrupt machine cycle that completes the following processing sequence: 1. reset (clear to "0") the global interrupt enable bit in the sym register (di, sym.2 = "0") to disable all subsequent interrupts. 2. save the program counter and status flags to stack. 3. branch to the interrupt vector to fetch the service routine's address. 4. pass control to the interrupt service routine. when the interrupt service routine is completed, an interrupt return instruction (iret) occurs. the iret restores the pc and status flags and sets sym.2 to "1" (ei), allowing the cpu to process the next interrupt request. generating interrupt vector addresses the interrupt vector area in the rom contains the address of the interrupt service routine. vectored interrupt processing follows this sequence: 1. push the program counter's low-byte value to stack. 2. push the program counter' s high-byte value to stack. 3. push the flags register values to stack. 4. fetch the service routine's high-byte address from the vector address 0000h. 5. fetch the service routine's low-byte address from the vector address 0001h. 6. branch to the service routine specified by the 16-bit vector address.
interrupt structure s3c9424/c9428/p9428 5 - 4 s3c9424/c9428/p9428 interrupt structure the s3c9424/c9428/p9428 microcontroller has nine peripheral interrupt sources: ? timer 0 match /capture interrupt ? timer 0 overflow interrupt ? timer 1 match interrupt ? zero-cross detection ? two external interrupts for port 1 , p 1.2- p 1.3 ? sio interrupt ? pwm overflow interrupt ? iic-bus tx/rx interrupt sources vector 0000h 0001h enable/disable and pending bits t0conl.1 t0conl.2 t1con.1 zcmod.1 p1con.1-0 p1con.3-2 siocon.1 sym.2 (ei, di) timer 0 match or capture timer 0 overflow timer 1 match zero-cross detect p1.2 external interrupt p1.3 external interrupt sio interrupt pwn overflow interrupt iic tx/rx interrupt siocon.0 t0conl.0 t0conh.0 t1con.0 zcmod.0 p1pnd.0 p1pnd.1 pwncon.1 pwncon.0 iccr.5 iccr.4 figure 5 - 3. s3c9424/c9428/p9428 interrupt structure
s3c9424/c9428/p9428 clock circuit 7 - 1 7 clock circuit overview an rc oscillation source provides a typical 4 mhz cl ock for s3c9424/c9428/p9428 . an internal capacitor supports the rc oscillator circuit. an external crystal or ceramic oscilla tion source provides a maximum 16 mhz clock. the x in and x out pins connect the oscillation source to the on-chip clock circuit. simplified rc oscillator and crystal/ceramic oscillator circuits are shown in figures 7 - 1 and 7 -2. x in x out r s3c9424 /c9428/p9428 figure 7 - 1. main oscillator circuit (rc oscillator with internal capacitor) x in x out s3c9424 /c9428/p9428 c1 c2 figure 7 - 2. main oscillator circuit (crystal/ceramic oscillator) main oscillator logic to increase processing speed and to reduce clock noise, non-divided logic is implemented for the main oscillator circuit. for this reason, very high resolution waveforms (square signal edges) must be generated in order for the cpu to efficiently process logic operations. clock status during power-down modes the two power-down modes, stop mode and idle mode, affect clock oscillation as follows: ? in stop mode, the main oscilla tor "freezes" , halting the cpu and peripherals. the contents of the register file and current system register values are retained. stop mode is released, and the oscillator started, by a reset operation or by an external interrupt with rc-delay noise filter (for s3c9424/c9428/p9428 , int0 - int1). ? in idle mode, the internal clock signal is gated off to the cpu, but not to interrupt control and the timer. the current cpu status is preserved, including stack pointer, program counter, and flags. data in the register file is retained. idle mode is released by a reset or by an interrupt (external or internally-generated).
clock circuit s3c9 424/c9428/p9428 7 - 2 system clock control register (clkcon) the system clock control register, clkcon, is located in location d4h. it is read/write addressable and has the following functions: ? oscillator irq wake-up function enable/disable (clkcon.7) ? oscillator frequency divide-by value: non-divided, 2, 8, or 16 (clkcon.4 and clkcon.3) the clkcon register controls whether or not an external interrupt can be used to trigger a stop mode release (this is called the "irq wake-up" function). the irq wake-up enable bit is clkcon.7. after a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the f osc /16 (the slowest clock speed) is selected as the cpu clock. if necessary, you can then increase the cpu clock speed to f osc , f osc /2 or f osc /8. .7 .6 .5 .4 .3 .2 .1 .0 lsb msb system clock contol register (clkcon) d4h, r/w not used for s3c9424/c9428/p9428 divide-by selection bits for cpu clock frequency: 00 = fosc/16 01 = fosc/8 10 = fosc/2 11 = fosc(non-divided) oscillator irq wake-up enable bit: 0 = enable irq for main system oscillator wake-up function in power down mode 1 = disable irq for main system oscillator wake-up function in power down mode not used for s3c9424/c9428/p9428 figure 7 - 3. system clock control register (clkcon)
s3c9424/c9428/p9428 clock circuit 7 - 3 main osc noise filter oscillator wake-up oscillator stop clkcon.7 int pin clkcon.3,.4 1/2 1/8 1/16 m u x stop instruction cup clock note: an external interrupt with an rc-delay nosie fillter can be used to release stop mode and "wake-up" the main ascillator . in the s3c9424/c9428/p9428, the int0-int1 external interrupts and zcd interrupt are of this type. p0.3/clo p0conl .7, .6 figure 7 - 4. system clock circuit diagram
s3c9424/c9428/p9428 reset reset and power-down 8 - 1 8 reset reset and power-down system reset overview the s3c9424/c9428/p9428 can be reset in four ways: ? by power-on reset ? by the external reset input pin pulled low ? by the d igital watchdog peripheral timing out ? by low voltage detection (lvd) during a power-on reset, the voltage at v dd is high level the reset pin is forced to low level. the reset signal is input through a schmitt trigger circuit where it is then synchronized with the cpu clock. this bring the s3c9424/c9428/p9428 into a known operating status. to ensure correct start-up, the user should take care that reset signal is not released before the v dd level is sufficient to allow mcu operation at the chosen frequency. the reset pin must be held to low level for a minimum time interval after the power supply comes within tolerance in order to allow time for internal cpu clock oscillation to stabilize. the minimum required oscillation stabilization time for a reset is approximately 6.55 ms ( @ 2 1 6 /f osc , f osc = 10 mhz). when a reset occurs during normal operation (with both v dd and reset at high level), the signal at the reset pin is forced low and the reset operation starts. all system and peripheral control registers are then set to their default hardware reset values (see table 8 - 1). the mcu provides a watchdog timer function in order to ensure graceful recovery from software malfunction. if watchdog timer is not refreshed before an end-of-counter condition (overflow) is reached, the internal reset will be activated. the on-chip low voltage detector, features static reset when supply voltage is below a reference value (typ. 2.6 v). thanks to this feature, external reset circuit can be removed while keeping the application safety. as long as the supply voltage is below the reference value, there is a internal and static reset . the mcu can start only when the supply voltage rises over the reference value. note to program the duration of the oscillation stabilization interval, you must make the appropriate settings to the basic timer control register, btcon, before entering stop mode. also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing " 1010b " to the upper nibble of btcon.
reset reset and power-down s3c9424/c9428/p9428 8 - 2 mcu initialization sequence the following sequence of events occurs during a reset operation: ? all interrupts are disabled. ? the watchdog function (basic timer) is enabled. ? port s 0-1 are set to input mode and all pull-up resistors are disabled. ? peripheral control and data registers are disabled an d reset to their initial values (see table 8-1). ? the program counter is loaded with the rom reset address, 0100h. ? when the programmed oscil lation stabilization time interval has elapsed, the address stored in rom location 0100h (and 0101h) is fetched and executed. v dd watchdog reset 200 k w reset internal reset lvd reset figure 8-1. reset block diagram reset input oscillation stabilization wait time (6.55ms/at 10 mhz) reset operation normal mode or power-down mode idle mode operation mode figure 8-2. timing for oscillation stabilization after reset reset
s3c9424/c9428/p9428 reset reset and power-down 8 - 3 power-down modes stop mode stop mode is invoked by the instruction stop (opcode 7fh). in stop mode, the operation of the cpu and all peripherals is halted. that is, the on-chip main oscillator stops and the supply current is reduced to less than 5 a. all system functions are halted when the clock "freezes" , but data stored in the internal register file is retained. stop mode can be released in one of two ways: by a reset signal or by an external interrupt. using reset reset to release stop mode stop mode is released when the reset signal is released and returns to high level. all system and peripheral control registers are then reset to their default values and the contents of all data registers are retained. a reset operation automatically selects a slow clock ( fosc/16 ) because clkcon.3 and clkcon.4 are cleared to " 00b " . after the oscillation stabilization interval has elapsed, the cpu executes the system initialization routine by fetching the 16-bit address stored in rom locations 0100h and 0101h. using an external interrupt to release stop mode only external interrupts with an rc-delay noise filter circuit can be used to release stop mode (clock-related external interrupts cannot be used). external interrupts int0 - int1 in the s3c9424/c9428/p9428 interrupt structure meet this criteria. note that when stop mode is released by an external interrupt, the current values in system and peripheral control registers are not changed. when you use an interrupt to release stop mode, the clkcon.3 and clkcon.4 register values remain unchanged, and the currently selected clock value is used. if you use an external interrupt for stop mode release, you can also program the duration of the oscillation stabilization interval. to do this, you must make the appropriate control and clock settings before entering stop mode. the external interrupt is serviced when the stop mode release occurs. following the iret from the service routine, the instruction immediately following the one that initiated stop mode is executed. idle mode idle mode is invoked by the instruction idle (opcode 6fh). in idle mode, cpu operations are halted while select peripherals remain active. during idle mode, the internal clock signal is gated off to the cpu, but not to interrupt logic and timer/counters. port pins retain the mode (input or output) they had at the time idle mode was entered. there are two ways to release idle mode: 1. execute a reset. all system and peripheral control registers are reset to their default values and the contents of all data registers are retained. the reset automatically selects a slow clock ( fosc/16 ) because clkcon.3 and clkcon.4 are cleared to " 00b " . if interrupts are masked, a reset is the only way to release idle mode. 2. activate any enabled interrupt, causing idle mode to be released. when you use an interrupt to release idle mode, the clkcon.3 and clkcon.4 register values remain unchanged, and the currently selected clock value is used. the interrupt is then serviced. following the iret from the service routine, the instruction immediately following the one that initiated idle mode is executed. note s 1. only external interrupts that are not clock-related can be used to release s top mode. to release idle mode, however, any type of interrupt (that is, internal or external) can be used. 2. before enter the stop or idle mode, the zcd (p1con) and adc (p0conh, p2conh, p2conl) must be disabled. otherwise, the stop or idle current will be increased significantly.
reset reset and power-down s3c9424/c9428/p9428 8 - 4 hardware reset values table 8 - 1 list s the values for cpu and system registers, peripheral control registers, and peripheral data registers following a reset operation in normal operating mode. ? a "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. ? an "x" means that the bit value is undefined following a reset. ? a dash (" ? ") means that the bit is either not used or not mapped. table 8- 1. register map and reset reset status register name mnemonic address & location reset value (bit) address r/w 7 6 5 4 3 2 1 0 timer 0 counter register t0cnt d0h r 0 0 0 0 0 0 0 0 timer 0 data register t0data d1h r/w 1 1 1 1 1 1 1 1 timer 0 control register (high) t0conh d2h r/w ? ? ? ? ? ? ? 0 timer 0 control register (low) t0conl d3h r/w 0 0 0 0 0 0 0 0 clock control register clkcon d4h r/w 0 0 0 0 0 0 0 0 system flags register flags d5h r/w x x x x ? ? ? ? locations d6h-d8h are not mapped. stack pointer register sp d9h r/w x x x x x x x x locations dah is reserved. mds special register mdsreg dbh r/w 0 0 0 0 0 0 0 0 basic timer control register btcon dch r/w 0 0 0 0 0 0 0 0 basic timer counter btcnt ddh r 0 0 0 0 0 0 0 0 test mode control register ftstcon deh w ? ? 0 0 0 0 0 0 system mode register sym dfh r/w ? ? ? ? ? 0 0 0 note: ??? is not mapped, ?x?is undefined
s3c9424/c9428/p9428 reset reset and power-down 8 - 5 table 8-1. register map and r eset status (continued) register name mnemonic address r/w reset value (bit) hex 7 6 5 4 3 2 1 0 port 0 data register p0 e0h r/w 0 0 0 0 0 0 0 0 port 1 data register p1 e1h r/w ? ? ? ? 0 0 0 0 port 2 data register p2 e2h r/w 0 0 0 0 0 0 0 0 port 3 data register p3 e3h r/w ? ? ? ? 0 0 0 0 timer 1 control register t1con e 4 h r/w 0 0 0 0 0 0 0 0 timer 1 data register t1data e 5 h r/w 1 1 1 1 1 1 1 1 port 0 control register (high) p0conh e6h r/w 0 0 0 0 0 0 0 0 port 0 control register (low) p0conl e 7 h r/w 0 0 0 0 0 0 0 0 port 0 pull-up resistor enable register p0pur e8h r/w 0 0 0 0 0 0 0 0 po rt 1 control register p1con e9h r/w 0 0 0 0 0 0 0 0 por t 1 pull-up, pending register p1pnd eah r/w 0 0 0 0 0 0 0 0 port 2 control register (high) p2conh ebh r/w 0 0 0 0 0 0 0 0 port 2 control register (low) p2conl ech r/w 0 0 0 0 0 0 0 0 port 2 pull-up resistor enable register p2pur e d h r/w 0 0 0 0 0 0 0 0 port 3 control register p3 con ee h r/w 0 0 0 0 0 0 0 0 sio data register siodata efh r/w 0 0 0 0 0 0 0 0 sio control register siocon f0h r/w 0 0 0 0 0 0 0 0 sio prescaler siops f1h r/w 0 0 0 0 0 0 0 0 iic-bus clock control register iccr f2h r/w 0 0 0 0 0 0 0 0 iic-bus clock/status register icsr f3h r/w 0 0 0 0 0 0 0 0 iic-bus address register iar f4h r/w x x x x x x x ? iic-bus tx/rx data shift register idsr f5h r/w x x x x x x x x 8-bit prescaler for buzzer output buzps f6h r/w 0 0 0 0 0 0 0 0 a/d control register adcon f7h r/w 0 0 0 0 0 0 0 0 a/d converter data register (high) addatah f8h r x x x x x x x x a/d converter data register (low) addatal f9h r 0 0 0 0 0 0 x x pwm 0 data register pwm0 fah r/w ? ? 0 0 0 0 0 0 pwm 0 extension data register pwm0ex fbh r/w 0 0 0 0 0 0 ? ? pwm 1 data register pwm1 fch r/w ? ? 0 0 0 0 0 0 pwm 1 extension data register pwm1ex fdh r/w 0 0 0 0 0 0 ? ? pwm control register pwmcon feh r/w 0 0 0 0 0 0 0 0 zero crossing detection control register zcmod ffh r/w ? ? ? 0 0 0 0 0 note: ??? is not mapped, ?x?is undefined
reset reset and power-down s3c9424/c9428/p9428 8 - 6 + + programming tip ? sample s3c9424/c9428/p9428 initialization routine the following sample program suggests how to program the initial program settings for ;--------------<< interrupt vector address >> org 0000h vector 00h,int_4208 ; s3c9428 ha s only one interrupt vector org 0100h initial: ld sym, #00h ; global/fast interrupt disable -> sym ld btcon, #10100010b ; watch-dog disable ld clkcon, #00011000b ; non-divided cpu clock ld sp, #0c0h ; 9428 00~bf (after decrease, push data) ;--------------<< port initialization >> ld p0conh, #0 ; input ld p0conl, #0 ; input ld p0pur, #0ffh ; pull-up enable ld p1con, #50h ; input, ext.int enable ld p1pnd, #0f0h ; pull-up enable ld p2conh, #0 ; input ld p2conl, #0 ; input ld p2pur, #0ffh ; pul l-up enable ld p3con, #0 ; push-pull output ;--------------<< timer 0 setting >> ld t0data, #41h ; interrupt interval --1.667msec (10mhz base) ld t0conl, #01000010b ; timer 0 match output ;--------------<< ram area clear >> ld r0, #0 ; ram clear area setting ram_clr: clr @r0 inc r0 cp r0, #0bfh ; general register area 00h~bfh jr ule, ram_clr
s3c9424/c9428/p9428 reset reset and power-down 8 - 7 + + programming tip ? sample s3c9424/c9428/p9428 initialization routine (continued) ;--------------<< initialize other register >> ei ;--------------<< main loop >> main: nop ld r0, #33h call sub_routine0 ; subroutine call call sub_routine1 ; subroutine call jp main ;--------------<< subroutine >> sub_routine0: nop ret sub_routine1: nop ret
reset reset and power-down s3c9424/c9428/p9428 8 - 8 + + programming tip ? sample s3c9424/c9428/p9428 initialization routine (continued) ;--------------<< interrupt service routine >> int_4208: ld r0, t0conl ; s3c9428 has just one interrupt vector and r0, #00000011b ; only timer 0 match interrupt enable cp r0 , #00000011b jp eq, int_timer0 ; t0con?s pending bit & int. enable bit check int_timer0: and t0conl, #11111110b ; pending clear iret end
s3c9424/c9428/p9428 i/o ports 9 - 1 9 i/o ports overview the s3c9424/c9428/p9428 has four i/o ports (0? 3): 32-sop type, with 24 i/o pins total and 28-sop type, with 20 i/o pins total . you access these ports directly by writing or reading port data register addresses. all ports can be configured as led drive. (high current output: typical 10 ma) table 9 - 1. s3c9424/c9428/p9428 port configuration overview port function description programmability 0 bit-programmable i/o port for schmitt trigger input or push-pull, open- drain out put. pull-up resistors are assignable by software. bit 1 bit-programable i/o port for schmitt trigger input or push-pull output. pull-up resistors are assignable by software. port1 pins can also be used as alternative function. bit 2 bit-programmable i/o port for schmitt trigger input or push-pul l, open drain output. pull-up resistors are assignable by software. port2 pins can also be used as a/d converter input . bit 3 push-pull or open-drain output port. pull-up resistors are assignable by software. bit
i/o ports s3c9424/c9428/p9428 9 - 2 port data registers table 9 - 2 gives you an overview of the port data register names, locations, and addressing characteristics. data registers for ports 0? 3 have the structure shown in figure 9 - 1. table 9 - 2. port data register summary register name mnemonic hex r/w port 0 data register p0 e0h r/w port 1 data register p1 e1h r/w port 2 data register p2 e2h r/w port 3 data register p3 e3h r/w note: a reset operation clears the p0-p3 data register to "00h". .7 .6 .5 .4 .3 .2 .1 .0 lsb msb i/o port n data register (n = 0-3) notes: 1. eight bits of the data register are used in the port 0 and port 2. 2. only lower four bits of the data register are used in the port 1. 3. only lower four bits of the data register are used in the port 3 (32-sop type). pn.0 pn.1 pn.2 pn.4 pn.3 pn.5 pn.6 pn.7 figure 9 - 1. port data register format
s3c9424/c9428/p9428 i/o ports 9 - 3 port 0 port 0 is a bit-programmable, general-purpose, i/o ports. you can select normal input or push-pull, o pen drain output mode. in addition, you can configure a pull-up resistor to individual pins using control register settings. you access port 0 directly by writing or reading the c orresponding port data register, p0 (e0h). a reset c lears the port control register, p0conh and p0conl, to " 00h " configuring port 0 pins as normal input s. one addition register is used to control port 0: p0pur (e8h). v dd v dd m u x open-drain ad, pwm, sio pull-up enable mux d0 d1 p0 data output disable (input mode) t0 adc input data circuit type a pull-up register (47 k w typical) in/out note: i/o pins have protection diodes through and v dd and v ss . mode d0 d1 input data output input p0conh p0conl figure 9 - 2. port 0 circuit diagram
i/o ports s3c9424/c9428/p9428 9 - 4 port 0 control registers (high byte) e6h, r/w [.7-.6] port 0, p0.7/ad11/pwm0 configuration bits 00 = schmitt trigger input 01 = a/d converter input (ad11); schmitt trigger input off 10 = push-pull output 11 = alternative function (pwm0 output) [.5-.4] port 0, p0.6/ad10 configuration bits 00 = schmitt trigger input 01 = a/d converter input (ad10); schmitt trigger input off 10 = push-pull output 11 = open-drain output [.3-.2] port0, p0.5/ad9 configuration bits 00 = schmitt trigger input 01 = a/d converter input (ad9); schmitt trigger input off 10 = push-pull output 11 = open-drain output [.1-.0] port0, p0.4/ad8 configuration bits 00 = schmitt trigger input 01 = a/d converter input (ad8); schmitt trigger input off 10 = push-pull output 11 = open-drain output .7 .6 .5 .4 .3 .2 .1 .0 lsb msb figure 9-3. port 0 high-byte control register (p0conh)
s3c9424/c9428/p9428 i/o ports 9 - 5 .7 .6 .5 .4 .3 .2 .1 .0 lsb msb port 0 control registers (low byte) e7h, r/w [.7-.6] port 0, p0.3/clo configuration bits 00 = schmitt trigger input 01 = alternative function; clo output 10 = push-pull output 11 = open-drain output [.5-.4] port 0, p0.2/si configuration bits 00 = schmitt trigger input; si input 01 = schmitt trigger input; si input 10 = push-pull output 11 = open-drain output [.3-.2] port0, p0.1/so configuration bits 00 = schmitt trigger input 01 = alternative function; so output 10 = push-pull output 11 = open-drain output [.1-.0] port0, p0.0/sck configuration bits 00 = schmitt trigger input; sck input 01 = alternative function; sck output 10 = push-pull output 11 = open-drain output figure 9-4. port 0 low-byte control register (p0conl)
i/o ports s3c9424/c9428/p9428 9 - 6 port 0 pull-up resistor enable registers e8h, r/w [.7] port 0.7 pull-up resistor enable bit 0 = disable pull-up 1 = enable pull-up [.6] port 0.6 pull-up resistor enable bit 0 = disable pull-up 1 = enable pull-up [.5] port 0.5 pull-up resistor enable bit 0 = disable pull-up 1 = enable pull-up [.4] port 0.4 pull-up resistor enable bit 0 = disable pull-up 1 = enable pull-up [.3] port 0.3 pull-up resistor enable bit 0 = disable pull-up 1 = enable pull-up [.2] port 0.2 pull-up resistor enable bit 0 = disable pull-up 1 = enable pull-up [.1] port 0.1 pull-up resistor enable bit 0 = disable pull-up 1 = enable pull-up [.0] port 0.0 pull-up resistor enable bit 0 = disable pull-up 1 = enable pull-up .7 .6 .5 .4 .3 .2 .1 .0 lsb msb figure 9 -5 . port 0 pull-up enable c ontrol registers (p0pur )
s3c9424/c9428/p9428 i/o ports 9 - 7 port 1 port 1, is a 4-bit i/o port with individually configurable pins. it can be used for general i/o port (schmitt trigger input mode or push-pull output mode). you can also use port1 as special input (zcd) or output (buz, pwm). in addition, you can configure a pull-up resistor to individual pin using control register settings. in normal operating mode, a reset clears p 1con to "00h", configuring p1 .0 - p 1 .3 as normal schmitt trigger input s, but you can also configure p1 con to " 0ffh " for alternative functions. you address port 1 bits directly by writing or reading the port 1 data register, p1 (e 1h). the port 1 control register , p 1 con is located at addresses e 9 h. v dd v dd m u x buz, pwm pull-up enable mux d0 d1 p1 data output disable (input mode) external interrupt input input data circuit type a pull-up register (47 k w typical) in/out note: i/o pins have protection diodes through and v dd and v ss . mode d0 d1 input data output input p1con noise filter figure 9-6. port 1 circuit diagram
i/o ports s3c9424/c9428/p9428 9 - 8 port 1 control registers e9h, r/w [.7-.6] port 1, p1.3/pwm1/int1 configuration bits 00 = schmitt trigger input; int1 interrupt disabled 01 = schmitt trigger input; interrupt on falling edge 10 = push-pull output 11 = alternative function (pwm1 output) [.5-.4] port 1, p1.2/int0 configuration bits 00 = schmitt trigger input; int0 interrupt disabled 01 = schmitt trigger input; interrupt on falling edge 10 = push-pull output 11 = schmitt trigger input; interrupt on rising edge [.3-.2] port1, p1.1/buz configuration bits 00 = schmitt trigger input; 01 = schmitt trigger input; 10 = push-pull output 11 = alternative function (buz output) [.1-.0] port1, p1.0/t0/zcd configuration bits 00 = schmitt trigger input (or t0 capture input) 01 = zcd input; zcd enable 10 = push-pull output 11 = alternative function (t0 output; match or pwm) .7 .6 .5 .4 .3 .2 .1 .0 lsb msb figure 9 -7 . port 1 control registers (p1con)
s3c9424/c9428/p9428 i/o ports 9 - 9 port 1 interrupt pending registers eah, r/w [.7] port 1.3/int1/pwm1, pull-up resistor enable bit 0 = disable pull-up 1 = enable pull-up [.6] port 1.2/int0, pull-up resistor enable bit 0 = disable pull-up 1 = enable pull-up [.5] port 1.1/buz, pull-up resistor enable bit 0 = disable pull-up 1 = enable pull-up [.4] port 1.0/t0/zcd, pull-up resistor enable bit 0 = disable pull-up 1 = enable pull-up [.3] port 1.3/int1/pwm1, open-drain enable bit 0 = push pull output mode 1 = open-drain output mode [.2] port 1.1/buz, open-drain enable bit 0 = push pull output mode 1 = open-drain output mode [.1] port 1.3/int1, interrupt pending bit 0 = no interrupt pending (when read) 0 = clear pending bit (when write) 1 = interrupt is pending (when read)/no effect (when write) [.0] port 1.2/int0 interrupt pending bit 0 = no interrupt pending (when read) 0 = clear pending bit (when write) 1 = interrupt is pending (when read)/no effect (when write) .7 .6 .5 .4 .3 .2 .1 .0 lsb msb figure 9-8. port 1 interrupt pending registers (p1pnd)
i/o ports s3c9424/c9428/p9428 9 - 10 port 2 port 2 is a 8 -bit i/o port with individually configurable pins. it can be used for general i/o port (schmitt trigger input mode or push-pull output mode or n-channel open-drain output mode). y ou can also use port 2 pins as a/d inputs. in addition, you can configure a pull-up resistor to individual pins using control register settings. in normal opera ting mode, a reset clears p2conh and p2conl to " 00h " , configuring p2.0 - p2. 7 as normal schmitt trigger inputs. you address port 2 bits directly by writing or reading the port 2 data register, p2 (e2h). the port 2 control register, p2con h is located at addresses e b h and p2conl at ech. one additional register is used to co ntrol port 2: p2pur (edh) . by setting port 2 open-drain and pull-up resistor enable register, p2pur, you can configure specific pins as open-drain or push-pull output. v dd v dd m u x open-drain ad, scl, sda pull-up enable mux d0 d1 p2 data output disable (input mode) adc sclk sdat input data circuit type a pull-up register (47 k w typical) in/out note: i/o pins have protection diodes through and v dd and v ss . mode d0 d1 input data output input p2conh p2conl figure 9-9. port 2 circuit diagram
s3c9424/c9428/p9428 i/o ports 9 - 11 port 2 control registers (high byte) ebh, r/w [.7-.6] port2, p2.7/ad7/sclk configuration bits 00 = schmitt trigger input 01 = a/d converter input (ad7); schmitt trigger input off 10 = push-pull output 11 = alternative function (iic clock pin):open-drain type [.5-.4] port 2, p2.6/ad6/sdat configuration bits 00 = schmitt trigger input 01 = a/d converter input (ad6); schmitt trigger input off 10 = push-pull output 11 = alternative function (iic data pin):open-drain type [.3-.2] port2, p2.5/ad5 configuration bits 00 = schmitt trigger input 01 = a/d converter input (ad5); schmitt trigger input off 10 = push-pull output 11 = open-drain output [.1-.0] port2, p2.4/ad4 configuration bits 00 = schmitt trigger input 01 = a/d converter input (ad4); schmitt trigger input off 10 = push-pull output 11 = open-drain output .7 .6 .5 .4 .3 .2 .1 .0 lsb msb figure 9 -10 . port 2 high-byte control registers (p2con h )
i/o ports s3c9424/c9428/p9428 9 - 12 .7 .6 .5 .4 .3 .2 .1 .0 lsb msb port 2 control registers (low byte) ech, r/w [.7-.6] port2, p2.3/ad3 configuration bits 00 = schmitt trigger input 01 = a/d converter input (ad3); schmitt trigger input off 10 = push-pull output 11 = open-drain output [.5-.4] port 2, p2.2/ad2 configuration bits 00 = schmitt trigger input 01 = a/d converter input (ad2); schmitt trigger input off 10 = push-pull output 11 = open-drain output [.3-.2] port2, p2.1/ad1 configuration bits 00 = schmitt trigger input 01 = a/d converter input (ad1); schmitt trigger input off 10 = push-pull output 11 = open-drain output [.1-.0] port2, p2.0/ad0 configuration bits 00 = schmitt trigger input 01 = a/d converter input (ad0); schmitt trigger input off 10 = push-pull output 11 = open-drain output figure 9-11. port 2 low-byte control register (p2conl)
s3c9424/c9428/p9428 i/o ports 9 - 13 port 2 pull-up resistor enable registers edh, r/w [.7] port 2.7 pull-up resistor enable bit 0 = disable pull-up 1 = enable pull-up [.6] port 2.6 pull-up resistor enable bit 0 = disable pull-up 1 = enable pull-up [.5] port 2.5 pull-up resistor enable bit 0 = disable pull-up 1 = enable pull-up [.4] port 2.4 pull-up resistor enable bit 0 = disable pull-up 1 = enable pull-up [.3] port 2.3 pull-up resistor enable bit 0 = disable pull-up 1 = enable pull-up [.2] port 2.2 pull-up resistor enable bit 0 = disable pull-up 1 = enable pull-up [.1] port 2.1 pull-up resistor enable bit 0 = disable pull-up 1 = enable pull-up [.0] port 2.0 pull-up resistor enable bit 0 = disable pull-up 1 = enable pull-up .7 .6 .5 .4 .3 .2 .1 .0 lsb msb figure 9 -12 . port 2 pull-up resistor enable register (p2pur )
i/o ports s3c9424/c9428/p9428 9 - 14 port 3 port 3 is a 4 -bit i/o port with individually configurable pins. it can be used only output port. in addition, you can configure a pull-up register to individual pins using control register settings. in normal operating mode, reset clears p3con to "00h", configures p3.0-p3.3 push-pull output mode . using the p3con register (ee h), you can alternatively configure the port 3 pins as push-pull output, or as open-drain output. v dd v dd open-drain pull-up enable p3 data output only pull-up register (47 k w typical) in/out note: i/o pins have protection diodes through and v dd and v ss . figure 9 -13 . port 3 circuit diagram
s3c9424/c9428/p9428 i/o ports 9 - 15 port 3 control registers eeh, r/w [.7-.6] port 3, p3.3 configuration bits 00 = push-pull output 01 = push-pull output 10 = open-drain output: pull-up resistor disable 11 = open-drain output: pull-up resistor enable [.5-.4] port 3, p3.2 configuration bits 00 = push-pull output 01 = push-pull output 10 = open-drain output: pull-up resistor disable 11 = open-drain output: pull-up resistor enable [.3-.2] port3, p3.1 configuration bits 00 = push-pull output 01 = push-pull output 10 = open-drain output: pull-up resistor disable 11 = open-drain output: pull-up resistor enable [.1-.0] port3, p3.0 configuration bits 00 = push-pull output 01 = push-pull output 10 = open-drain output: pull-up resistor disable 11 = open-drain output: pull-up resistor enable .7 .6 .5 .4 .3 .2 .1 .0 lsb msb figure 9 -14 . port 3 control register s (p3con)
i/o ports s3c9424/c9428/p9428 9 - 16 + + programming tip ? configuring i/o port pins to specification the following sample program shows how to configure the s3c9424/c9428/p9428 i/o ports to specification program comments show the effect of the settings: ld p0conh, #01101010b ; 0.7 - ad input ; 0.6?0.4 - push-pull output ld p0conl, #10010101b ; 0.3 - push-pull output 0.2?0.0 - sio setting ld p1con, #10101010b ; 1.3?1.0 - push-pull output ld p2conh, #11111010b ; 2.7, 2.6 - iic setting ; 2.5, 2.4 - push-pull output ld p2conl, #10101010b ; 2.0?2.3 - push-pull output ld p3con, #00000000b ; 3.3?3.0 - push-pull output
s3c9424/c9428/p9428 basic timer and timers 10 - 1 10 basic timer and timers module overview the s3c9424/c9428/p9428 has three default timers: an 8-bit basic timer , one 8-bit general-purpose timer/counter, called ti mer 0, and one 8-bit timer/counter for the zero-crossing detection circuit called timer 1 . basic timer (bt) you can use the basic timer (bt) in two different ways: ? as a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. ? to signal the end of the required oscillation stabilization interval after a reset or a stop mode release. the functional components of the basic timer block are: ? clock frequency divider (f osc divided by 409 6, 1024, or 128) with multiplexe r ? 8-bit basic timer coun ter, btcnt (ddh, read-only) ? basic timer control register, btcon (dch, read/write) timer 0 timer 0 has three operating modes, one of which you select by an appropriate t0con l setting: ? interval timer mode ? capture input mode ? 8-bit pwm output mode timer 0 has the following functional components: ? clock frequency divider (f osc divided by 4096, 256, 8, or 1 ) with multiplexer ? 8- bit counter (t0cnt), 8-bit comparato r, and 8- bit data register (t0data) ? i/o pin (p1 . 0, t0 match ) for timer 0 match/pwm output or capture input ? timer 0 overflow interrupt (t0ovf) and match interrupt (t0int) generation ? timer 0 control register s , t0con h and t0conl (d2h and d3h respectively) timer 1 timer 1 has one operating mode, interval timer mode. you can clear the timer 1 counter by appropriate setting of t1con register. if t1con.3 is set to ?1?, t1cnt is cleared by the zcd edge detection. timer 1 has the following components: ? clock frequency divider (f osc divided by 4096, 1024, 512 , 256, 128, or 32 ) ? 8-bit counter (t1cnt), 8-bit comparator, and a 8-bit data register (t1data) ? timer 1 control register, t1con
basic timer and timer s s3c9424/c9428/p9428 10 - 2 basic timer (bt) basic timer control register (btcon) the basic timer control register, btcon, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. a reset clears btcon to " 00h " . this enables the watchdog function and selects a basic timer clock frequency of f osc /4096. to disable the watchdog function, you must write the signature code " 1010b " to the basic timer register control bits btcon.7 - btcon.4. the 8-bit basic timer counter, btcnt, can be cleared during normal operation by writing a "1" to btcon.1. to clear the frequency dividers for both the basic timer input clock and the timer 0 clock, you write a "1" to btcon.0. .7 .6 .5 .4 .3 .2 .1 .0 lsb msb basic timer control register (btcon) dch, r/w watchdog timer enable bits: 1010b = disable watchdog function other value = enable watchdog function basic timer counter clear bits: 0 = no effect 1 = clear basic timer counter basic timer input clock selection bits: 00 = fosc/4096 01 = fosc/1024 10 = fosc/128 11 = invalid selection divider clear bit for basic timer and timer 0: 0 = no effect 1 = clear both dividers figure 10 - 1. basic timer control register (btcon)
s3c9424/c9428/p9428 basic timer and timers 10 - 3 basic timer function description watchdog timer function you can program the basic timer overflow signal (btovf) to generate a reset by setting btcon.7 - btcon.4 to any value other than " 1010b " (the " 1010b " value disables the watchdog function). a reset clears btcon to " 00h " , automatically enabling the watchdog timer function. a reset also selects the cpu clock (as determined by the current c lk con register setting) divided by 4096 as the bt clock. a reset whenever a basic timer counter overflow s occurs. during normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring. to do this, the btcnt value must be cleared (by writing a "1" to btcon.1) at regular intervals. if a system malfunction occurs due to circuit noise or some other error condition, the bt counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. in other words, during normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, btcnt) is always broken by a btcnt clear instruction. if a malfunction does occur, a reset is triggered automatically. oscillation stabilization interval timer function you can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop mode has been released by an external interrupt. in stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. the btcnt value then starts increasing at the rate of f osc /4096 (for reset), or at the rate of the preset clock source (for an external interrupt). when btcnt.4 i s set , a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the cpu so that it can resume normal operation. in summary, the following events occur when stop mode is released: 1. during stop mode, a power-on reset or an external interrupt occurs to trigger the stop mode release and oscillation starts. 2. if a power-on reset occurred, the basic timer counter will increase at the rate of f osc /4096. if an external interrupt is used to release stop mode, the btcnt value increases at the rate of the preset clock source. 3. clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter i s set . 4. when a btcnt.4 i s set , normal cpu operation resumes. figure 10 - 2 and 10 - 3 shows the oscillation stabilization time on reset and stop mode release .
basic timer and timer s s3c9424/c9428/p9428 10 - 4 oscillation stabilization normal operating mode 0.8 v dd t wait = 4096x16x1/f osc basic timer increment and cpu operations are idle mode 10000b 00000b reset releasevoltage note: during of the oscillator stabilization wait time, t wait , when it is released by a power-on-reset is 4096x16/fosc. v dd reset internal reset release oscillator (x out ) btcnt clock btcnt value 0.8 v dd oscillator stabilization time trst ~ rc ~ figure 10- 2. oscillation stabilization time on reset reset
s3c9424/c9428/p9428 basic timer and timers 10 - 5 note: duration of the oscillator stabilzation wait time, twait, it is released by an interrupt is determined by the setting in basic timer control register, btcon. v dd oscillation stabilization time reset external interrupt oscillator (x out ) btcnt clock btcnt value t wait basic timer increment 10000b stop release signal 00000b normal operating mode normal operating mode stop mode stop mode release signal stop instruction execution btcon.3 btcon.2 0 0 1 1 0 1 0 0 t wait 4096 x 16/fosc 1024 x 16/fosc 128 x 16/fosc invalid setting t wait (when f osc is 10 mhz) 6.55 ms 1.64 ms 0.2 ms figure 10 - 3. oscillation stabilization time on stop mode release
basic timer and timer s s3c9424/c9428/p9428 10 - 6 + + programming tip ? configuring the basic timer this example shows how to configure the basic timer to sample specification ;----------<> org 0100h ; reset start address reset di ; disable interrupt ld btcon,#10100010b ; disable watchdog function ; clock source: f osc/4096 (104 ms overflow at 10 mhz) ld clkcon,#00011000b ; cpu clock source select (non-divided) ld sp,#0c0h ; s3c9424/c9428/p9428 stack pointer initial ? ? ? ? ei ; enable interrupt ;----------<< main loop >> main ? ? ? ld btcon,#02h ; enable watchdog function ; clear basic timer counter (btcon) before overflow occurs ? ? ? jp t,main ? ? ?
s3c9424/c9428/p9428 basic timer and timers 10 - 7 timer 0 timer 0 control register s (t0con h and t 0conl ) the timer 0 control register low byte , t0con l , is used to select the timer 0 operating mode (interval timer, capture mode, or pwm mode) and input clock frequency, to clear the timer 0 counter, and to enable the t0 overflow interrupt and t0 match/capture interrupt. it also contains a pending bit for t0 match/capture interrupts. timer 0 control register high byte, t0conh, contains a pending bit for t0 overflow interrupt. only one bit in t0conh register is used, t0conh.0. a reset clears t0con l to " 00h " . this sets timer 0 to normal interval timer mode, selects an input clock frequency of f osc /4096, and disables the t0 overflow interrupt and match/capture interrupts. the t0 counter can be cleared at any time during normal operation by writing a "1" to t0con l .3. the t0 overflow interrupt, t0 ovf , is irq0 with vector 00 h. when a t0 overflow interrupt occurs and is serviced by the cpu, the pending condition is cleared manually set by writing ?0? to t0conh.0 . to enable the t0 match/capture interrupt (t0int, irq0, vector 00h ), you must set t0con l .1 to "1". the interrupt service routine must clear the pending condition by writing a "0" to the t0 interrupt pending bit, t0con l .0. .7 .6 .5 .4 .3 .2 .1 .0(8) lsb msb timer 0 control registers (high byte) d2h, r/w not used timer 0 overflow interrupt pending bit(overflow interrupt): 0 = no interrupt pending (when read) 0 = clear pending bit (when write) 1 = interrupt is pending (when read) figure 10 -4 . timer 0 high-byte control register s (t0con h )
basic timer and timer s s3c9424/c9428/p9428 10 - 8 .7 .6 .5 .4 .3 .2 .1 .0 lsb msb timer 0 control registers (low byte) d3h, r/w timer 0 interrupt pending bit: 0 = no t0 interrupt pending (when read) 0 = clear t0 pending bit (when write) 1 = t0 interrupt is pending (when read) timer 0 interrupt clock selection bits: 00 = fosc/4096 01 = fosc/256 10 = fosc/8 11 = fosc/1 timer 0 operating mode selection bits: 00 = interval mode 01 = capture mode (capture on rising edge, counter running, ovf can occur) 10 = capture mode (capture on falling edge, counter running, ovf can occur) 11 = pwm mode (ovf interrupt can occur) timer 0 counter clear bit: 0 = no effect 1 = clear the timer 0 counter (when write) timer 0 overflow interrupt enable bit: 0 = disable t0 overflow interrupt 1 = enable t0 overflow interrupt timer 0 interrupt enable bit: 0 = disable t0 interrupt 1 = enable t0 interrupt figure 10 -5 . timer 0 low-byte control register s (t0con l )
s3c9424/c9428/p9428 basic timer and timers 10 - 9 timer 0 function description t imer 0 interrupts (irq0, vectors 00 h) the t imer 0 mod ule can generate two interrupts; the timer 0 overflow interrupt (t0ovf), and the timer 0 match/capture interrupt (t0int). t0ovf is interrupt lev el irq0, vector 00 h; t0int is also level irq0, vector 00 h. the t0ovf interrupt pending condition is cleared by setting the t0conh.0 pending bit to ?0? . the t0int pending condition must be cleared by software by writing a "0" to the t0con l .0 pending bit. interval timer mode in interval timer mode, a match signal is generated when the counter value is identical to the value written to the t imer 0 reference data register, t0data. the match signal generates a t imer 0 m atch interrupt (t0int, vector 00 h) and then clears the counter. if, for example, you write the value " 10h " to t0data, the counter will increment until it reaches " 10h " . at this point, the t imer 0 interrupt request is generated, the counter value is reset and counting resumes. with each match, the level of the signal at the t imer 0 output pin is inverted . counter comparator pnd data register pnd ctl r (clear) match interrupt enable/disable irq0 (t0ovf) irq0 (t0int) toggle p1.0/t0 interrupt enable/disable clk p1con.1, .0 figure 10 -6 . simplified timer 0 function diagram (interval timer mode)
basic timer and timer s s3c9424/c9428/p9428 10 - 10 match compare value (t0data) match match up counter value (t0cnt) 00h count start t0con .3 <-1 counter clear (t0conl.3) interrupt request (t0conl.0) match match match match clear clear t0data value change clear figure 10-7. timer 0 timing diagram
s3c9424/c9428/p9428 basic timer and timers 10 - 11 pulse width modulation mode pulse width modulation (pwm) mode lets you program the width (duration) of the pulse that is output at the t0 pin. as in interval timer mode, a match signal is generated when the counter value is identical to the value written to the t0 data register (t0data) . in pwm mode, however, the match signal does not clear the counter (it runs continuously, overflowing at " ffh " , and continues incrementing from " 00h " ). although it is possible to use the match signal to generate a t0int interrupt, an interrupt is typically not used in pwm-type applications. instead, the pulse at the t0 pin is held to high level as long as the data register (t0data) value is greater than the counter (t0cnt) value for 8-bit pwm operation . timer 0 counter clock (4mhz) 250ns t0data = "0" t0data = "1" t0data = 80h t0data = ffh 32 m s 64 m s 250ns pwm cycle notes: 1. a system clock frequency of 4mhz is assumed. 2. the input clock of timer 0 count(t0cnt) is assumed in non-divided (fosc/1). figure 10 -8 . simplified timer 0 function diagram ( pwm mode)
basic timer and timer s s3c9424/c9428/p9428 10 - 12 counter comparator data register r (clear) match interrupt enable/disable irq0 (t0ovf) irq0 (t0int) t0con p1.0/t0 interrupt enable/disable clk pnd ctl pnd p1con.1, .0 high level when data > counter; low level when data <= counter figure 10 -9 . pwm block function diagram
s3c9424/c9428/p9428 basic timer and timers 10 - 13 capture mode in capture mode, a signal edge that is detected at the t0 pin opens a gate and loads the current counter value into the t0 data register. rising edges or falling edges can be selected to trigger this operation. both kinds of t0 interrupts can be used in capture mode: t0ovf is generated when a counter overflow occurs, and t0int is generated when the counter value is loaded into the data register. by reading the captured data value in t0data, and assuming a specific value for t clk , you can determine the pulse width (duration) of the signal being input at the t0 pin. (see figure 10 -10 .) counter data register interrupt enable/disable irq0 (t0ovf) irq0 (t0int) interrupt enable/disable clk pnd t0conl pnd p1.0/to (cap) figure 10 -10 . simplified timer 0 function diagram (capture mode)
basic timer and timer s s3c9424/c9428/p9428 10 - 14 mux mux div r 1/4096 1/1 1/8 1/256 t0cnt (d0h) (read-only) 8-bit compatator t0data (d1h) (read/write) data bus bits 5, 4 t0 (cap) bits 5, 4 bit 0 bit 1 irq0 bit 3 clear data bus bits 7, 6 bit 0 bit 8 bit 2 irq0 ovf 8-bit up counter (btcnt, read-only) div r x in x in ovf bits 3, 2 1/4096 1/1024 1/128 bit 1 reset or stop reset data bus clear when btcnt.4 is set after releasing from reset or stop mode, cpu clock starts. t0 (pwm interval) match basic timer control register (write '1010xxxxb' to disable.) basic timer control register timer 0 control register note: during a power-on reset operation, the cpu is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter is set). figure 10 -11 . basic timer and timer 0 block diagram
s3c9424/c9428/p9428 basic timer and timers 10 - 15 + + programming tip ? configuring timer 0 (interval mode) the following sample program sets timer 0 to interval timer mode. org 0000h vector 00h, int_4208 ; s3c9428 has only one interrupt vector org 0100h initial: ld sym, #00h ; global/fast interrupt disable -> sym ld btcon, #10100010b ; watch-dog disable ld clkcon, #00011000b ; non-divided cpu clock ld sp, #0c0h ; 9428 ? 00~bf (after decrease, push data) ld t0data, #41h ; interrupt interval ? 1.69msec (10mhz base) ld t0conl, #01000010b ; timer 0 match interrupt enable ei main: call sub_routine jp main sub_routine: nop ret
basic timer and timer s s3c9424/c9428/p9428 10 - 16 + + programming tip ? configuring timer 0 (interval mode) (continued) int_4208: ; s3c9428 has just one interrupt vector ld r0, t0conl ; only timer 0 match interrupt enable and r0, #00000011b cp r0, #00000011b jp eq, int_timer 0 ; t0con?spending bit & int. enable bit check int_timer 0: and t0conl, #11110110b ; pending clear iret
s3c9424/c9428/p9428 basic timer and timers 10 - 17 + + programming tip ? configuring timer 0 (pwm mode) the following sample program sets timer 0 to 8-bit pwm mode. org 0100h initial: ld sym, #00h ; global/fast interrupt disable -> sym ld btcon, #10100010b ; watch-dog disable ld clkcon, #00011000b ; non-divided cpu clock ld sp, #0c0h ; 9428 ? 00~bf (after decrease, push data) ld p1con, #00000011b ; p1.0 ? t0 (pwm) output ld t0data, #80h ; half duty ld t0conl, #01111000b ; timer 0 pwm mode main: jp main
basic timer and timer s s3c9424/c9428/p9428 10 - 18 timer 1 timer 1 control register (t1con) the timer 1 control register,t1con, located at e4h operates in interval timer mode. by setting the appropriate bits in t1con you can select the input clock frequency and enable the timer 1 interrupt. t1con also contains a pending bit for timer 1 interrupt. a reset clears t1con to "00h". this sets timer 1 to normal interval mode and selects an input clock frequency of fosc/4096 and disables the timer 1 interrupt. you may clear the timer 1 counter by either setting t1con.2 to ?1? or enable zcd clear signal to clear the timer 1 counter by setting t1con.3 to ?1?. to enable timer 1 match interrupt (irq0, vector 00h) you must set t1con.1 to ?1?. the interrupt service routine must clear the pending condition by writing a ?0? to the timer 1 interrupt pending bit, t1con.0. .7 .6 .5 .4 .3 .2 .1 .0 lsb msb timer 1 control registers e4h, r/w timer 1 interrupt pending bit: 0 = no interrupt pending (when read) 0 = clear pending bit (when write) 1 = interrupt is pending (when read) timer 1counter control bit: 0 = disable operation 1 = enable counter operation timer 1 input clock selection bits: 000 = fosc/4096 001 = fosc/1024 010 = fosc/512 011 = fosc/256 100 = fosc/128 101 = fosc/32 timer 1 counter automatic clear enable bit: 0 = disable 1 = enable zcd clear signal to clear the timer 1 counter timer 1 counter clear enable bit: 0 = no effect 1 = clear the timer 1 counter ( when write) timer 1 interrupt enable bit: 0 = disable interrupt 1 = enable interrupt figure 10-12. timer 1 control register (t1con)
s3c9424/c9428/p9428 basic timer and timers 10 - 19 clear mux 1/4096 1/256 8-bit counter r 8-bit comparator data register data bus bit 0 bit 1 irq0 bit 3 data bus bits 6, -4 x in match note: when p1.1/buzzer is used as buzzer output pin, the initial value is "0" (low level). (when the bit7 of buzps is set to "0", the output of p1.1 is low.) 1/512 1/1024 1/128 1/32 bit 7 bit 2 from zcd mux 6-bit prescaler .7 .6 toggle mux p1.1 bit 7 p1con.3, 2 p1.1/buzze div r 1/64 1/256 figure 10-13. timer 1 block diagram
basic timer and timer s s3c9424/c9428/p9428 10 - 20 buzzer output control register (buzps) buzzer output control register is used to select the frequency from 200 hz to 20 khz. and these various frequency can be used to generate the melody signal. by selecting the clock source (bit of buzps) and the value of prescaler, the desire frequency can be obtained. the buzps.7 can be used to control the buzzer output when p1.1 is set to buzzer output mode (configure p1con). .7 .6 .5 .4 .3 .2 .1 .0 lsb msb buzps control registers f6h, r/w buzzer output enable bit: 0 = disable buzzer output (buzzer off) 1 = enable buzzer output (buzzer on) buzzer clock selection bit: 0 = divided by 256 (fosc/256) 1 = divided by 64 (fosc/64) prescaler value: 000000 divided by 2 [fosc/(256 or 64)] 000001 divided by 4 [fosc/(256 or 64)] 000010 divided by 6 [fosc/(256 or 64)] . . . . . divided by 2x(n+1) [fosc/(256 or 64)] . . . . 111111 divided by 128 [fosc/(256 or 64)] figure 10-14. buzzer output control register (buzps)
s3c9424/c9428/p9428 basic timer and timers 10 - 21 + + programming tip ? configuring timer 1 the following sample program sets timer 1 to interval timer mode. org 0000h vector 00h, int_4208 ; s3c9428 has only one interrupt vector org 0100h initial: ld sym, #00h ; global/fast interrupt disable -> sym ld btcon, #10100010b ; watch-dog disable ld clkcon, #00011000b ; non-divided cpu clock ld sp, #0c0h ; 9428 ? 00~bf (after decrease, push data) ld t1data, #41h ; interrupt interval ? 6.76msec (10mhz base) ld t1con, #10010110b ; timer1 match interrupt enable ei main: call sub_routine jp main sub_routine: nop ret
basic timer and timer s s3c9424/c9428/p9428 10 - 22 + + programming tip ? configuring timer 1 (continued) int_4208: ; s3c9428 has just one interrupt vector ld r0, t1con and r0, #00000011b cp r0, #00000011b jp eq, int_t1 ; timer 0 interrupt routine int_t1: and t1con, #11111010b ; pending bit clear iret
s3c9424/c9428/p9428 basic timer and timers 10 - 23 + + programming tip ? configuring buzzer the following sample program sets buzzer output. org 0000h vector 00h, int_4208 ; s3c9428 has only one interrupt vector org 0100h initial: ld sym, #00h ; global/fast interrupt disable -> sym ld btcon, #10100010b ; watch-dog disable ld clkcon, #00011000b ; non-divided c pu clock ld sp, #0c0h ; 9428 ? 00~bf (after decrease, push data) ld p1con, #00001100b ; p1.1 ? buzzer output ld buzps, #10000000b ; fosc/512 buzzer wave output ei main: call sub_routine jp main sub_routine: nop ret
s3c9424/c9428/p9428 a/d converter 11- 1 1 1 a/d converter overview the a/d converter (adc) module uses successive approximation logic to convert analog levels at one of the twelve input channels to equivalent 10 -bit digital values. the analog inp ut level must lie between the av ref and av ss values. the a/d converter has the following components: ? twelve multiplexed analog input pins (ad0 - ad 11 ) ? analog comparator with successive approximation logic ? 10 -bit a/d conversion data output register s (addata h, addatal) ? adc control register (adcon) an analog-to-digital conversion procedure is initiated when the cpu writes a value to the adcon register at address f 7 h to select one of the twelve available input pins. you select the desired input channel by setting the appropriate bits in the adcon register. the s3c9424/c9428/p9428 microcontroller performs 10 -bit conversions for only one input channel at a time. you can dynamically select different analog input channels during program execution by manipulating selection bits in the adcon register. during a normal conversion, adc logic initially sets the successive approximation register to 200h (the approximate half-way point of an 10-bit register). this register is then updated automatically during each conversion step. the successive approximation block performs 10-bit conversions for one input channel at a time. you can dynamically select different channels by mainpulating the channel selection bit value (adcon.7-4) in the adcon register. to start the a/d conversion, you should set a the enable bit, adcon.0. when a conversion is completed, adcon.3, the end-of-conversion (eoc) bit is automatically set to 1 and the result is dumped into the addata register where it can be read. the a/d converter then enters an idle state. remember to read the contents of addata before another conversion starts. otherwise, the previous result will be overwritten by the next conversion result. note because the adc does not use sample-and-hold circuitry, it is important that any fluctuations in the analog level at the ad0 - ad 11 input pins during a conversion procedure be kept to an absolute minimum. any change in the input level, perhaps due to circuit noise, will invalidate the result.
a/d converter s3c9424/c9428/p942 8 11- 2 i nternal reference voltage levels in the adc function block, the analog input voltage level is compared to the reference voltage. the analog input level must remain within the range av ss to av ref (usually, av ref = v dd ). different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. the reference voltage level for the first bit conversion is always 1/2 av ref . using a/d pins for standard digital input the adc module's input pins are alternatively used as digital input in port 0 and port 2 . the ad0 -ad7 share pin names are p 2.0- p 2.7 and ad8-ad11 share pin names are p0.4-p0.7 , respectively a/d converter control register (adcon) the a/d converter control register, adcon, is located at address f 7 h. adcon has four functions: ? bits 7? 4 select an analog input pin (ad0 - ad 11 ). ? bit 3 indicates the status of the a/d conversion . ? bit2-1 select clock source. ? bit 0 st arts the a/d conversion. only one analog input channel can be selected at a time. you can dynamically select any one of the eight analog input pins (ad0 -ad11 ) by manipulating the 4 -bit value for adcon. 7- adcon.4 lsb msb a/d converter control registers f7h, r/w end-of-conversion status bit: 0 = a/d conversion is in progress 1 = a/d conversion complete conversion start bit: 0 = no meaning 1 = a/d conversion start a/d converter input pin selection bits: 0000 ad0 (p2.0) 0001 ad1 (p2.1) 0010 ad2 (p2.2) 0011 ad3 (p2.3) 0100 ad4 (p2.4) 0101 ad5 (p2.5) 0110 ad6 (p2.6) 0111 ad7 (p2.7) 1000 ad8 (p0.4) 1001 ad9 (p0.5) 1010 ad10 (p0.6) 1011 ad11 (p0.7) 1100 internally connected to gnd 1101 internally connected to gnd 1110 internally connected to gnd 1111 internally connected to av ref clock source selection bit: 00 = fosc/16 01 = fosc/8 10 = fosc/4 11 = fosc/1 .7 .6 .5 .4 .3 .2 .1 .0 figure 11- 1. a/d converter control register (adcon)
s3c9424/c9428/p9428 a/d converter 11- 3 a/d converter control register adcon (f7h) adcon .7-4 _ control circuit successive approximation circuit clock selector d/a converter av ref av ss addatah (f8h) addatal (f9h) adcon .0 adcon .2-1 adcon .3 (eoc flag) analog comparator conversion result to data bus ad0/p2.0 ad1/p2.1 ad8/p0.4 ad7/p2.7 ad11/p0.7 .9 .8 .7 .6 .5 .4 .3 .2 lsb msb - - - - - - .1 .0 lsb msb addatah addatal multiplexer figure 1 1- 2. a/d converter circuit diagram
a/d converter s3c9424/c9428/p942 8 11- 4 50 adc clock 40 clock conversion start eoc addata previous value valid data 9 8 7 6 5 4 3 2 1 0 adcon.0 <-1 set up time 10 clock . . . addatah (8-bit) + addata (2-bit) figure 1 1-3 . a/d converter timing diagram conversion timing the a/d conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to step-up a/d conversion. therefore, total of 50 clocks are required to complete an 10-bit conversion: with an 10mhz cpu clock frequency, one clock cycle is 400 ns (4/fosc). if each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit x 10-bits + set-up time (10 clock) = 50 clocks 50 clock x 400 ns = 20 m s at 10mhz, 1 clock time = 4/fosc (assuming adcon.2-.1 = 10) internal a/d conversion procedure 1. analog input must remain between the voltage range of av ss and av ref . 2. configure the analog input pins to input mode by mak ing the appropriate settings in p2conh, p 2 conl and p0conh registers. 3. before the conversion operation starts, you must first select one of the twelve input pins (ad0? ad11 ) by writing the appropriate value to the adcon register. 4. when conversion has been completed, (40 cpu clocks have elapsed ), the eoc flag is set to ?1?, so that a check can be made to verify that the conversion was successful. 5 . t he converted digital value is loaded to the output register, addata h (high 8-bit) and addatal (low 2- bit) , then the adc module enters an idle state. 6. the digital conversion result can now be read from the addata h and addata register s .
s3c9424/c9428/p9428 a/d converter 11- 5 v ss s3c9424 /c9428/p9428 av ss ad0-ad11 av ref reference voltage input analog input pin notes: 1. the symbol 'r' signifies an offset resistor with a value of from 50 to 100 ohms. 2. it is recommended that gnd of the oscillator and gnd of the av ss /v ss must be connected separately with gnd of the power. r 104 101 x in x out figure 1 1-4 . recommended a/d converter circuit for highest absolute accuracy
a/d converter s3c9424/c9428/p942 8 11- 6 + + programming tip programming tip ? configuring 10-bit a/d converter org 0000h vector 00h, int_4208 ; s3c9428 has only one interrupt vector org 0100h initial: ld sym, #00h ; global/fast interrupt disable -> sym ld btcon, #10100010b ; watch-dog disable ld clkcon, #00011000b ; non-divided cpu clock ld sp, #0c0h ; 9428 ? 00?bf (after decrease, push data) ei main: call sub_adc jp main sub_adc: ld p0conh, #55h ; p0.7~0.4: ad input enable ld p0pur, #00h ; pull-up disable ld adcon, #10000001b ; select p0.4, conversion star t conv_loop: tm adcon, #00001000b ; check e0c bit jp z, conv_loop ; conversion is completed ld r8, addatah ; high 8-bit of result ld r9, addatal ; low 2-bit of result ret
s3c9424/c9428/p9428 zero-crossing detec tion circuit 12- 1 12 zero-crossing detection circuit overview zero-crossing detection circuit in samsung's s3c9424/c9428/p9428, generates a digital signal in synchronism with an ac signal input. it provides the timing signal for operations which are synchronized with the ac line. the zero crossing detection circuit digitizes the ac signal it receives from the power supply. by setting bits 1 and 0 in port 1 control register (p1con), you can enable zero-crossing detection. zero-crossing detector is shown in figure 12-1. timer 1 counter clear zcmod .3-2 n/f edge detection bit 0 zcmod.4 zcd enable normal input ac input p1.0 0.1 m f irq0 (zcint) p1con.1-0 note: n/f is the abbreviation of noise filter. bit 1 figure 12-1. zero-crossing detector diagram
zero-crossing detection circuit s 3c9424/c9428/p9428 12-2 zero-crossing detector control register the zero crossing detector control register, zcmod, is used to select interrupt mode (interrupt on falling edge, rising edge or both). reset clears zcmod to ?00h?, and configures interrupt selection mode to falling edge and disables zcd interrupt. the interrupt pending bit must be cleared by writing ?0? to zcmod.0 lsb msb zero crossing detecor control registers ffh, r/w zcd interrupt enable bit: 0 = disable interrupt 1 = enable interrupt zcd interrupt pending bit: 0 = no interrupt pending (when read) 0 = clear pending bit (when write) 1 = interrupt is pending (when read) .7 .6 .5 .4 .3 .2 .1 .0 not used interrupt mode selection bits: 00 interrupt on falling edge 01 interrupt on rising edge 10 interrupt on both edge 11 not used zcd operation enable bit: 0 = disable operation 1 = enable operation figure 12-2. zero-crossing detector control register (zcmod)
s3c9424/c9428/p9428 zero-crossing detec tion circuit 12 - 3 zero cross detector zcd circuit detects the zero-cross point of the ac waveform. three types of detection can be selected, the point from positive to negative, the point from negative to positive, and both. the zero cross detection circuit has the noise filter circuit in it. the detected zero cross point can be used to clear the timer 1 counter (t1con.3 = 1). 1/fzc v azc zcint ac input v az(p-p) figure 12-3. zero-crossing waveform diagram
zero-crossing detection circuit s 3c9424/c9428/p9428 12 - 4 + + programming tip ? configuring zcd org 0000h vector 00h, int_4208 ; s3c9428 has only one interrupt vector org 0100h initial: ld sym, #00h ; global/fast interrupt disable -> sym ld btcon, #10100010b ; watch-dog disable ld clkcon, #00011000b ; non-divided cpu clock ld sp, #0c0h ; 9428 ? 00?bf (after decrease, push data) ld p1con, #00000001b ; p1.0 ? zcd input enable ; input sine wave to p1.0 ld zcmod, #00010010b ; zcd operation/interrupt enable ei main: call sub_routine jp main sub_routine: nop ret
s3c9424/c9428/p9428 zero-crossing detec tion circuit 12 - 5 + + programming tip1 ? configuring zcd (continued) int_4208: ld r0, zcmod and r0, #00000011b cp r0, #00000011b jp eq, int_zcd ; zcd interrupt routine int_zcd: and zcmod, #11111110b ; pending clear iret
s3c9424/c9428/p9428 12-bit pwm 13- 1 13 12-bit pwm (pulse width modulation) overview this microcontroller has the 12-bit pwm circuit. the operation of all pwm circuit is controlled by a single control register, pwmcon. the pwm counter is a 12-bit incrementing counter. it is used by the 12-bit pwm circuits. to start the counter and enable the pwm circuits, you set pwmcon.2 to "1". if the counter is stopped, it retains its current count value; when re-started, it resumes counting from the retained count value. when there is a need to clear the counter you set pwmcon.3 to "1". you can select a clock for the pwm counter by set pwmcon.6-.7. clocks which you can select are fosc/256, fosc/64, fosc/8, fosc/1. function description pwm the 12-bit pwm circuits ha ve the following components: ? 6-bit comparator and extension cycle circuit ? 6 -bit reference data registers (pwm0, pwm1) ? 6 -bit extension data registers (pwm0ex, pwm1ex) ? pwm output pins ( p0.7/ pwm 0, p1.3/pwm1 ) pwm counter the pwm counter is a 12-bit incrementing counter comprised of a lower 6-bit counter and an upper 6-bit counter. to determine the pwm module's base operating frequency, the lower byte counter is compared to the pwm data register value. in order to achieve higher resolutions, the six bits of the upper counter can be used to modulate the "stretch" cycle. to control the "stretching" of the pwm output duty cycle at specific intervals, the 6-bit extended counter value is compared with the 6-bit value (bits 7-2) that you write to the module's extension register.
12-bit pwm s3c9424/ c9428/p9428 13- 2 pwm data and extension registers pwm (duty) data registers, located in fah and fch, determine the output value generated by each 12-bit pwm circuit. these registers, pwm is read/write addressable. ? 8-bit data register pwm0 and pwm1, of which only bits 5-0 are used. ? 8-bit extension registers pwm0ex (fbh) and pwm1ex (fdh), of which only bits 7-2 are used to program the required pwm output, you load the appropriate initialization values into the 6-bit data registers (pwm0, pwm1) and the 6-bit extension registers (pwm0ex, pwm1ex). to start the pwm counter, or to resume counting, you set pwmcon.2 to "1". a reset operation disables all pwm output. the current counter value is retained when the counter stops. when the counter starts, counting resumes at the retained value. pwm clock rate the timing characteristics of both 12-bit output channels are identical, and are based on the fosc clock frequency. the counter clock value is determined by the setting of pwmcon.6-.7. table 13-1. pwm control and data registers register name mnemonic address function pwm data registers pwm0, pwm1 fah, fch 6-bit pwm basic cycle frame value pwm0ex, pwm1ex fbh, fdh 6-bit extension ("stretch") value pwm control registers pwmcon feh pwm counter stop/start (resume), and fosc clock settings pwm function description the pwm output signal toggles to low level whenever the lower 6-bit counter matches the reference value stored in the module's data register (pwm0, pwm1). if the value in the pwm0 or pwm1 register is not zero, an overflow of the lower counter causes the pwm output to toggle to high level. in this way, the reference value written to the data register determines the module's base duty cycle. the value in the 6-bit extension counter is compared with the extension settings in the 6-bit extension data registers (pwm0ex, pwm1ex). this 6-bit extension counter value, together with extension logic and the pwm module's extension register , is then used to "stretch" the duty cycle of the pwm output. the "stretch" value is one extra clock period at specific intervals, or cycles (see table 13-2). if, for example, the value in the extension register is '04h', the 32nd cycle will be one pulse longer than the other 63 cycles. if the base duty cycle is 50 %, the duty of the 32nd cycle will therefore be "stretched" to approximately 51% duty. for example, if you write 80h to the extension register, all odd-numbered pulses will be one cycle longer. if you write fch to the extension register, all pulses will be stretched by one cycle except the 64th pulse. pwm output goes to an output buffer and then to the corresponding pwm output pin. in this way, you can obtain high output resolution at high frequencies.
s3c9424/c9428/p9428 12-bit pwm 13- 3 table 13-2. pwm output "stretch" values for extension registers pwm0ex pwm0ex bit "stretched" cycle number 7 1, 3, 5, 7, 9, . . . , 55, 57, 59, 61, 63 6 2, 6, 10, 14, . . . , 50, 54, 58, 62 5 4, 12, 20, . . . , 44, 52, 60 4 8, 24, 40, 56 3 16, 48 2 32 1 not used 0 not used pwm clock: 4mhz 250ns 0h 1h 20h 3fh 8 m s 250ns 250ns 8 m s 0h pwm0 or pwm1 register values: 40h 80h figure 13-1. 12-bit pwm basic waveform
12-bit pwm s3c9424/ c9428/p9428 13- 4 pwm clock: 500ns 1st 0h pwm0 or pwm1 register values: 02h 40h 32th 64th 1st 32th 64th 750ns 0h 40h 2h 4mhz pwm0ex or pwm1ex register values: (extended value is 04h) 4h 4mhz figure 13-2. 12-bit extended pwm waveform
s3c9424/c9428/p9428 12-bit pwm 13- 5 pwm control register (pwmcon) the control register for the pwm module, pwmcon, is located at register address f e h . pwmcon is used the 12-bit pwm modules. bit settings in the pwmcon register control the following functions: ? pwm counter clock selection ? pwm data reload interval selection ? pwm counter clear ? pwm counter stop/start (or resume) operation ? pwm counter overflow (upper 6-bit counter overflow) interrupt control a reset clears all pwmcon bits to logic zero, disabling the entire pwm module. lsb msb pwm control registers(pwmcon) feh, reset: 00h pwm counter interrupt enable bit: 0 = disable pwm ovf interrupt 1 = enable pwm ovf interrupt pwm 12-bit ovf interrupt pending bit: 0 = no interrupt pending 0 = clear pending condition (when write) 1 = interrupt is pending .7 .6 .5 .4 .3 .2 .1 .0 pwm input clock selection bits: 00 = fosc/256 01 = fosc/64 10 = fosc/8 11 = fosc/1 pwm counter clear bit: 0 = no effect 1 = clear the 12-bit up counter pwm counter enable bit: 0 = stop counter 1 = start (resume countering) pwm0 data reload interval selection bit: 0 = reload from 12-bit up counter overflow 1 = reload from 6-bit up counter overflow pwm1 data reload interval selection bit: 0 = reload from 12-bit up counter overflow 1 = reload from 6-bit up counter overflow figure 1 3- 3. pwm/capture module control register (pwmcon)
12-bit pwm s3c9424/ c9428/p9428 13- 6 pending pwmcon.0 ovfint 6-bit basic register pwm0, pwm1 6-bit comparator 6-bit buffer 6 6 lower 6-bit counter mux pwmcon.6-7 6 upper 6-bit counter p1.3/pwm1 p0.7/pwm0 pwmcon.1 extension control logic bit 2 bit 7 (1,3,...,61,63) 32 pwmcon.2 fosc/256 fosc/64 fosc/8 fosc/1 pwmdata = counter "1" when pwm0 or pwm1 > counter "0" when pwm0 or pwm1 < counter = reload (overflow of the lower 6-bit counter) 6-bit extension registers (pwm0ex, pwm1ex) figure 1 3- 4. pwm/capture module functional block diagram
s3c9424/c9428/p9428 12-bit pwm 13- 7 + + programming tip ? programming the pwm module to sample specifications org 0000h vector 00h, int_4208 ; s3c9428 has only one interrupt vector org 0100h initial: ld sym, #00h ; global/fast interrupt disable -> sym ld btcon, #10100010b ; watch-dog disable ld clkcon, #00011000b ; non-divided cpu clock ld sp, #0c0h ; 9428 ? 00?bf (after decrease, push data) ld p0conh, #0c0h ; p0.7 pwm0 output ld pwm0ex, #0 ; extension register setting ld pwm0, #20h ; data register setting ld pwmcon, #00000100b ; start counting ; half dutypwm wave out to p0.7 ei main: call sub_routine jp main sub_routine: nop ret
s3c9424/c9428/p9428 serial i/o interface 1 4- 1 14 serial i/o interface overview serial i/o module , sio can interface with various types of external devices that require serial data transfer. the components of each sio function block are: ? 8 -bit control register (siocon) ? clock selection logic ? 8-bit data buffer (siodata) ? 8 -bit prescaler (siops) ? 3-bit serial clock counter ? serial data i/o pins (si, so) ? external clock input pin (sck) sio module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control register settings. to ensure flexible data transmission rates, you can select an internal or external clock source. programming procedure to program the sio module, follow these basic steps: 1. configur e the i/o pins at port 0 (so, sck , si ) by loading the appropriate value to the p 1 con l register. 2 . load an 8-bit value to the siocon control register to properly configure the serial i/o module. in this operation, siocon.2 must be set to "1" to enable the data shifter. 3 . for interrupt generation, set the serial i/o interrupt enable bit (siocon. 1 ) to "1". 4 . when you the transmit data to the serial buffer, write data to siodata and set siocon.3 to 1, the shift operation starts. 5 . when the shift operation ( transmit/receive) is completed, the sio pending bit (siocon. 0 ) is set to "1" and an sio interrupt request is generated.
serial i/o interface s3c9424/c9428/p9428 1 4- 2 serial i/o control registers (siocon) the control registers for serial i/o interface, siocon, is located at f0 h . it has the control settings for sio module. ? clock source selection (internal or external) for shift clock ? interrupt enable ? edge selection for shift operation ? clear 3-bit counter and start shift opera tion ? shift operation (transmit) enable ? mode selection (transmit/receive or receive-only) ? data direction selection (msb first or lsb first) a reset clears the siocon value to "0 0h " . this configures the corresponding module with an internal clock source at the sck, selects receive-only operating mode, and clears the 3-bit counter. the data shift operation and the interrupt are disabled. the selected data direction is msb-first. lsb msb sio control registers(siocon) f0h,r/w, reset: 00h siointerrupt enable bit: 0 = disable sio interrupt 1 = enable sio interrupt sio interrupt pending bit: 0 = no interrupt pending 0 = clear pending condition (when write) 1 = interrupt is pending .7 .6 .5 .4 .3 .2 .1 .0 sio shift clock select bit: 0 = internal clock (p.s clock) 1 = external clock (sck) data direction control bit: 0 = msb-first mode 1 = lsb-first mode sio counter clear and shift start bit: 0 = no action 1 = clear 3-bit counter and start shifting sio shift operation enable bit: 0 = disable shifter and clock counter 1 = enable shfter and clock counter sio mode selction bit: 0 = rececive-only mode 1 = transmit/receive mode shift clock edge selction bit: 0 = tx falling edges, rx at rising edges 1 = tx rising edges, rx at falling edges figure 14- 1. serial i/o interface control register (siocon)
s3c9424/c9428/p9428 serial i/o interface 1 4- 3 sio prescaler register (siops) the control register for serial i/o interface module, siops is located at f1h. the value stored in the sio prescaler registers, siops, lets you determine the sio clock rate (baud rate) as follows: baud rate = input clock(xin/2) / 2(pre-scaler value + 1), or external sck input clock lsb msb sio pre-scaler registers(siops) f1h,r/w .7 .6 .5 .4 .3 .2 .1 .0 baud rate = (x in /4)/(siops + 1) figure 14-2. sio pre-scaler register (siops) sio int pending 3-bit counter siocon.0 8-bit sio shift buffer (siodata) 8-bit prescaler 1/2 x in /2 siops(f1h) sck siocon.7 (shift clock source select) toggle prescaler value = 1/(siops + 1) clear clk siocon.1 (interrupt enable) clk si siocon.3 siocon.4 (edge select) siocon.5 (mode select) siocon.2 (shift enable) siocon.6 (lsb/msb first mode select) data bus 8 so figure 14-3 . sio functional block diagram
serial i/o interface s3c9424/c9428/p9428 1 4- 4 so transmit complete irqs set siocon.3 do7 do6 do5 do4 do3 do2 do1 do0 d17 d16 d15 d14 d13 d12 d11 d10 si sck figure 13-4 . serial i/o timing in transmit-receive mode (tx at falling, siocon.4 = 0) irqs do7 do6 do5 do4 do3 do2 do1 do0 d17 d16 d15 d14 d13 d12 d11 d10 sck transmit complete set siocon.3 si so figure 14-5. serial i/o timing in transmit-receive mode (tx at rising, siocon.4 = 1)
s3c9424/c9428/p9428 serial i/o interface 1 4- 5 data output transmit complete irq5 start d7 d6 d5 d4 d3 d2 d1 d0 data input shift clock high impedance figure 14-6 . serial i/o timing in receive-only mode + + programming tip ? sio org 0000h vector 00h, int_4208 ; s3c9428 has only one interrupt vector org 0100h initial: ld sym, #00h ; global/fast interrupt disable -> sym ld btcon, #10100010b ; watch-dog disable ld clkcon, #00011000b ; non-divided cpu clock ld sp, #0c0h ; 9428 00~bf (after decrease, push data) ld p0conl, #10010101b ; 0.2~0.0 ? sio setting ld siocon, #00100110b ; enable sio/interrupt ld siops, #20 ; setting baud rate ei
serial i/o interface s3c9424/c9428/p9428 1 4- 6 + + programming tip ? sio (continued) main: call sub_sio ; data transmit routine jp main sub_sio: ld siodata, transbuf ; 1-byte transmission or siocon, #00001000b ; shift start (8-bit tr ansmit) ret int_4208: ; s3c9428 has just one interrupt vector ld r0, siocon and r0, #00000011b cp r0, #00000011b jp eq, int_sio ; siocon?s pending bit & int. enable bit check int_sio: and siocon, #11111110 ; pending bit clear iret
s3c9424/c9428/p9428 iic-bus interface 15 - 1 15 iic-bus interface overview the s3c9424/c9428/p9428 microcontroller s support a multi-master iic-bus serial interface . a dedicated serial data line (sda t ) and a serial clock line (scl k ) carry information between bus masters and peripheral devices which are connected to the iic-bus. the sda t and scl k lines are bi-directional. in multi-master iic-bus mode, multiple s3c9424/c9428/p9428 microcontrollers can receive or transmit serial data to or from slave devices. the master s3c9424/c9428/p9428 which initiates a data transfer over the iic-bus is responsible for terminating the transfer. standard bus arbitration functions are supported. to control multi-master iic-bus operations, you write values to the following registers: ? iic-bus control register, iccr ? iic-bus control/status register, icsr ? iic-bus tx/rx data shift register, idsr ? iic-bus address register, iar when the iic-bus is free, the sda t and scl k lines are both at high level. a high-to-low transition of sda t initiates a start condition. a low-to-high transition of sda t while scl k remains steady at high level initiates a stop condition. start and stop conditions are always generated by the bus master. a 7-bit address value in the first data byte that is put onto the bus after the start condition is initiated determines which slave device the bus master selects. the 8th bit determines the direction of the transfer (read or write). every data byte that is put onto the sda t line must total eight bits. the number of bytes which can be sent or received per bus transfer operation is unlimited. data is always sent most -significant bit (msb) first and every byte must be immediately followed by an acknowledge (ack) bit.
iic-bus interface s3c9424/c9428/p9428 1 5 - 2 multi-master iic-bus control register (iccr) the multi-master iic-bus control register, iccr, is located at address f 2 h. it is read/write addressable. iccr settings control the following iic-bus functions: ? cpu acknowledge signal (ack) enable or suppress ? iic-bus clock source selection (f osc /16 or f osc /512) ? transmit/receive interrupt enable or disable ? transmit/receive interrupt pending control ? 4-bit prescaler for the serial transmit clock (scl k ) in the s3c9424/c9428/p9428 interrupt structure, the iic-bus tx/rx interrupt is assigned level irq2, vector f8h. to enable this interrupt, you set iccr.5 to ?1?. program software can then poll the iic-bus tx/rx interrupt pending bit (iccr.4) to detect iic-bus receive or transmit requests. when the cpu acknowledges the interrupt request from the iic-bus, the interrupt service routine must clear the interrupt pending condition by writing a ?0? to iccr.4. the scl frequency is determined by the iic-bus clock source selection (f osc /16 or f osc /512) and the 4-bit prescaler value in the iccr register (see figure 15-1 ). lsb msb multi-master iic-bus control registers (iccr) f2h, r/w iic-bus transmit (tx) clock prescaler: the iic-bus transmit clock (sclk) frequency is determined by the clock source selection (iccr.6) and this 4-bit prescaler value, according to the following formula: tx clock (scl) = iiclk/(iccr.3-iccr.0) + 1 where iiclk = fosc/16 (iccr.6 = "0") or iiclk = fosc /512 (iccr.6 = "1") iic-bus tx/rx interrupt pending flag: 0 = no interrupt pending (when read) 0 = clear pending condition (when write) 1 = interrupt is pending (when read) 1 = no effect (when write) .7 .6 .5 .4 .3 .2 .1 .0 iic-bus acknowledge (ack) enable bit: 0 = disable ack generation 1 = enable ack generation iic-bus clock source selection bit: 0 = fosc/16 1 = fosc/512 note: a iic-bus interrupt occurs 1) when a 1-byte transmit or receive operation is terminated, 2) when a general call or a slave address match occurs, or 3) if bus arbitration fails. iic-bus tx/rx interrupt enable/disable bit: 0 = disable interrupt 1 = enable interrupt figure 15-1 . multi-master iic-bus control register (iccr)
s3c9424/c9428/p9428 iic-bus interface 15 - 3 table 15- 1. sample timing calculations for the iic-bus transmit clock (scl) iccr.3 - iccr.0 value iiclk (iccr.3 - iccr.0 settings + 1) (f osc = 8 mhz) iccr.6 = 0 (f osc /16) iiclk = 500 khz (f osc = 8 mhz) iccr.6 = 1 ( fosc /512) iiclk = 15.625 khz 0000 iiclk/1 4 00 khz (note) 15.625 khz 0001 iiclk/2 250 khz 7.1825 khz 0010 iiclk/3 116.7 khz 5.2038 khz 0011 iiclk/4 125 khz 3.9063 khz 0100 iiclk/5 100 khz 3.1250 khz 0101 iiclk/6 83.3 khz 2.6042 khz 0110 iiclk/7 71.4 khz 2.2321 khz 0111 iiclk/8 62.5 khz 1.9531 khz 1000 iiclk/9 55.6 khz 1.7361 khz 1001 iiclk/10 50 khz 1.5625 khz 1010 iiclk/11 45.5 khz 1.4205 khz 1011 iiclk/12 41.7 khz 1.3021 khz 1100 iiclk/13 38.5 khz 1.2019 khz 1101 iiclk/14 35.7 khz 1.1160 khz 1110 iiclk/15 33.3 khz 1.0417 khz 1111 iiclk/16 31.25 khz 0.9766 khz note: max. iiclk = 400 khz.
iic-bus interface s3c9424/c9428/p9428 1 5 - 4 multi-master iic-bus control/status register (icsr) the multi-master iic-bus control/status register, icsr, is located at address f3 h. four bits in this register, icsr.3 - icsr.0, are read-only status flags. icsr register settings are used to control or monitor the following iic-bus functions (see figure 15-2 ): ? master/slave transmit or receive mode selection ? iic-bus busy status flag ? serial output enable/disable ? failed bus arbitration procedure status flag ? slave address/address register match or general call received status flag ? slave address 00000000b (general call) received status flag ? last received bit status flag (not ack = ?1?, ack = ?0?) lsb msb multi-master iic-bus control/status registers (icsr) f3h, r/w (bit 3-0: read-only) iic-bus arbitration procedure status flag: 0 = bus arbitration status okay 1 = bus arbitration failed during serial i/o .7 .6 .5 .4 .3 .2 .1 .0 iic-bus master/slave tx/rx mode selection bits: 00 = slave receive mode (default mode) 01 = slave transmit mode 10 = master receive mode 11 = master transmit mode iic-bus busy signal status bit: 0 = iic-bus not busy (when read), iic interface stop signal generation (when write) 1 = iic-bus is busy (when read), iic interface start signal generation (when write) note: icsr.3 is automatically set to "1" when a bus arbitration procedure fails over serial i/o interface, while the iic-bus is set to "master transmit mode" (icsr.7 and icsr.6 = "11b"). if slave transmit or receive mode is selected, icsr.3 is automatically set to "1" if data is written to the shift register (idsr) when the busy signal bit, icsr.5 is "1". iic-bus serial output enable/disable bit: 0 = disable serial tx/rx 1 = enable serial tx/rx iic-bus address-as-slave status flag: 0 = start/stop condition was generated 1 = received slave address matches the address value in the iar iic-bus address zero status flag: 0 = start/stop condition was generated 1 = received slave address is "00000000b" (general call) iic-bus last-received bit status flag: 0 = last-received bit is "0" (ack was received) 1 = last-received bit is "1" (ack wsa not received) figure 15-2 . multi-master iic-bus control/status register (icsr)
s3c9424/c9428/p9428 iic-bus interface 15 - 5 multi-master iic-bus transmit/receive data shift register (idsr) the iic-bus data shift register, idsr, is located at address f5 h. in a transmit operation, data that is written to the idsr is transmitted serially, msb first. (for receive operations, the input data is written into the idsr register lsb first.) the icsr.4 setting enables or disables serial transmit/receive operations. when icsr.4 = ?1?, data can be written to the shift register. the iic-bus shift register can, however, be read at any time, regardless of the current icsr.4 setting. lsb msb multi-master iic-bus tx/rx data shift registers (idsr) f5h, r/w .7 .6 .5 .4 .3 .2 .1 .0 8-bit data shift register for iic-bus tx/rx operations: when icsr.4 = "1", idsr is write-enabled. you can read the idsr value at any time, regardless of the current icsr.4 setting. figure 15-3 . multi-master iic-bus tx/rx data shift register (idsr) multi-master iic-bus address register (iar) the address register for the iic-bus interface, iar, is located at address f4 h. it is used to store a latched 7 -bit slave address. this address is mapped to iar.7 - iar.1; bit 0 is not used (see figure 15-4 ). the latched slave address is compared to the next received slave address. if a match condition is detected, and if the latched value is 00000000b, a general call status is detected. lsb msb multi-master iic-bus address registers (iar) f4h, r/w .7 .6 .5 .4 .3 .2 .1 _ 7-bit slave address, latch from the iic-bus: when icsr.4 = "1", iar is write-enabled. you can read the iar value at any time, regardless of the current icsr.4 setting. not used for the s3c9424/c9428/p9428 figure 15-4 . multi-master iic-bus address register (iar)
iic-bus interface s3c9424/c9428/p9428 1 5 - 6 address register (iar) comparator sclk irq0 shift register (idsr) iic-bus control logic iccr icsr sdat data bus note: the iic-bus interrupt (irq0) is generated when a 1-byte receive or transmit operation is terminated before the shift operation has been completed. figure 15-5 . iic-bus block diagram
s3c9424/c9428/p9428 iic-bus interface 15 - 7 the iic-bus interface the s3c9424/c9428/p9428 iic-bus interface has four operating modes: ? master transmitter mode ? master receive mode ? slave transmitter mode ? slave receive mode functional relationships between these operating modes are described below. start and stop conditions when the iic-bus interface is inactive, it is in slave mode. the interface is therefore always in slave mode when a start condition is detected on the sda t line. (a start condition is a high-to-low transition of the sda t line while the clock signal, scl k , is high level.) when the interface enters master mode, it initiates a data transfer and generates the scl k signal. a start condition initiates a one-byte serial data transfer over the sda t line and a stop condition ends the t ransfer. (a stop condition is a low-to-high transition of the sda t line while scl k is high level.) start and stop conditions are always generated by the master. the iic-bus is ?busy? when a start condition is generated. a few clocks after a stop condition is generated, the iic -bus is again ?free?. when a master initiates a start condition, it sends its slave address onto the bus. the address byte consists of a 7-bit address and a 1-bit transfer direction indicator (that is, write or read). if bit 8 is ?0?, a transmit operation (write) is indicated; if bit 8 is ?1?, a request for data (read) is indicated. the master ends the indicated transfer operation by transmitting a stop condition. if the master wants to continue sending data over the bus, it can the generate another s lave address and another start condition . in this way, read-write operations can be performed in various formats.
iic-bus interface s3c9424/c9428/p9428 1 5 - 8 stop condition start condition sclk sdat figure 15-6 . start and stop conditions start condition hold time data must remain stable while clock is high change of data allowed stop condition setup data must remain stable while clock is high start condition hold time figure 15-7 . input data protocol
s3c9424/c9428/p9428 iic-bus interface 15 - 9 sclk interrupt pending bit set point 9 2 1 sdat high or low state is possible according to data. interrupt pending bit clear point if stop signal is not generated in interval a , next clock is generated. note: in iic operation, interrupt pending information is indispensable, therefore it is not possible to control iic operation only in main routine without interrupt. acknowledgement low 1 2 a figure 15-8. interrupt pending information
iic-bus interface s3c9424/c9428/p9428 1 5 - 10 data transfer formats every byte put on the sda t line must be eight bits in length. the number of bytes which can be transmitted per transfer is unlimited. the first byte following a start condition is the address byte. this address byte is transmitted by the master when the iic-bus is operating in master mode. each byte must be followed by an acknowledge (ack) bit. serial data and addresses are always sent msb first. single byte write mode format data transferred (data + acknowledge) a data a p a sub address a data multigle byte write mode format a data a p data transferred (data n + acknowledge) auto increment of sub address single byte read mode format data transferred (data + acknowledge) a data a p a sub address a multigle byte read mode format notes: 1. s: start, a: acknowledge, p: stop 2. the "sub address" indicates the internal address of the slave device. slave address data a p a data a data transferred (data n + acknowledge) r s slave address w "0" (write) s slave address w "0" (write) s slave address r "1" (read) s slave address w "0" (write) s figure 15-9 . iic-bus interface data formats
s3c9424/c9428/p9428 iic-bus interface 15 - 11 ack signal transmission to complete a one-byte transfer operation, the receiver must send an ack bit to the transmitter. the ack pulse occurs at the ninth clock of the scl k line (eight clocks are required to complete the one-byte transfer). the clock pulse required for the transmission of the ack bit is always generated by the master. the transmitter releases the sda t line (that is, it sends the sda t line high) when the ack clock pulse is received. the receiver must drive the sda t line low during the ack clock pulse so that sda t is low during the high period of the ninth scl k pulse. the ack bit transmit function can be enabled and disabled by software (iccr.7). however, the ack pulse on the ninth clock of scl k is required to complete a one-byte data transfer operation. sclk from master clock to output data output from transmitter data output from receiver clock to output ack 9 8 1 start condition figure 15-10 . acknowledge response from receiver
iic-bus interface s3c9424/c9428/p9428 1 5 - 12 start signal generation slave address transmission with write condition ack? sub address of slave transmission ack? transmit data ack? stop signal generation yes no no no main routine interrupt routine yes figure 15-11. write operation sequence
s3c9424/c9428/p9428 iic-bus interface 15 - 13 start signal generation slave address transmission with write condition ack? sub address of slave transmission ack? yes no no main routine interrupt routine yes transmit data ack? stop signal generation no slave address transmission with read condition ack? no yes figure 15-12. read operation sequence
iic-bus interface s3c9424/c9428/p9428 1 5 - 14 read-write operations when operating in transmitter mode, the iic-bus interface interrupt routine waits for the master (the s3c9424/c9428/p9428 ) to write a data byte into the iic-bus data shift register (idsr). to do this, it holds the scl line low prior to transmission. in receive mode, the iic-bus interface waits for the master to read the byte from the iic-bus data shift register (idsr). it does this by holding the scl k line low following the complete reception of a data byte. bus arbitration procedures arbitration takes place on the sda t line to prevent contention on the bus between two masters. if a master with a sda t high level detects another master with an sda t active low level, it will not initiate a data transfer because the current level on the bus does not correspond to its own. the master which loses the arbitration can generate scl k pulses only until the end of the last-transmitted data byte. the arbitration procedure can continue while data continues to be transferred over the bus. the first stage of arbitration is the comparison of address bits. if a master loses the arbitration during the addressing stage of a data transfer, it is possible that the master which won the arbitration is attempting to address the master which lost. in this case, the losing master must immediately switch to slave receiver mode. abort conditions if a slave receiver does not acknowledge the slave address, it must hold the level of the sda t line high. this signals the master to generate a stop condition and to abort the transfer. if a master receiver is involved in the aborted transfer, it must also signal the end of the slave transmit operation. it does this by not generating an ack after the last data byte received from the slave. the slave transmitter must then release the sda t to allow a master to generate a stop condition. configuring the iic-bus to control the frequency of the serial clock (scl k ), you program the 4-bit prescaler value in the iccr register. the iic-bus interface address is stored in iic-bus address register, iar. (by default, the iic-bus interface address is an unknown value.)
s3c9424/c9428/p9428 iic-bus interface 15 - 15 + + programming tip ? programming the iic-bus interface org 0000h vector 00h, int_4208 ; s3c9428 has only one interrupt vector iiccounter equ 32h ; counter the total number of reading/wri ting iicflag equ 33h ; to check read or write mode iicfinish equ 34h ; iic is completed? iicbufaddr equ 35h ; to store read data (point base address of iic) slaveaddr equ 36h ; eeprom?s identifier subaddr equ 37h ; internal memory address of eeprom to read or datanum equ 38h ; how many data will be read or written? readorwrite equ 39h ; which operation will be executed? iicbuf equ 3ah ; (3ah?3fh) org 0100h initial: ld sym, #00h ; global/fast interrupt disable -> sym ld btcon, #10100010b ; watch-dog disable ld clkcon, #00011000b ; non-divided cpu clock ld sp, #0c0h ; 9428 ? 00?bf (after decrease, push data) ei main: call sub_iic jp main
iic-bus interface s3c9424/c9428/p9428 1 5 - 16 + + programming tip ? programming the iic-bus interface (cont inued ) ;--------------<< iic mode >> sub_iic: ld p2conh, #0f0h ; p2.7/2.6 ? iic setting ld iccr, #11100000b ; ack enable/int. enable/prescaler set tm readorwrite, #00000001b; .0 bit ? 1 read operation jp nz, read_operation write_operation: ; .0 bit ? 0 write operation ld slaveaddr, #0a0h ; first (u3) eeprom address/write inc datanum ; add 1 for sub address (subaddr) call bus_busy ; iic bus busy? ld iicbufaddr, #iicbuf ; buffer address load ld idsr, slaveaddr ld icsr, #11110000b ; master trans/start signal/enable iic call finish_wait ; wait until operation is completed jp iic_md_end read_operation: ld slaveaddr, #0a1h ; first (u3) eeprom address/read or iicflag, #00000100b ; iic_flag.2 ? indicate read operation call bus_busy ; iic bus busy? ld idsr, #0a0h ; first (u3) eeprom address with write condition ld icsr, #11110000b ; master trans/start signal/enable iic call finish_wait ; wait until operation is completed. iic_md_end: ret
s3c9424/c9428/p9428 iic-bus interface 15 - 17 + + programming tip ? programming the iic-bus interface (cont inued ) ;--------------<< check iic bus >> bus_busy ; called by iic test routine ld r9, icsr tm r9, #00100000b ; bus check jp nz, bus_busy ret finish_wait: ; called by iic test routine nop cp iicfinish, #0ffh ; if iic op eration is finished jp ne, finish_wait ; iicfinish is set ffh in int. routine clr iicfinish ; iic operation completed ret int_4208: ; s3c9428 has only one interrupt vector ld r0, iccr and r0, #00110000b cp r0, #00110000b jp eq,int_iic ; iic interrupt routine ;--------------<< iic interrupt service routine >> int_iic: tm iiccounter, #10000000b jp nz, read_byte ld r1, icsr tm r1, #00000001b ; ack check jp z, ack_ok or iicflag, #00000010b ; ? ack fail stop_condition: and ic sr, #11011111b ; stop condition generation ld iicflag, #0ffh ; ? operation end: check it in main routine jp int_iic_end
iic-bus interface s3c9424/c9428/p9428 1 5 - 18 + + programming tip ? programming the iic-bus interface (cont inued ) ack_ok: clr iicfinish tm iicflag, #00001000b ; test if in read mode jp nz, read_modd inc iiccounter ; update data trans procedure cp iiccounter, #02h jp uge, data_load ld idsr, subaddr ; counter = 1 sub address (memory in eeprom) ; slave address was transmitted in main jp int_iic_end data_load: tm iicf lag, #00000100b ; read mode jp nz, read_mod ld r0, iicbufaddr cp iiccounter, #03h jp ult, next_byte cp datanum, iiccounter jp ult, stop_condition ld r0, iicbufaddr inc r0 ; indirect addressing ld iicbufaddr, r0 ; update iicbufaddr value next_byte: ld idsr,@r0 jp int_iic_end read_mod: ld idsr, slaveaddr ; slave address with read condition ld icsr, #10110000b ; change to master receiver mode and iicflag, #11111011b ; clear read flag ld iicbufaddr, #iicbuf ; to store received data or iicflag, #00001000b ; first data read flag set jp int_iic_end read_modd: ; after trans slave address with read and iicflag, #11110111b ; clear first data read flag clr iiccounter or iiccounter, #80h ; jump to read_modd routine without ack check jp int_iic_end
s3c9424/c9428/p9428 iic-bus interface 15 - 19 + + programming tip ? programming the iic-bus interface (con cluded ) read_byte: ; data read inc iiccounter ld r1, iiccounter ; .7 bit of iiccounter is important and r1, #01111111b cp r1, datanum jp ugt, stop_condition ld r1, iicbufaddr ; ne xt data read ld @r1, idsr ; store read data inc iicbufaddr int_iic_end: and iccr, #11101111b ; pending clear iret
s3c9424/c9428/p9428 electrical data 1 6- 1 1 6 electrical data overview in this section, the following s3c9424/c9428/p9428 electrical characteristics are presented in tables and graphs: ? absolute maximum ratings ? d.c. electrical characteristics ? a.c. electrical characteristics ? operating voltage range ? schmitt trigger input characteristics ? oscillator characteristics ? oscillation stabilization time ? data retention supply voltage in stop mode ? stop mode release timing when initiated by a reset ? power-on reset circuit characteristics ? a/d converter electrical characteristics ? zero-crossing detector ? zero crossing waveform diagram
electrical data s3c9424/c9428/p942 8 1 6- 2 table 1 6- 1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i all input ports ? 0.3 to v dd + 0.3 v output v oltage v o all output ports ? 0.3 to v dd + 0.3 v output c urrent i oh one i/o pin active ? 25 ma high all i/o pins active ? 80 output current i ol one i/o pin active + 30 ma l ow total pin current for ports 1, 2, 3 + 100 total pin current for ports 0 + 200 operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c
s3c9424/c9428/p9428 electrical data 1 6- 3 table 1 6- 2. d . c . electrical characteristics (30sdip, 32sop) (t a = ? 4 0 c to + 85 c, v dd = 3.0 v to 5.5 v) parameter symbol conditions min typ max unit input high v oltage v i h1 ports 0, 1, 2 and reset v dd = 3.0 to 5.5 v 0. 8 v dd ? v dd v v i h3 x in and x out v dd ? 0.1 input low v oltage v i l1 ports 0, 1, 2 and reset v dd = 3.0 to 5.5 v ? ? 0.2 v dd v v i l2 x in and x out 0.1 out put high v oltage v oh i oh = ? 10 m a ports 0-3 v dd = 4.5 to 5.5 v v dd ? 1. 5 v dd ? 0.4 ? v output low v oltage v o l i o l = 25 m a port 0-3 v dd = 4. 5 to 5.5 v ? 0.4 2.0 v input high leakage current i lih1 all input pins except i lih2 v in = v dd ? ? 1 m a i lih2 x in , x out v in = v dd 20 input low leakage current i lil1 all input pins except i lil2 and reset v in = 0 v ? ? ? 1 m a i lil2 x in , x out v in = 0 v ? 20 output high leakage current i loh all output pins v out = v dd ? ? 2 m a output low leakage current i lol all output pins v out = 0 v ? ? ? 2 m a pull-up resistor r p v in = 0 v port 0-2 v dd = 5 v 30 47 70 k w reset v dd = 5 v 100 200 350 supply current i dd1 run mode 16-mhz cpu clock v dd = 4.5 to 5.5 v ? 11 20 ma 4-mhz cpu clock v dd = 3 v 1.5 4 i dd2 idle mode 16-mhz cpu clock v dd = 4.5 to 5.5 v ? 3 8 4-mhz cpu clock v dd = 3.3 v 0.5 2 i dd3 stop mode v dd = 4.5 to 5.5 v ? 65 100 m a v dd = 3.3 v 45 80 note: d.c. electrical values for supply current (i dd1 to i dd3 ) do not include current drawn through internal pull-up resisters, output port drive current, zcd and a dc.
electrical data s3c9424/c9428/p942 8 1 6- 4 table 1 6-3 . d . c . electrical characteristics ( 28sop ) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max unit input high v oltage v i h1 ports 0, 1, 2 and reset v dd = 1.8 to 5.5 v 0. 8 v dd ? v dd v v i h3 x in and x out v dd ? 0.1 input low v oltage v i l1 ports 0, 1, 2 and reset v dd = 1.8 to 5.5 v ? ? 0.2 v dd v v i l2 x in and x out 0.1 out put high v oltage v oh i oh = ? 10 m a ports 0-3 v dd = 4.5 to 5.5 v v dd ? 1.0 v dd ? 0.4 ? v output low v oltage v o l i o l = 25 m a port 0-3 v dd = 4. 5 to 5.5 v ? 0.4 2.0 v input high leakage current i lih1 all input pins except i lih2 v in = v dd ? ? 1 m a i lih2 x in , x out v in = v dd 20 input low leakage current i lil1 all input pins except i lil2 and reset v in = 0 v ? ? ? 1 m a i lil2 x in , x out v in = 0 v ? 20 output high leakage current i loh all output pins v out = v dd ? ? 2 m a output low leakage current i lol all output pins v out = 0 v ? ? ? 2 m a pull-up resistor r p v in = 0 v port 0-2 v dd = 5 v 30 47 70 k w reset v dd = 5 v 100 200 350 supply current i dd1 run mode 16-mhz cpu clock v dd = 4.5 to 5.5 v ? 11 20 ma 3-mhz cpu clock v dd = 1.8 to 2.2 v 1 3 i dd2 idle mode 16-mhz cpu clock v dd = 4.5 to 5.5 v ? 3 9 3-mhz cpu clock v dd = 1.8 to 2.2 v 0.3 1.0 i dd3 stop mode v dd = 4.5 to 5.5 v ? 0.1 5 m a v dd = 3 v v dd = 1.8 to 2.2 v note: d.c. electrical values for supply current (i dd1 to i dd3 ) do not include current drawn through internal pull-up resisters, output port drive current, zcd and adc.
s3c9424/c9428/p9428 electrical data 1 6- 5 table 1 6-4 . a . c . electrical characteristics (t a = ?4 0 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max unit interrupt input high, low width t inth , t intl p ort 1v(int0, int1) v dd = 5v 10% ? 200 ? ns reset input l ow width t rsl ? input v dd = 5v 10% ? 1 ? us 0.8 v dd 0.2 v dd t intl t inth t rsl 1/t cpu note: the unit tcpu means one cpu clock period. figure 1 6-1 . input timing measurement points
electrical data s3c9424/c9428/p942 8 1 6- 6 cpu clock 16mhz 8mhz 4mhz 3mhz 2mhz 1mhz 1 2 3 4 5 6 7 2.7 5.5 supply voltage (v) 1.8 4.5 figure 16-2. operating voltage range (ks86c4204/c4208) 0.3 v dd a = 0.2 v dd b = 0.4 v dd c = 0.6 v dd d = 0.8 v dd v out a 0.7 v dd v dd v ss b c d v in figure 16-3. schimtt trigger input characteristic diagram
s3c9424/c9428/p9428 electrical data 1 6- 7 table 1 6-5 . oscillator characteristics (30sdip, 32sop) (t a = ? 40 c to + 85 c) oscillator clock circuit test condition min typ max unit main crystal or ceramic x in x out c1 c2 v dd = 4. 5 to 5.5 v v dd = 3.0 to 4.5 v 1 1 ? ? 16 8 mhz external clock (main system) x in x out v dd = 4. 5 to 5.5 v v dd = 3.0 to 4.5 v 1 1 ? ? 16 8 rc oscillator x in x out r v dd = 4.75 to 5.25 v tolerance: 10% ? 4 ? table 16-6. oscillation stabilization time (28sop) (t a = ? 40 c to + 85 c) oscillator clock circuit test condition min typ max unit main crystal or ceramic x in x out c1 c2 v dd = 4. 5 to 5.5 v v dd = 2.7 to 4.5 v v dd = 1.8 to 2.7 v 1 1 1 ? ? ? 16 8 3 mhz external clock (main system) x in x out v dd = 4. 5 to 5.5 v v dd = 2.7 to 4.5 v vdd = 1.8 to 2.7 v 1 1 1 ? ? ? 16 8 3 rc oscillator x in x out r v dd = 4.75 to 5.25 v tolerance: 10% ? 4 ?
electrical data s3c9424/c9428/p942 8 1 6- 8 table 1 6-7 . oscillation stabilization time (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) oscillator test condition min typ max unit main crystal fosc > 1.0 mhz ? ? 20 ms main ceramic oscillation stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 10 external clock (main system) x in input high and low width (t xh , t xl ) 25 ? 500 ns oscillator stabilization t wait when released by a reset (1) ? 2 1 6 /f osc ? ms wait time t wait when released by an interrupt (2) ? ? ? notes : 1. fosc is the oscillator frequency. 2. the duration of the oscillator stabilization wait time, t wait , when it is released by an interrupt is determined by the setting in the basic timer control register, btcon.
s3c9424/c9428/p9428 electrical data 1 6- 9 table 1 6-8 . data retention supply voltage in stop mode (t a = ? 40 c to + 85 c , v dd = 1.8 v to 5.5v ) parameter symbol conditions min typ max unit data retention supply voltage v dddr stop mode 1.8 ? 5.5 v data retention supply current i dddr stop mode; v dddr = 1.8 v ? 0.1 5 a note: supply current does not include current drawn through internal pull-up resistors or external output current loads. data retention mode ~ ~ ~ v dddr execution of stop instrction v dd normal operating mode oscillation stabilization time ~ stop mode internal reset operation reset t wait note: t wait is the same as 4096 x 16 x 1/fosc 0.8 v dd 0.2 v dd figure 1 6-4 . stop mode release timing when initiated by a reset reset
electrical data s3c9424/c9428/p942 8 1 6- 10 table 1 6-9 . power-on reset reset circuit characteristics (t a = ? 40 c to + 85 c , v dd = 3.0 v to 5.5 v ) parameter symbol conditions min typ max unit power-on reset voltage high v dd h 3.0 ? 5.5 v power-on reset voltage low v ddl 0 2.6 3.0 v power supply voltage rise time t r 10 (1) us power supply voltage off time t off 0.5 s power-on reset circuit i ddpr v dd = 5 v 10% 65 100 m a cunsumption current (2) v dd = 3.3 v 45 80 notes: 1. 216/fx (= 6.55 ms at fx = 10 mhz) 2. current consumed when power-on reset circuit is provided internally. v dd v ddh v ddl t off t r figure16-5. power-on reset reset timing
s3c9424/c9428/p9428 electrical data 1 6- 11 table 16-10. a/d converter electrical characteristics (t a = ? 40 c to + 85 c , v dd = 1.8/3.0 v to 5.5 v, v ss = 0 v ) parameter symbol test conditions min typ max unit total accuracy v dd = 5.12 v cpu clock = 10 mhz av ref = 5.12 v av ss = 0 v ? ? 3 lsb integral linearity error ile ? ? ? 2 lsb differential linearity error dle ? ? ? 1 offset error of top eot ? ? 1 3 offset error of bottom eob ? ? 1 2 conversion time (1) t con fosc = 10 mhz 20 ? ? m s analog input voltage v ian ? av ss ? av ref v analog input impedance r an ? 2 ? ? m w adc reference voltage av ref ? 2.5 ? v dd v adc reference ground av ss ? v ss ? v ss + 0.3 v analog input current i adin av ref = v dd = 5 v ? ? 10 m a adc block i adc av ref = v dd = 5 v ? 1 3 ma current (2) av ref = v dd = 3 v 0.5 1.5 av ref = v dd = 5 v power down mode ? 100 500 na notes: 1. ?conversion time? is the time required from the moment a conversion operation starts until it ends. 2. i adc is operating current during a/d conversion. 11 1111 1111 11 1111 1110 11 1111 1101 . . . . . . . 00 0000 0010 00 0000 0001 00 0000 0000 v eob av ss v 2 v (k-1) v (k) v eot av ref analog input digital output figure 16-6. definition of dle and ile
electrical data s3c9424/c9428/p942 8 1 6- 12 table 16-11. zero crossing detector (t a = ? 40 c to + 85 c , v dd = 4.5 v to 5.5 v, v ss = 0 v ) parameter symbol test conditions min typ max unit zero-crossing detection input voltage v zc ac connection c = 0.1 m f 1.0 ? 3.0 vp-p zero-crossing detection accuracy v azc f zc = 60 hz (sine wave) v dd = 5 v f osc = 10 mhz ? ? 150 mv zero-crossing detection input frequency f zc ? 40 ? 200 hz 1/fzc v azc zcint ac input v az(p-p) figure 1 6-7 . zero crossing waveform diagram
s3c9424/c9428/p9428 mechanical data 1 7- 1 1 7 mechanical data overview the s3c9424/c9428 is available in a 30 -pin s dip package (samsung: 30 - s dip- 4 00) and a 32 -pin so p package ( 32 - sop - 450a) and a 28-pin sop p ackage (28-sop-375). package dimensions are shown in figures 1 7- 1 , 17-2, and 17-3 note : dimensions are in millimeters. 27.88max 27.48 0 .2 1.778 (1.30) 0.51 min 3.30 0.3 3.81 0.2 5.08 max 0-15 1.12 0.1 0.25 + 0.1 - 0.05 10.16 #30 #16 #15 #1 30-sdip-400 0.56 0.1 8.94 0.2 figure 1 7- 1. 30 -pin s dip package dimensions
mechanical data s3c9424/c9428/p9428 1 7- 2 32-sop-450a #1 #16 #17 #32 2.40 max (0.43) 0.05 min 1.27 note: dimensions are in millimeters 19.90 0 .2 0.40 0 .1 12.00 0 .3 2.00 0 .2 11.43 0-8 8.34 0 .2 0.78 0 .2 0.20 + 0.1 - 0.05 figure 1 7- 2. 32 - sop-450a package dimensions
s3c9424/c9428/p9428 mechanical data 1 7- 3 28-sop-375 #1 #14 #15 #28 note: dimensions are in millimeters 10.45 0 .3 7.70 0 .2 0.60 0 .2 0.15 + 0.10 - 0.05 2.50 max (0.56) 0.05 min 17.62 0 .2 0.41 0 .1 2.15 0 .1 18.02 max 1.27 9.53 8 figure 1 7-3 . 28 - sop-375 package dimensions
s3c9424/c9428/p9428 S3P9428 otp 18- 1 18 S3P9428 otp overview the S3P9428 single-chip cmos microcontroller is the otp (one time programmable) version of the s3c9424/c9428 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the S3P9428 is fully compatible with the s3c9424/c9428, both in function and in pin configuration. because of its simple programming requirements, the S3P9428 is ideal for use as an evaluation chip for the s3c9424/c9428. note: the bolds indicate an otp pin name. v ss x in x out test/v pp p0.1/so p0.0/sck reset reset p3.0 p2.0/ad0 p2.1/ad1 p2.2/ad2 p2.3/ad3 p2.4/ad4 p2.5/ad5 av ss v d d p0.2/si/ scl p0.3/clo/ sda p0.4/ad8 p0.5/ad9 p0.6/ad10 p0.7/ad11/pwm0 p3.1 p1.0/t0/zcd p1.1/buz p1.2/int0 p1.3/int1/pwm1 p2.7/ad7/sclk p2.6/ad6/sdat av ref S3P9428 30-sdip (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 figure 1 8-1 . pin assignment diagram ( 30 -pin s dip package)
S3P9428 otp s3c9424/ c9428/p9428 18- 2 note: the bolds indicate an otp pin name. S3P9428 32-sop (top view) v ss x in x out test/v pp p0.1/so p0.0/sck reset reset p3.0 p3.2 p2.0/ad0 p2.1/ad1 p2.2/ad2 p2.3/ad3 p2.4/ad4 p2.5/ad5 av ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd p0.2/si/ scl p0.3/clo/ sda p0.4/ad8 p0.5/ad9 p0.6/ad10 p0.7/ad11/pwm0 p3.1 p3.3 p1.0/t0/zcd p1.1/buz p1.2/int0 p1.3/int1/pwm1 p2.7/ad7/sclk p2.6/ad6/sdat av ref 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 figure 1 8-2 . pin assignment diagram ( 32 -pin sop package) note: the bolds indicate an otp pin name. S3P9428 28-sop (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v ss x in x out test / v pp p0.1/so p0.0/sck reset reset p2.0/ad0 p2.1/ad1 p2.2/ad2 p2.3/ad3 p2.4/ad4 p2.5/ad5 av ss v d d p0.2/si/ scl p0.3/clo/ sda p0.4/ad8 p0.5/ad9 p0.6/ad10 p0.7/ad11/pwm0 p1.0/t0/zcd p1.1/buz p1.2/int0 p1.3/int1/pwm1 p2.7/ad7/sclk p2.6/ad6/sdat av ref figure 1 8-3 . pin assignment diagram ( 28 -pin sop package)
s3c9424/c9428/p9428 S3P9428 otp 18- 3 table 18-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p0.3 sdat S3P9428 - 30 sdip: 28 - 32 sop: 30 i/o serial data pin (output when reading, input when writing) input and push-pull output port can be assigned p0.2 sclk S3P9428 - 30 sdip: 29 - 32 sop: 31 i serial clock pin (input only pin) test v pp (test) 4 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 7 i chip initialization v dd /v ss v dd /v ss S3P9428 - 30 sdip: 30/1 - 32 sop: 32/1 i logic power supply pin. table 18-2. comparison of S3P9428 and s3c9424/c9428 features characteristic S3P9428 s3c9424/c9428 program memory 8-kbyte eprom 4/8-kbyte mask rom operating voltage (v dd ) 3.0 v to 5.5 v (28 sop: 1.8 v to 5.5) 3.0 v to 5.5 v (28 sop: 1.8 v to 5.5) otp programming mode v dd = 5 v, v pp (test) = 12.5 v pin configuration 30 sdip/32 sop/28sop eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the S3P9428, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 18-3 below. table 18-3. operating mode selection criteria v dd v pp (test) reg/ mem mem address (a15-a0) r/ w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note: "0" means low level; "1" means high level.
s3c9424/c9428/p9428 development tools 1 9- 1 1 9 development tools overview samsung provides a powerf u l and easy-to-use development support system in turnkey form. the development support system is configured with a host system, debugging tools, and support software. for the host system, any standard computer that operates with ms-dos as its operating system can be used. one type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, smds2+, for s3c7 , s3c8 , s3c9 families of microcontrollers. the smds2+ is a new and improved version of smds2. samsung also offers support software that includes debugger, a s sembler, and a program for setting options. shine samsung host interface for i n -circuit emulator, shine, is a multi-window based debugger for smds2+. shine provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. it has an advanced, multiple-windowed user interface that emphasizes ease of use. each window can be sized, moved, scrolled, hig hlighted, added, or removed compl etely. sama assembler the samsung arrangeable microcontroller (sam) assembler, sama, is a universal assembler, and generates object code in standard hexadecimal format. assembled program code includes the object code that is used for rom data and required smds program control data. to assemble programs, sama requires a source file and an auxiliary definition (def) file with device specific information. sasm86 the sasm86 is an relocatable assembler for samsung's s3c9 -series microcontrollers. the sasm86 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. the sasm86 supports macros and conditional assembly. it runs on the ms-dos operating system. it produces the relocatable object code only, so the user should link object file. object files can be linked with other object files and loaded into memory. hex2rom hex2rom file generates rom code from hex file which has been produced by assembler. rom code must be needed to fabricate a microcontroller which has a mask rom. when generating the rom code (.obj file) by hex2rom, the value " ff " is filled into the unused rom area upto the maximum rom size of the targe t device automatically. target boards target boards are available for all s3c9 -series microcontrollers. all required target system cables and adapters are included with the device-specific target board. otp s one times programmable microcontrollers (otps) for s3c9424/c9428 microcontroller already have been developed .
development tools ks86c4204/c4208/p4 208 1 9- 2 bus smds2+ rs-232c pod probe adapter prom/otp writer unit ram break/display unit trace/timer unit sam8 base unit power supply unit ibm-pc or compatible tb9424/9428 target board eva chip target application system figure 1 9-1 . smds product configuration (smds2+)
s3c9424/c9428/p9428 development tools 1 9- 3 tb9424/9428 target board the tb9424/9428 target board is used for the S3P9428 microcontroller s . it is supported by the smds2+ development systems. 25 tb9424/9428 sm1324a to user_vcc off on 1 cn1 100-pin connector reset vcc gnd u1 + stop + idle 16 30-pin dip socket j101 15 1 30 100 qfp s3c9400 eva chip 30 1 smds2+ smds2 external triggers ch1 ch2 figure 1 9-2 . tb9424/9428 target board configuration
development tools ks86c4204/c4208/p4 208 1 9- 4 table 1 9- 1. power selection settings for tb86 4204a/08a " to user_vcc " settings operating mode comments to user_vcc off on external tb9424 /92428 target system vcc v ss v cc smds2+ the smds2+ main board supplies v cc to the target board (evaluation chip) and the target system. on to user_vcc off tb9424 /9428 target system v ss v cc smds2+ v cc the smds2+ main board supplies v cc only to the target board (evaluation chip). the target system must have its own power supply. note: the following symbol in the " to user_vcc " setting column indicates the electrical short (off) configuration: smds2+ selection (sam8) in order to write data into program memory that is available in smds2+, the target board should be selected to be for smds2+ through a switch as follows. otherwise, the program memory writing function is not available. table 1 9-2 . the smds2+ tool selection setting "sw1" setting operating mode smds2 smds2+ smds2+ target board r/w* r/w*
s3c9424/c9428/p9428 development tools 1 9- 5 table 1 9-3 . using single header pins as the input path for external trigger sources target board part comments external triggers ch1 ch2 connector from external trigger sources of the application system you can connect an external trigger source to one of the two external trigger channels (ch1 or ch2) for the smds2+ breakpoint and trace functions.
development tools ks86c4204/c4208/p4 208 1 9- 6 v ss test p0.1 p0.0 reset p3.0 p3.2 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 av ss v dd p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p3.1 p3.3 p1.0 p1.1 p1.2 p1.3 p2.7 p2.6 av ref j101 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 30-pin connector figure 1 9-3 . 3 0-pin connector for tb9424/9428 15 1 16 30 target system target board 30-pin connector j101 part name: ap30sd-f order code: sm6536 1 30 15 16 1 30 15 16 30sdip conversion pcb figure 1 9-4 . S3P9428 probe adapter for 30-sdip package

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