may 2012 ? 2001 fairchild semiconductor corporation www.fairchildsemi.com fstd3125 ? rev. 1.0.3 fstd3125 ? 4-bit bus switch with level shifting fstd3125 ? 4-bit bus switch with level shifting features ? 4 switch connection between two ports ? minimal propagation delay through the switch ? low i cc ? zero bounce in flow-through mode ? control inputs compatible with ttl level ? trutranslation voltage trans lation from 5.0v inputs to 3.3v outputs description fairchild switch fstd3125 provides four high-speed cmos ttl-compatible bus switches. the low on resistance of the switch allo ws inputs to be connected to outputs without adding propagat ion delay or generating additional ground bounce noise. a diode to v cc has been integrated into the circuit to allow for level shifting between 5v inputs and 3.3v outputs. the device is organized as f our one-bit switches with separate /oe inputs. when /oe is low, the switch is on and port a is connected to port b. when /oe is high, the switch is o pen and a high-impedance state exists between the two ports. ordering information part number operating temperature range package packing method fstd3125mtcx -40 to 85c 14-lead, thin shrink small outline package (tssop), jedec mo-153, 4mm wide tape and reel 1a /oe 1 /oe 2 /oe 4 /oe 3 4a 3a 2a 1b 2b 3b 4b 1 23 4 56 8 10 9 13 11 12 figure 1. logic diagram
? 2001 fairchild semiconductor corporation www.fairchildsemi.com fst3d125 ? rev. 1.0.3 2 fstd3125 ? 4-bit bus switch with level shifting pin configuration /oe 1 1a 1b /oe 2 2a 2b gnd v cc /oe 4 4a 4b /oe 3 3a 3b 14 13 12 11 10 9 8 1 2 3 4 5 6 7 figure 2. pin assignments pin descriptions pin # pin names description 1, 4, 10, 13 /oe 1 , /oe 2 , /oe 3 , /oe 4 bus switch enables 2, 5, 9, 12 1a, 2a, 3a, 4a bus a 3, 6, 8, 11 1b, 2b, 3b, 4b bus b 14 v cc supply voltage 7 gnd ground truth table inputs inputs/outputs /oe a, b low a = b high high impedance
? 2001 fairchild semiconductor corporation www.fairchildsemi.com fst3d125 ? rev. 1.0.3 3 fstd3125 ? 4-bit bus switch with level shifting absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditi ons may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc supply voltage -0.5 7.0 v v s dc switch voltage -0.5 7.0 v v in dc input voltage (1) -0.5 7.0 v i ik dc input diode current, v in <0v -50 ma i out dc output sink current 128 ma i cc / i gnd dc v cc / gnd current 100 ma t stg storage temperature range -65 +150 c note : 1. the input and output negativ e voltage ratings may be exceeded if the i nput and output diode current ratings are observed. recommended operating conditions the recommended operating conditions table defines the conditions for actual device oper ation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificat ions. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit v cc power supply operating 4.5 5.5 v v in input voltage 0 5.5 v v out output voltage 0 5.5 v t r , t f input rise and fall time switch control input (2) 0 5 ns/v switch i/o 0 dc t a operating temperature, free air -40 +85 c note : 2. unused control inputs must be held high or low. they may not float.
? 2001 fairchild semiconductor corporation www.fairchildsemi.com fst3d125 ? rev. 1.0.3 4 fstd3125 ? 4-bit bus switch with level shifting dc electrical characteristics typical values are at v cc = 5.0v and t a = 25c. symbol parameter condition v cc (v) t a =-40 to +85c unit min. typ. max. v ik clamp diode voltage i in = -18ma 4.5 -1.2 v v ih high-level input voltage 4.5 to 5.5 2.0 v v oh high-level figure 5, figure 6, and figure 7 4.0 to 5.5 v v il low-level input voltage 4.5 to 5.5 0.8 v i in input leakage current 0 v in 5.5v 5.5 1.0 a v in = 5.5v 0 10 a i oz off-state leakage current 0 a, b v cc 5.5 1.0 a r on switch on resistance (3) v in = 0v, i in = 64ma 4.5 4 7 v in = 0v, i in = 30ma 4.5 4 7 v in = 2.4v, i in = 15ma 4.5 35 50 i cc quiescent supply current /oe 1 = /oe 2 = gnd v in = v cc or gnd, i out = 0 5.5 1.5 a /oe 1 = /oe 2 = v cc v in = v cc or gnd, i out = 0 10 i cc increase in i cc per input one input at 3.4v, other inputs at v cc or gnd 5.5 2.5 ma note : 3. measured by the voltage drop between the a and b pins at the indi cated current through the switch. on resistance is determined by the lower of the voltages on the a or b pins. ac electrical characteristics t a = -40 to +85c, c l = 50pf, and r u = r d = 500 . symbol parameter condition v cc = 4.5 ? 5.5v unit figure min. max. t phl , t plh propagation delay, bus-to-bus (4) v in = open 0.25 ns figure 3 figure 4 t pzh ,t pzl output enable time v in = 7v for t pzl v in = open for t pzh 1.0 6.1 ns figure 3 figure 4 t phz , t plz output disable time v in = 7v for t plz v in = open for t phz 1.5 6.4 ns figure 3 figure 4 note : 4. this parameter is guaranteed by desi gn, but is not tested. the bus switch contributes no pr opagation delay other than the rc delay of the typical on resistance of the switch and the 50pf load capacitance when driven by an ideal voltage source (zero output impedance). capacitance t a = +25c, f = 1mhz. capacitance is characterized, but not tested. symbol parameter condition typ. unit c in control pin input capacitance v cc = 5.0v 3 pf c i/o input/output capacitance v cc , /oe = 5.0v 6 pf
? 2001 fairchild semiconductor corporation www.fairchildsemi.com fstd3125 ? rev. 1.0.3 5 fstd3125 ? 4-bit bus switch with level shifting ac loadings and waveforms notes : input driven by 50 source terminated in 50 . c l includes load and stray capacitance. input prr = 1.0mhz, t w = 500ns. figure 3. ac test circuit figure 4. ac waveforms
? 2001 fairchild semiconductor corporation www.fairchildsemi.com fstd3125 ? rev. 1.0.3 6 fstd3125 ? 4-bit bus switch with level shifting performance characteristics figure 5. output voltage vs. supply voltage, v in = v cc, t a = 85c figure 6. output voltage vs. supply voltage, v in = v cc, t a = 25c figure 7. output voltage vs. supply voltage, v in = v cc, t a = 0c
? 2001 fairchild semiconductor corporation www.fairchildsemi.com fstd3125 ? rev. 1.0.3 7 fstd3125 ? 4-bit bus switch with level shifting physical dimensions c. dimensions are exclusive of burrs, mold flash, and tie bar extrusions f. drawing file name: mtc14rev6 r0.09 min 12.00 top & bottom 0.43 typ 1.00 d. dimensioning and tolerances per ansi y14.5m, 1982 r0.09min e. landpattern standard: sop65p640x110-14m 0.65 6.10 1.65 0.45 a. conforms to jedec registration mo-153, variation ab, ref note 6 b. dimensions are in millimeters figure 8. 14-lead, thin shrink small outline package (tssop) mo-153, 4mm wide package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
? 2001 fairchild semiconductor corporation www.fairchildsemi.com fstd3125 ? rev. 1.0.3 8 fstd3125 ? 4-bit bus switch with level shifting
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