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a ad1896 * information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. rev. a 192 khz stereo asynchronous sample rate converter functional block diagram grpdlys vdd_io vdd_core serial input fifo fs out fs in serial output digital pll fir filter clock divider rom ad1896 bypass mute_o mute_i sdata_i sclk_i lrclk_i smode_in_0 smode_in_1 smode_in_2 mclk_i mclk_o msmode_0 msmode_2 msmode_1 wlngth_o_0 wlngth_o_1 smode_o_0 smode_o_1 tdm_in sdata_o sclk_o lrclk_o reset product overview the ad1896 is a 24-bit, high performance, single-chip, second- generation asynchronous sample rate converter. based on analog devices experience with its first asynchronous sample rate converter, the ad1890, the ad1896 offers improved performance and additional features. this improved performance includes a thd + n range of ?17 db to ?33 db depending on the sample rate and input frequency, 142 db (a-weighted) dynamic range, 192 khz sampling frequencies for both input and output sample rates, improved jitter rejection, and 1:8 upsampling and 7.75:1 downsampling ratios. additional features include more serial formats, a bypass mode, better interfacing to digital signal pro- cessors, and a matched-phase mode. the ad1896 has a 3-wire interface for the serial input and output ports that supports left-justified, i 2 s, and right-justified (16-, 18-, 20-, 24-bit) modes. additionally, the serial output port supports tdm mode for daisy-chaining multiple ad1896s to a digital signal processor. the serial output data is dithered down to 20, 18, or 16 bits when 20-, 18-, or 16-bit output data is se- lected. the ad 1896 sample rate converts the data from the serial input port to the sample rate of the serial output port. the sample rate at the serial in put port can be asyn chronous with respect to the output sample rate of the output serial port. the master clock to the ad1896, mclk, can be asynchronous to both the serial input and output ports. mclk can be generated either off-chip or on-chip by the ad1896 ma ster clock oscillator. since mclk can be asynchronous to the input or output serial ports, a crystal can be used to gene rate mclk internally to reduce noise and emi emissions on the board. when mclk is synchronous to either the output or input serial port, the ad1896 can be configured in a master mode where m clk is divided down and used to generate the left/right and bit clocks for the serial port that is synchronous to mclk. the ad1896 supports master modes of 256 f s , 512 f s , and 768 f s for both input and output serial ports. conceptually, the ad1896 interpolates the serial input data by a rate of 2 20 and samples the interpolated data stream by the output sample rate. in practice, a 64-tap fir filter with 2 20 polyphases, a fifo, a digital servo loop that measures the time difference between the input and output samples within 5 ps, and a digital circuit to track the sample rate ratio are used to perform the interpolation and output sampling. refer to the theory of operation section. the digital servo loop and sample rate ratio circuit automatically track the input and output sample rates. (continued on page 17 ) features automatically senses sample frequencies no programming required attenuates sample clock jitter 3.3 v? v input and 3.3 v core supply voltages accepts 16-/18-/20-/24-bit data up to 192 khz sample rate input/output sample ratios from 7.75:1 to 1:8 bypass mode multiple ad1896 tdm daisy-chain mode multiple ad1896 matched-phase mode 142 db signal-to-noise and dynamic range (a-weighted, 20 hz?0 khz bw) up to ?33 db thd + n linear phase fir filter hardware controllable soft mute supports 256 f s , 512 f s , or 768 f s master mode clock flexible 3-wire serial data port with left-justified, i 2 s, right-justified (16-,18-, 20-, 24-bits), and tdm serial port modes master/slave input and output modes 28-lead ssop plastic package applications home theater systems, studio digital mixers, automotive audio systems, dvd, set-top boxes, digital audio effects processors, studio-to-transmitter links, digital audio broadcast equipment, digitaltape varispeed applications * patents pending.
rev. a ? ad1896?pecifications test conditions, unless otherwise noted. supply voltages vdd_core 3.3 v vdd_io 5.0 v or 3.3 v ambient temperature 25 c input clock 30.0 mhz input signal 1.000 khz, 0 dbfs measurement bandwidth 20 to f s_out /2 hz word width 24 bits load capacitance 50 pf input voltage high 2.4 v input voltage low 0.8 v specifications subject to change without notice. digital performance (vdd_core = 3.3 v 5%, vdd_io = 5.0 v 10%) parameter min typ max unit resolution 24 bits sample rate @ mclk_i = 30 mhz 6 215 khz sample rate (@ other master clocks) 1 mclk_i/5000 f s < mclk_i/138 khz sample rate ratios upsampling 1:8 downsampling (short grpdlys) 7.75:1 downsampling (long grpdlys) 7.0:1 dynamic range 2 (20 hz to f s_out /2, 1 khz, ?0 dbfs input) a-weighted worst-case (192 khz:48 khz) 132 db 44.1 khz:48 khz 142 db 48 khz:44.1 khz 141 db 48 khz:96 khz 142 db 44.1 khz:192 khz 141.5 db 96 khz:48 khz 140 db 192 khz:32 khz 140 db (20 hz to f s_out /2, 1 khz, ?0 dbfs input) no filter worst-case (192 khz:48 khz) 132 db 44.1 khz:48 khz 139 db 48 khz:44.1 khz 139 db 48 khz:96 khz 139 db 44.1 khz:192 khz 137 db 96 khz:48 khz 137 db 192 khz:32 khz 138 db total harmonic distortion + noise 2 (20 hz to f s_out /2, 1 khz, 0 dbfs input) no filter worst-case (32 khz:48 khz) 3 ?17 db 44.1 khz:48 khz ?23 db 48 khz:44.1 khz ?24 db 48 khz:96 khz ?20 db 44.1 khz:192 khz ?23 db 96 khz:48 khz ?32 db 192 khz:32 khz ?33 db interchannel gain mismatch 0.0 db interchannel phase deviation 0.0 degrees mute attenuation (24 bits word width) (a-weighted) ?44 db notes 1 lower sampling rates than given by this formula are possible, but the jitter rejection will decrease. 2 refer to the typical performance characteristics section for dnr and thd + n numbers over wide range of input and output sample rates. 3 for any other sample rate ratio, the minimum thd + n will be better than ?17 db. please refer to detailed performance plots. specifications subject to change without notice.
rev. a ? ad1896 digital timing (?0 c < t a < +105 c, vdd_core = 3.3 v 5%, vdd_io = 5.0 v 10%) parameter 1 min typ max unit t mclki mclk_i period 33.3 ns f mclk mclk_i frequency 30.0 2, 3 mhz t mpwh mclk_i pulsewidth high 9 ns t mpwl mclk_i pulsewidth low 12 ns input serial port timing t lris lrclk_i setup to sclk_i 8 ns t sih sclk_i pulsewidth high 8 ns t sil sclk_i pulsewidth low 8 ns t dis sdata_i setup to sclk_i rising edge 8 ns t dih sdata_i hold from sclk_i rising edge 3 ns propagation delay from mclk_i rising edge to sclk_i rising edge (serial input port master) 12 ns propagation delay from mclk_i rising edge to lrclk_i rising edge (serial input port master) 12 ns output serial port timing t tdms tdm_in setup to sclk_o falling edge 3 ns t tdmh tdm_in hold from sclk_o falling edge 3 ns t dopd sdata_o propagation delay from sclk_o, lrclk_o 20 ns t doh sdata_o hold from sclk_o 3 ns t lros lrclk_o setup to sclk_o (tdm mode only) 5 ns t lroh lrclk_o hold from sclk_o (tdm mode only) 3 ns t soh sclk_o pulsewidth high 10 ns t sol sclk_o pulsewidth low 5 ns t rstl reset pulsewidth low 200 ns propagation delay from mclk_i rising edge to sclk_o rising edge (serial output port master) 12 ns propagation delay from mclk_i rising edge to lrclk_o rising edge (serial output port master) 12 ns notes 1 refer to timing diagrams section. 2 the maximum possible sample rate is: fs max = f mclk /138. 3 f mclk of up to 34 mhz is possible under the following conditions: 0
rev. a ad1896 ? timing diagrams t lris t sih t dis t sil t dih t lros t soh t dopd t sol t doh t lroh t tdms t tdmh lrclk_i sclk i sdata i lrclk o sclk o sdata o lrclk o sclk o tdm in figure 1. input and output serial port timing (sclk i/o, lrclk i/o, sdata i/o, tdm_in) t rstl mclk i reset figure 2. reset timing t mpwh t mpwl figure 3. mclk_i timing
rev. a e5e ad1896 digital filters (vdd_core = 3.3 v 5%, vdd_io = 5.0 v 10%) parameter min typ max unit pass-band 0.4535 f s_out hz pass-band ripple 0.016 db transition band 0.4535 f s_out 0.5465 f s_out hz stop-band 0.5465 f s_out hz stop-band attenuation e125 db group delay refer to the group delay equations section. specifications subject to change without notice. digital i/o characteristics (vdd_core = 3.3 v 5%, vdd_io = 5.0 v 10%) parameter min typ max unit input voltage high (v ih ) 2.4 input voltage low (v il ) 0.8 v input leakage (i ih @ v ih = 5 v) 1 +2 m a input leakage (i il @ v il = 0 v) 1 e2 m a input leakage (i ih @ v ih = 5 v) 2 +150 m a input leakage (i il @ v il = 0 v) 2 e150 m a input capacitance 5 10 pf output voltage high (v oh @ i oh = e4 ma) vdd_core e 0.5 vdd_core e 0.4 v output voltage low (v ol @ i ol = +4 ma) 0.2 0.5 v output source current high (i oh )e4ma output sink current low (i ol )+4ma notes 1 all input pins except grpdlys. 2 grpdlys pin only. specifications subject to change without notice. power supplies parameter min typ max unit supply voltage vdd_core 3.135 3.3 3.465 v vdd_io * vdd_core 3.3/5.0 5.5 v active supply current i_core_active 48 khz:48 khz 20 ma 96 khz:96 khz 26 ma 192 khz:192 khz 43 ma i_io_active 2 ma power-down supply current: (all clocks stopped) i_core_pwrdn 0.5 ma i_io_pwrdn 10 m a * for 3.3 v tolerant inputs, vdd_io supply should be set to 3.3 v; however, vdd_core supply voltage should not exceed vdd_io. specifications subject to change without notice.
rev. a ad1896 ? caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad1896 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings * parameter min max unit power supplies vdd_core ?.3 +3.6 v vdd_io ?.3 +6.0 v digital inputs input current 10 ma input voltage dgnd ?0.3 vdd_io + 0.3 v ambient temperature (operating) ?0 +105 c * stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress ra ting only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide model temperature range package description package option ad1896ayrs ?0 c to +105 c 28-lead ssop rs-28 ad1896ayrsrl ?0 c to +105 c 28-lead ssop rs-28 on 13" reel power supplies (vdd_core = 3.3 v 5%, vdd_io = 5.0 v 10%) parameter min typ max unit total active power dissipation 48 khz:48 khz 65 mw 96 khz:96 khz 85 mw 192 khz:192 khz 132 mw total power-down dissipation: (reset lo) 2 mw specifications subject to change without notice. temperature range parameter min typ max unit specifications guaranteed 25 c functionality guaranteed ?0 +105 c storage ?5 +150 c thermal resistance, q ja (junction to ambient) 109 c/w specifications subject to change without notice.
rev. a ad1896 e7e pin configuration 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad1896 top view (not to scale ) mute_in reset smode_in_2 smode_in_1 smode_in_0 bypass dgnd grpdlys mclk_in mclk_out sdata_i vdd_io lrclk_i sclk_i mute_out wlngth_out_1 wlngth_out_0 smode_out_1 smode_out_0 tdm_in dgnd mmode_2 mmode_1 mmode_0 sclk_o vdd_core sdata_o lrclk_o pin function descriptions pin no. in/out mnemonic description 1i n grpdlys group delay high = short, low = long 2i n mclk_in master clock or crystal input 3 out mclk_out master clock output or crystal output 4i n sdata_i input serial data (at input sample rate) 5 in/out sclk_i master/slave input serial bit clock 6 in/out lrclk_i master/slave input left/right clock 7i n vdd_io 3.3 v/5 v input/output digital supply pin 8i n dgnd digital ground pin 9i n bypass asrc bypass mode, active high 10 in smode_in_0 input port serial interface mode select pin 0 11 in smode_in_1 input port serial interface mode select pin 1 12 in smode_in_2 input port serial interface mode select pin 2 13 in reset r te tet t tet tt ss tt ss set ss set ss t s re s t st ssr t r sr t s ss e srs e srs e srs
rev. a e200 0 e180 e160 e140 e120 e100 e80 e60 e40 e20 10 90 20 30 40 50 60 70 80 frequency e khz dbfs tpc 4. wideband fft plot (16k points) 44.1 khz:192 khz, 0 dbfs 1 khz tone e200 0 e180 e160 e140 e120 e100 e80 e60 e40 e20 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 frequency e khz dbfs tpc 5. wideband fft plot (16k points) 48 khz:44.1 khz, 0 dbfs 1 khz tone 22.5 e200 0 e180 e160 e140 e120 e100 e80 e60 e40 e20 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 frequency e khz dbfs tpc 6. wideband fft plot (16k points) 96 khz:48 khz, 0 dbfs 1 khz tone e200 0 e180 e160 e140 e120 e100 e80 e60 e40 e20 2.5 22.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 frequency e khz dbfs tpc 1. wideband fft plot (16k points) 0 dbfs 1 khz tone, 48 khz:48 khz (asynchronous) 2.5 22.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 frequency e khz e200 0 e180 e160 e140 e120 e100 e80 e60 e40 e20 dbfs tpc 2. wideband fft plot (16k points) 0 dbfs 1 khz tone, 44.1 khz:48 khz (asynchronous) e200 0 e180 e160 e140 e120 e100 e80 e60 e40 e20 545 10 15 20 25 30 35 40 frequency e khz dbfs tpc 3. wideband fft plot (16k points) 48 khz:96 khz, 0 dbfs 1 khz tone e8e ad1896 etypical performance characteristics
rev. a ad1896 e9e 22.5 e200 0 e180 e160 e140 e120 e100 e80 e60 e40 e20 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 frequency e khz dbfs tpc 7. wideband fft plot (16k points) 192 khz:48 khz, 0 dbfs 1 khz tone e200 e50 e190 e180 e170 e160 e150 e140 e130 e120 e110 e100 e90 e80 e70 e60 2.5 22.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 frequency e khz dbfs tpc 8. wideband fft plot (16k points) e60 dbfs 1 khz tone, 48 khz:48 khz (asynchronous) e200 e50 e190 e180 e170 e160 e150 e140 e130 e120 e110 e100 e90 e80 e70 e60 2.5 22.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 frequency e khz dbfs tpc 9. wideband fft plot (16k points) 44.1 khz:48 khz, e60 dbfs 1 khz tone e200 e50 e190 e180 e170 e160 e150 e140 e130 e120 e110 e100 e90 e80 e70 e60 545 10 15 20 25 30 35 40 frequency e khz dbfs tpc 10. wideband fft plot (16k points) 48 khz:96 khz, e60 dbfs 1 khz tone e200 e50 e190 e180 e170 e160 e150 e140 e130 e120 e110 e100 e90 e80 e70 e60 10 90 20 30 40 50 60 70 80 frequency e khz dbfs tpc 11. wideband fft plot (16k points) 44.1 khz:192 khz, e60 dbfs 1 khz tone e200 e50 e190 e180 e170 e160 e150 e140 e130 e120 e110 e100 e90 e80 e70 e60 2.5 7.5 12.5 17.5 frequency e khz dbfs 5.0 10.0 15.0 20.0 tpc 12. wideband fft plot (16k points) 48 khz:44.1 khz, e60 dbfs 1 khz tone
rev. a ad1896 e10e e200 e50 e190 e180 e170 e160 e150 e140 e130 e120 e110 e100 e90 e80 e70 e60 2.5 22.5 7.5 12.5 17.5 frequency e khz dbfs 5.0 10.0 15.0 20.0 tpc 13. wideband fft plot (16k points) 96 khz:48 khz, e60 dbfs 1 khz tone e200 e50 e190 e180 e170 e160 e150 e140 e130 e120 e110 e100 e90 e80 e70 e60 2.5 22.5 7.5 12.5 17.5 frequency e khz dbfs 5.0 10.0 15.0 20.0 tpc 14. wideband fft plot (16k points) 192 khz:48 khz, e60 dbfs 1 khz tone e180 0 e160 e140 e120 e100 e80 e60 e40 e20 frequency e khz dbfs 2.5 20.0 5.0 7.5 10.0 12.5 15.0 17.5 22.5 tpc 15. imd, 10 khz and 11 khz 0 dbfs tone 44:1 khz:48 khz e180 0 e160 e140 e120 e100 e80 e60 e40 e20 frequency e khz dbfs 2.5 20.0 5.0 7.5 10.0 12.5 15.0 17.5 22.5 tpc 16. imd, 10 khz and 11 khz 0 dbfs tone 96 khz:48 khz e180 0 e160 e140 e120 e100 e80 e60 e40 e20 frequency e khz dbfs 2.5 20.0 5.0 7.5 10.0 12.5 15.0 17.5 tpc 17. imd, 10 khz and 11 khz 0 dbfs tone 48 khz:44.1 khz frequency e khz e200 0 e180 e160 e140 e120 e100 e80 e60 e40 e20 dbfs 2.5 20.0 5.0 7.5 10.0 12.5 15.0 17.5 22.5 tpc 18. wideband fft plot (16k points) 44.1 khz:48 khz, 0 dbfs 20 khz tone
rev. a ad1896 e11e 10 90 20 30 40 50 60 70 80 frequency e khz e200 0 e180 e160 e140 e120 e100 e80 e60 e40 e20 dbfs tpc 19. wideband fft plot (16k points) 192 khz:192 khz, 0 dbfs 80 khz tone e200 0 e180 e160 e140 e120 e100 e80 e60 e40 e20 2.5 22.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 frequency e khz dbfs tpc 20. wideband fft plot (16k points) 48 khz:48 khz, 0 dbfs 20 khz tone frequency e khz e200 0 e180 e160 e140 e120 e100 e80 e60 e40 e20 dbfs 2.5 20.0 5.0 7.5 10.0 12.5 15.0 17.5 tpc 21. wideband fft plot (16k points) 48 khz:44:1 khz, 0 dbfs 20 khz tone 545 10 15 20 25 30 35 40 frequency e khz e200 0 e180 e160 e140 e120 e100 e80 e60 e40 e20 dbfs tpc 22. wideband fft plot (16k points) 48 khz:96 khz, 0 dbfs 20 khz tone frequency e khz e200 0 e180 e160 e140 e120 e100 e80 e60 e40 e20 dbfs 2.5 20.0 5.0 7.5 10.0 12.5 15.0 17.5 22.5 tpc 23. wideband fft plot (16k points) 96 khz:48 khz, 0 dbfs 20 khz tone e119 e121 e123 e125 e127 e129 e131 e133 e135 30 55 80 105 130 155 180 thd+n e dbfs ou tput sample rate e khz tpc 24. thd + n vs. output sample rate, f s_in = 192 khz, 0 dbfs 1 khz tone
rev. a ad1896 e12e e119 e121 e123 e125 e127 e129 e131 e133 e135 30 55 80 105 130 155 180 thd+n e dbfs ou tput sample rate e khz tpc 25. thd + n vs. output sample rate, f s_in = 48 khz, 0 dbfs 1 khz tone e119 e121 e123 e125 e127 e129 e131 e133 e135 30 55 80 105 130 155 180 thd+n e dbfs ou tput sample rate e khz tpc 26. thd + n vs. output sample rate, f s_in = 44.1 khz, 0 dbfs 1 khz tone e119 e121 e123 e125 e127 e129 e131 e133 e135 30 55 80 105 130 155 180 thd+n e dbfs ou tput sample rate e khz tpc 27. thd + n vs. output sample rate, f s_in = 32 khz, 0 dbfs 1 khz tone e119 e121 e123 e125 e127 e129 e131 e133 e135 30 55 80 105 130 155 180 thd+n e dbfs ou tput sample rate e khz tpc 28. thd + n vs. output sample rate, f s_in = 96 khz, 0 dbfs 1 khz tone e130 e131 e132 e133 e134 e135 e136 e137 e138 e139 e140 30 55 80 105 130 155 180 dnr e dbfs ou tput sample rate e khz tpc 29. dnr vs. output sample rate, f s_in = 192 khz, e60 dbfs 1 khz tone e135 e136 e137 e138 e139 e140 e141 e142 e143 e144 e145 30 55 80 105 130 155 180 dnr e dbfs ou tput sample rate e khz tpc 30. dnr vs. output sample rate, f s_in = 32 khz, e60 dbfs 1 khz tone
rev. a ad1896 e13e e130 e131 e132 e133 e134 e135 e136 e137 e138 e139 e140 30 55 80 105 130 155 180 dnr e dbfs ou tput sample rate e khz tpc 31. dnr vs. output sample rate, f s_in = 96 khz, e60 dbfs 1 khz tone 0 e20 e40 e60 e80 e100 e120 e140 0 10 20 30 40 50 60 dbfs frequency e khz 192khz:96khz 192khz:48khz 192khz:32khz tpc 32. digital filter frequency response e135 e136 e137 e138 e139 e140 e141 e142 e143 e144 e145 30 55 80 105 130 155 180 dnr e dbfs ou tput sample rate e khz tpc 33. dnr vs. output sample rate, f s_in = 48 khz, e60 dbfs 1 khz tone e135 e136 e137 e138 e139 e140 30 55 80 105 130 155 180 output sample rate e khz dnr e dbfs tpc 34. dnr vs. output sample rate, f s_in = 44.1 khz, e60 dbfs 1 khz tone 0.00 e0.01 e0.02 e0.03 e0.04 e0.05 e0.06 e0.07 e0.08 e0.09 e0.10 dbfs 0 2 4 6 8 10 12 14 16 18 20 22 24 frequency e khz 192khz:48khz tpc 35. pass-band ripple, 192 khz:48 khz e5 5 e4 e3 e2 e1 0 1 2 3 4 e140 0 e120 e100 e80 e60 e40 e20 input level e dbfs linearity error e dbr tpc 36. linearity error, 48 khz:48 khz, 0 dbfs to e140 dbfs input, 200 hz tone
rev. a ad1896 e14e e5 5 e4 e3 e2 e1 0 1 2 3 4 e 140 0 e 120 e 100 e 80 e 60 e 40 e 20 input level e dbfs linearity error e dbr tpc 37. linearity error, 48 khz:44.1 khz, 0 dbfs to e140 dbfs input, 200 hz tone e5 5 e4 e3 e2 e1 0 1 2 3 4 e 140 0 e 120 e 100 e 80 e 60 e 40 e 20 input level e dbfs linearity error e dbr tpc 38. linearity error, 96 khz:48 khz, 0 dbfs to e140 dbfs input, 200 hz tone e5 5 e4 e3 e2 e1 0 1 2 3 4 e 140 0 e 120 e 100 e 80 e 60 e 40 e 20 input level e dbfs linearity error e dbr tpc 39. linearity error, 44.1 khz:48 khz, 0 dbfs to e140 dbfs input, 200 hz tone e5 5 e4 e3 e2 e1 0 1 2 3 4 e 140 0 e 120 e 100 e 80 e 60 e 40 e 20 input level e dbfs linearity error e dbr tpc 40. linearity error, 48 khz:96 khz, 0 dbfs to e140 dbfs input, 200 hz tone e5 5 e4 e3 e2 e1 0 1 2 3 4 e 140 0 e 120 e 100 e 80 e 60 e 40 e 20 input level e dbfs linearity error e dbr tpc 41. linearity error, 44.1 khz:192 khz, 0 dbfs to e140 dbfs input, 200 hz tone e5 5 e4 e3 e2 e1 0 1 2 3 4 e 140 0 e 120 e 100 e 80 e 60 e 40 e 20 input level e dbfs linearity error e dbr tpc 42. linearity error, 192 khz:44:1 khz, 0 dbfs to e140 dbfs input, 200 hz tone
rev. a ad1896 e15e e180 e110 e175 e170 e165 e160 e155 e150 e145 e140 e135 e130 e125 e120 e115 e140 0 e120 e100 e80 e60 e40 e20 input level e dbfs dbr tpc 43. thd + n vs. input amplitude, 48 khz:44.1 khz, 1 khz tone e180 e110 e175 e170 e165 e160 e155 e150 e145 e140 e135 e130 e125 e120 e115 e140 0 e120 e100 e80 e60 e40 e20 input level e dbfs dbr tpc 44. thd + n vs. input amplitude, 96 khz:48 khz, 1 khz tone e180 e110 e175 e170 e165 e160 e155 e150 e145 e140 e135 e130 e125 e120 e115 e140 0 e120 e100 e80 e60 e40 e20 input level e dbfs dbr tpc 45. thd + n vs. input amplitude, 44.1 khz:48 khz, 1 khz tone e180 e110 e175 e170 e165 e160 e155 e150 e145 e140 e135 e130 e125 e120 e115 e140 0 e120 e100 e80 e60 e40 e20 input level e dbfs dbr tpc 46. thd + n vs. input amplitude, 48 khz:96 khz, 1 khz tone e180 e110 e175 e170 e165 e160 e155 e150 e145 e140 e135 e130 e125 e120 e115 e140 0 e120 e100 e80 e60 e40 e20 input level e dbfs dbr tpc 47. thd + n vs. input amplitude, 44.1 khz:192 khz, 1 khz tone e180 e110 e175 e170 e165 e160 e155 e150 e145 e140 e135 e130 e125 e120 e115 e140 0 e120 e100 e80 e60 e40 e20 input level e dbfs dbr tpc 48. thd + n vs. input amplitude, 192 khz:48 khz, 1 khz tone
rev. a ad1896 e16e e180 e110 e175 e170 e165 e160 e155 e150 e145 e140 e135 e130 e125 e120 e115 2.5 20.0 5.0 7.5 10.0 12.5 15.0 17.5 frequency e khz dbr tpc 49. thd + n vs. frequency input, 48 khz:44.1 khz, 0 dbfs e180 e110 e175 e170 e165 e160 e155 e150 e145 e140 e135 e130 e125 e120 e115 2.5 20.0 5.0 7.5 10.0 12.5 15.0 17.5 frequency e khz dbr tpc 50. thd + n vs. frequency input, 44.1 khz:48 khz, 0 dbfs e180 e110 e175 e170 e165 e160 e155 e150 e145 e140 e135 e130 e125 e120 e115 frequency e khz dbr 2.5 20.0 5.0 7.5 10.0 12.5 15.0 17.5 tpc 51. thd + n vs. frequency input, 48 khz:96 khz, 0 dbfs e180 e110 e175 e170 e165 e160 e155 e150 e145 e140 e135 e130 e125 e120 e115 frequency e khz dbr 2.5 20.0 5.0 7.5 10.0 12.5 15.0 17.5 tpc 52. thd + n vs. frequency input, 96 khz:48 khz, 0 dbfs
rev. a ad1896 e17e ( continued from page 1 ) t he dig ital servo loop measures the time difference between the input and output sample rates within 5 ps. this is necessary in order to select the correct polyphase filter coefficient. the digital servo loop has excellent jitter rejection for both input and output sample rates as well as the master clock. the jitter rejec- tion be gins at less than 1 hz. this requires a long settling time whenever reset t reset tet tet te tte t r t t t t t ss t
rev. a ad1896 e18e asrc functional overview theory of operation asynchronous sample rate conversion is converting data from one clock source at some sample rate to another clock source at the same or a different sample rate. the simplest approach to an asynchronous sample rate conversion is the use of a zero-order hold between the two samplers shown in figure 4. in an asyn- chronous system, t2 is never equal to t1 nor is the ratio between t2 and t1 rational. as a result, samples at f s_out will be repeated or dropped producing an error in the resampling process. the frequency domain shows the wide side lobes that result from this error when the sampling of f s_out is convolved with the attenuated images from the sin(x)/x nature of the zero-order hold. the images at f s_in , dc signal images, of the zero-order hold are infinitely attenuated. since the ratio of t2 to t1 is an irrational number, the error resulting from the resampling at f s_out can never be eliminated. however, the error can be sig- nificantly reduced through interpolation of the input data at f s_in . the ad1896 is conceptually interpolated by a factor of 2 20 . zero-order hold in out f s_in = 1/t1 f s_out = 1/t2 original signal sampled at f s_in sin(x)/x of zero-order hold spectrum of zero-order hold output spectrum of f s_out sampling f s_out 2 f s_out frequency response of f s_out convolved with zero-order hold spectrum figure 4. zero-order hold being used by f s_out to resample data from f s_in the conceptual high interpolation model interpolation of the input data by a factor of 2 20 involves placing (2 20 e 1) samples between each f s_in sample. figure 5 shows both the time domain and the frequency domain of interp olation by a factor of 2 20 . conceptually, interpolation by 2 20 would in volve the steps of zero-stuffing (2 20 e 1) number of sam ples b etween each f s_in sample and convolving this interpolated signal with a digital low-pass filter to suppress the images. in the t ime domain, it can be seen that f s_out selects the closest f s_in 2 20 s ample from the zero- order hold as opposed to the nearest f s_in sample in the case of no interpolation. this significantly reduces the resampling error. in out f s_in f s_out time domain of f s_in samples time domain output of the low-pass filter time domain of f s_out r esampling time domain of the zero-order hold output interpolate by n low-pass filter zero-order hold figure 5. time domain of the interpolation and resam pling in the frequency domain shown in figure 6, the interpolation expands the frequency axis of the zero-order hold. the images from the interpolation can be sufficiently attenuated by a good low-pass filter. the images from the zero-order hold are now pushed by a factor of 2 20 closer to the infinite attenuation point of the zero-order hold, which is f s_in 2 20 . the images at the zero-order hold are the determining factor for the fidelity of the o utput at f s_out . the w orst-case images can be com puted from the zero-order hold frequency response, maximum image = sin ( p f / f s_interp )/( p f / f s_interp ). f is the frequency of the worst-c ase image that would be 2 20 f s_in f s_in /2 , and f s_interp is f s_in 2 20 . t he following worst-case images would appear for f s_in = 192 khz: image at f s_interp e 96 khz = e125.1 db image at f s_interp + 96 khz = e125.1 db
rev. a ad1896 e19e frequency domain of samples at f s_in frequency domain of the interpolation frequency domain of f s_out r esampling frequency domain after resampling in out f s_in f s_out interpolate by n low-pass filter zero-order hold f s_in 2 20 f s_in 2 20 f s_in 2 20 f s_in sin(x)/x of zero-order hold fi gure 6. frequency domain of the interpolation and resampling hardware model the output rate of the low-pass filter of f igure 5 would be the interpolation rate, 2 20 192000 khz = 201.3 ghz. sampling at a rate of 201.3 ghz is clearly impractical, not to mention the number of taps required to ca lculate each interpolated sample. however, since interpolation by 2 20 involves zero-stuffing 2 20 e 1 sam ple s between each f s_in sample, most of the m ultiplies in th e low-pass fir filter are by zero. a further reduction can be realized by the fact that since only one interpolated sample is ta ken at the output at the f s_out rate, only one convolution needs to be performed per f s_out period instead of 2 20 convo- lutions. a 64-tap fir filter for each f s_out sam ple is sufficient to suppress the images caused by the interpolation. the difficulty with the above approach is that the correct inter- polated sample needs to be selected upon the a rrival of f s_out . since there are 2 20 possible convolutions per f s_out period, the arrival of the f s_out clock must be measured with an accuracy of 1/201.3 ghz = 4.96 ps. measuring the f s_out period with a clock of 201.3 ghz frequency is clearly impossible; instead, several coarse measurements of the f s_out clock period are made and averaged over time. a nother difficulty with the above approach is the number of coefficients required. since there are 2 20 possible convolutions with a 64-tap fir filter, there needs to be 2 20 polyphase coeffi- cients for each tap, which requires a total of 2 26 coefficients. to reduce the amount of coefficients in rom, the ad1896 stores a small subset of coefficients and performs a high order interpola- tion between the stored coefficients. so far the above approach works for the case of f s_out > f s_in . however, in the case when the output sample rate, f s_out , is less than the input sample rate, f s_in , the rom starting address, input data, and the length of the convolution must be scaled. as the input sam ple rate rises over the output sample rate, the antialiasing filter?s cutoff frequency has to be lowered because the nyquist frequency of the output samples is less than the nyquist frequ ency of the input samples. to move the cutoff frequency of the antialiasing filter, the coefficients are dynamically altered and the length of the convolution is increased by a factor of ( f s_in / f s_out ). this technique is supported by the fourier transform property that if f ( t ) is f ( w ), then f ( k t ) is f ( w / k ). thus, the range of decimation is simply limited by the size of the ram. the sample rate converter architecture the architecture of the sample rate converter is shown in figure 7. the sample rate converter?s fifo block adjusts the left and right input samples and stores them for the fir filter?s convolution cycle. the f s_in counter provides the write address to the fifo block and the ramp input to the digital servo loop. the rom stores the coefficients for the fir filter convo- lution and performs a high order interpolation between the stored co efficients. the sample rate ratio block measures the sample rate for d ynamically altering the rom coefficients and scaling of the fir filter length as well as the input data. the digital servo loop automatically tracks the f s_in and f s_out sample rates and provides the ram and rom start addresses for the start of the fir filter convolution. r ight data in l eft data in fifo rom a rom b rom c rom d high order interp digital servo loop fir filter sample rate ratio f s_in counter sa mple rate ratio e xternal ratio f s_in f s_out l/r data out figure 7. architecture of the sample rate converter the fifo receives the left and right input data and adjusts the amplitude of the data for both the soft muting of the sample rate converter and the scaling of the input data by the sample rate ratio before storing the samples in the ram. the input data is scaled by the sample rate ratio because as the fir filter length of the convolution increases, so does the amplitude of the convo lution output. to keep the output of the fir filter from saturating, the input data is scaled down by multiplying it by ( f s_out / f s_in ) when f s_out < f s_in . the fifo also scales the input data for muting and unmuting of the ad1896. the ram in the fifo is 512 words deep for both left and right ch annels. an offset to the write address provided by the f s_in co unter is added to prevent the ram read pointer from ever overlapping the write address. the offset is selectable by the g rpdlys, group delay select, signal. a small offset, 16, is a dded to the write address pointer when grpdlys is high, and a large offset, 64, is added to the write address pointer when grpdlys is low. increasing the offset of the write address pointer is useful for applications when small changes in the sample rate ratio between f s_in and f s_out are expected. the maximum deci- mation rate can be calculated from the ram word depth and grpdlys as (512 e 16)/64 taps = 7.75 for sh ort group delay and (512 e 64)/64 taps = 7 for long group delay.
rev. a ad1896 e20e the digital servo loop is essentially a ramp filter that provides the initial pointer to the address in ram and rom for the start of the fir convolution. the ram pointer is the integer output of the ramp filter while the rom is the fractional part. the digital servo loop must be able to provide excellent rejection of jitter on the f s_in and f s_out clocks as well as measure the arrival of the f s_out clock within 4.97 ps. the digital servo loop will also divide the fractional part of the ramp output by the ratio of f s_in /f s_out for the case when f s_in > f s_out , to dynamically alter the rom coefficients. the digital servo loop is implemented with a multirate filter. to s ettle the digital servo loop filter quicker upon start-up or a change in the sample rate, a fast mode was added to the filter. when the digital servo loop starts up or the sample rate is changed, the di gital servo loop kicks into fast mode to adjust and settle on the new sample rate. upon sensing the digital servo loop settling down to some reasonable value, the digital servo loop will kick into normal or slow mode. during fast mode th e mute_out signal of the sample rate converter is asserted to l et the user know that they should mute the sample rate con verter to avoid any clicks or pops. the frequency response of the digital servo loop for fast mode and slow mode are shown in figure 8. the fir filter is a 64-tap filter in the case of f s_out u f s_in and is (f s_in /f s_out ) 64 taps for the case when f s_in > f s_out . the fir filter performs its convolution by loading in the starting address of the ram address pointer and the rom address pointer from the digital servo loop at the start of the f s_out period. the fir filter then steps through the ram by d ecrementing its address by 1 for each tap, and the rom pointer in crements its address by the (f s_out /f s_in ) 2 20 ratio for f s_in > f s_out or 2 20 for f s_out u f s_in . once the rom address rolls over, the con- volution is completed. the convolution is performed for both the left and right channels, and the multiply accumulate circuit used for the convolution is shared between the channels. the f s_in /f s_out sample rate ratio circuit is used to dynamically al ter the coefficients in the rom for the case w hen f s_in > f s_out . the ratio is calculated by comparing the output of an f s _out counter to the output of an f s_in counter. if f s_out > f s_in , the ratio is held at one. if f s_in > f s_out , the sam ple rate ratio is updated if it is different by more than two f s_out periods from the previous f s_out to f s_in com parison. this is done to provide some hysteresis to prevent the filter length from oscillat- ing and causing distortion. 10 0 e10 e20 e30 e40 e50 e60 e70 e80 e90 e100 e110 e120 e130 e140 e150 e160 e170 e180 e190 e200 e210 e220 0.01 0.1 1 10 100 1e3 1e4 1e5 frequency e hz slow mode fa st mode figure 8. frequency response of the digital servo loop. f s_in is the x-axis, f s_out = 192 khz, master clock frequency is 30 mhz.
rev. a ad1896 e21e however, the hysteresis of the f s_out /f s_in ratio circuit can cause phase mismatching between two ad1896s operating with the same input clock and the same output clock. since the hyster- esis requires a difference of more than two f s_out periods for the f s_out /f s_in ratio to be updated, two ad1896s may have dif- ferences in their ratios from 0 to 4 f s_out period counts. the f s_out /f s_in ratio adjusts the filter length of the ad1896, which corresponds directly with the group delay. thus, the magnitude in the phase difference will depend upon the resolution of the f s_out a nd f s_in counters. the greater the resolution of the counters, the smaller the phase differ ence error will be. the f s_in and f s_out counters of the ad1896 have three bits of extra resolution over the ad1890, which reduces the phase mismatch error by a factor of 8. however, an additional feature was added to the ad1896 to eliminate the phase mismatching completely. one ad1896 can set the f s_out /f s_in ratio of o ther ad1896s by transmitting its f s_out /f s_in ratio through the serial output port. operating features reset reset reset reset reset tet reset sr t reset reset reset reset sr t re re rere t rst t rs rers s s s s st s s s s st st s rs rs s s st s s s s st st s te tete te te r tte r te r resetr rtett tet tettet te t
rev. a ad1896 ?2 ad1896 mclk_i mclk_o c1 c2 r figure 9a. fundamental-mode circuit configuration ad1896 mclk_i mclk_o c1 c2 r 1nf l1 figure 9b. third-overtone circuit configuration there are, of course, maximum and minimum operating fre- quencies for the ad1896 master clock. the maximum master clock f requency at which the ad1896 is guaranteed to operate is 30 mhz. a frequency of 30 mhz is more than sufficient to sample rate convert sampling frequencies of 192 khz + 12%. the minimum required frequency for the master clock generation for the ad1896 depends upon the input and output sample rates. the master clock has to be at least 138 times greater than th e maximum input or output sample rate. serial data ports?ata format the serial data input port mode is set by the logic levels on the smode_in_0/smode_in_1/smode_in_2 pins. the serial data input port modes available are left justified, i 2 s, and right justified (rj), 16, 18, 20, or 24 bits as defined in table i. table i. serial data input port mode smode_in_[0:2] interface format 21 0 00 0 left justified 00 1i 2 s 01 0u ndefined 01 1u ndefined 10 0r ight justified, 16 bits 10 1r ight justified, 18 bits 11 0r ight justified, 20 bits 11 1r ight justified, 24 bits the serial data output port mode is set by the logic levels on the smode_out_0/smode_out_1 and wlngth_out_0/ wlngth_out_1 pins. the serial mode can be changed to left justified, i 2 s, right justified, or tdm as defined in the fol- lowing table. the output word width can be set by using the wlngth_out_0/wlngth_out_1 pins as shown in table iii. when the output word width is less than 24 bits, dither is added to the truncated bits. the right justified serial data out mode assumes 64 sclk_o cycles per frame, divided evenly for left and right. please note that 8 bits of each 32-bit subframe are used for transmitting matched-p hase mode data. please refer to figure 14. the ad1896 also supports 16-bit, 32-clock packed input and output serial data in lj and i 2 s format. table ii. serial data output port mode smode_out_[0:1] interface format 10 00 left justified (lj) 01i 2 s 10 tdm mode 11 right justified (rj) table iii. word width wlngth_out_[0:1] word width 10 00 24 bits 01 20 bits 10 18 bits 11 16 bits the following timing diagrams show the serial mode formats.
rev. a ad1896 ?3 tdm mode application in tdm mode, several ad1896s can be daisy-chained together and connected to the serial input port of a sharc dsp. the ad1896 contains a 64-bit parallel load shift register. when the lrclk_o pulse arrives, each ad1896 parallel loads its left and right data into the 64-bit shift register. the input to the shift register is connected to tdm_in, while the output is connected to sdata_o. by connecting the sdata_o to the tdm_in of the next ad1896, a large shift register is created, which is clocked by sclk_o. the number of ad1896s that can be daisy-chained together is limited by the maximum frequency of sclk_o, which is about 25 mhz. for example, if the output sample rate, f s , is 48 khz, up to eight ad1896s could be connected since 512 f s is less than 25 mhz. in master/tdm mode, the number of ad1896s that can be daisy-chained is fixed to four. msb 1/f s tdm mode ?16 bits to 24 bits per channel left channel right channel left channel left channel right channel right channel msb lsb lsb lsb lsb lsb lsb msb lsb msb lsb lrclk sclk sdata lrclk sclk sdata lrclk sclk sdata lrclk sclk sdata notes 1 lrclk normally operates at associative input or output sample frequency (f s ). 2 sclk frequency is normally 64 figure 10. input/output serial data formats ad1896 tdm_in sdata_o lrclk_o p hase-master m1 m2 m0 0 0 0 sclk_o sharc dsp dr0 rfs0 rclk0 slave-1 slave-n st andard mode ma tched-phase mode ad1896 tdm_in sdata_o lrclk_o m1 m2 m0 0 0 0 0 1 0 sclk_o ad1896 tdm_in sdata_o lrclk_o m1 m2 m0 sclk_o 0 0 0 0 1 0 sclk lrclk figure 11. daisy-chain configuration for tdm mode (all ad1896s being clock-slaves)
rev. a ad1896 e24e serial data port master clock modes either of the ad1896 serial ports can be configured as a master serial data port. however, only one serial port can be a master while the other has to be a slave. in master mode, the ad1896 requires a 256 f s , 512 f s , or 768 f s master clock (mclk_i). for a maximum master clock frequency of 30 mhz, the maxi- mum sample rate is limited to 96 khz. in slave mode, sample rates up to 192 khz can be handled. when either of the serial ports is operated in master mode, the master clock is divided down to derive the associated left/ right subframe clock (lrclk) and serial bit clock (sclk). the m aster clock frequency can be selected for 256, 512, or 768 times the input or output sample rate. both the input and out- put serial ports will support master mode lrclk and sclk ge neration for all serial modes, left justified, i 2 s, right justified, and tdm for the output serial port. table iv. serial data port clock modes mmode_0/ mmode_1/ mmode_2 interface format 210 000b oth serial ports are in slave mode. 001 output serial port is master with 768 f s_out . 010o utput serial port is master with 512 f s_out . 011 output serial port is master with 256 f s_out . 100m atched-phase mode 101 input serial port is master with 768 f s_in . 110 input serial port is master with 512 f s_in . 111 input serial port is master with 256 f s_in . ad1896 tdm_in sdata_o lrclk_o cl ock-master and p hase-master m1 m2 m0 1 0 1 sclk_o sharc dsp dr0 rfs0 rclk0 slave-1 slav e -n st andard mode mat ched-phase mode ad1896 tdm_in sdata_o lrclk_o m1 m2 m0 0 0 0 0 1 0 sclk_o ad1896 tdm_in sdata_o lrclk_o m1 m2 m0 sclk_o 0 0 0 0 1 0 figure 12. daisy-chain configuration for tdm mode (first ad1896 being clock-master) matched-phase mode (non-tdm mode) application ad1896 slave1 m2 m1 m0 ad1896 tdm_in sdata_i lrclk_i sclk_i mclk reset sdata_o lrclk_o sclk_o phase-master m2 m1 m0 ad1896 slave2 m2 m1 m0 ad1896 slaven m2 m1 m0 0 0 0 1 0 0 1 0 0 1 0 0 lrclk i (f s_in ) sclk i lrclk o (f s_out ) sclk o (64f s_out ) mclk reset sdom sdo1 sdo2 sdon tdm_in sdata_i lrclk_i sclk_i mclk reset sdata_o lrclk_o sclk_o tdm_in sdata_i lrclk_i sclk_i mclk reset sdata_o lrclk_o sclk_o tdm_in sdata_i lrclk_i sclk_i mclk reset sdata_o lrclk_o sclk_o figure 13. typical configuration for matched-phase mode operation
rev. a ad1896 e25e matched-phase mode the matched-phase mode is the mode discussed in the theory of operation section that eliminates the phase mismatch between multiple ad1896s. the master ad1896 device transmits its f s_out /f s_in ratio through the sdata_o pin to the slave a d1896?s tdm_in pins. the slave ad1896s receive the transmitted f s_out /f s_in ratio and use the transmitted f s_out / f s_in ratio instead of their own internally derived f s_out /f s_in ratio. the master device can have both its serial ports in slave mo de as depicted or either one in master mode. the slave ad1896s must have their mmode_2, mmode_1, and mm ode_0 pins set to 100, respectively. lrclk_i and lrclk_o may be asynchronous with respect to each other in this mode. another requirement of the matched- phase mode is t hat there must be 32 sclk_o cycles per subframe. the ad1896 will support the matched-phase mode for all serial output data formats, left justified, i 2 s, right justified, and tdm. in the case of tdm, the ad1896 shown in the tdm mode operation figure with its tdm _in tied to ground would be co nfigured as the master, while the rest of the ad1896s in the c hain would be configured as slaves with their mmode_2, mmode_1, and mmode_0 pins set to 100, respectively. p lease note that in the left-justified, i 2 s, and tdm modes, th e lower eight b its of each channel subframe are used to transmit the matched-phase data. in right-justified mode, the upper eight bits are used to transmit the matched-phase data. this is shown in figures 14a and 14b. bypass mode when the bypass pin is asserted high, the input data bypasses the sample rate converter and is sent directly to the serial output p ort. dithering of the output data when the word length is set to less than 24 bits is disabled. this mode is ideal when the input and output sample rates are the same and lrclk_i and lrclk_o are synchronous with respect to each other. this mode can also be used for passing through non-audio data since no processing is performed on the input data in this mode. a udio data left channel, 24 bits ma tched-phase data, 8 bits a udio data right channel, 24 bits ma tched-phase data, 8 bits figure 14a. matched-phase data transmission (left-justified, i 2 s, and tdm mode) a udio data left channel, 16 bits e 24 bits a udio data right channel, 16 bits e 24 bits ma tched-phase data, 8 bits ma tched-phase data, 8 bits figure 14b. matched-phase data transmission (right-justified mode)
rev. a ad1896 ?6 outline dimensions 28-lead shrink small outline package [ssop] (rs-28) dimensions shown in millimeters 0.25 0.09 0.95 0.75 0.55 8 4 0 0.05 min 1.85 1.75 1.65 2.00 max 0.38 0.22 seating plane 0.65 bsc 0.10 coplanarity 28 15 14 1 10.50 10.20 9.90 5.60 5.30 5.00 8.20 7.80 7.40 compliant to jedec standards mo-150ah
rev. a ad1896 ?7 revision history location page 3/03?ata sheet changed from rev. 0 to rev. a. edits to digital performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 edits to digital timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 edits to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 edits to reset and power-down section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 edits to figures 9a and 9b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 edits to serial data ports?ata format section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 edits to figure 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 update to outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
?8 c02403?3/03(a) printed in u.s.a.

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