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NT3883 dot matrix lcd 80-channel driver 1 v2.1 november, 1999 features ? provides 80-channel lcd driver ? internal serial to parallel conversion circuits: 40-bit bi-direction shift register 2 80-bit latch 1 80-bit 4-level driver 1 ? logic circuit supply voltage range: 4.5v - 5.5v ? lcd driving voltage range (v dd - v ee ): 3.5v to 11v ? applicable lcd duty cycle: 1/2 to 1/16 ? interfaces with a nt3881b/c/d lcd controller ? lcd bias voltage can be supplied externally ? available in 100-pin qfp and in chip form general description the NT3883 is a dot matrix lcd 80-channel driver fabricated by low power cmos technology. this ic consists of two 40-bit bi-directional shift registers, 80-bit latch and 80-bit 4-level lcd driver. the NT3883 converts serial data that are received from the lcd controller, such as nt3881b/c/d, to parallel data and outputs lcd driving waveforms to drive lcd. expansion of character-type liquid crystal display can be easily obtained according to the number and structure of characters. pin configuration 100 s 3 1 93 99 92 86 83 81 87 84 98 82 94 96 85 90 89 88 97 91 95 s 7 1 s 7 2 s 7 3 s 7 4 s 7 5 s 7 6 s 7 7 s 7 8 s 7 9 s 8 0 s 4 0 s 3 9 s 3 8 s 3 7 s 3 6 s 3 5 s 3 4 s 3 3 s 3 2 NT3883f s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s1 s2 1 2 18 8 7 11 9 5 6 3 4 10 17 15 16 14 13 12 20 19 27 28 29 30 25 24 23 22 21 26 s58 s59 s60 s61 s62 s63 s64 s65 s66 s67 s68 s69 s70 s43 s44 s45 s46 s47 s48 s49 s50 s51 s52 s53 s54 s55 s56 s57 s41 s42 80 79 63 73 74 70 72 76 75 78 77 71 64 66 65 67 68 69 61 62 54 53 52 51 56 57 58 59 60 55 31 38 32 39 45 48 50 44 47 33 49 37 35 46 41 42 43 34 40 36 v e e n c n c m d r 2 d l 2 d r 1 d l 1 c l 2 n c n c n c s l 2 s l 1 c l 1 g n d v 2 v 3 v d d n c
NT3883 2 pad configuration 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 95 31 33 34 35 36 37 38 39 43 44 45 46 47 48 51 52 94 93 92 91 90 89 88 99 98 97 96 87 86 85 84 83 82 NT3883h s31 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s2 s3 s4 s5 s6 s7 s12 s13 s14 s15 s16 s17 s8 s9 s10 s11 s1 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 s 3 2 s 3 9 s 3 8 s 3 7 s 3 6 s 3 5 s 3 4 s 3 3 s 4 0 s 7 4 s 7 5 s 7 6 s 7 7 s 7 8 s 7 9 s 8 0 s 7 2 s 7 3 m d r 2 d l 2 d r 1 d l 1 c l 2 s l 2 s l 1 g l 1 g n d v 2 v 3 v d d v e e s71 s58 s59 s60 s61 s62 s63 s64 s65 s66 s67 s68 s69 s70 s52 s53 s54 s55 s56 s57 s51 s47 s48 s49 s50 s46 s42 s43 s44 s45 s41
NT3883 3 block diagram 80-bit 4-level lcd drivers 80-bit latch first 40-bit shift re g ister second 40-bit shift register s1 s2 s39 s40 s41 s42 s79 s80 dr2 gnd dl2 dr1 cl2 dl2 cl1 m v ee v 3 v 2 v dd sl1 sl2
NT3883 4 absolute maximum ratings* power supply voltage (v dd -gnd) . . . . . . -0.3v to 7.0v power supply voltage (v dd -v ee ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v dd - 13.5v to v dd + 0.3v input voltage . . . . . . . . . . . . . . -0.3v to v dd + 0.3v operating temperature . . . . . . . . . . -20 q c to + 75 q c storage temperature . . . . . . . . . . . . . -55 q c to + 125 q c *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied and exposure to the absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics (v dd = 5.0v, gnd = 0v, v ee = 0v, t a = 25 q c) parameter symbol terminal min. typ. max. unit conditions input voltage v ih 0.7 v dd - v dd v v il cl1, cl2, dl1, dl2 *1 0- 0.3 v dd v output voltage v oh dr1, dr2 *1 v dd - 0.4 --v i oh = -0.4ma v ol --0.4v i ol = +0.4ma vi - sj voltage v d1 --1.1v i on = 0.1ma for one of sj descending v d2 *2 --1.5v i on = 0.05ma for each of sj input leakage current i il cl1, cl2 dl1, dl2*1 -5 - 5 p a v in = 0 or v dd vi leakage current i vl v 2 , v 3 , v ee -10 - 10 p a s1 to s80 open power supply current i dd *3 - - 500 p a f cl1 = 1khz f cl2 = 1mhz note *1: sl1 and sl2 determine the input or output of dl1, dl2, dr1 and dr2 and the configuration is as follows. terminal sl1 = high sl1 = low sl2 = high sl2 = low dl1 output input - - dr1 input output - - dl2 - - output input dr2 - - input output *2: v i C s j (v i = v dd , v 2 , v 3 , v ee ; j = 1 to 80) equivalent circuit (for reference) *3: input/output current is excluded. when the input is at the intermediate level with cmos, some excessive v i 1kmax. 10kmax. power switch data swtich s j current will flow thr ough the input circuit to power supply. to avoid this, the input level must be fixed at high or low state.
NT3883 5 ac characteristics (v dd = 5.0v, gnd = 0v, v ee = 0v, t a = 25 q c) parameter symbol terminal min. typ. max. unit data shift frequency f cl2 cl2 - - 400 khz high t cwh cl1, cl2 800 - - ns clock width low t cwl cl2 800 - - ns data hold time t dh dl1~2, dr1~2 300 - - ns data set-up time t sud dl1~2, dr1~2 300 - - ns clock set-up time(cl2 ( cl1) t suc1 cl1, cl2 500 - - ns clock set-up time(cl1 ( cl2) t suc2 cl1, cl2 500 - - ns clock rise/fall time t cl cl1, cl2 - - 200 ns data delay time t pd - - - 500 ns timing waveforms t cl v ih v il t cl t cwh t cwl t cl t dh t sud t suc1 t pd t suc2 t suc2 t cwh t cl v oh v ol cl2 dl1, dl2 dr1, dr2 cl1
NT3883 6 pin and pad descriptions pin no. pad no. designation i/o external connection description 1~30, 51~100 1~30, 51~100 s1~s30, s80~s31 o lcd panel segment signal output pins 33 33 v dd p power supply power for logic circuits 36 36 gnd p power supply 0v 37 37 cl1 i controller clock to latch serial data 38 38 sl1 i mpu shift left control for 1st 40-bit shift register (see note*4) 39 39 sl2 i mpu shift left control for 1st 40-bit shift register (see note*4) 43 43 cl2 i controller clock to shift serial data 44 44 dl1 i/o controller or nt3882a/nt3 883 data input/output of 1st 40-bit shift register (see note*4) 45 45 dr1 i/o controller or nt3882a/nt3 883 data input/output of 1st 40-bit shift register (see note*4) 46 46 dl2 i/o controller or nt3882a/nt3 883 data input/output of 2nd 40-bit shift register (see note*4) 47 47 dr2 i/o controller or nt3882a/nt3 883 data input/output of 2nd 40-bit shift register (see note*4) 48 48 m i controller alternate signal for lcd drivers 31, 34, 35 31, 34, 35 v ee , v 3 , v 2 p power supply power for lcd drivers 32, 40, 41, 42, 49,50 - nc - - no connection note *4: relation of sl1, sl2, dl1, dr1, dl2 and dr2 sl1 sl2 shift direction dl1 dr1 dl2 dr2 1(high) - left(s40 to s1) output input - - 0(low) - right(s1 to s40) input output - - - 1(high) left(s80 to s41) - - output input - 0(low) right(s41 to s80) - - input output
NT3883 7 functional d escription NT3883 is a dot matrix lcd segment driver lsi. it operates with the controller, such as nt3881b/c/d, and/or another segment driver lsi nt3882a/3883. NT3883 receives serial data from the controller or another NT3883, converts it to parallel data and then supplies the lcd driving waveforms to the lcd panel. 1. cl1 this signal is used for latching the shift register contents. when cl1 is set at high, the shift register contents are transferred to the 80-bit 4level lcd driver. when cl1 is set at low, the last display output data (s1 to s80) is held. 2. cl2 clock pulse inputs for the two 40-bit shift registers. the data is shifted to an 80-bit latch at the falling edge of cl2. the clock signal cl2 must be active when operating to refresh shift registers' contents. 3. dl1 data input/output of the 1 st - 40 th register. when sl1 is connected to gnd or open, the data from lcd controller is fed into the 1 st - 40 th register through dl1 serially. if sl1 is connected to v dd , the dl1 becomes the output of the 1 st - 40 th register. 4. dr1 data input/output of the 1 st - 40 th register. when sl1 is connected to gnd, the 20 th bit of the 1 st - 40 th register output from dr1. by connecting dr1 to dl2, two 40-bit shift registers cascaded to one 80-bit shift register. if sl1 is connected to v dd , the dr1 becomes the input of the 1 st - 40 th register, in this case, the data may come from dl2. 5. dl2 data input/output of the 41 st - 80 th register. when sl2 is connected to gnd, the data from lcd controller is fed into the 41 st - 80 th register through dl2 serially. if sl2 is connected to v dd , the dl2 becomes the output of the 41 st - 80 th register. 6. dr2 data input/output of the 41 st - 80 th register. when sl2 is connected to gnd, the 80 th bit of the 41 st - 80 th register output from dr2. by connecting dr2 to dl1 of next nt3882a/3883, the cascade structure is obtained to drive a wider lcd panel. if sl2 is connected to v dd , the dr2 becomes the input of the 41 st - 80 th register, in this case, the data may come from the next nt3882a/3883. 7. sl1 the shift direction of s1 to s40, i.e. 1 st to 40 th shift register, is selected by sl1. the detail function description is listed in note*4 of page5. 8. sl2 the shift direction of s41 to s80, i.e. 41 st to 80 th shift register, is selected by sl2. the detail function description is listed in note*4 of page5. 9. s1 to s80 lcd driver output pins. these 80 bits represent the 80 data bits in the 80-bit latch and one of v dd , v 2 , v 3 and v ee is selected as a lcd driving voltage source according to the combination of latched data level and the alternate signal (m). the truth table is listed as follows: latched data m output level of s1 to s80 1(high) v ee 1(high) (selected) 0(low) v dd 1(high) v 3 0(low) (non-selected) 0(low) v 2
NT3883 8 application circuit (for reference only) 20 chars x 4 lines lcd panel nt3881d NT3883 NT3883 c1 - c16 s1 - s40 d cl2 cl1 m v dd gnd v 1 v 2 v 3 v 4 v 5 dl1 cl2 cl1 m v dd gnd v 2 v 3 v ee dr1 dl2 dr2 s1 - s80 s1 - s80 dr2 dl2 dr1 v ee v 3 v 2 gnd v dd m cl1 cl2 dl1 r r r r r vr c c c c c gnd or other negative voltage
NT3883 9 bonding diagram 95 31 33 34 35 36 37 38 39 43 44 45 46 47 48 s71 s58 s59 s60 s61 s62 s63 s64 s65 s66 s67 s68 s69 s70 s52 s53 s54 s55 s56 s57 s51 s47 s48 s49 s50 s46 s42 s43 s44 s45 94 93 92 91 90 89 88 99 98 97 96 87 86 85 84 83 82 s41 NT3883h y x (0,0) s 3 2 s 3 9 s 3 8 s 3 7 s 3 6 s 3 5 s 3 4 s 3 3 s 4 0 s 7 4 s 7 5 s 7 6 s 7 7 s 7 8 s 7 9 s 8 0 s 7 2 s 7 3 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 51 52 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 3940 p m 2590 p m m d r 2 d l 2 d r 1 d l 1 c l 2 s l 2 s l 1 g l 1 g n d v 2 v 3 v d d v e e s31 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s2 s3 s4 s5 s6 s7 s12 s13 s14 s15 s16 s17 s8 s9 s10 s11 s1 * connecting ic substrate to v dd or keeping floating is recommended. * pad window area 100 p m 100 p m.
NT3883 10 bonding dimensions unit: p m pad no. designation x y pad no. designation x y 1 s30 -1194 1677 54 s44 1195 -1442 2 s29 -1194 1557 55 s45 1195 -1311 3 s28 -1194 1437 56 s46 1195 -1202 4 s27 -1194 1317 57 s47 1195 -1082 5 s26 -1194 1197 58 s48 1195 -962 6 s25 -1194 1077 59 s49 1195 -842 7 s24 -1194 957 60 s50 1195 -722 8 s23 -1194 837 61 s51 1195 -602 9 s22 -1194 717 62 s52 1195 -482 10 s21 -1194 597 63 s53 1195 -362 11 s20 -1194 477 64 s54 1195 -242 12 s19 -1194 357 65 s55 1195 -122 13 s18 -1194 237 66 s56 1195 -2 14 s17 -1194 117 67 s57 1195 117 15 s16 -1194 -2 68 s58 1195 237 16 s15 -1194 -122 69 s59 1195 357 17 s14 -1194 -242 70 s60 1195 477 18 s13 -1194 -362 71 s61 1195 597 19 s12 -1194 -482 72 s62 1195 717 20 s11 -1194 -602 73 s63 1195 837 21 s10 -1194 -722 74 s64 1195 957 22 s9 -1194 -842 75 s65 1195 1077 23 s8 -1194 -962 76 s66 1195 1197 24 s7 -1194 -1082 77 s67 1195 1317 25 s6 -1194 -1202 78 s68 1195 1437 26 s5 -1194 -1322 79 s69 1195 1557 27 s4 -1194 -1442 80 s70 1195 1677 28 s3 -1194 -1562 81 s71 1185 1811 29 s2 -1194 -1682 82 s72 995 1821 30 s1 -1184 -1812 83 s73 875 1821 31 vee -945 -1822 84 s74 755 1821 33 vdd -807 -1822 85 s75 635 1821 34 v3 -670 -1822 86 s76 515 1821 35 v2 -520 -1822 87 s77 395 1821 36 gnd -353 -1822 88 s78 275 1821 37 cl1 -204 -1822 89 s79 155 1821 38 sl1 -54 -1822 90 s80 35 1821 39 sl2 95 -1822 91 s40 -84 1821 43 cl2 245 -1822 92 s39 -204 1821 44 dl1 395 -1822 93 s38 -324 1821 45 dr1 545 -1822 94 s37 -444 1821 46 dl2 695 -1822 95 s36 -564 1821 47 dr2 845 -1822 96 s35 -684 1821 48 m 995 -1822 97 s34 -805 1821 51 s41 1185 -1812 98 s33 -925 1821 52 s42 1195 -1682 99 s32 -1045 1821 53 s43 1195 -1562 100 s31 -1184 1811
NT3883 11 ordering information part no. package NT3883h chip form NT3883f 100l qfp
NT3883 12 package information qfp 100l outline dimensions unit: inches/mm a 1 a 2 a seating plane 1 24 b 25 40 41 64 65 80 e e g e g d see detail f detail f d h d h e d y l g d ~ ~ ~ l 1 c symbol dimensions in inches dimensions in mm a 0.130 max. 3.30 max. a 1 0.004 min. 0.10 min. a 2 0.1120.005 2.850.13 b 0.014 +0.004 0.35 +0.10 -0.002 -0.05 c 0.006 +0.004 0.15 +0.10 -0.002 -0.05 d 0.5510.005 14.000.13 e 0.7870.005 20.000.13 e 0.0310.006 0.800.15 g d 0.693 nom. 17.60 nom. g e 0.929 nom. 23.60 nom. h d 0.7400.012 18.800.31 h e 0.9760.012 24.790.31 l 0.0470.008 1.190.20 l 1 0.0950.008 2.410.20 y 0.006 max. 0.15 max. t 0 q ~ 12 q 0 q ~ 12 q notes: 1. dimensions d & e do not include resin fins. 2. dimensions g d & g e are for pc board surface mount pad pitch design reference only

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