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10511 sy 20100330-s00005 no.1887-1/12 LE24CB1283 overview the LE24CB1283 (hereinafter referred to as ?this device?) is two-wire serial interface ee prom (electrically erasable and programmable rom). this device realizes high speed an d a high level reliability by sanyo?s high performance cmos eeprom technology. this device is compatible with i 2 c memory protocol, therefore it is best suited for application that requires re-writable nonvolatile parameter memory. functions ? capacity : 128k bits (16k 8 bits) ? single supply voltage : 2.7v to 5.5v. ? interface : two wire serial interface (i 2 c bus *) ? operating clock frequency : 400khz ? low power consumption : standby: 2 a (max), active(read): 1ma (max.) ? automatic page write mode: 64 bytes ? read mode : sequential read and random read ? erase/write cycles : 10 6 cycles ? data retention : 20 years ? high reliability : adopts sanyo?s proprietary sy mmetric memory array configuration (usp6947325) noise filters connected to scl and sda pins incorporates a feature to prohibit write operations under low voltage conditions. ? package : LE24CB1283m mfp8 (225mil) ordering number : ena1887 cmos ic two wire serial interface eeprom (128k eeprom) * : i 2 c bus is a trademark of philips corporation. * this product is licensed from silicon storage te chnology, inc. (usa), and manufactured and sold by sanyo semiconductor co., ltd. specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
LE24CB1283 no.1887-2/12 package dimensions unit:mm (typ) 3032d [LE24CB1283m] pin assignment pin descriptions pin.1 s0 slave device address 0 pin.2 s1 slave device address 1 pin.3 s2 slave device address 2 pin.4 gnd ground pin.5 sda serial data input/output pin.6 scl serial clock input pin.7 wp write protect pin.8 v dd power supply block diagram sanyo : mfp8(225mil) 14 85 5.0 0.63 6.4 0.15 0.35 1.27 (0.65) 4.4 (1.5) 1.7max 0.1 s0 s1 s2 gnd scl sda 1 2 3 4 5 6 7 8 v dd wp eeprom array high voltage generator y decoder & sense amp serial-parallel converter x decoder address generator serial controller condition detector write controller wp i/o buffer input buffer s0 s1 s2 scl sda
LE24CB1283 no.1887-3/12 specifications absolute maximum ratings parameter symbol conditions ratings unit supply voltage -0.5 to +6.5 v dc input voltage -0.5 to +5.5 v over-shoot voltage below 20ns -1.0 to +6.5 v storage temperature tstg -65 to +150 q c operating conditions parameter symbol conditions ratings unit operating supply voltage 2.7 to 5.5 v operating temperature -40 to +85 q c dc electrical characteristics parameter symbol conditions typ. min. max unit power supply current at reading i cc 1 f=400khz, v dd =v dd max 1 ma power supply current at writing i cc 2 f=400khz, t wc =5ms, v dd =v dd max 5ma v in =v dd or gnd, (v dd = 2.7v) 2 p a cmos standby current i sb v in =v dd or gnd, (v dd = 5.5v) 5 p a input leakage current i li v in =gnd to v dd , v dd =v dd max -2.0 +2.0 p a output leakage current i lo v in =gnd to v dd , v dd =v dd max -2.0 +2.0 p a input low voltage v il v dd *0.3 v input high voltage v ih v dd *0.7 v i ol =0.7ma, v dd 1=2.7v 0.2 v i ol =2.0ma, v dd 1=2.7v 0.4 v output low voltage v ol i ol =3.0ma, v dd 1=5.5v 0.4 v capacitance /ta=25 q c, f=1.0mhz parameter symbol conditions min typ max unit in/output capacitance c i/o v i/o =0v (sda) 10 pf input capacitance c i v in =0v 10 pf note: this parameter is sampled and not 100% tested. ac electric characteristics input pulse level 0.1*v dd to 0.9*v dd input rise / fall time 20ns input / output timing level 0.5*v dd output load 50pf + pull up resistor 3.0k ? r=3.0k sda v dd c=50pf
LE24CB1283 no.1887-4/12 fast mode spec parameter symbol min typ max unit scl clock frequency f scls 0 400 khz scl pulse with low t low 1200 ns scl pulse with high t high 600 ns access time t aa 100 900 ns data output hold time t dh 100 ns start condition setup time t su.sta 600 ns start condition hold time t hd.sta 600 ns data in setup time t su.dat 100 ns data in hold time t hd.dat 0 ns stop condition setup time t su.sto 600 ns scl, sda rise time t r 300 ns scl, sda fall time t f 300 ns bus free time for next mode t buf 1200 ns noise suppression time t sp 100 ns write time t wc 5 ms standard mode spec parameter symbol min typ max unit scl clock frequency f scls 0 100 khz scl pulse with low t low 4700 ns scl pulse with high t high 4000 ns access time t aa 100 3500 ns data output hold time t dh 100 ns start condition setup time t su.sta 4700 ns start condition hold time t hd.sta 4000 ns data in setup time t su.dat 250 ns data in hold time t hd.dat 0 ns stop condition setup time t su.sto 4000 ns scl, sda rise time t r 1000 ns scl, sda fall time t f 300 ns bus free time for next mode t buf 4700 ns noise suppression time t sp 100 ns write time t wc 5 ms
LE24CB1283 no.1887-5/12 bus timing write timing pin functions scl (serial clock) the scl signal is used to control serial input data timing. the scl is used to latch input data synchronously at the rising edge and read output data synchronously at the falling edge. sda (serial input/output data) the sda pin is bidirectional for serial data transfer. it is an open-drain structure that needs to be pulled up by resistor. wp (write protect) when the wp signal is high, write protections are enabled. when this signal is low, write operation for all memory arrays are allowed. the read operation is always activated irrespective of the wp pin status. s0/s1/s2 (slave address) when many devices are connected on the same bus, the s0/s1/ s2 are used to select the de vice. the s0/s1/s2 must be tied to v dd or gnd. scl sda d0 t wc write data acknowledge stop condition start condition scl sda/in sda/out t f t su.sta t hd.sta t aa t high t low t hd.dat t hd.sta t dh t r t su.sto t sp t buf t sp
LE24CB1283 no.1887-6/12 functional description the device supports the i 2 c protocol. any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to a receiver. the device that cont rols the data transfer is kn own as the bus master, and the other as the slave device. 1. start condition a start condition is needs to start the ee prom operation, it is to set falling edge of the sda while the scl is stable in the high status. 2. stop condition a start condition is identified by rising edge of the sda signal while the scl is stable in the high status. the device becomes the standby mode from a read operation by a stop condition. in a write sequence, a stop condition is trigger to start the internal write cycle. after the inte rnally write cycle time which is specified as t wc , the device enters a standby mode. 3. data input during data input, the device latches the sda on the rising edge of the scl. for correct the operation, the sda must be stable during the rising edge of the scl. 4. acknowledge the acknowledge bit is used to indicate a successful byte data transfer. the receiver sends a zero to acknowledge that it has received each word (device code, slave address etc) fr om the transmitter. scl sda t su.sta t hd.sta t su.sto start condition stop condition t aa t dh 1 89 scl (eeprom input) sda (master output) sda (eeprom output) start condition acknowledge bit output scl sda t su.dat t hd.dat
LE24CB1283 no.1887-7/12 5. device addressing to transmit between the bus master an d slave device (eeprom), the master must send a start condition to the eeprom. the device address word of the eeprom consists of 4-bit device code, 3-bit slave device address code and 1-bit read/write code. by sending these, it become s possible to communicate between the bus master and the eeprom. the upper 4-bit of the device address word are called the device code, the device code of the eeprom uses 1010b fixed code. this device has the 3-bit of the slave device addr ess as the slave address (s0, s1, s2), so it can connect up to eight device on the bus. when the device code is received on the sda, the device only responds if slave address pin tied to v dd or gnd is the same as the slave address signal input. the 8 th bit is the read/write bit. the bit is set to 1 for read operation and 0 for write operation. if a match occurs on the device code, the corresponding device gives an acknowledgement on sda during the 9 th bit time. if device does not match the device code, it deselects itself from the bus, and goes into the standby mode. use the random read command when yo u execute reading after the slave device was switched. 1 00 1 s2 s1 s0 r/w msb lsb device code slave address device address word
LE24CB1283 no.1887-8/12 6 eeprom write operation 6-1. byte writes the write operation requires a 7-bit device address word with the 8 th bit = 0(write). then the eeprom sends acknowledgement 0 at the 9 th clock cycle. after these, the eeprom receives word addr ess (a15 to a8), and the eeprom outputs acknowledgemen t 0. and then, the eeprom receives word address (a7 to a0), and the eeprom outputs acknowledgement 0. th en the eeprom receives 8-b it write data, the eeprom ou tputs acknowledgement 0 after receipt of write data. if the eeprom receives a stop condition, the eeprom enters an internally timed (t wc ) write cycle and terminates receipt of i nputs until completion of the write cycle. 6-2. page writes the page write allows up to 64 bytes to be written in a sing le write cycle. the page write is the same sequence as the byte writes except for inputting the more write data. the pa ge write is initiated by a start condition, device code, device address, memory address (n) and write data (n) with every 9 th bit acknowledgement. the device enters the page write operation if this device receives more write da ta (n+1) instead of receiving a stop condition. the page address (a0 to a5) bits are automatically incremented on receiving write data (n+1). the device can continue to receive write data up to 64 bytes. if th e page address bits reach the last addres s of the page, the page address bits will roll over to the first address of the same page and previous write data will be overwritten. after these, if the device receives a stop condition, the devi ce enters an internally timed (t wc u (n+x)) write cycle and terminates receipt of inputs until completion of the write cycle. 6-3. acknowledge polling the acknowledge polling operation is used to show if the eep rom is in an internally timed write cycle or not. this operation is initiated by the stop condition after inputting write data. this requires the 8-bit device address word with the 8 th bit = 0 (write) following the start condition during an internally timed write cycle. if the eeprom is busy with the internal write cycle, no acknowledge will be re turned. if the eeprom has terminated the internal write cycle, it responds with an acknowledge. the terminated write cycle of the eeprom can be known by this operation. sda a 15 a 14 a 13 a 12 a 11 a 10 a9 a8 d7 d6 d5 d4 d3 d2 d1 d0 stop ack ack ack r/w w s0 s1 s2 0 1 0 1 start word address data access from master a7 a6 a5 a4 a3 a2 a1 a0 ack sda d7 d6 d1 d0 d7 d6 d1 d0 d7 d6 d1 d0 d7 d6 d1 d0 stop ack ack ack data(n+1) data(n+x) access from master a 15 a 14 a 13 a 12 a 11 a 10 a9 a8 d7 d6 d5 d4 d3 d2 d1 d0 ack ack ack r/w w s0 s1 s2 0 1 0 1 start word address(n) data(n) a7 a6 a5 a4 a3 a2 a1 a0 ack ack sda no ack r/w w s1 s2 0 1 0 1 start w s1 s2 0 1 0 1 start w s1 s2 0 1 0 1 start no ack r/w ack r/w access from master during write during write end of write s0 s0 s0
LE24CB1283 no.1887-9/12 7 eeprom read operations 7-1. current address reading the device has an internal address counter. it maintains that last address during the last read or write operation, with incremented by one. the current address read accesses the address kept by the internal address counter. after receiving a start conditio n and the device addr ess word with the 8 th bit = 1 (read), the eeprom outputs the 8-bit current address data from following acknowledgement 0. if the eeprom receive s acknowledgement 1 and a following stop condition, the eeprom stops the read opera tion and is returned to a standby mode. in case the eeprom has accessed the last address of the last page at pr evious read operation, the current address will roll over and returns to zero address. in case eeprom has accessed the last address of the last page at previous write operation, the current address roll over within page addressing an d returns to the first address in the same page. the current address is valid while power is on. afte r power on, the current address will be reset (all 0). note: after the page writes operation, the current address is the specified memory address in the last page write. if the write data is more than 64-bytes. 7-2. random read the random read requires a du mmy write to set read addr ess. the eeprom receives a start condition and the device address word with the 8 th bit = 0 (write), the memory address. th e eeprom outputs acknowledgement 0 after receiving memory address then enters a current address r ead with receiving a start co ndition. the eeprom outputs the read data of the address which was defined in the du mmy write operation. after r eceiving no acknowledgement and a following stop condition, the eeprom stop the random read operation and returns to standby mode. 7-3. sequential read the sequential read operation is initiated by either a current address re ad or random read. if the eeprom receives acknowledgement 0 afte r 8-bit read data, the read addr ess is incremented and the next 8-bit read data outputs. the current address will roll over and returns address zero if it reaches the last address of the last page. the sequential read can be continued after roll over. the sequential read is terminated if the eeprom receives no acknowledgement and a following stop condition. sda ack r/w r s1 s2 0 1 0 1 start stop no ack device address data(n) data(n+1) d7 d6 d1 d0 d7 d6 d1 d0 ack ack d7 d6 d1 d0 data(n+x) access from master s0 data(n+2) d7 d6 d1 d0 ack sda d7 d6 d5 d4 d3 d2 d1 d0 no ack ack r/w r s1 s2 0 1 0 1 start device address stop access from master data(n+1 address) s0 no ack ack d7 d0 stop data(n) r s1 s2 0 1 0 1 start device address ack r/w dummy write current address read access from master sda a 15 a 14 a 13 a 12 a 11 a 10 a9 a8 ack ack r/w w s0 s1 s2 0 1 0 1 start word address(n) a7 a6 a5 a4 a3 a2 a1 a0 ack s0 d6 d1
LE24CB1283 no.1887-10/12 application notes 1) software reset function software reset (start condition + 9 dummy clock cycles + st art condition), shown in the figure below, is executed in order to avoid erroneous operation after power-on and to reset while the command input sequence. during the dummy clock input period, the sda bus must be opened (set to high by a pull-up resistor). since it is possible for the ack output and read data to be output from the eeprom during the dummy clock period, forcibly entering h will result in an overcurrent flow. note that this software reset function does not work during the internal write cycle. 2) pull-up resistor of sda pin due to the demands of the i 2 c bus protocol function, the sda pin must be connected to a pull-up resistor (with a resistance from several k : to several tens of k : ) without fail. the appropriate value must be selected for this resistance (r pu ) on the basis of the v il and i il of the microcontroller and other devices controlling this product as well as the v ol ?i ol characteristics of the product. generally, when the resistance is too high, the operating frequency will be restricted; conversely, when it is too low, the operating current consumption will increase. r pu maximum resistance the maximum resistance must be set in such a way that the bus potential, which is determined by the sum total (i l ) of the input leaks of the devices connected to the sda bus and by r pu , can completely satisfy the input high level (v ih min) of the microcontroller and eeprom. however, a resistance value that satisfies sda rise time t r and fall time t f must be set. r pu maximum value = (v dd - v ih )/i l example: when v dd =3.0v and i l = 2 p a r pu maximum value = (3.0v 3.0v u 0.8)/2 p a = 300k : r pu minimum value a resistance corresponding to the low-level output voltage (v ol max) of sanyo?s eeprom must be set. r pu minimum value = (v dd v ol )/i ol example: when v dd =3.0v, v ol = 0.4v and i ol = 1ma r pu minimum value = (3.0v 0.4)/1ma = 2.6k : recommended r pu setting r pu is set to strike a good balance between the operating frequency requirements and power consumption. if it is assumed that the sda load capacitance is 50pf and the sda output data strobe time is 500ns, r pu will be about r pu = 500ns/50pf = 10k : . scl sda 1 2 89 dummy clock
LE24CB1283 no.1887-11/12 3) precautions when turning on the power this product contains a power-on reset circuit for prev enting the inadvertent writing of data when the power is turned on. the following conditions must be met in order to ensure stable operation of this circuit. no data guarantees are given in the event of an instantaneous power failure during the internal write operation. item symbol min typ max unit power rise time t rise 100 ms power off time t off 10 ms power bottom voltage v bot 0.2 v notes: 1) the sda pin must be set to high and the scl pin to low or high. 2) steps must be taken to ensure that the sda and scl pins are not placed in a high-impedance state. a. if it is not possible to satisfy the instruction 1 in note above, and sda is set to low during power rise after the power has stabilized, the scl and sda pins must be controlled as shown below, with both pins set to high. b. if it is not possible to satisfy the instruction 2 in note above after the power has stabilized, soft ware reset must be executed. c. if it is not possible to satisfy the instructions both 1 and 2 in note above after the power has stabilized, the steps in a must be executed, then software reset must be executed. 4) noise filter for the scl and sda pins this product contains a filter circuit for eliminating noise at the scl and sda pins. pulses of 100ns or less are not recognized because of this function. 5) function to inhibit writing when supply voltage is low this product contains a supply voltage monitoring circu it that inhibits inadvertent writing below the guaranteed operating supply voltage range. the data is protected by ensuring that write operations are not started at voltages (typ.) of 1.3v and below. v dd 0v t off t rise v bot t low t dh t su.dat v dd scl sda t su.dat v dd scl sda
LE24CB1283 no.1887-12/12 6) notes on write protect operation this product prohibits all memory arrays writing when the wl pin is high. to ensure full write protection, the wp is set high for all periods from the start condition to the stop condition, and the conditions below must be satisfied. spec symbol parameter min typ max unit t su.wp wp setup time 600 ns t hd.wp wp hold time 600 ns ps this catalog provides information as of january, 2011. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. scl sda t su.wp t hd.wp start condition stop condition wp

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