advanced power electronics corp. ap1280agn 3 2a sink/source bus termination regulator features descriptioon ideal for ddr-i, ddr-ii and ddr-iii v tt applications sink and source up to 2amp integrated power mosfets generates termination voltage for sstl_2, sstl_18, hstl, scsi-2 and scsi-3 interfaces. high accuracy output voltage at full-load output adjustment by two external resistors built-in soft-start function shutdown for suspend to ram (str) functionality with high-impedance output current limiting protection on-chip thermal protection available in dfn 3x3-8l packages v in and v cntl under voltage protection rohs compliant and 100% lead (pb)-free application desktop pcs, notebooks, and workstations graphics card memory termination set top boxes, digital tvs, printers embedded systems active termination buses ddr-i, ddr-ii and ddr-iii memory systems data and specifications subject to change without notice 201205172fc typical application 1 the AP1280AGN3 is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (ddr) memory system to comply with the jedec sstl_2 and sstl_18 or other specific interfaces such as hstl, scsi-2 and scsi-3 etc. devices requirements. the regulator is capable of actively sinking or sourcing up to 2a while regulating an output voltage to within 40mv. the output termination voltage cab be tightly regulated to track 1/2v ddq by two external voltage divider resistors or the desired output voltage can be pro-grammed by externally forcing the refen pin voltage. the AP1280AGN3 also incorporates a high-speed differential amplifier to provide ultra-fast response in line/load transient. other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection.built-in softstart function avoids a misoperation by inrush current. the AP1280AGN3 are available in the dfn 3x3-8l surface mount packages. vin shutdown enable vcntl vout vin refen vcntl vout gnd r1 r2 css cin ccntl cout rdummy rtt AP1280AGN3 r1 = r2 = 100k ? , rtt = 50 ? / 33 ? / 25 ? cout = 10uf ( + 100 uf under the worst case testing condition ) css = 1uf , cin = 470uf (low esr) , ccntl = 47uf www.datasheet.net/ datasheet pdf - http://www..co.kr/
advanced power electronics corp. ap1280agn 3 absolute maximum ratings (note1) input voltage (v in ) ----------------------------------------- - 6v cntl pin voltage (v cntl ) ------------------------------- - 6v power dissipation (p d ) ----------------------------------- - internally limited storage temperature range (t st ) -------------------- - -65 to +150c lead temperature (soldering, 10sec.) --------------- 260c 40c/w note1 : exceeding the absolute maximum rating may damage the device. operating rating (note2) input voltage (v in ) ----------------------------------------- - 2.5v to 1.5v + 3% cntl pin voltage (v cntl ) ------------------------------- - 5.5v or 3.3v + 5% junction temperature range (t j ) --------------------- -40 to +125c ambient temperature range (t a ) --------------------- -40 to +85c note2 : the device is not guaranteed to function outside its operating conditions. ordering / package information (v in =1.8v/1.5v, v cntl =5v, v refen =0.9v/0.75v, c out =10uf(ceramic), t a =25 o c, unless otherwise specified) parameter sym test condition min typ max units vcntl operation current i cntl i out = 0a - 1 2.5 ma standby current i stby v refen= 0v (shutdown) - 25 ua vin shutdown current i vin v refen= 0v (shutdown) - - 5 ua vcntl uvp rising threshold v cop v cntl rising 2.4 2.55 2.7 v vcntl uvp hysteresis v chys - 0.35 -v vin uvp rising threshold v iop v iop rising 0.8 0.95 1.1 v vin uvp hysteresis v ihys - 0.15 -v i out = 10ma -13 - 13 i out = -10ma -13 - 13 i out = 10ma ~ 2a -13 - 13 i out = -10ma ~ -2a -13 - 13 electrical specifications input 2 thermal resistance from junction to case (rth jc ) output (ddr / ddrii / ddriii) load regulation (note4) v load mv uvp function output offset voltage (note3) v os rth j a = 150 o c/w ap1280 ax-hf package type halogen-free gn3 : dfn 3x3-8l ( top view ) dfn 3 x3-8l gnd vin 1 2 3 45 6 7 8 gnd refen vout nc vcntl nc nc www.datasheet.net/ datasheet pdf - http://www..co.kr/
advanced power electronics corp. ap1280agn 3 parameter sym test condition min typ max units current limit i lim 2.2 - - a thermal shutdown temperature t sd 3.3v < v cntl < 5v - 150 - thermal shutdown hysteresis t sd 3.3v < v cntl < 5v - 20 - refen threshold v en 0.15 - 0.4 v soft-start interval t ss ? v out =1v - 0.8 - ms note3. v os offset is the voltage measurement defined as v out subtracted from v refen . note4. regulation is measured at constant junction temperature by using a 1ms(on) / 9ms(off) current pulse. devices are tested for load regulation in the load range from 10ma to 2a for source and -10ma to -2a for sink capability. pin descriptions pin symbol pin description vin power input voltage. gnd ground pin vout output voltage vcntl gate drive voltage refen reference voltage input and chip enable block diagram 3 electrical specifications (continued ) enable and soft-start protection o c vcntl enable function soft-start function gate control logic ocp function uvp function otp function refen vin vout gnd error amplifier www.datasheet.net/ datasheet pdf - http://www..co.kr/
advanced power electronics corp. AP1280AGN3 application informatio n input capacitor and layout consideration consideration while designs the resistance of voltage divider thermal consideration 4 make sure the sinking current capability of pull-down nmos if the lower resistance was chosen so that the voltage on v refen is below 0.15v. in addition, the capacitor and voltage divide r form the lowpass filter. there are two reasons doing this design; one is for output voltage soft-start while another is for noise immunity. AP1280AGN3 regulators have internal thermal limiting circuitry designed to protect the device during overload conditions.for continued operation, do not exceed maximum operation junction temperature 125 o c. the power dissipation definition in device is: p d = (v in - v out ) x i out + v in x i q the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula: p d(max) = ( t j(max) -t a ) / rth ja where t j(max) is the maximum operation junction temperature 125 o c, t a is the ambient temperature and the rth ja is the junction to ambient thermal resistance. the junction to ambient thermal resistance (rth ja is layout dependent) for dfn 3x3-8l is 150 o c/w on standard jedec 51-7 (4 layers, 2s2p) thermal test board. the maximum power dissipation at t a =25 o c can be calculated by following formula: p d(max) = (125 o c - 25 o c) / 150 o c/w = 0.66w the thermal resistance rth ja of dfn 3x3-8l is determined by the package design and the pcb design. however, the package design has been decided. if possible, it's useful to increase thermal performance by the pcb design. the thermal resistance can be decreased by adding copper unde r the expose pad of dfn 3x3-8l package. we have to consider the copper couldn't stretch infinitely and avoid the tin overflow. place the input bypass capacitor as close as possible to the AP1280AGN3. a low esr capacitor larger than 470uf is recommended for the input capacitor. use short and wide traces to minimize parasitic resistance and inductance. inappropriate layout may result in large parasitic inductance and cause undesired oscillation between AP1280AGN3 and the preceding powe converter. www.datasheet.net/ datasheet pdf - http://www..co.kr/
advanced power electronics corp. AP1280AGN3 marking information dfn 3x3-8l 5 1280a ywwsss part number date code (ywws) y last digit of the year ww week sss sequence www.datasheet.net/ datasheet pdf - http://www..co.kr/
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