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general description the MAX5322 dual, 12-bit, serial-interface, digital-to-ana- log converter (dac) provides bipolar ?v to ?0v out- puts from ?2v to ?5v analog power-supply voltages, or unipolar 5v to 10v outputs from a single 12v to 15v ana- log power-supply voltage. the MAX5322 features excellent linearity with both inte- gral nonlinearity (inl) and differential nonlinearity (dnl) guaranteed to ? lsb (max). the device also features a fast 10? to 0.5 lsb settling time, and a hardware-shut- down feature that reduces current consumption to 2.8?. the output goes to midscale at power-up in bipolar mode (0v), and to zero scale at power-up in unipolar mode (0v). a clear input ( clr ) asynchronously clears the dac register and sets the outputs to 0v. the outputs can be asynchronously updated with the load dac ( ldac ) input. the device features a fast 10mhz spi-/qspi- /microwire-compatible serial interface that operates with 3v or 5v logic. additional features include a serial- data output (dout) for daisy chaining and read-back functions. the MAX5322 requires external reference volt- ages of 2v to 5.25v and is available in a 28-pin ssop package that operates over the extended (-40 c to +85 c) temperature range. applications features ? unipolar or bipolar output-voltage ranges unipolar: 0 to +2 x v ref (single or dual supply) bipolar: -2 x v ref to +2 x v ref (dual supply) ? guaranteed inl ? lsb (max) ? guaranteed monotonic: dnl ? lsb (max) ? 10? settling time to 0.5 lsb ? low 2.8? shutdown current ? fast 10mhz spi-/qspi-/microwire-compatible serial interface ? power-on reset sets dac output to 0v ? schmitt trigger inputs for direct optocoupler interface ? serial-data output allows daisy-chaining of devices ? 28-pin ssop (8mm x 10mm) MAX5322 10v, dual, 12-bit, serial, voltage-output dac ________________________________________________________________ maxim integrated products 1 ordering information 19-3150; rev 1; 4/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package MAX5322eai -40 c to +85 c 28 ssop outa sgnda refa 2r 2r 12-bit dac a a1 a2 sw1 sw2 sw3 12 outb sgndb 2r 2r 12-bit dac b a3 a4 sw4 sw5 sw6 12 refb 2r 2r 2r 2r input registers dac registers din sclk serial interface and control 16-bit shift register 12 12 cs uni/bipb uni/bipa shdn dout digital power v cc dgnd analog power v ss v dd agnd MAX5322 clr ldac spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. motor control industrial process controls industrial automation automatic test equipment (ate) analog i/o boards data-acquisition systems functional diagram
MAX5322 10v, dual, 12-bit, serial, voltage-output dac 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (dual supply) (v dd = +15v ?%, v ss = -15v ?%, v cc = +5v ?0%, agnd = dgnd = sgnd_ = 0v, v ref_ = 5v, r load = 2k ? , c load = 250pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to agnd..........................................................-0.3v to +17v v ss to agnd ..........................................................-17v to +0.3v v dd to v ss ..........................................................................+34v v cc to dgnd ...........................................................-0.3v to +6v agnd to dgnd.....................................................-0.3v to +0.3v sgnd_ to agnd ...................................................-0.3v to +0.3v sclk, din, cs , shdn , uni/ bip _, clr , ldac , dout to dgnd ..........................-0.3v to (v cc + 0.3v) out_ to agnd.................................(v ss - 0.3v) to (v dd + 0.3v) ref_ to agnd..........................................................-0.3v to +6v maximum current into ref_ .............................................?0ma maximum current into any pin excluding ref_...............?0ma continuous power dissipation (t a = +70?) 28-pin ssop (derate 9.5mw/? above +70?) ........761.9mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units static accuracy resolution n 12 bits integral nonlinearity inl 1 lsb differential nonlinearity dnl guaranteed monotonic 1 lsb bipolar, code = 800hex 2 zero-scale error unipolar, code = 000hex 2 lsb bipolar 0.9 zero-scale temperature coefficient unipolar 0.09 ppm fsr/ c bipolar (output unloaded) 2 gain error unipolar (output unloaded) 2 lsb bipolar (output unloaded) 2 gain-error temperature coefficient unipolar (output unloaded) 2 ppm fsr/ c analog outputs (outa, outb) output voltage range (v ss + 1.5v) < v out < (v dd - 1.5v) -2 x v ref +2 x v ref v resistive load to gnd r load 2k ? capacitive load to gnd c load 250 pf dc output resistance 0.5 ? sgnd inputs (sgnda, sgndb) input impedance 92 k ? reference inputs (refa, refb) reference voltage input range 2.00 5.25 v input resistance r ref code = 555hex, worst-case code 15 22 k ? reference bandwidth v ref = 200mv p-p + 5v dc 200 khz
MAX5322 10v, dual, 12-bit, serial, voltage-output dac _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units digital inputs (sclk, din, cs , shdn , uni/ bip a, uni/ bip b, clr , ldac ) +2.7v v cc +3.6v 0.7 x v cc input voltage high v ih +4.5v v cc +5.5v 2.4 v +2.7v v cc +3.6v 0.8 input voltage low v il +4.5v v cc +5.5v 0.8 v +2.7v v cc +3.6v 10 input capacitance c +4.5v v cc +5.5v 10 pf 0 all digital inputs v cc , +2.7v v cc +3.6v ? input current (note 1) 0 all digital inputs v cc , +4.5v v cc +5.5v ? ? digital output (dout) output voltage high v oh i source = 2ma v cc - 0.5 v output voltage low v ol i sink = 2ma 0.4 v tri-state leakage current 0.1 ? tri-state capacitance 10 pf dynamic performance voltage output slew rate 2.5 v/? output settling time to 0.5 lsb of full scale, code 000 to code fff 10 ? digital feedthrough cs = high, f sclk = 10mhz, v out = 0v 10 nv-s dac-to-dac crosstalk 2.5 nv-s output-noise spectral density at 10khz 130 nv/ hz power supplies positive analog-supply voltage v dd 10.80 15.75 v negative analog-supply voltage v ss -10.80 -15.75 v positive digital-supply voltage v cc 2.7 5.5 v positive analog-supply current i dd output unloaded, v out = 0 2.8 8ma negative analog-supply current i ss output unloaded, v out = 0 -1.5 -8 ma digital-supply current i cc all digital inputs = 0 or v cc 200 ? positive analog supply 0.0006 power-supply rejection ratio (note 2) psrr negative analog supply 0.03 lsb/v positive analog supply 2.8 50 negative analog supply 4 50 shutdown current digital supply 4 10 ? electrical characteristics (dual supply) (continued) (v dd = +15v ?%, v ss = -15v ?%, v cc = +5v ?0%, agnd = dgnd = sgnd_ = 0v, v ref_ = 5v, r load = 2k ? , c load = 250pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.)
MAX5322 10v, dual, 12-bit, serial, voltage-output dac 4 _______________________________________________________________________________________ electrical characteristics (single supply) (v dd = +15v ?%, v ss = 0v, v cc = +5v ?0%, agnd = dgnd = sgnd_ = 0v, v ref_ = 5v, r load = 10k ? , c load = 250pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units static accuracy resolution n 12 bits integral nonlinearity inl (note 3) 1 lsb differential nonlinearity dnl guaranteed monotonic 1 lsb unipolar zero-scale error 2 lsb unipolar zero-scale temperature coefficient 0.09 ppm fsr/ c gain error no load 2 lsb gain-error temperature coefficient no load 2 ppm fsr/ c analog outputs (outa, outb) output voltage range 0 +2 x v ref v resistive load to gnd r load 10 k ? capacitive load to gnd c load 250 pf dc output resistance 0.5 ? sgnd inputs (sgnda, sgndb) input impedance 92 k ? reference inputs (refa, refb) reference voltage input range 2.00 5.25 v input resistance code = 555hex, worst-case code 15 22 k ? reference input bandwidth v ref = 200mv p-p + 5v dc 150 khz digital inputs (sclk, din, cs , shdn , uni/ bip a, uni/ bip b, clr , ldac ) +2.7v v cc +3.6v 0.7 x v cc input voltage high v ih +4.5v v cc +5.5v 2.4 v +2.7v v cc +3.6v 0.8 input voltage low v il +4.5v v cc +5.5v 0.8 v +2.7v v cc +3.6v 10 input capacitance c in +4.5v v cc +5.5v 10 pf 0 v in v cc, +2.7v v cc +3.6v ? input current i in 0 v in v cc, +4.5v v cc +5.5v ? ? digital output (dout) output voltage high v oh i source = 2ma v cc - 0.5 v output voltage low v ol i sink = 2ma 0.4 v tri-state leakage current 0.1 ?
MAX5322 10v, dual, 12-bit, serial, voltage-output dac _______________________________________________________________________________________ 5 electrical characteristics (single supply) (continued) (v dd = +15v ?%, v ss = 0v, v cc = +5v ?0%, agnd = dgnd = sgnd_ = 0v, v ref_ = 5v, r load = 10k ? , c load = 250pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units tri-state capacitance 10 pf dynamic performance voltage output slew rate 2.5 v/? output settling time to 0.5 lsb of full scale 10 ? digital feedthrough cs = high, f sclk = 10mhz, v out = 0v 10 nv-s dac-to-dac crosstalk 2.5 nv-s output-noise spectral density at 10khz 130 nv/ hz power supplies positive analog supply voltage v dd 10.80 15.75 v negative analog supply voltage v ss 0v positive digital supply voltage v cc 2.7 5.5 v positive analog supply current i dd output unloaded, v out = 0 2.5 8 ma negative analog supply current i ss output unloaded, v out = 0 -0.5 -8 ma digital supply current i cc all digital inputs = 0 or v cc 9 200 ? power-supply rejection ratio psrr 0.001 lsb/v analog supply 2.8 5 shutdown current digital supply 2.8 5 ?
MAX5322 10v, dual, 12-bit, serial, voltage-output dac 6 _______________________________________________________________________________________ timing characteristics (v dd = +15v, v ss = -15v or 0v, v cc = +2.7v to +5.5v, agnd = dgnd = sgnd_ = 0, v ref_ = 5v, r load = 2k ? , ,c load = 250pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units sclk frequency 10 mhz sclk clock period t cp 100 ns sclk pulse-width high t ch for nondaisy-chain use 45 ns for nondaisy-chain use 45 sclk pulse-width low t cl for daisy-chain use 98 ns cs fall to sclk rise setup time t css 40 ns +2.7v v cc +3.6v 15 sclk rise to cs rise hold time t csh +4.5v v cc +5.5v 10 ns din setup time t ds 20 ns din hold time t dh 10 ns ldac pulse width t ld 50 ns +2.7v v cc +3.6v 100 cs rise to ldac low setup time t lds +4.5v v cc +5.5v 50 ns c load = 20pf, +2.7v v cc +3.6v 100 sclk fall to dout valid propagation delay t do1 c load = 20pf, +4.5v v cc +5.5v 80 ns sclk rise to cs fall delay t cs0 10 ns cs low to dout valid time t cse c load = 20pf 120 ns cs high to dout disabled time t csd 120 ns cs rise to sclk rise hold time t cs1 50 ns +2.7v v cc +3.6v 200 cs pulse-width high t csw +4.5v v cc +5.5v 100 ns clr pulse-width low t clr 50 ns note 1: output unloaded, digital inputs = v cc or dgnd. note 2: ? v dd = 15.5v to 14.5v, ? v ss = -15.5v to -14.5v, input code = 14hex to fffhex note 3: accuracy is guaranteed from code 14hex to fffhex
MAX5322 10v, dual, 12-bit, serial, voltage-output dac _______________________________________________________________________________________ 7 intergral nonlinearity vs. input code MAX5322 toc01 input code (decimal) inl (lsb) 3072 2048 1024 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 4096 integral nonlinearity vs. reference voltage MAX5322 toc02 reference voltage (v) inl (lsb) 5.0 4.5 3.5 4.0 3.0 2.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 2.0 5.5 differential nonlinearity vs. input code MAX5322 toc03 input code (decimal) dnl (lsb) 3072 2048 1024 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 4096 differential nonlinearity vs. reference voltage MAX5322 toc04 reference voltage (v) dnl (lsb) 5.0 4.5 3.5 4.0 3.0 2.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 2.0 5.5 bipolar inl vs. temperature MAX5322 toc05 temperature ( c) inl (lsb) 60 35 10 -15 0 0.2 0.4 -0.1 0.1 0.3 0.5 -0.2 -40 85 worst case bipolar dnl vs. temperature MAX5322 toc06 temperature ( c) dnl (lsb) 60 35 10 -15 0.1 0.2 0.3 0.4 0.5 0 -40 85 worst case unipolar settling time (c load = 270pf, r load = 2k ? ) MAX5322 toc07 t = 10.0 s/div a b 0 a: cs, 5.0v/div b: out, 2.0v/div cs 5v/div 2v/div v out bipolar settling time (c load = 270pf, r load = 10k ? ) MAX5322 toc08 t = 10.0 s/div a b 0 a: cs, 5.0v/div b: out, 5.0v/div cs v out 5v/div 5v/div bipolar major carry glitch energy, c load = 230pf MAX5322 toc09 t = 4.00 s/div 5v/div 100mv/div cs v out typical operating characteristics (v dd = +15v, v ss = -15v for bipolar graphs, v ss = 0 for unipolar graphs, v cc = +5v, agnd = dgnd = sgnd_ = 0, v ref_ = +5.0v, output unloaded, t a = +25 c, all graphs apply to both unipolar and bipolar, unless otherwise noted.)
MAX5322 10v, dual, 12-bit, serial, voltage-output dac 8 _______________________________________________________________________________________ bipolar major carry glitch c load = 10pf MAX5322 toc10 t = 4.00 s/div 5v/div 100mv/div cs v out unipolar zero-scale voltage vs. temperature MAX5322 toc11 temperature ( c) v out (mv) 60 35 -15 10 43 44 45 46 47 48 49 50 42 -40 85 code = 0x014hex bipolar zero-scale voltage vs. temperature MAX5322 toc12 temperature ( c) v out (mv) 60 35 10 -15 0.5 1.0 1.5 2.0 2.5 0 -40 85 code = 0x800hex unipolar full-scale voltage vs. temperature MAX5322 toc13 temperature ( c) v out (v) 60 35 10 -15 9.995 9.996 9.997 9.998 9.999 10.000 9.994 -40 85 code = 0xfffhex positive bipolar full-scale voltage vs. temperature MAX5322 toc14 temperature ( c) v out (v) 60 35 10 -15 9.995 9.996 9.997 9.998 9.994 9.993 9.992 -40 85 code = 0xfffhex negative bipolar full-scale voltage vs. temperature MAX5322 toc15 temperature ( c) v out (v) 60 35 10 -15 -9.995 -9.996 -9.997 -9.998 -9.994 -9.993 -9.992 -40 85 code = 0x000hex unipolar supply current vs. supply voltage MAX5322 toc16 v dd (v) i dd (ma) 14.8 13.8 12.8 11.8 1 2 3 4 5 0 10.8 15.8 v ss = 0v bipolar positive supply current vs. supply voltage MAX5322 toc17a v dd (v) i dd (ma) 14.8 13.8 12.8 11.8 1 2 3 4 5 0 10.8 15.8 v ss = -15v bipolar negative supply current vs. supply voltage MAX5322 toc17b v ss (v) i ss (ma) -11.8 -12.8 -13.8 -14.8 -4 -3 -2 -1 0 -5 -15.8 -10.8 v dd = 15v typical operating characteristics (continued) (v dd = +15v, v ss = -15v for bipolar graphs, v ss = 0 for unipolar graphs, v cc = +5v, agnd = dgnd = sgnd_ = 0, v ref_ = +5.0v, output unloaded, t a = +25 c, all graphs apply to both unipolar and bipolar, unless otherwise noted.)
MAX5322 10v, dual, 12-bit, serial, voltage-output dac _______________________________________________________________________________________ 9 unipolar supply current vs. temperature MAX5322 toc18 temperature ( c) i dd (ma) 60 35 10 -15 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 -40 85 v ss = 0v bipolar positive supply current vs. temperature MAX5322 toc19a temperature ( c) i dd (ma) 60 35 10 -15 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 -40 85 bipolar negative supply current vs. temperature MAX5322 toc19b temperature ( c) i ss (ma) 60 35 10 -15 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 -5.0 -40 85 bipolar shutdown current vs. temperature MAX5322 toc20 temperature ( c) shutdown current ( a) 60 35 -15 10 -2 -1 0 1 2 3 4 5 -3 -40 85 i cc i dd i ss unipolar shutdown current vs. temperature MAX5322 toc21 temperature ( c) shutdown current ( a) 60 35 -15 10 0 1 2 3 4 5 -1 -40 85 i cc i dd unipolar output voltage vs. output current MAX5322 toc22b i out (ma) v out (v) 1.0 0.8 0.6 0.4 0.2 0.055 0.065 0.075 0.085 0.095 0.105 0.115 0.125 0.135 0.045 01.2 code = 014hex bipolar output voltage vs. output current MAX5322 toc23a i out (ma) v out (v) -4 -8 -16 -12 -10.000 -9.995 -9.990 -9.985 -9.980 -9.975 -9.970 -9.965 -10.005 -20 0 code = 000hex bipolar output voltage vs. output current MAX5322 toc23b i out (ma) v out (v) 16 12 48 10.000 9.995 9.990 9.985 9.980 9.975 9.970 9.960 9.965 10.005 020 code = fffhex typical operating characteristics (continued) (v dd = +15v, v ss = -15v for bipolar graphs, v ss = 0 for unipolar graphs, v cc = +5v, agnd = dgnd = sgnd_ = 0, v ref_ = +5.0v, output unloaded, t a = +25 c, all graphs apply to both unipolar and bipolar, unless otherwise noted.) unipolar output voltage vs. output current MAX5322 toc22a i out (ma) v out (v) 16 12 8 4 9.965 9.970 9.975 9.980 9.985 9.990 9.995 10.000 10.005 9.960 020 code = fffhex
MAX5322 10v, dual, 12-bit, serial, voltage-output dac 10 ______________________________________________________________________________________ bipolar reference input resistance vs. input code MAX5322 toc25 input code (decimal) ref input resistance (k ? ) 3072 2048 1024 10 20 30 40 50 60 70 80 90 100 0 0 4096 bipolar reference input bandwidth MAX5322 toc27 frequency (khz) response (db) 100 10 1 0.1 -15 -10 -5 0 5 -20 0.01 1000 200mv p-p into ref_ unipolar startup response, c load = 10pf MAX5322 toc28a t = 10.0 s/div v dd v cc v ref v out 20v/div 5v/div 5v/div 2v/div unipolar startup response, c load = 230pf MAX5322 toc28b t = 10.0 s/div v dd v cc v ref v out 20v/div 5v/div 5v/div 1v/div bipolar startup response, c load = 10pf MAX5322 toc29a t = 10.0 s/div v dd v cc v ss v out 20v/div 5v/div 10v/div 2v/div bipolar startup response, c load = 230pf MAX5322 toc29b t = 10.0 s/div v dd v cc v ss v out 5v/div 20v/div 10v/div 1v/div typical operating characteristics (continued) (v dd = +15v, v ss = -15v for bipolar graphs, v ss = 0 for unipolar graphs, v cc = +5v, agnd = dgnd = sgnd_ = 0, v ref_ = +5.0v, output unloaded, t a = +25 c, all graphs apply to both unipolar and bipolar, unless otherwise noted.) unipolar reference input resistance vs. input code MAX5322 toc24 input code (decimal) ref input resistance (k ? ) 3072 2048 1024 10 20 30 40 50 60 70 80 90 100 0 0 4096 unipolar reference input bandwidth MAX5322 toc26 frequency (khz) response (db) 100 10 1 0.1 -15 -10 -5 0 5 -20 0.01 1000 200mv p-p into ref_
MAX5322 10v, dual, 12-bit, serial, voltage-output dac ______________________________________________________________________________________ 11 MAX5322 toc32a t = 40.0 s/div v out unipolar software-shutdown response cs 5v/div 5v/div MAX5322 toc32b t = 40.0 s/div v out bipolar software-shutdown response cs 5v/div 10v/div dac-to-dac crosstalk MAX5322 toc33 outb outa 0v 1mv/div 0v 5v/div t = 100 s/div MAX5322 toc30 t = 100 s/div v out unipolar release from hardware shutdown response v shdn 5v/div 2v/div MAX5322 toc31 t = 100 s/div v out bipolar release from hardware shutdown response v shdn 5v/div 2v/div typical operating characteristics (continued) (v dd = +15v, v ss = -15v for bipolar graphs, v ss = 0 for unipolar graphs, v cc = +5v, agnd = dgnd = sgnd_ = 0, v ref_ = +5.0v, output unloaded, t a = +25 c, all graphs apply to both unipolar and bipolar, unless otherwise noted.)
MAX5322 10v, dual, 12-bit, serial, voltage-output dac 12 ______________________________________________________________________________________ pin name function 1, 2, 13?6, 27, 28 n.c. no connection. not internally connected. 3 uni/ bip b dac b output-mode selection input. selects unipolar or bipolar output. logic high = unipolar, logic low = bipolar. in unipolar mode, the analog output range is 0 to 2 x v ref . in bipolar mode, the analog output range is (-2 x v ref ) to (+2 x v ref ). 4 shdn active-low shutdown input. pulling shdn low forces the dac buffers into high impedance. drive shdn high for normal operation. 5 ldac active-low load dac input. dac a and dac b are updated with information in the input register on the ldac falling edge. 6 clr acti ve- low asynchr onous c l ear d ac inp ut. p ul l i ng c lr l ow cl ear s al l d ac s and i np ut r eg i ster s; r esets al l outp uts to zer o. 7 dgnd digital ground 8v cc digital power input. connect v cc to a +2.7v to +5.5v power supply. bypass v cc to dgnd with a 10? and 0.1? capacitor in parallel as close to the device as possible. 9dout serial-data output. data is clocked out on sclk? falling edge. dout is high impedance when cs is high. data shifted into din appears at dout 16.5 clock cycles later. 10 sclk serial-clock input. sclk clocks data in and out of the serial interface. 11 din serial-data input. data is clocked in on the rising edge of sclk. 12 cs active-low chip-select input. data is not clocked into din unless cs is low. 17 uni/ bip a dac a output-mode selection. selects unipolar or bipolar output. logic high = unipolar, logic low = bipolar. in unipolar mode, the analog output range is 0 to 2 x v ref . in bipolar mode, the analog output range is (-2 x v ref ) to (+2 x v ref ). 18 outa dac a output 19 sgnda dac a sense ground. connect to agnd. 20 refa reference input for dac a 21 v dd positive analog-power input. connect v dd to a +10.8v to +15.75v power supply. bypass v dd to agnd with a 10? and 0.1? capacitor in parallel as close to the device as possible. 22 refb dac b reference input 23 agnd analog ground 24 sgndb dac b sense ground. connect to agnd. 25 outb dac b output 26 v ss negative analog-power input. for single-supply operation, connect v ss to agnd. for dual-supply operation, connect v ss to a -10.8v to -15.75v power supply and bypass v ss to agnd with a 10? and 0.1? capacitor in parallel, as close to the device as possible. pin description
detailed description the MAX5322 dual, 12-bit dac operates from either single or dual analog supplies. dual ?2v to ?5v power supplies provide bipolar ?v to ?0v outputs, or unipolar 0v to 10v outputs. single 12v to 15v analog power supplies only provide unipolar 0 to 10v outputs. the reference inputs accept voltages from 2v to 5.25v. the dac features inl and dnl less than ? lsb (max), a fast 10? settling time, and a hardware shutdown mode that reduces current consumption to 2.8?. the device features a 10mhz spi-/qspi-/microwire-com- patible serial interface that operates with 3v or 5v logic, an asynchronous load input, and a serial-data output. the device offers a clr that sets the dac outputs to 0v. figure 1 shows the functional diagram of the MAX5322. serial interface an spi-/qspi-/microwire-compatible serial interface allows complete control of the dac through a 16-bit control word. the first 4 bits form the control bits that determine register loading and software shutdown functions. the last 12 bits form the dac data. the 16- bit word is entered msb first. table 1 shows the serial-data control-word format. table 2 shows the interface commands. the MAX5322 can be programmed while in shutdown. the serial interface contains five registers: a 16-bit shift register, two 12-bit input registers, and two 12-bit dac registers (figure 1). the shift register accepts data from the serial interface. the input registers act as holding registers for data going to the dac registers MAX5322 10v, dual, 12-bit, serial, voltage-output dac ______________________________________________________________________________________ 13 control bits data bits msb lsb c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 table 1. control-word format 16-bit serial word control bits data bits c3 c2 c1 c0 d11?0 function 0 0 0 0 xxxxxxxxxxxx no operation (nop). 0 0 0 1 12-bit dac data load both dac registers and both input registers from the shift register. (start both dacs with new data.) 0 0 1 0 12-bit dac data load input register a from the shift register; dac registers are unchanged. 0 0 1 1 12-bit dac data load input register b from the shift register; dac registers are unchanged. 0 1 0 0 12-bit dac data load dac register a and input register a from the shift register. 0 1 0 1 12-bit dac data load dac register b and input register b from the shift register. 0 1 1 0 xxxxxxxxxxxx update dac register a from input register a (no data sent). 0 1 1 1 xxxxxxxxxxxx update dac register b from input register b (no data sent). 1 0 0 0 xxxxxxxxxxxx shut down dac a (provided shdn = 1). 1 0 0 1 xxxxxxxxxxxx shut down dac b (provided shdn = 1). 1 0 1 0 xxxxxxxxxxxx update both dac registers from their respective input registers. (start both dacs with data previously stored in the input register.) 1 0 1 1 xxxxxxxxxxxx shut down both dacs (provided shdn = 1). 1 1 0 0 xxxxxxxxxxxx power up dac a (no change to any registers). 1 1 0 1 xxxxxxxxxxxx power up dac b (no change to any registers). 1 1 1 0 xxxxxxxxxxxx power up both dacs (no change to any registers). 1 1 1 1 xxxxxxxxxxxx not used. table 2. serial-interface programming commands x = don? care. note: the dacs can be programmed in shutdown mode.
MAX5322 and isolate the shift register from the dac registers. the dac registers control the dac ladder and thus the output voltage. any update to a dac register updates the respective output voltage. data in the shift register is transferred to the input regis- ters during the appropriate software command only. data in the input registers is transferred to the dac registers in two ways: using the software command, or through external logic control using the asynchronous load input ( ldac ). table 2 shows the software com- mands that transfer the data from the shift register to the input and/or dac registers. the clr , an external logic control, asynchronously forces all outputs to 0v, in both unipolar and bipolar modes. interface timing is shown in figures 2 and 3. wait a minimum of 100ns after cs goes high before implementing ldac or clr . if either of these logic inputs activates during a data transfer, the incoming data is corrupted and needs to be reloaded. for soft- ware control only, tie ldac and clr high. dac architecture the MAX5322 uses an inverted dac ladder architec- ture to convert the digital input into an analog output voltage. the digital input controls weighted switches that connect the dac-ladder nodes to either refa (refb) or gnd (figure 4). the sum of the weights pro- duces the analog equivalent of the digital-input word and is then buffered at the output. external reference and transfer functions connect an external reference of 2v to 5.25v to refa and refb. set the output voltage range with the refer- ence and the input code by using the equations below. unipolar output voltage: v lsb code out uni uni _ = 10v, dual, 12-bit, serial, voltage-output dac 14 ______________________________________________________________________________________ sclk din command executed 9 8 16 (1) 1 c2 c3 d0 c1 c0 d11 d10 d9 d6 d5 d4 d3 d2 d1 d8 d7 cs figure 2. serial-interface signals sclk din dout t cs0 t css t cp t csh t cs1 t csw t csd t lds t ld t ch t ds t cse t do1 t dh t cl msb lsb cs ldac figure 3. serial-interface timing diagram
where: bipolar output voltage: where: where v out_uni is the unipolar output voltage, v out_bip is the bipolar output voltage, lsb uni is the unipolar lsb step size, lsb bip is the bipolar lsb step size, v ref is the reference voltage, and code is the decimal equiva- lent of the binary, 12-bit, dac input code. in either case, a 000hex input code produces the mini- mum output (-2 x v ref for bipolar and zero for unipo- lar), an 800hex input code produces the midscale output (zero for bipolar and v ref for unipolar), and a fffhex input code produces the full-scale output (2 x v ref for bipolar and unipolar). output amplifiers the output-amplifier section can be configured as either unipolar or bipolar by the uni/ bip logic input. with uni/ bip a (uni/ bip b) forced low, sw1 (sw4) and sw2 (sw5) in figure 1 are closed, and sw3 (sw6) is open. this configuration channels the dac output through two output stages to generate the ? x v ref output swing. the first amplifier generates the ? ref voltage range and the second amplifier gains it up by two. when configured for bipolar operation, the MAX5322 must be driven with dual ?2v to ?5v power supplies. with uni/ bip a (uni/ bip b) forced high, switches sw1 (sw4) and sw2 (sw5) are open and sw3 (sw6) is closed. this configuration channels the dac output through only a single gain stage to generate a 0 to 2 x v ref output swing. daisy-chaining spi-/qspi-/microwire-compatible devices can be daisy-chained to reduce i/o lines from the host controller (figure 7). daisy-chain devices by connecting the dout of one device to the din of the next, and connect the sclk of all devices to a common clock. data is shifted out of dout 16.5 clock cycles after it is shifted into din, and is available on the rising edge of the 17th clock cycle. the spi-/qspi-/microwire-compatible serial interface normally works at up to 10mhz, but must be slowed to 6mhz if daisy-chaining. dout is high imped- ance when cs is high. shutdown shutdown is controlled by software commands or by the shdn logic input. the shdn logic input may be imple- mented at any time. the spi-/qspi-/microwire-com- patible serial interface remains fully functional, and the device is programmable while shutdown. when shut down, the MAX5322 supply current reduces to 2.8? lsb v bip ref = 4 2 12 v lsb code v out bip bip ref _ ( )( ) =? 2 lsb v uni ref = 2 2 12 MAX5322 10v, dual, 12-bit, serial, voltage-output dac ______________________________________________________________________________________ 15 rrr 2r 2r 2r 2r 2r d0 d11 d10 d1 refa agnd 0 10 10 10 1 outa control logic 2r 2r 2r 2r sgnda dac register a sw1 sw2 sw3 MAX5322 uni/bipa figure 4. basic inverted dac ladder
MAX5322 10v, dual, 12-bit, serial, voltage-output dac 16 ______________________________________________________________________________________ (max), dout is high impedance, and outa and outb are pulled to sgnda and sgndb, respectively, through the internal feedback resistors of the output amplifier (figure 1). when coming out of shutdown, or during device power-up, allow 350? for the output to stabilize. applications information power supplies a single supply of +12v to +15v is required to realize an output swing of 0 to 10v. a dual supply of ?2v to ?5v is required to realize an output swing of ?0v, and allows unipolar, 0 to +10v output if uni/ bip _ is forced high. a +3v to +5v digital power supply and two +2.000v to +5.250v external reference voltages are also required. always bring up the reference voltages last; the other power supplies do not require sequencing. power-supply bypassing and ground management bypass v dd and v ss with 1.0? and 0.1? capacitors to agnd, and bypass v cc with a 1.0? and 0.1? capaci- tors to dgnd. minimize trace lengths to reduce induc- tance. digital and ac transient signals on agnd or dgnd can create noise at the output. connect agnd and dgnd to the highest quality ground available. use proper grounding techniques, such as a multilayer board with a low-inductance ground plane or star connect all ground return paths back to agnd. carefully lay out the traces between channels to reduce ac cross coupling and crosstalk. wire-wrapped boards, sockets, and breadboards are not recommended. binary dac code analog output msb lsb unipolar (uni/ bip _ = high) bipolar (uni/ bip _ = low) 1111 1111 1111 +2 x v ref (4095 / 4096) +2 x v ref (2047 / 2048) 1000 0000 0001 +2 x v ref (2049 / 4096) +2 x v ref (1 / 2048) 1000 0000 0000 +2 x v ref (2048 / 4096) = v ref 0 0111 1111 1111 +2 x v ref (2047 / 4096) -2 x v ref (1 / 2048) 0000 0000 0001 +2 x v ref (1 / 4096) -2 x v ref (2047 / 2048) 0000 0000 0000 0 -2 x v ref (2048 / 2048) = -2 x v ref table 3. output voltage as input code examples hex digital input code (lsb) -2048 -2047 -2046 -2045 +2047 +2046 +2045 +2044 +1 0 -1 analog output voltage (lsb) 001 000 002 003 7ff 800 801 ffc ffd fff ffe 4 x v ref 1 lsb = 4 x v ref 4096 figure 6. bipolar transfer function hex digital input code (lsb) 0 1 2 3 4095 4094 4093 4092 2049 2048 2047 analog output voltage (lsb) 001 000 002 003 7ff 800 801 ffc ffd fff ffe 2 x v ref 1 lsb = 2 x v ref 4096 figure 5. unipolar transfer function
MAX5322 10v, dual, 12-bit, serial, voltage-output dac ______________________________________________________________________________________ 17 MAX5322 MAX5322 MAX5322 to other serial devices din sclk dout din sclk dout din sclk dout sclk din cs cs cs cs figure 7. daisy-chaining devices chip information transistor count: 5914 process: bicmos pin configuration 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 n.c. n.c. v ss outb sgndb agnd n.c. refb v dd refa sgnda outa uni/bipa n.c. n.c. n.c. cs din sclk dout v cc dgnd clr ldac shdn uni/bipb n.c. n.c. ssop top view MAX5322
MAX5322 10v, dual, 12-bit, serial, voltage-output dac maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) ssop.eps package outline, ssop, 5.3 mm 1 1 21-0056 c rev. document control no. approval proprietary information title: notes: 1. d&e do not include mold flash. 2. mold flash or protrusions not to exceed .15 mm (.006"). 3. controlling dimension: millimeters. 4. meets jedec mo150. 5. leads to be coplanar within 0.10 mm. 7.90 h l 0 0.301 0.025 8 0.311 0.037 0 7.65 0.63 8 0.95 max 5.38 millimeters b c d e e a1 dim a see variations 0.0256 bsc 0.010 0.004 0.205 0.002 0.015 0.008 0.212 0.008 inches min max 0.078 0.65 bsc 0.25 0.09 5.20 0.05 0.38 0.20 0.21 min 1.73 1.99 millimeters 6.07 6.07 10.07 8.07 7.07 inches d d d d d 0.239 0.239 0.397 0.317 0.278 min 0.249 0.249 0.407 0.328 0.289 max min 6.33 6.33 10.33 8.33 7.33 14l 16l 28l 24l 20l max n a d e a1 l c h e n 1 2 b 0.068

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