1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | copyright ?intersil corporation 1999 ordering information part number temperature range screening level package hcts74dmsr -55 o c to +125 o c intersil class s equivalent 14 lead sbdip hcts74kmsr -55 o c to +125 o c intersil class s equivalent 14 lead ceramic flatpack hcts74d/sample +25 o c sample 14 lead sbdip hcts74k/sample +25 o c sample 14 lead ceramic flatpack hcts74hmsr +25 o c die die HCTS74MS radiation hardened dual-d flip-flop with set and reset pinouts 14 lead ceramic dual-in-line metal seal package (sbdip) mil-std-183s cdip2-t14, lead finish c top view 14 lead ceramic metal seal flatpack package (flatpack) mil-std-183s cdfp3-f14, lead finish c top view r1 d1 cp1 s1 q1 q1 gnd vcc r2 d2 cp2 s2 q2 q2 1 2 3 4 5 6 7 14 13 12 11 10 9 8 14 13 12 11 10 9 8 2 3 4 5 6 7 1 r1 d1 cp1 s1 q1 q1 gnd vcc r2 d2 cp2 s2 q2 q2 features 3 micron radiation hardened sos cmos total dose 200k rad (si) sep effective let no upsets: >100 mev-cm 2 /mg single event upset (seu) immunity < 2 x 10 -9 errors/ bit-day (typ) dose rate survivability: >1 x 10 12 rad (si)/s dose rate upset >10 10 rad (si)/s 20ns pulse latch-up free under any conditions military temperature range: -55 o c to +125 o c signi?ant power reduction compared to lsttl ics dc operating voltage range: 4.5v to 5.5v lsttl input compatibility - vil = 0.8v max - vih = vcc/2 min input current levels ii 5 a at vol, voh description the intersil HCTS74MS is a radiation hardened positive edge triggered ?p-?p with set and reset. the HCTS74MS utilizes advanced cmos/sos technology to achieve high-speed operation. this device is a member of radiation hardened, high-speed, cmos/sos logic family. the HCTS74MS is supplied in a 14 lead ceramic ?tpack (k suf?) or a sbdip package (d suf?). september 1995 spec number 518626 file number 2143.2
2 HCTS74MS functional diagram truth table inputs outputs set reset cp d q q lhxxhl hlxxlh l l x x h* h* hh hhl hh l lh hhl xq0 q0 note: l = logic level low, h = logic level high, x = don? care = transition from low to high level q0 = the level of q before the indicated input conditions were established. * this con?uration is non-stable, that is, it will not persist when set and reset inputs return to their inactive (high) level. 4(10) p n 2(12) cl cl p n cl cl 3(11) p n cl cl p n cl cl cl cl 6(8) 5(9) q q s d r cp 1(13) spec number 518626
3 speci?ations HCTS74MS absolute maximum ratings reliability information supply voltage (vcc). . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +7.0v input voltage range, all inputs . . . . . . . . . . . . .-0.5v to vcc +0.5v dc input current, any one input . . . . . . . . . . . . . . . . . . . . . . . . 10ma dc drain current, any one output . . . . . . . . . . . . . . . . . . . . . . . 25ma (all voltage reference to the vss terminal) storage temperature range (tstg) . . . . . . . . . . . -65 o c to +150 o c lead temperature (soldering 10sec) . . . . . . . . . . . . . . . . . . +265 o c junction temperature (tj) . . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c esd classi?ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 thermal resistance ja jc sbdip package. . . . . . . . . . . . . . . . . . . . 74 o c/w 24 o c/w ceramic flatpack package . . . . . . . . . . . 116 o c/w 30 o c/w maximum package power dissipation at +125 o c ambient sbdip package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68w ceramic flatpack package . . . . . . . . . . . . . . . . . . . . . . . . . 0.43w if device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: sbdip package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5mw/ o c ceramic flatpack package . . . . . . . . . . . . . . . . . . . . . . 8.6mw/ o c caution: as with all semiconductors, stress listed under ?bsolute maximum ratings?may be applied to devices (one at a time) w ithout resulting in permanent damage. this is a stress rating only. exposure to absolute maximum rating conditions for extended periods may affect device rel iability. the conditions listed under ?lectrical performance characteristics?are the only conditions recommended for satisfactory device operation. operating conditions supply voltage (vcc). . . . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v operating temperature range (t a ) . . . . . . . . . . . . -55 o c to +125 o c input rise and fall times at vcc = 4.5v (tr, tf) . . 100ns/v max. input low voltage (vil). . . . . . . . . . . . . . . . . . . . . . . . . 0.0v to 0.8v input high voltage (vih) . . . . . . . . . . . . . . . . . . . . . . .vcc/2 to vcc table 1. dc electrical performance characteristics parameter symbol (note 1) conditions group a sub- groups temperature limits units min max quiescent current icc vcc = 5.5v, vin = vcc or gnd 1 +25 o c-20 a 2, 3 +125 o c, -55 o c - 400 a output current (sink) iol vcc = 4.5v, vih = 4.5v, vout = 0.4v, vil = 0v 1 +25 o c 4.8 - ma 2, 3 +125 o c, -55 o c 4.0 - ma output current (source) ioh vcc = 4.5v, vih = 4.5v, vout = vcc -0.4v, vil = 0v 1 +25 o c -4.8 - ma 2, 3 +125 o c, -55 o c -4.0 - ma output voltage low vol vcc = 4.5v, vih = 2.25v, iol = 50 a, vil = 0.8v 1, 2, 3 +25 o c, +125 o c, -55 o c - 0.1 v vcc = 5.5v, vih = 2.75v, iol = 50 a, vil = 0.8v 1, 2, 3 +25 o c, +125 o c, -55 o c - 0.1 v output voltage high voh vcc = 4.5v, vih = 2.25v, ioh = -50 a, vil = 0.8v 1, 2, 3 +25 o c, +125 o c, -55 o c vcc -0.1 -v vcc = 5.5v, vih = 2.75v, ioh = -50 a, vil = 0.8v 1, 2, 3 +25 o c, +125 o c, -55 o c vcc -0.1 -v input leakage current iin vcc = 5.5v, vin = vcc or gnd 1 +25 o c- 0.5 a 2, 3 +125 o c, -55 o c- 5.0 a noise immunity functional test fn vcc = 4.5v, vih = 2.25v, vil = 0.8v (note 2) 7, 8a, 8b +25 o c, +125 o c, -55 o c--- notes: 1. all voltages reference to device gnd. 2. for functional tests vo 4.0v is recognized as a logic ?? and vo 0.5v is recognized as a logic ?? 3. force/measure functions may be interchanged. spec number 518626
4 speci?ations HCTS74MS table 2. ac electrical performance characteristics parameter symbol (notes 1, 2) conditions group a sub- groups temperature limits units min max cp to q, q tphl vcc = 4.5v 9 +25 o c 2 31 ns 10, 11 +125 o c, -55 o c 2 37 ns tplh vcc = 4.5v 9 +25 o c 2 27 ns 10, 11 +125 o c, -55 o c 2 31 ns s to q tplh vcc = 4.5v 9 +25 o c 2 21 ns 10, 11 +125 o c, -55 o c 2 24 ns s to q tphl vcc = 4.5v 9 +25 o c 2 33 ns 10, 11 +125 o c, -55 o c 2 38 ns r to q tphl vcc = 4.5v 9 +25 o c 2 35 ns 10, 11 +125 o c, -55 o c 2 40 ns r to q tplh vcc = 4.5v 9 +25 o c 2 29 ns 10, 11 +125 o c, -55 o c 2 34 ns notes: 1. all voltages referenced to device gnd. 2. ac measurements assume rl = 500 ? , cl = 50pf, input tr = tf = 3ns, vil = gnd, vih = 3v. table 3. electrical performance characteristics parameter symbol conditions notes temperature limits units min max capacitance power dissipation cpd vcc = 5.0v, f = 1mhz 1 +25 o c - 53 pf 1 +125 o c, -55 o c - 55 pf input capacitance cin vcc = open, f = 1mhz 1 +25 o c - 10 pf 1 +125 o c, -55 o c - 10 pf output transition time tthl ttlh vcc = 4.5v 1 +25 o c - 15 ns 1 +125 o c, -55 o c - 22 ns max operating frequency fmax vcc = 4.5v 1 +25 o c - 25 mhz 1 +125 o c, -55 o c - 16 mhz data to cp set-up time tsu vcc = 4.5v 1 +25 o c11-ns 1 +125 o c, -55 o c12-ns hold time th vcc = 4.5v 1 +25 o c3-ns 1 +125 o c, -55 o c3-ns removal time r, s to cp trem vcc = 4.5v 1 +25 o c5-ns 1 +125 o c, -55 o c6-ns pulse width r, s tw vcc = 4.5v 1 +25 o c14-ns 1 +125 o c, -55 o c16-ns pulse width cp tw vcc = 4.5v 1 +25 o c14-ns 1 +125 o c, -55 o c16-ns note: 1. the parameters listed in table 3 are controlled via design or process parameters. min and max limits are guaranteed but not d irectly tested. these parameters are characterized upon initial design release and upon design changes which affect these characteristi cs. spec number 518626
5 speci?ations HCTS74MS table 4. dc post radiation electrical performance characteristics parameters symbol (notes 1, 2) conditions temperature 200k rad limits units min max quiescent current icc vcc = 5.5v, vin = vcc or gnd +25 o c - 0.4 ma output current (sink) iol vcc = 4.5v, vin = vcc or gnd, vout = 0.4v +25 o c 4.0 - ma output current (source) ioh vcc = 4.5v, vin = vcc or gnd, vout = vcc -0.4v +25 o c -4.0 - ma output voltage low vol vcc = 4.5v and 5.5v, vih = vcc/2, vil = 0.8v, iol = 50 a +25 o c - 0.1 v output voltage high voh vcc = 4.5v and 5.5v, vih = vcc/2, vil = 0.8v, ioh = -50 a +25 o c vcc -0.1 -v input leakage current iin vcc = 5.5v, vin = vcc or gnd +25 o c- 5 a noise immunity functional test fn vcc = 4.5v, vih = 2.25v, vil = 0.8v, (note 3) +25 o c --- cp to q, q tphl vcc = 4.5v +25 o c 2 37 ns tplh vcc = 4.5v +25 o c 2 31 ns s to q tplh vcc = 4.5v +25 o c 2 24 ns s to q tphl vcc = 4.5v +25 o c 2 38 ns r to q tphl vcc = 4.5v +25 o c 2 40 ns r to q tplh vcc = 4.5v +25 o c 2 34 ns notes: 1. all voltages referenced to device gnd. 2. ac measurements assume rl = 500 ? , cl = 50pf, input tr = tf = 3ns, vil = gnd, vih = 3v. 3. for functional tests vo 4.0v is recognized as a logic ?? and vo 0.5v is recognized as a logic ?? table 5. burn-in and operating life test, delta parameters (+25 o c) parameter group b subgroup delta limit icc 5 6 a iol/ioh 5 -15% of 0 hour spec number 518626
6 speci?ations HCTS74MS table 6. applicable subgroups conformance groups method group a subgroups read and record initial test (preburn-in) 100%/5004 1, 7, 9 icc, iol/h interim test i (postburn-in) 100%/5004 1, 7, 9 icc, iol/h interim test ii (postburn-in) 100%/5004 1, 7, 9 icc, iol/h pda 100%/5004 1, 7, 9, deltas interim test iii (postburn-in) 100%/5004 1, 7, 9 icc, iol/h pda 100%/5004 1, 7, 9, deltas final test 100%/5004 2, 3, 8a, 8b, 10, 11 group a (note 1) sample/5005 1, 2, 3, 7, 8a, 8b, 9, 10, 11 group b subgroup b-5 sample/5005 1, 2, 3, 7, 8a, 8b, 9, 10, 11, deltas subgroups 1, 2, 3, 9, 10, 11, (note 2) subgroup b-6 sample/5005 1, 7, 9 group d sample/5005 1, 7, 9 notes: 1. alternate group a testing in accordance with method 5005 of mil-std-883 may be exercised. 2. table 5 parameters only. table 7. total dose irradiation conformance groups method test read and record pre rad post rad pre rad post rad group e subgroup 2 5005 1, 7, 9 table 4 1, 9 table 4 (note1) note: 1. except fn test which will be performed 100% go/no-go. table 8. static and dynamic burn-in test connections open ground 1/2 vcc = 3v 0.5v vcc = 6v 0.5v oscillator 50khz 25khz static burn-in i test connections 5, 6, 8, 9 1, 2, 3, 4, 7, 10, 11, 12, 13 14 static burn-in ii test connections 5, 6, 8, 9 7 1, 2, 3, 4, 10, 11, 12, 13, 14 dynamic burn-in test connections - 7 5, 6, 8, 9 1, 4, 10, 13, 14 3, 11 2, 12 notes: 1. each pin except vcc and gnd will have a resistor of 10k ? 5% for static burn-in. 2. each pin except vcc and gnd will have a resistor of 1k ? 5% for dynamic burn-in. table 9. irradiation test connections open ground vcc = 5v 0.5v 5, 6, 8, 9 7 1, 2, 3, 4, 10, 11, 12, 13, 14 note: each pin except vcc and gnd will have a resistor of 47k ? 5% for irradiation testing. group e, subgroup 2, sample size is 4 dice/wafer 0 failures. spec number 518626
7 HCTS74MS intersil space level product flow - ?s wafer lot acceptance (all lots) method 5007 (includes sem) gamma radiation veri?ation (each wafer) method 1019, 4 samples/wafer, 0 rejects 100% nondestructive bond pull, method 2023 sample - wire bond pull monitor, method 2011 sample - die shear monitor, method 2019 or 2027 100% internal visual inspection, method 2010, condition a 100% temperature cycle, method 1010, condition c, 10 cycles 100% constant acceleration, method 2001, condition per method 5004 100% pind, method 2020, condition a 100% external visual 100% serialization 100% initial electrical test (t0) 100% static burn-in 1, condition a or b, 24 hrs. min., +125 o c min., method 1015 100% interim electrical test 1 (t1) 100% delta calculation (t0-t1) 100% static burn-in 2, condition a or b, 24 hrs. min., +125 o c min., method 1015 100% interim electrical test 2 (t2) 100% delta calculation (t0-t2) 100% pda 1, method 5004 (notes 1and 2) 100% dynamic burn-in, condition d, 240 hrs., +125 o c or equivalent, method 1015 100% interim electrical test 3 (t3) 100% delta calculation (t0-t3) 100% pda 2, method 5004 (note 2) 100% final electrical test 100% fine/gross leak, method 1014 100% radiographic, method 2012 (note 3) 100% external visual, method 2009 sample - group a, method 5005 (note 4) 100% data package generation (note 5) notes: 1. failures from interim electrical test 1 and 2 are combined for determining pda 1. 2. failures from subgroup 1, 7, 9 and deltas are used for calculating pda. the maximum allowable pda = 5% with no more than 3% o f the failures from subgroup 7. 3. radiographic (x-ray) inspection may be performed at any point after serialization as allowed by method 5004. 4. alternate group a testing may be performed as allowed by mil-std-883, method 5005. 5. data package contents: cover sheet (intersil name and/or logo, p.o. number, customer part number, lot date code, intersil part number, lot number, qu an- tity). wafer lot acceptance report (method 5007). includes reproductions of sem photos with percent of step coverage. gamma radiation report. contains cover page, disposition, rad dose, lot number, test package used, speci?ation numbers, test equipment, etc. radiation read and record data on ?e at intersil. x-ray report and ?m. includes penetrometer measurements. screening, electrical, and group a attributes (screening attributes begin after package seal). lot serial number sheet (good units serial number and lot number). variables data (all delta operations). data is identi?d by serial number. data header includes lot number and date of test. the certi?ate of conformance is a part of the shipping invoice and is not part of the data book. the certi?ate of conformanc e is signed by an authorized quality representative. spec number 518626
8 HCTS74MS ac timing diagrams and load circuit vs input output output tthl 80% 20% 80% 20% vih vil voh vol voh vol tplh tphl vs ttlh ac voltage levels parameter hcts units vcc 4.50 v vih 3.00 v vs 1.30 v vil 0 v gnd 0 v dut test cl rl point cl = 50pf rl = 500 ? pulse width, setup, hold timing diagram positive edge trigger tw th vs tsu input vih vil input cp vih vil tw vs th = hold time tsu = setup time tw = pulse width voltage levels parameter hcts units vcc 4.50 v vih 3.00 v vs 1.30 v vil 0 v gnd 0 v spec number 518626
9 HCTS74MS die characteristics die dimensions: 89 x 88 mils 2.25 x 2.24mm metallization: type: sial metal thickness: 11k ? 1k ? glassivation: type: sio 2 thickness: 13k ? 2.6k ? worst case current density: <2.0 x 10 5 a/cm 2 bond pad size: 100 m x 100 m 4 mils x 4 mils metallization mask layout HCTS74MS note: the die diagram is a generic plot from a similar hcs device. it is intended to indicate approximate die size and bond pad location. the mask series for the hcts74 is ta14438a. r1 vcc cp1 (3) s1 (4) q1 (5) q1 (6) (8) (9) (10) s2 (11) cp2 (12) d2 (13) r2 (1) (14) q2 q2 d1 (2) nc nc (7) gnd spec number 518626
10 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?ations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com HCTS74MS spec number
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