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v er 1. 7 12/01/12 1 es519 9 7 (60 0 00counts) dmm analog front end features ? 60000 counts dual - slope s adc (2 cnvs/s.) ? input signal full scale: 630mv (m a x. 63 0 00 c ount ) ? built - in 600 counts fast speed (x10) f adc ? fast adc conversion rate: 2 0 times/s ? 1 00l l qfp package ? 3v dc regulated power supply ? s upport digital multi - meter function *voltage measurement (ac/dc) *current measurement (ac/dc) * dual mode for f requency with v oltage or c urrent *resistan ce measureme n t (600. 0 0 ? C 60. 0 00m ? ) *conductance measurement (60.00ns) *capacitance measurement (6. 0 00nf C 60.00mf) (taiwan patent no.: 323347, 453443) *diode or continuity mode measurement *frequency counter with duty cycle display: 6 0 . 0 00hz C 6 0 . 0 00mhz 5 .0 % C 9 5 .0 % ? adp mode (ac or dc mode is available) ? 3db bw selectable for l ow pass filter at ac mode ( taiwan patent no.: 362409 ) ( china patent no.: 1363073 ) ? band - gap reference voltage output ? peak - hold measurement ( taiwan patent no.:476418 ) ? 3 - wire serial bus for mpu i/o por t ? mpu i/o power level selectable by external pins ? on - chip buzzer driver and frequency selectable by mpu command ? high - crest - factor signal detection ( taiwan patent no.: 234661 ) ? multi - level b attery voltage detection ? support sleep mode by external chip select pin application clamp - on meter digital multi - meter description ES51997 is a n analog frond end chip of dmm built - in 60000 (sadc) /600 (fadc) counts dual adc s. the sadc is operated at slower speed for higher resolution. the fadc is operated at higher speed for lower resolution. ES51997 provide s volt age & current (ac/dc) measurement, resistance measurement, capacitance measurement, diode/continuity measurement, f requency measurement, duty cycle measurement and voltage peak - hold function. t he ES51997 also support s multi - level battery detection, low - pass - filter feature for ac mode and dual mode measurement for v+f & a+f. a 3 - wire serial bus for mpu i/o port will be used easily for firmware design. flexible function design is supported for different kinds of dmm or clamp - on meter application. .
v er. 1. 7 12/01/12 2 es519 9 7 (60 0 00counts) dmm analog front end pin assignment 1 2 3 4 5 6 a b c d 6 5 4 3 2 1 d c b a bufh 1 caz h 2 nc 3 cl+ 4 cl- 5 ci l 6 caz l 7 bufl 8 raz 9 o hmc3 10 o hmc2 11 o hmc1 12 v rh 13 v a+ 14 v a- 15 extsrc 16 o r1 19 v r5 20 v r4 21 v r3 22 v r2 23 o vsg 24 v r1 25 ivsh 37 ivsl 38 a dp 39 acvl 43 acvh 44 a di 45 a do 46 test5 47 sgn d 36 ca- 48 ca+ 49 r9k 55 r1k 56 o vx 26 o vh 27 lpc1 57 lpc2 58 lpc3 59 lpfout 60 nc 54 nc 52 nc 53 stbeep 64 freq 65 nc 66 nc 67 nc 68 nc 69 nc 70 nc 71 nc 72 nc 73 nc 74 nc 75 nc 76 nc 77 cih 1 00 o sc2 78 o sc1 79 cs 80 i o_ c t rl 81 bzout 82 nc 83 data_new 84 s cl k 85 sda t a 86 c+ 87 c- 88 l ba t 89 v- 90 v- 91 u pv cc 92 v+ 93 v+ 94 dgnd 95 agnd 96 agnd 97 ch+ 98 ch- 99 ovh1 28 opin- 40 opin+ 41 opout 42 o hm c4 50 nc 51 p mi n 61 p ma x 62 cpki n 63 nc 17 nc 18 nc 35 nc 34 nc 29 nc 30 nc 31 nc 32 nc 33 ES51997
v er. 1. 7 12/01/12 3 es519 9 7 (60 0 00counts) dmm analog front end pin description pin no symbol type description 1 bufh o high - speed buffer output pin. connect to integral resistor. 2 cazh o high - speed auto - zero capacitor connection. 3 nc - not connected 4 cl+ io positive connection for reference capacitor of high - resolution a/d. 5 cl - io negative connection for reference capacitor of high - resolution a/d. 6 cil o high - resolution integrator output. connect to integral capacitor. 7 cazl o high - resolution auto - zer o capacitor connection. 8 bufl o high - resolution buffer output pin. connect to integral resistor 9 raz o buffer output pin in az and zi phase. 10 ohmc3 o filter capacitor connection for resistance mode. 11 ohmc2 o filter capacitor connection for resist ance mode. 12 ohmc1 o filter capacitor connection for resistance mode. 13 vrh o output of band - gap voltage reference. typically C 1.23v 14 va + i de - integrating voltage positive input. the input should be higher than va - . 15 va - i de - integrating voltage negative input. the input should be lower than va + . 16 extsrc i external source input available for res/diode/adp mode 17 nc - not connected 18 nc - not connected 19 or1 o reference resistor connection for 60 0. 0 0 range 20 vr5 o voltage measurement 10000 attenuator(1000 .0 v) 21 vr4 o voltage measurement 1000 attenuator( 60 0.0 0 v) 22 vr3 o voltage measurement 100 attenuator( 60 .00 0 v) 23 vr2 o voltage measurement 10 attenuator( 6.0 0 0 0v) 24 ovsg o sense low volt age for resistance /voltage measurement 25 vr1 i measurement input. connect to a precise 10m res istor. 26 ovx i sense input for resistance /capacitance measurement 27 ovh o output connection for resistance measurement 28 ovh 1 o output connection 1 for re sistance measurement (optional) 29 nc - not connected 30 nc - not connected 31 nc - not connected 32 nc - not connected 33 nc - not connected 34 nc - not connected 35 nc - not connected 36 sgnd g signal ground. 37 ivsh i current measurement input for 6000 .0 a, 6 0 0 .00 ma and 60 .000 a modes . 38 ivsl i current measurement input for 6 0 0 .00 a, 6 0 .000 ma. 39 adp i measurement input in adp mode. 40 opin - i independent operational amplifier nega tive input 41 opin + i independent operational amplifier posi tive input 42 opout o independent operational amplifier output 43 acvl o dc signal low input in acv/aca mode. connect to negative output of external ac to dc converter. 44 acvh o dc signal high input in acv/aca mode. connect to positive output of external ac to dc converter. 45 adi i negative input of internal ac - to - dc opa mp . 46 ado o output of internal ac - to - dc opa mp . 47 test5 o buffer output of ovsg 48 ca - io negative auto - zero capacitor connection for capacitor measurement
v er. 1. 7 12/01/12 4 es519 9 7 (60 0 00counts) dmm analog front end 49 ca+ io positive auto - zero ca pacitor connection for capacitor measurement 50 ohmc 4 o filter capacitor connection for resistance mode. 51 nc - not connected 52 nc - not connected 53 nc - not connected 54 nc - not connected 55 r9k o connect to a precise 9k resister for capacitor measurement. 56 r1k o connect to a precise 1k resister for capacitor measurement. 57 lpc1 o capacitor c1 connection for internal low - pass filter 58 lpc2 o capacitor c2 connection for internal low - pass filter 59 lpc3 o capacitor c3 connection for inter nal low - pass filter 60 lp f out o capacitor c1 connection for internal low - pass filter 61 pmin o minimum peak hold output 62 pmax o maximum peak hold output. 63 cpkin i bypass capacitor for peak mode 64 stbeep o fast low - impedance sensed output for cont ./diode mode build - in a internal comparator for ovx pin. 65 freq i frequency counter input, offset v - /2 internally by the chip. 66 - 77 nc - not connected 78 osc2 o crystal oscillator output connection 79 osc1 i crystal oscillator input connection 80 cs i set to high to enable ES51997 . set to low to enter sleep mode 81 io_ctrl i mpu i/o level low setting. connect to dgnd or v - . 82 bzout i buzzer frequency output . normal low state. 83 nc - not connected 84 data_new o new adc data ready 85 sclk i seri al clock input 86 s d ata i o serial data input/output 87 c+ o positive capacitor connection for on - chip dc - dc converter. 88 c - o negative capacitor connection for on - chip dc - dc converter. 89 l b at i low battery configuration input. 90 v - p negative supp ly voltage. 91 v - p negative supply voltage. 92 upvcc p switch 5 for function selection. 93 v+ o output of on - chip dc - dc converter. 94 v+ o output of on - chip dc - dc converter. 95 dgnd g digital ground. 96 agnd g analog ground. 97 agnd g analog grou nd. 98 ch+ io positive connection for reference capacitor of high - speed a/d. 99 ch - io negative connection for reference capacitor of high - speed a/d. 100 cih o high - speed integrator output. connect to integral capacitor.
v er. 1. 7 12/01/12 5 es519 9 7 (60 0 00counts) dmm analog front end absolute maximum ratings char acteristic rating supply voltage (v - to agnd) - 4v analog input voltage & extsrc pin v - - 0.6 to v+ +0.6 v+ v+ (agnd/dgnd+0.5v) agnd/dgnd agnd/dgnd (v - - 0.5v) digital input (io_ctrl=v - ) v - - 0.6 to upvcc +0.6 power dissipation. flat package 500mw op erating temperature 0 to 70 storage temperature - 5 5 to 125 electrical characteristics ta=25 , v - = - 3.0v parameter symbol test condition min. typ. max units power supply v - - 2.8 - 3. 0 - 3.2 v operating supply current in dcv mode i dd normal operation 2. 8 3.2 ma i ss in sleep mode 1 3 a sadc 2 voltage roll - over error 10m input resistor 0. 0 1 %f.s 1 f adc 3 voltage roll - over error 10m input resistor 0. 5 %f.s 1 sadc 2 v oltage nonlinearity nl v 1 best case straight line 0. 0 1 %f.s 1 fadc 3 v oltage nonlinearity nlv 2 best case straight line 1.0 %f.s 1 v oltage f ull scale range of sadc 2 va + - va - = 200mv 600 630 mv v o ltage f ull scale range of fadc 3 va + - va - = 200mv 600 mv input leak age for vr1 input - 10 1 10 p a zero input reading 10m input resistor - 000 000 +000 c ount band - gap r eference voltage v rh 100k resistor between vrh and agnd - 1. 30 - 1.2 2 - 1.1 4 v o pen circuit voltage for 6 0 0 range measurement v - v o pen circuit voltage for other measurement v rh v open c ircuit voltage for 60.00ns range measurement - 0.68 v internal pull - high to 0v current between v - pin and cs 1.2 a ac frequency response at 6. 0 00v range 1% 40 - 400 hz 5% 400 - 2000 op unity gain bandwidth gb c l =10pf r l =10m : 200 khz op slew rate at unity gain sr 3.5 v/us op input offset voltage v io 0.1 mv op input bias current i b 10 pa op input common mode voltage range v icr + 2 v
v er. 1. 7 12/01/12 6 es519 9 7 (60 0 00counts) dmm analog front end 3db frequency for lpf 4 active f 3db 3db=full (adp) 100 k hz 3db=10k (adp) 10 k hz 3db=1k (adp) 1 k hz multi - level low battery detector v t1 l b at v s . v - 2.15 v v t2 2. 03 v v t 3 1. 83 v peak - hold mode pulse width acin = 4 0 ~ 400hz 1000 us stbeep comparator in diode mode ovx to sgnd +9 mv stbeep comparator in cont. mode ovx to sgnd - 7 mv hcf detection voltage vr 2 - vr5 1 100 mv frequency input sensitivity ( freq ) fin s quare wave with d uty cycle 40 - 60% 500 mvp frequency input sensitivity ( freq ) fin s ine wave 400 mvrms ref erence voltage temperature coefficient tc rf 100k resister between vrh 0 ES51997 built - in 3 rd order low pass filter available for ac mode 5. gain calibration is necessary for higher accuracy
v er. 1. 7 12/01/12 7 es519 9 7 (60 0 00counts) dmm analog front end ac electrical characteristics parameter symbol min. typ. max. unit sclk clock frequency f sclk - - 100 khz sclk clock time l t low 4.7 - - us slck clock time h t high 4.0 - - sdata output delay time t aa 0.1 - 3.5 sdata output hold time t dh 100 - - ns start condition setup time t su.sta 4.7 - - us start condition hold time t hd.sta 4.0 - - da ta input setup time t s u . d at 200 - - ns data input hold time t hd.dat 0 - - stop condition setup time t su.sto 4.7 - - us sclk/sdata rising time t r - - 1.0 sclk/sdata falling time t f - - 0.3 bus release time t buf 4.7 - - eoc setup time in read mode t su.eoc 0 ns eoc hold time in read mode t hd.eoc 0 - - ns mpu i/o timing diagram sclk s d ata i n sdata out
v er. 1. 7 12/01/12 8 es519 9 7 (60 0 00counts) dmm analog front end function description 1. mpu serial i/o function overview 1.1 introduction ES51997 configures a 3 - wire serial i/o interface to external microprocessor unit (mpu) . the sdata pin is bi - directional and sclk & data_new are unilateral. the sdata pin is configured by open - drain circuit design. the data_new is used to check the data buffer of adc ready or not. when the adc conversion cycle is finished, the data_new pin w ill be pulled high until mpu send a valid read command to ES51997. after the first id byte is confirm ed , the data_new will be driven to low until the next adc conversion finished again. the data communication protocol is shown below. t h e write protocol is configured by an id byte with four command bytes. t h e read protocol is configured by an id byte with ten data bytes. write command : id byte, write c ontrol byte1, write c ontrol byte2, write c ontrol byte3, write c ontrol byte4 read command : id byte, read d ata byte1, read d ata byte2 ~ read d ata byte9, read d ata byte10 1 1 0 0 0 1 write a c k a c k a c k a c k start bit stop bit 0 b u z a c k 1 1 0 0 0 1 write a c k a c k a c k a c k start bit stop bit 0 b u z a c k a c k 1 1 0 0 0 1 a c k start bit stop bit a c k a c k a c k a c k n a k read 1 b u z 1 1 0 0 0 1 a c k start bit stop bit a c k a c k a c k a c k n a k read 1 b u z sclk sdata data_new adc data ready next adc data ready 1 1 0 0 1 0 id code confirmed 1 read command start bit stop bit id code sclk sdata data_new adc data ready next adc data ready 1 1 0 0 1 0 id code confirmed 1 read command start bit stop bit id code
v er. 1. 7 12/01/12 9 es519 9 7 (60 0 00counts) dmm analog front end the id byte of ES51997 is header of 110010 followed by a buzzer on/off control bit and r/w bit. the start/stop bit definition is shown on the diagram below. 1.2 rea d/write command description the write command includes one id byte with four command bytes. if the valid write id code is received by ES51997 at any time , the write command operation will be enabled. the next table shows the content of write command. by te b it7 b it6 b it5 b it4 b it3 b it2 b it1 b it0 id 1 1 0 0 1 0 buz r/w=0 w1 shbp f 3 f 2 f 1 f 0 q 2 q 1 q 0 w2 b0 b1 b2 0 0 fq 2 fq1 fq 0 w3 ac 0 0 ext 0 lpf 1 lpf 0 rp w4 peak pcal 0 0 0 op 0 op1 ext_adp auxiliary low - resistance detection control bit for continuity and diode modes: shbp measurement function control bit: f 3 /f 2/f 1/f 0 range control bit for v/a/r/c modes : q 2 /q1/q 0 range control bit for freq mode : fq 2 /fq1/fq 0 buzzer frequency selection: b 2 /b1/b 0 buzzer driver on/off control bit: buz ac mode control enab le bit: ac peak/calibration mode enable bit: peak/pcal 3db bw for low - pass - filter selection: lpf 1 /lpf 0 external source for diode mode control bit: ext op configuration control bit: op 1/op 0 frequency mode input resistance control bit or conductance mode con trol bit : rp adp mode control bit: ext_adp
v er. 1. 7 12/01/12 10 es519 9 7 (60 0 00counts) dmm analog front end the read command includes one id byte with ten data bytes. when data_new is ready 1 , mpu could send the read data command to get the result of adc conversion (d0/d1/d2/d3) 2 or status flag from ES51997. the nex t table shows the content of read command. byte b it7 b it6 b it5 b it4 b it3 b it2 b it1 b it0 id 1 1 0 0 1 0 buz r/w=1 r1 asign bsign pmax pmin bts0 bts1 sta0 alarm r2 hf lf l duty sta1 f_ fin d0:0 d0:1 d0:2 r3 d0:3 d0:4 d0:5 d0:6 d0:7 d0:8 d0:9 d0:10 r4 d0:1 1 d0:12 d0:13 d0:14 d0:15 d0:16 d0:17 d0:18 r5 d1:0 d1:1 d1:2 d1:3 d1:4 d1:5 d1:6 d1:7 r6 d1:8 d1:9 d2:0 d2:1 d2:2 d2:3 d2:4 d2:5 r7 d2:6 d2:7 d2:8 d2:9 d2:10 d2:11 d2:12 d2:13 r8 d2:14 d2:15 d2:16 d2:17 d2:18 d3:0 d3:1 d3:2 r9 d3:3 d3:4 d3:5 d3:6 d3: 7 d3:8 d3:9 d3:10 r10 d3:11 d3:12 d3:13 d3:14 d3:15 d3:16 d3:17 d3:18 1 note: data_new will be active with d1 data updated when one fast adc (fadc) conversion finished. if mcu access slow adc output only, ten fadc conversion cycle delay is necessary. d at a_new for frequency or capacitance mode will be active when d0 or d3 data ready. 2 note: d0/d1/d2/d3 all are binary code format. d0 is sadc output and d1 is fadc output . the maximum data is 63 0 00 counts for sadc and 604 counts for fadc. the maximum counts f or peak mode is 103 0 00, so d0 bit 1 7 - 18 could be ignored.. the adc data output for measurement mode: f3/f2/f1/f0 f 3 f 2 f 1 f 0 measurement mode read data bytes 0 0 0 0 v mode d0(0:18), d1(0:9) 0 0 0 1 ac v + hz (%) mode d0(0:18), d1(0:9), d2 (0:18) , d3(0:18) 0 0 1 0 a mode d0(0:18), d1(0:9) 0 0 1 1 ac a + hz (%) mode d0(0:18), d1(0:9), d 2 (0:18) , d3(0:18) 0 1 0 0 res istance mode d0(0:18), d1(0:9) 0 1 0 1 cont inuity mode d0(0:18), d1(0:9) 0 1 1 0 diode mode d0(0:18), d1(0:9) 0 1 1 1 f + duty mode d0(0:18), d2(0:18), d3(0:18) 1 0 0 0 cap acitance mode d0(0:18) 1 0 0 1 adp mode d0(0:18), d1(0:9) 1 0 1 0 adp + hz (%) mode d0(0:18), d1(0:9), d 2 (0:18) , d3(0:18)
v er. 1. 7 12/01/12 11 es519 9 7 (60 0 00counts) dmm analog front end buzzer frequency selection: b2/b1/b0 b2 b1 b0 buzzer frequency 0 0 0 1.00khz 0 0 1 1.33khz 0 1 0 2.00khz 0 1 1 2.22khz 1 0 0 2.67khz 1 0 1 3.08khz 1 1 0 3.33khz 1 1 1 4.00khz set b2 - b0 properly to get the target frequency. use buz control bit to enable/disable the buzout (pin82) driver output. if mpu control buz only, it is available to set i d byte with ending of stop bit. a c k 1 1 0 1 0 0 0 start bit stop bit r /w buzzer off a c k 1 1 0 1 0 0 0 start bit stop bit r /w buzzer off 1 1 1 1 0 0 0 start bit stop bit r /w buzzer on 1 1 1 1 0 0 0 start bit stop bit r /w buzzer on
v er. 1. 7 12/01/12 12 es519 9 7 (60 0 00counts) dmm analog front end status flags for measurement mode: = function available measurement mode asign bsign pmax pmin bts0 bts1 alarm v mode ac v + hz mode a mode ac a + hz mode res. mode cont. mode diode mode f + duty mode cap. mode adp mode adp + hz mode measurement mode hf lf l duty sta 0 sta 1 f_ fin v mode v + hz mode a mode a + hz mode res. mode cont. mode diode mode f + duty mode cap. mode adp mode adp + hz mode description of status flags: asign: sign bit of sadc output ( - 1 * d0 if asign=1 ) bsign: sign bit of fadc output ( - 1 * d1 if bsign=1 ) pmax: indicates d0 outpu t is the voltage of the peak maximum capacitor (pin 62) pmin: indicates d0 output is the voltage of the peak minimum capacitor (pin 61) bts0/bts1: m ulti - level battery voltage indication alarm: large capacitor in dication /high crest factor signal detection in acv mode hf: higher frequency indication for hz mode lf: lower frequency indication for hz mode ld uty: low duty indication for hz + duty mode sta0/sta1: divider indication for hz mode sta0: status flag for capacitor discharging mode f_fin: measurement cycl e finished for hz mode
v er. 1. 7 12/01/12 13 es519 9 7 (60 0 00counts) dmm analog front end 1.3 power & i/o level selection t he ES51997 provide a flexible i/o level setting for different mpu system configuration. the up_vcc should be connected to the same potential of external vcc of mcu. the up_vcc is allowed to be set betwe en dgnd ~ v+. the io_ctrl pin selects the vss level of mcu. if io_ctrl is set to dgnd, the vss level of mcu is the same as dgnd. if io_ctrl is set to v - , the vss level of mcu is the same as v - .
v er. 1. 7 12/01/12 14 es519 9 7 (60 0 00counts) dmm analog front end 2. operating modes 2.1. voltage mea surement mpu send write command to select the voltage measurement function. t he hz mode measurement is available to be enabled with the acv function (set ac bit to 1) simultaneously. the measured signal is applied to vr1 terminal (pin25) through 10m ? . se e the next table of function command: f 3 f 2 f 1 f 0 ac measurement mode read data bytes 0 0 0 0 0 dc v mode d0(0:18), d1(0:9) 0 0 0 0 1 acv mode d0(0:18), d1(0:9) 0 0 0 1 1 ac v + hz (%) mode d0(0:18), d1(0:9), d 2 (0:18) , d3(0:18) note 1 : d0/d1/ d2/ d3 all are binary format. asign/bsign are the sign bit of d0/d1, respectively. note2: see peak mode (section 2.10) also . range control for voltage mode (acv/dcv) q 2 q1 q 0 full scale range divider ratio resister connection 0 0 0 6 0 0. 0 0mv 1 vr1 (10m ? ) 0 0 1 6. 0 0 0 0v 1/10 vr2 (1.111m ? ) 0 1 0 6 0 .0 0 0v 1/100 vr3 (101k ? ) 0 1 1 6 0 0. 0 0v 1/1000 vr4 (10.01k ? ) 1 0 0 1000 .0 v 1/10000 vr5 (1k ? ) frequency r ange control for acv+hz (%) mode fq 2 fq1 fq 0 full scale range 0 0 0 60.00hz 0 0 1 600.0hz 0 1 0 6.00 0khz 0 1 1 60.00khz duty cycle 20% ~ 80% note: see frequency /duty mode (section 2.8) also a larm bit at voltage mode is used for high crest factor (hcf) signal detection . if mpu check the alarm status flag active when data and range are stable, it shoul d consider the mak ing the existing range up to avoid the signal clamping s a tu r ation caused by hcf signal. there is high er peak voltage with lower rms value for hcf signal . so if the range is up according to the alarm bit, mcu should set the lower under - lim it counts temporarily to avoid the ranging unstable for this case.
v er. 1. 7 12/01/12 15 es519 9 7 (60 0 00counts) dmm analog front end 2.2 current measurement mpu send write command to select the current measurement function. t h e hz mode measurement is available to be enabled with the aca function (set ac bit to 1) simulta neously. the measured signal is applied to ivsl/ivsh terminals (pin37- 38). see the next table of function command: f 3 f 2 f 1 f 0 ac measurement mode read data bytes 0 0 1 0 0 dca mode d0(0:18), d1(0:9) 0 0 1 0 1 aca mode d0(0:18), d1(0:9) 0 0 1 1 1 aca + hz (%) mode d0(0:18), d1(0:9), d 2 (0:18) , d3(0:18) note 1 : d0/d1/d3 all are binary format. asign/bsign are the sign bit of d0/d1, respectively. note2: see peak mode (section 2.10) also . range control for current mode (aca/dca) q2 q1 q0 full scale range inp ut terminal 0 0 0 300mv ? 60000 counts ivsl 0 0 1 300mv ? 60000 counts ivsh current measurement mode configuration example s : (max. voltage drop 300mv) 1 a 1 com ua / ma 1 0.005 0.495 49. 5 - 2 6 + 3 4 7 1 5 tl061 100k 1 . 5k v + v - v - 90k 10k v - v + ivsh ivsl zero of fset 100k 100k fuse fuse 600.00 / 6000.0ua 60.000 / 600.00ma 6a / 20a 0.1uf 0.1uf (max voltage drop = ~ 1v) 100k 100k 450 45 4.5 0.45 0.005 ma ma ua ua ua ma ivsl ivsh agnd a sgnd 0.045 2 0a 6a
v er. 1. 7 12/01/12 16 es519 9 7 (60 0 00counts) dmm analog front end frequency range control for aca+hz (%) mode fq2 fq1 fq0 full scale range 0 0 0 60.00hz 0 0 1 600.0hz 0 1 0 6.000khz 0 1 1 60.00khz duty cycle 20% ~ 80% note: see frequency mode (section 2.8) also . 2.3 low pass filter (lp f) mode for aca/acv mode a 3 rd order low pass filter with is built in ES51997 . t h e 3db bandwidth of the low pass filter could be selectable by mpu . the lpf mode is active when the lpf control bit is set to be active. when peak mode is active, the lpf mode will be disabled temporarily until the peak mode is cancelled . the lpf mode is allowed to be enabled in f + duty mode to reject high - frequency noise for sine wave input, but the 3db will be fixed at 10khz only. lp f 1 lp f 0 low pass filter effect 0 0 di sable 0 1 3db = 1khz 1 0 3db = 10khz 1 1 3db > 100khz 2.4 resistance /conductance measurement mpu send write command to select the resistance measurement function. f 3 f 2 f 1 f 0 measurement mode read data bytes 0 1 0 0 res istance mode d0(0:18), d1(0:9) note 1 : d0/d1 both are binary format. asign /bsign bits are ignored . range control for resistance mode q2 q1 q0 full scale range relative resistor equivalent value 0 0 0 6 0 0. 0 0 or1 100 0 0 1 6. 0 0 0 0k vr5 1k 0 1 0 6 0 . 0 00k vr4 || vr1 10k 0 1 1 6 0 0. 0 0k vr 3 || vr1 100k 1 0 0 6. 0 0 0 0m vr2 || vr1 1m 1 0 1 6 0. 0 0 0m vr1 10m
v er. 1. 7 12/01/12 17 es519 9 7 (60 0 00counts) dmm analog front end set rp =1 when range control is 10m ? range, the conductance mode is available. the status sta1 bit is used for converted data indication of reference voltage or input voltage. q2 q1 q0 full scale range relative resistor equivalent value 1 0 1 60.00ns vr1 10m the maximum displayed count is 6000 and the resolution should be 0.01ns. the mcu should check the status bit sta1 and d0 simultaneously. when sta1=1 the d0 data should be v d1 . if sta1=0, then the d0 data should be v d2 . the dut conductance value could be calculated by simple formula.
v er. 1. 7 12/01/12 18 es519 9 7 (60 0 00counts) dmm analog front end 2.5 capacitance measurement mpu send write command to select the capacitance measurement function. f 3 f 2 f 1 f 0 measurement m ode read data bytes 1 0 0 0 capacitance mode d0(0:18) note 1 : d0 is binary format. asign bit is ignored. range control for capacitance mode q2 q1 q0 full scale range relative resistor measurement period 0 0 0 6. 0 0 0 0nf * - 0. 5 sec 0 0 1 6 0 .00 0 nf * ovx pin vr 0. 5 sec 0 1 0 6 0 0. 0 0 nf * - 1.25 sec 0 1 1 6. 0 0 0 0 uf * r9k / r1k 0. 4 sec max. 1 0 0 6 0 .00 0 uf * r9k / r1k 0. 5 sec max. 1 0 1 6 0 0.0 0 uf * r9k / r1k 1. 0 sec max. 1 1 0 6. 0 00 0 mf * r9k / r1k 1. 35 sec max. 1 1 1 6 0 .0 0 0mf * r9k / r1k 6 . 75 sec max. ? the displayed counts in ES51997 capacitance mode is recommended to be divided by 10. (6000 counts displayed is recommended) ? a larm bit at capacitance mode is used for increasing the ranging speed. if mpu check the alarm =1 at lower range , it could set the next range to 6 .000uf directly and the adc output should be ignored. ? sta0 status bit is used for detection of dut capacitor voltage. if sta0=1, the internal capacitor discharging mode is active and the capacitance measurement is inhibited. it is recommended to discharge the dut capacitor externally. 2.6 continuity check measurement mpu send write command to select the continuity measurement function. f 3 f 2 f 1 f 0 measurement mode read data bytes 0 1 0 1 continuity mode d0(0:18), d1(0:9) note 1 : d0/d1 both are binary format . asign/bsign bits both are ignored. continuity mode shares the same configuration with 6 00.0 0 resistance measurement circuit and support the low - resistance d ete ction . i f the stbeep output (pin64) is low, it means the low - resistance status is detected (it means the ovx terminal voltage less than - 7mv) . it could be faster than the fadc result , s o mpu could monitor the stbeep output and fadc (d1) data output make the high speed detection for short circuit detection . set shbp =1 to enable the built - in buzzer d riving automatically when stbeep is active.
v er. 1. 7 12/01/12 19 es519 9 7 (60 0 00counts) dmm analog front end 2.7 diode measurement mpu send write command to select the diode measurement function. f 3 f 2 f 1 f 0 measurement mode read data bytes 0 1 1 0 diode mode d0(0:18), d1(0:9) note 1 : d0/d1 both are binary format. asig n/bsign are the sign bit of d0/d1, respectively . diode measurement mode shares the same configuration with 6. 0000 v voltage measurement circuit and support the low - resistance d ete ction . if the stbeep output (pin64) is low, it means the low - resistance statu s is detected (it means the ovx terminal voltage less than 9mv) . it could be faster than the fadc result, so mpu could monitor the stbeep output and fadc (d1) data output make the high speed detection for short circuit detection . set shbp =1 to enable the b uilt - in buzzer driving automatically when stbeep is active. the default source voltage at diode mode is the same as v+ potential. mpu could set the control bit ext =1 to change the source voltage to external source. the external voltage source (positive or negative) input applied from extsrc (pin16). the available external source range should be from v+ to v - .
v er. 1. 7 12/01/12 20 es519 9 7 (60 0 00counts) dmm analog front end 2.8 frequency /duty cycle mode measurement t h e default typical input impedance of frequency with dut y cycle mode is 1m ? . the mpu could set control bit rp =1 to change the input impedance down to 100k ? . mpu send write command to select the frequency/duty cycle measurement function. f 3 f 2 f 1 f 0 measurement mode read data bytes 0 1 1 1 hz + duty mode d0(0:18), d 2 (0: 18), d3 (0:18) note 1 : d0/d 2/d3 all are binary format. asign bit is ignored . note2: set lpf1 = 1 to enable the smooth function for sine wave input automatically range control for frequency mode fq2 fq1 fq0 full scale 0 0 0 6 0 .0 0 0hz 0 0 1 6 0 0.0 0 hz 0 1 0 6. 0 0 0 0k hz 0 1 1 6 0 .0 0 0khz 1 0 0 6 0 0. 0 0khz 1 0 1 6. 0 00 0 mhz 1 1 0 6 0 .00 0 mhz available minimum frequency input f min = 4.000hz frequency & duty cycle mode comput ed by d0/d2/d3 (if f_fin=1) flag sta0=1 sta0=0 range * sta1=1 sta1=0 60.0 0 0hz freq=100000 0 000/d 3 freq=40 0 0000000/d3 freq=800 0 000000/d3 6 0 0.0 0 hz freq=1000000 0 0/d3 freq=400 0 00000/d3 freq=1 600 0 00 000/d3 ** 6. 0 00 0 khz freq=2000000 0 /d3 freq=3200 0 0000/d3 freq=25 600 0 00 00/d3 *** 6 0 .00 0 khz freq=200000 0 /d3 freq=25 600 0 00 0/d3 freq=204800 0 000/d3 6 0 0.0 0 khz freq = d0 - 1 6. 0 00 0 mhz 6 0 .00 0 mhz *note: the hz measurement of ac+hz mode is recommended to support 6000 counts dis p l a yed. **note: if d3 < 40000, simple arithmetic mean is necessary to get the 0.01hz resolution ***note: if d3 < 50000, simple arithmetic mean i s necessary to get the 0.0001 khz resolution
v er. 1. 7 12/01/12 21 es519 9 7 (60 0 00counts) dmm analog front end status flag lduty=1 lduty=0 duty cycle (<60khz) 10000 - d2*10000/d3 d2*10000/d3 the status flag f_fin indicate the frequency input signal available (> f min ) or not. if the computed result less than f min , th e frequency /duty cycle readings should be set to zero. the status flags hf & lf are used for fast judgment of proper range. if frequency input is larger than 7 khz, hf will be active. if frequency input is floating or frequency detected too low , lf will be active. auto range consideration for mpu by using status flags of frequency mode flag f_fin=0 f_fin= 1 f_fin=1 range lf=0 lf=1 * hf =lf =0 hf=1 ** 60.0 0 0hz 600.00hz 6. 0 00 0 khz data and range is not necessary to be updated hz/duty=0 change range depends on data computed set range to 60.00 0khz range set range to 60.00 0hz range 6 0 .0 0 0khz 600.0 0khz 6.000 0mhz 60.00 0mhz change range depends on data computed *note: lf=1 @ 60hz range implies the frequency is not available to be measured. t h e h z/duty readings should be set to zero. * *note: when acv+hz / aca+hz / adp+hz mode is selected, the hf status should be ignored . change range depends on data calcu lation result. duty cycle mode range (input sensitivity > 2 vpp @ duty cycle = 5 .0 % & 95 .0% ) freq. range duty range * 60. 0 00hz 600.0 0hz 5.0% - 95.0% 6.000 0khz 10.0 % - 90.0% 60.00 0khz 20.0% C 80.0% * note: duty range for ac+hz(%) is 20% ~ 80%.
v er. 1. 7 12/01/12 22 es519 9 7 (60 0 00counts) dmm analog front end 2.9 a dp mode mpu send write command to select the adp mode measurement function. t h e hz mode measurement is available to be enabled with the adp ac function (set ac bit to 1) simultaneously. the measured signal is applied to adp terminal (pin39). t h e signal full scale is 600mv for dc mode and 600mvrms for ac mode. see the next table of function command: f 3 f 2 f 1 f 0 ac measurement mode read data bytes 1 0 0 1 0 adp dc mode d0(0:18), d1(0:9) 1 0 0 1 1 adp ac mode d0(0:18), d1(0:9) 1 0 1 0 1 adp + hz (%) mode d0(0:18), d1(0:9), d 2 (0:18) , d3(0:18) note 1 : d0/d1/d3 all are binary format. asign/bsign are the sign bit of d0/d1, respectively. note2: see peak mode (section 2.10) also . frequency range control for adp+hz (%) mode fq2 fq1 fq0 full scale range 0 0 0 60.00hz 0 0 1 600.0hz 0 1 0 6.000khz 0 1 1 60.00khz duty cycle 20% ~ 80% note: see frequency mode (section 2.8) also if mpu set the control bit ext _adp =1, the voltage on extsrc pin could be switched to adp terminal internally. it is helpful for a voltage pulled application of adp mode. adc in+ adc in - sgnd ext_adp adp_n e adn adn sgnd ext_adp adp_n e
v er. 1. 7 12/01/12 23 es519 9 7 (60 0 00counts) dmm analog front end 2.10 peak - hold measurement mode ES51997 provide s a p eak h old function to capture the real peak value for voltage or current measurement mode. in a case of a 1v sine wave input voltage, the p eak h old function gets a maximum peak value of 1.414v and minimum peak value of C 1.414v ideally . set the control bit peak =1 to force the ES51997 enter ing peak measurement mode. peak hold function is divided into two parts of peak maximum and peak minimum conversion. high resolution sadc performs peak maximum and peak minimum conversion in turn, not at the same time. the status flag pmax or pmin shows which type the peak value is . if pmax=1(pmin=1), the sadc output d0 is the conversion data on pmax (pmin) terminals (pin 61/62) . the mpu should make the comparison procedure to get the maximum value of pmax data and minimum value of pmin data. the m ax counts for d0 is 1030 00. p eak c alibration mode at peak - hold measurement mode, the offset voltage of internal operation amplifier will cause an error. to obtain a more accurate value, th e offset error mu st be canceled. ES51997 provides the p eak c alibration feature to remove the influence on accuracy by internal offset voltage. set the control bit pcal =1 to enter p eak c alibration mode. when pcal mode is active, the sadc of ES51997 will output the calibration value of peak maximum and minimum conversion in turn. the offset value s should be memorized respectively and deducted from the data of pmax/pmin at the normal peak measurement mode. set pcal=1 or peak=1 status indication pmax=1, pmin=0 pmax=0, pmin=1 adc data v pmax .c v pmin .c v pmax.c and v pmin.c are not the real - time value of peak - hold voltage . they are the voltage stored on terminal capacitor (pin61 - 62) . because the capacitor will be self - discharging, so mcu need to compare the v pmax.c & v pmin.c respectively and memorize the maximum and minimum peak values in turn.
v er. 1. 7 12/01/12 24 es519 9 7 (60 0 00counts) dmm analog front end 2.11 sleep set cs pin (pin 80) to logic low to make the ES51997 enter ing the sleep mode. t he current consumption will be less than 3 ua typ ically . set cs pin to logic high or kept floating, the ES51997 will return to normal operation. 2.12 multi - level battery voltage indication the ES51997 is built - in a comparator for batter voltage indication. t he v oltage is applied to lbat pin (pin 89) vs. v - terminal. mpu could check the status bit bts 1 /bts 0 and monitor the lbat voltage status. battery voltage bts1 bst0 v lbt > v t1 1 1 v t2 < v lbt < v t1 1 0 v t3 < v lbt < v t2 0 1 v lbt < v t3 0 0 low battery co nfiguration for 9v/1.5v*4/1.5v*3 battery low battery test circuit (a) 360 k 270 k ba tt lbat v - agnd 0.1u 0v 6 v low battery test circuit (b) 470 k 180 k ba tt lbat v - agnd 0.1u 0v 9 v low battery test circuit (c) 360 k 470 k ba tt lbat v - agnd 0.1u 0v 4.5 v
v er. 1. 7 12/01/12 25 es519 9 7 (60 0 00counts) dmm analog front end 2.13 independent opamp ES51997 is built- in a n independent opamp with low drift offset using for general purpose. mpu could control the op1/op0 to change the opamp configuration: op1 op0 opamp confi guration 0 0 normal 0 1 op disable 1 0 unity gain buffer 1 1 z ero calibration independent opamp configuration normal operation + - opin+ opin - opout u + - opin+ opin - opout + - opin+ opin - opout iopp n + - opin+ opin - opout + - opin+ opin - opout u + - opin+ opin - opout + - opin+ opin - opout + - opin+ opin - opout + - opin+ opin - opout
v er. 1. 7 12/01/12 26 es519 9 7 (60 0 00counts) dmm analog front end 3. application circuit 3 .1 avg circuit 1 2 3 4 a b c d 4 3 2 1 d c b a title num b e r revision size a4 date : 24-nov-2011 sh ee t of file: f:\protel file\ka029\ka029.ddb drawn by : r7 100k r6 100k r8 100k c8 470nf +/- 10% c14 470pf +/- 10% c15 100pf +/- 10% c19 3.3nf +/- 10% r12 200 r13 2 . 2k p tc 1 2 jp1 fi n + c20 2.2uf c4 10nf v cc v + v1 - lbat9 c5 470nf sda s cl data_new v ss cs buz o ut stbeep r1 470k c2 22nf c1 22nf c13 100nf c7 220nf r9 0 r5 220k c10 220nf c6 470nf c9 47nf v r1 500 r2 11k r11 56k + c12 4.7uf c11 220nf extsrc v a+ v a- r18 100 r19 1 k r21 101k r22 1.111m r20 10.01k o vsg r23 10m c21 680pf r16 2 . 2k p tc r25 1k close to ic r17 180k o vx r15 2 . 2k p tc 1 2 jp3 insulation r14 2 . 2k p tc r24 1k o vh ovh1 ivsh ivsl a dp acvh c3 22nf r32 9k r26 1k + c22 1uf r9k r1k opin+ test5 acvl q5 q6 q7 q8 q1 q2 q3 q4 opin- hi gh v opout v r2 50k mpu v dd v ss u pvcc ( dgnd or +3v) v- or dgnd sda ta sclk data_new cs ver : 9 ES51997 sc hematic circ uit (avg) demo board schematic r35 10k v r3 10k d1 1n4148 d2 1n4148 r33 15k r34 15k test5 a di acvh a do acvl + c23 4.7uf + c25 1uf + c26 1uf c24 0.1uf r37 56k r36 56k metallized polypropylene film capacitor : c7 metallized polyester capacitor : c1 , c13 , c11 , c16 , c17 a do a di 47k v dd stbeep y1 4 mh z 1 2 jp2 vin insulation r+ + c17 10uf + c16 10uf z r2 7 . 5v v + c18 0.1uf c28 0.1uf z r1 5 . 6v v - regulator dc 3.0v c29 5pf opt i o n r39 0 v1 - close to ic sw1 sw_ rc c17 10nf c16 10nf c18 22pf bufh 1 caz h 2 nc 3 cl+ 4 cl- 5 ci l 6 caz l 7 bufl 8 raz 9 o hmc3 10 o hmc2 11 o hmc1 12 v rh 13 v a+ 14 v a- 15 extsrc 16 o r1 19 v r5 20 v r4 21 v r3 22 v r2 23 o vsg 24 v r1 25 ivsh 37 ivsl 38 a dp 39 acvl 43 acvh 44 a di 45 a do 46 test5 47 sgn d 36 ca- 48 ca+ 49 r9k 55 r1k 56 o vx 26 o vh 27 lpc1 57 lpc2 58 lpc3 59 lpfout 60 nc 54 nc 52 nc 53 stbeep 64 freq 65 nc 66 nc 67 nc 68 nc 69 nc 70 nc 71 nc 72 nc 73 nc 74 nc 75 nc 76 nc 77 cih 1 00 o sc2 78 o sc1 79 cs 80 i o_ c t rl 81 bzout 82 nc 83 data_new 84 s cl k 85 sda t a 86 c+ 87 c- 88 l ba t 89 v- 90 v- 91 u pv cc 92 v+ 93 v+ 94 dgnd 95 agnd 96 agnd 97 ch+ 98 ch- 99 ovh1 28 opin- 40 opin+ 41 opout 42 o hm c4 50 nc 51 p mi n 61 p ma x 62 cpki n 63 nc 17 nc 18 nc 35 nc 34 nc 29 nc 30 nc 31 nc 32 nc 33 u1 ka029-997 c27 220pf cl os e t o ic
v er. 1. 7 12/01/12 27 es519 9 7 (60 0 00counts) dmm analog front end 3 .2 rms circuit (es636) 1 2 3 4 a b c d 4 3 2 1 d c b a title num b e r revision size a4 date : 24-nov-2011 sh ee t of file: f:\protel file\ka029\ka029.ddb drawn by : r7 100k r6 100k r8 100k c14 470pf +/- 10% c15 100pf +/- 10% c19 3.3nf +/- 10% r12 200 r13 2 . 2k p tc 1 2 jp1 fi n + c20 2.2uf c4 10nf v cc v + v1 - lbat9 c5 470nf sda s cl data_new v ss cs buz o ut stbeep r1 470k c2 22nf c1 22nf c13 100nf c7 220nf r9 0 r5 220k c10 220nf c6 470nf c9 47nf v r1 500 r2 11k r11 56k + c12 4.7uf c11 220nf extsrc v a+ v a- r18 100 r19 1 k r21 101k r22 1.111m r20 10.01k o vsg r23 10m c21 680pf r16 2 . 2k p tc r25 1k close to ic r17 180k o vx r15 2 . 2k p tc 1 2 jp3 insulation r14 2 . 2k p tc r24 1k o vh ovh1 ivsh ivsl a dp acvh r32 9k r26 1k + c22 1uf r9k r1k opin+ q5 q6 q7 q8 q1 q2 q3 q4 opin- hi gh v opout v r2 50k sw2 a cv rm s mpu v dd v ss u pvcc ( dgnd or +3v) v- or dgnd sda ta sclk data_new cs ver : 9 ES51997 sc hematic circ uit (trms) demo board schematic c8 470nf +/- 10% c3 22nf metallized polypropylene film capacitor : c7 metallized polyester capacitor : c1 , c13 , c11 , c16 , c17 a di 47k v dd bufh 1 caz h 2 nc 3 cl+ 4 cl- 5 ci l 6 caz l 7 bufl 8 raz 9 o hmc3 10 o hmc2 11 o hmc1 12 v rh 13 v a+ 14 v a- 15 extsrc 16 o r1 19 v r5 20 v r4 21 v r3 22 v r2 23 o vsg 24 v r1 25 ivsh 37 ivsl 38 a dp 39 acvl 43 acvh 44 a di 45 a do 46 test5 47 sgn d 36 ca- 48 ca+ 49 r9k 55 r1k 56 o vx 26 o vh 27 lpc1 57 lpc2 58 lpc3 59 lpfout 60 nc 54 nc 52 nc 53 stbeep 64 freq 65 nc 66 nc 67 nc 68 nc 69 nc 70 nc 71 nc 72 nc 73 nc 74 nc 75 nc 76 nc 77 cih 1 00 o sc2 78 o sc1 79 cs 80 i o_ c t rl 81 bzout 82 nc 83 data_new 84 s cl k 85 sda t a 86 c+ 87 c- 88 l ba t 89 v- 90 v- 91 u pv cc 92 v+ 93 v+ 94 dgnd 95 agnd 96 agnd 97 ch+ 98 ch- 99 ovh1 28 opin- 40 opin+ 41 opout 42 o hm c4 50 nc 51 p mi n 61 p ma x 62 cpki n 63 nc 17 nc 18 nc 35 nc 34 nc 29 nc 30 nc 31 nc 32 nc 33 u1 ES51997 stbeep y1 4 mh z 1 2 jp2 vin insulation r+ + c17 10uf + c16 10uf z r2 7 . 5v v + c18 0.1uf c28 0.1uf z r1 5 . 6v v - regulator dc 3.0v c30 5pf opt i o n r37 0 v1 - close to ic sw1 sw_ rc c17 10nf c16 10nf c18 22pf acvh vin 1 en 2 - vs 3 cav 4 db 5 buf out 6 buf i n 7 i o ut 8 rl 9 common 10 nc 11 nc 12 nc 13 + vs 14 u2 es63 6 + c23 4.7uf + c24 2.2uf v r4 500k r34 10k r33 200 + c25 22uf v r3 500 a di r3 200k + vs - vs - vs + vs + vs + c26 10uf + c27 10uf + vs - vs cl os e t o i c c29 220pf cl os e t o ic
v er. 1. 7 12/01/12 28 es519 9 7 (60 0 00counts) dmm analog front end 4. package information 4.1 100l l qfp outline drawin g 4.2 dimension parameters

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