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description the CXD2507AQ is a digital signal processor for cd players and is equipped with the following functions. features digital pll efm frame sync protection sec strategy-based error correction subcode demodulation, crc checking digital spindle servo servo auto-sequencer asymmetry compensation circuit digital audio interface output 16k ram double-speed playback capability new microcomputer interface circuit absolute maximum ratings supply voltage v dd ?.3 to +7.0 v supply voltage variatio n v s s ?av ss ?.3 to +0.3 v v d d ?av dd ?.3 to +0.3 v input voltage v i ?.3 to +7.0 v v in v ss ?0.3 to v dd + 0.3 v output voltage v o ?.3 to +7.0 v storage temperature tstg ?0 to +125 ? recommended operating conditions supply voltage v dd 4.5 to 5.5v (double-speed playback) 3.5 to 5.5v (normal-speed playback) 3.0 to 5.5v (low power consumption, special playback mode) * operating temperature topr ?0 (min. ) 75 (max.) ? * when the internal operation of the lsi is set to double-speed mode and the crystal oscillation frequency is halved, normal-speed playback results. ? 1 CXD2507AQ e9460 1 a11 cd digital signal processor sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 64 pin qfp (plastic) -l01 -l121
?2 CXD2507AQ pin configuration 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 1 mnt1 mnt3 xrof c2po rfck gfs v dd xpck xugf gtop bck pcmd lrck xlat clok sein cnin dato xlto v dd clko spoa spob spoc spod xlon data xrst sens mute sqck sqso exck sbso scor vss wfck emph dout c4m fstt xtsl xtao xtai mnt0 fok mon mdp mds lock test filo fili pco vss avss cltv av dd rf bias asyi asyo asye wdck
?3 CXD2507AQ block diagram 2 3 4 5 7 8 9 12 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 43 44 45 46 47 48 49 51 52 53 54 55 56 57 59 60 64 1 rfck c2po mute wdck lrck pcmd bck dout mnt0 mnt1 mnt3 wfck emph gfs xugf gtop xtsl xtao xtai fstt c4m rf asyi asyo asye bias xpck filo fili pco cltv fok sein cnin dato xlto clko sens data xlat clok spoa to d xlon scor sbso exck sqso sqck mon mdp mds lock xrof d/a interface digital out digital clv error corrector 16k ram cpu interface sub code processor efm demodulator clock generator asymmetry corrector digital pll servo auto sequencer
?4 CXD2507AQ pin description pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 fok mon mdp mds lock test filo fili pco v ss av ss cltv av dd rf bias asyi asyo asye wdck lrck pcmd bck gtop xugf xpck v dd gfs rfck c2po xrof mnt3 mnt1 mnt0 xtai xtao xtsl i o o o o i o i o i i i i o i o o o o o o o o o o o o o o i o i 1, 0 1, z, 0 1, z, 0 1, 0 analog 1, z, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 focus ok input. used for sens output and the servo auto sequencer. spindle motor on/off control output. spindle motor servo control. spindle motor servo control. gfs is sampled at 460hz; when gfs is high, this pin outputs a high signal. if gfs is low eight consecutive samples, this pin outputs low. test pin. normally gnd. master pll (slave = digital pll) filter output. master pll filter input. master pll charge pump output. gnd. analog gnd. master vco control voltage input. analog power supply (+5v). efm signal input. constant current input of asymmetry circuit. asymmetry comparator voltage input. efm full-swing output (low = vss, high = v dd ). low: asymmetry circuit off; high: asymmetry circuit on. d/a interface. word clock f = 2fs. d/a interface. lr clock f = fs. d/a interface. serial data (two's complement, msb first). d/a interface. bit clock. gtop output. xugf output. xplck output. power supply (+5v). gfs output. rfck output. c2po output. xraof output. mnt3 output. mnt1 output. mnt0 output. 16.9344mhz crystal oscillation circuit input, or 33.8688mhz input. 16.9344mhz crystal oscillation circuit output. crystal selection input. set low when the crystal is 16.9344mhz, high when 33.8688mhz. symbol i/o description
?5 CXD2507AQ notes) 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 fstt c4m dout emph wfck v ss scor sbso exck sqso sqck mute sens xrst data xlat clok sein cnin dato xlto v dd clko spoa spob spoc spod xlon o o o o o o o i o i i o i i i i i i o o o i i i i o 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 2/3 frequency divider output for pins 34 and 35. 4.2336mhz output. digital out output. outputs high signal when the playback disc has emphasis, low signal when no emphasis. wfck output. gnd. outputs high signal when either subcode sync s0 or s1 is detected. sub p to w serial output. sbso readout clock input. subq 80-bit serial output. sqso readout clock input. high: mute; low: release sens output to cpu. system reset. reset when low. serial data input from cpu. latch input from cpu. serial data is latched at the falling edge. serial data transfer clock input from cpu. sense input from ssp. track jump count signal input. serial data output to ssp. serial data latch output to ssp. latched at the falling edge. power supply (+5v). serial data transfer clock output to ssp. microcomputer extended interface (input a). microcomputer extended interface (input b). microcomputer extended interface (input c). microcomputer extended interface (input d). microcomputer extended interface (output). pin no. symbol i/o description pcmd is two's complement output of msb first. gtop is used to monitor the frame sync protection status. xugf is the negative pulse for the frame sync derived from the efm signal. it is the signal before sync protection. xplck is the inverse of the efm pll clock. the pll is designed so that the falling edge and the efm signal transition point coincide. gfs goes high when the frame sync and the insertion protection timing match. rfck is derived from the crystal accuracy. this signal has a cycle of 136. c2po represents the data error status. xraof is generated when the 16k ram exceeds the 4f jitter margin.
?6 CXD2507AQ electrical characteristics dc characteristics (v dd = av dd = 5.0v 5%, v ss = av ss = 0v, topr = ?0 to +75?) input voltage (1) input voltage (2) input voltage (3) output voltage (1) output voltage (2) output voltage (3) item high level input voltage low level input voltage high level input voltage low level input voltage high level output voltage low level output voltage high level output voltage low level output voltage high level output voltage low level output voltage input leak current tri-state pin output leak current input voltage v ih (1) 0.7v dd 0.3v dd 0.2v dd v dd 0.4 v dd 0.4 v dd 0.4 ? ? v dd v il (1) v ih (2) v il (2) v ss 0.8v dd v dd ?0.8 0 v dd ?0.8 0 v dd ?0.5 0 v oh (1) v ol (1) v oh (2) v ol (2) v oh (4) v ol (4) i li i lo v in (3) v v v v v v v v v v ? ? v * 1 * 2 * 4 * 5 * 6 * 1 , * 2 , * 3 * 7 * 3 i oh = ?ma i ol = 4ma i oh = ?ma i ol = 4ma i oh = ?.28ma i ol = 0.36ma v i = 0 to 5.25v v o = 0 to 5.25v analog input schmitt input conditions min. typ. max. unit applicable pins applicable pins * 1 xtsl, data, xlat * 2 clok, xrst, exck, sqck, mute, fok, sein, cnin, asye * 3 cltv, fili, rf * 4 mdp, pco * 5 asyo, dout, fstt, c4m, c16m, sbso, sqso, scor, emph, mon, lock, wdck, dato, clko, xlto, sens, mds, lrck, wfck, pcmd, bck, gtop, xugf, xpck, gfs, rfck, xrof, mnt0, mnt1, mnt3 * 6 filo * 7 mds, mdp, pco
?7 CXD2507AQ ac characteristics 1) xtai and vcoi pins (1) when using self-oscillation (topr = ?0 to +75?, v dd =av dd = 5.0v 5%) (2) when inputting pulses to xtai and vcoi (topr = ?0 to +75?, v dd = av dd = 5.0v 5%) (3) when inputting sine waves to xtai and vcoi pins via a capacitor (topr = ?0 to +75?, v dd = av dd = 5.0v 5%) oscillation frequency f max 7 34 mhz item symbol min. typ. max. unit high level pulse width low level pulse width pulse cycle input high level input low level rise time, fall time t whx 13 500 ns t wlx 13 500 ns t cx 26 1,000 ns v ihx v dd ?1.0 v v ilx 0.8 v t r , t f 10 ns item symbol min. typ. max. unit input amplitude v 1 2.0 v dd + 0.3 vp-p item symbol min. typ. max. unit t r t f t whx t wlx t cx v ilx v ihx 0.1 v ihx 0.9 v ihx xtai v dd /2
?8 CXD2507AQ 2) clok, data, xlat, cnin, sqck exck pins (v dd = av dd = 5.0v 5%, v ss = av ss = 0v, topr = ?0 to +75?) clock frequency clock pulse width setup time hold time delay time latch pulse width exck sqck frequency exck sqck pulse width f ck t wck t su t h t d t wl f t t wt 750 300 300 300 750 750 * 0.65 0.65 * mhz ns ns ns ns ns mhz ns item symbol min. typ. max. unit t wck t wck 1/f cx t h t su t wl t d 1/f r t wt t wt t h t su clk data xlt exck cnin sqck sbso sqso * in low power consumption and special playback mode, when sl0 = sl1 = 1, the maximum operating frequency for sqck is 300khz and the minimum pulse width is 1.5s. description of functions 1. cpu interface and instructions cpu interface this interface uses data, clok, and xlat to set the modes. the interface timing chart is shown below. information on each address and the data is provided in table 1-1. the internal registers are initialized by a reset when xrst = 0; the initialization data is shown in table 1-2. note) when xlat is low, exck and sqck must be set high. 750ns or more d1 data address d2 d3 d0 d1 d2 d3 750ns or more 300ns max valid clok data xlat registers 4 to e
?9 CXD2507AQ cd2507 command table table 1-1 register name 4 auto sequence blind (a, e), overflow (c) brake (b) kick (d) auto sequence (n) track jump count setting mode specification function specification audio ctrl serial bus ctrl servo coefficient setting clv ctrl clv mode test mode 0 0 1 1 1 1 1 1 1 1 command address data 1 d3 d2 as3 as2 as1 as0 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 data 2 data 3 data 4 5 0 0 1 1 0 0 0 0 1 1 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 1 0 1 0 1 1 1 0 2048 0 1024 0 512 0 256 128 64 32 16 8 4 2 1 7 6 8 9 a b c d e f dclv pwmmod gain mdp1 0.18ms 0.09ms 0.05ms 0.02ms 0.36ms 0.18ms 0.09ms 0.05ms 11.6ms 5.8ms 2.9ms 1.45ms 32768 16384 8192 4096 cd- rom wsel 0 0 0 0 0 mute att sl1 sl0 cpusr 0 tb tp cm3 cm2 cm1 cm0 gain mdp0 gain mds1 gain mds0 clvs gain dout mute dout on/off dspb on/off don't use values shown as "0" in the above table must be sent as "0".
?10 CXD2507AQ cxd2507 reset initialization table 1-2 4 auto sequence blind (a, e), overflow (c) brake (b) kick (d) auto sequencer (n) track jump count setting mode specification function specification audio ctrl serial bus ctrl servo coefficient setting clv ctrl clv mode test mode 0 0 1 1 1 1 1 1 1 1 command address data 1 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 data 2 data 3 data 4 5 0 0 1 1 0 0 0 0 1 1 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 7 6 8 9 a b c d e f don't use register name
?11 CXD2507AQ 1-1. the meaning of the data for each address is explained below. $4x commands rxf = 0 forward rxf = 1 reverse when the focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted. when the track jump/move commands ($48 to $4f) are canceled, $25 is sent and the auto sequence is interrupted. $5x commands auto sequence timer setting setting timers: a, e, c, b ex.) d2 = d0 = 1, d3 = d1 = 0 (initial reset) a = e = c = 0.11ms b = 0.23ms $6x commands auto sequence timer setting setting timer: d ex.) d3 = 0, d2 = d1 = d0 = 1 (initial reset) d = 10.15ms $7x commands auto sequence track jump/move count setting (n) this command is used to set n when a 2n track jump and an n track move are executed for auto sequence. the maximum track count is 65,535, but note that with 2n track jumps the maximum track jump count is determined by the mechanical limitations of the optical system. the number of track jump is counted according to the signals input from cnin pin. cancel focus-on 1 track jump 10 track jump 2n track jump n track move 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 rxf rxf rxf rxf command as3 as2 as1 as0 blind (a, e), over flow (c) brake (b) 0.18ms 0.36ms 0.09ms 0.18ms 0.05ms 0.09ms 0.02ms 0.05ms command d3 d2 d1 d0 kick (d) 11.6ms 5.8ms 2.9ms 1.45ms command command data 1 data 2 data 3 data 4 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 auto sequence track jump count setting d3 d2 d1 d0
?12 CXD2507AQ command mode specification cdrom dout mute dout on-off wsel d3 d2 d1 d0 command bit c2po timing cdrom = 1 cdrom = 0 1-3 1-3 cdrom mode; average value interpolation and pre-value hold are not performed. audio mode; average value interpolation and pre-value hold are performed. processing command bit dout mute = 1 dout mute = 0 digital out output is muted. (da output is not muted.) when no other mute conditions are set, digital out is not muted. processing command bit dout on-off = 1 dout on-off = 0 digital out is output from the dout pin. digital out is not output from the dout pin. processing command bit sync protection window width wsel = 1 wsel = 0 26 channel clock * 6 channel clock anti-rolling is enhanced. sync window protection is enhanced. application command data 1 function specifications 0 dspb on-off 00 d3 d2 d1 d0 data 2 0000 d3 d2 d1 d0 command bit dspb = 0 dspb = 1 normal-speed playback double-speed playback processing $8x commands * in normal-speed playback, channel clock = 4.3218mhz. $9x commands command data 1 audio ctrl 0 0 mute att d3 d2 d1 d0 command bit mute = 0 mute = 1 mute off if other mute conditions are not set. mute on. meaning command bit att = 0 att = 1 attenuation off. ?2db meaning $ax commands
?13 CXD2507AQ serial bus ctrl sl1 sl0 cpusr 0 command d3 d2 d1 d0 command bits sl1 0 0 1 1 sl0 0 1 0 1 same interface mode as the cdl40 series. sbso is output from sqso pin. in other words, subcodes p to w are read out from sqso. input the read clock to sqck. sens is output from sqso pin. each output signal is output from sqso pin. input the read clock to sqck. (see to timing chart 1-4.) processing command bits cpusr = 1 cpusr = 0 xlon pin is high. xlon pin is low. processing $bx commands this command switches the method of interfacing with the cpu. with the cdl500 series, the number of signal lines between the cpu and the dsp can be reduced in comparison with the cdl40 series. also, the error rate can be measured with the cpu. $cx commands clvs mode gain setting: gclvs clvp mode gain setting: gmdp, gmds servo coefficient setting clv ctrl ($dx) gain mdp1 gain mdp0 gain mds1 gain mds0 gain clvs gain mds1 0 0 0 0 1 1 gain mds0 0 0 1 1 0 0 gain clvs 0 1 0 1 0 1 gclvs ?2db ?db ?db 0db 0db +6db command d3 d2 d1 d0 gain mdp1 0 0 1 gain mdp0 0 1 0 gmdp ?db 0db +6db gain mds1 0 0 1 gain mds0 0 1 0 gmds ?db 0db +6db
?14 CXD2507AQ clv ctrl dclv pwm md tb tp clvs gain command d3 d2 d1 d0 clv mode cm3 cm3 0 1 1 1 1 0 cm2 0 0 0 1 1 1 cm1 0 0 1 1 1 1 cm0 0 0 0 0 1 0 mode stop kick brake clvs clvp clva explanation see timing chart 1-6. see timing chart 1-9. see timing chart 1-8. cm2 cm1 cm0 command d3 d2 d1 d0 command bit dclv pwm md = 1 dclv pwm md = 0 clv pwm mode specified. both mds and mdp are used. clv pwm mode specified. ternary mdp values are output. explanation (see timing chart 1-5.) command bit tb = 0 tb = 1 tp = 0 tp = 1 bottom hold in clvs mode at cycle of rfck/32 bottom hold in clvs mode at cycle of rfck/16 peak hold in clvs mode at cycle of rfck/4 peak hold in clvs mode at cycle of rfck/2 explanation $dx commands see the $cx command. $ex commands stop : spindle motor stop mode kick : spindle motor forward rotation mode brake : spindle motor reverse rotation mode clvs : rough servo mode. when rf-pll circuit lock is disengaged, this mode is used to pull the disc rotations within the rf-pll capture range. clvp : pll servo mode. clva : automatic clvs/clvp switching mode. this mode is normally used during playback.
?15 CXD2507AQ timing chart 1-3 rch 16bit c1 pointer lch 16bit c2 pointer if c2 pointer = 1, data is ng c2 pointer for upper 8bits c2 pointer for lower 8bits rch c2 pointer c2 pointer for upper 8bits c2 pointer for lower 8bits lch c2 pointer lrck wdck cdrom = 0 c2p0 cdrom = 1 c2p0
?16 CXD2507AQ timing chart 1-4 c1f1 0 1 1 c1f2 0 0 1 c1 correction status no error single error correction irretrievable error c2f1 0 1 1 c2f2 0 0 1 c2 correction status no error single error correction irretrievable error $bc latch set sqck and exck high during this interval. internal signal latch 750ns or more (1500ns or more in low power consumption mode) xlat sqck sqso spob spoc spod wfck scor gfs gtop emph fok lock rfck xraof c1f1 c1f2 c2f1 c2f2 spoa
?17 CXD2507AQ timing chart 1-5 timing chart 1-6 mds mdp dclv pwm md = 0 z acceleration 132khz 7.6s n ?236(ns) n = 0 to 31 deceleration z dclv pwm md = 1 mds mdp 7.6s acceleration n ?236(ns) n = 0 to 31 deceleration dclv pwm md=0 mds mdp mon stop z z l dclv pwm md=1 mds mdp mon stop l l
?18 CXD2507AQ dclv pwm md=1 mds mdp mon stop l l dclv pwm md = 0 mds mdp mon kick z z h 7.6s h kick dclv pwm md = 1 mds mdp mon h h h l timing chart 1-7
?19 CXD2507AQ timing chart 1-8 dclv pwm md = 0 mds mdp mon brake z z l h dclv pwm md = 1 mds mdp mon h
?20 CXD2507AQ 1-2. description of sens output the following signals are output from sens, depending on the microcomputer serial register value (latching not required). note that the sens output can be read from the sqso pin when sl1=1 and sl0=0. (see the $bx commands.) 2. subcode interface this section explains the subcode interface. there are two methods for reading out a subcode externally. the 8-bit subcodes p to w can be read from sbso by inputting exck to the cxd2507. sub q can be read out after the crc check of the 80 bits of information in the subcode frame. this accomplished, after checking scor and crcf, by inputting 80 clock pulses to sqck and reading data from sqso pin. 2-1. p to w subcode read data can be read out by inputting exck immediately after wfck falls. (see fig. 2-1.) also, sbso can be read out from sqso pin when sl1 = 0 and sl0 = 1. (see the $bx commands.) 2-2. 80-bit sub q read fig. 2-2 shows the peripheral block of the 80-bit sub q register. first, sub q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the crc check circuit. 96-bit sub q is input, and if the crc is ok, it is output to sqso with crcf = 1. in addition, the 80 bits are loaded into the parallel/serial register. when sqso goes high 400s or more later (monostable multivibrator time constant) after the subcode is read out, the cpu determines that new data (which passed the crc check) has been loaded. in the cxd2507, when 80-bit data is loaded, the order of the msb and lsb is inverted for each byte. as a result, although the sequence of bytes is the same, the bits within the bytes are now ordered lsb first. once the fact that the 80-bit data has been loaded is confirmed, sqck is input so that the data can be read. in the cxd2507, the sqck input is detected, and the retriggerable monostable multivibrator for low is reset. the retriggerable monostable multivibrator has a time constant from 270 to 400s. when the duration of sqck is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the s/p register is not loaded into the p/s register. while the monostable multivibrator is being reset, data can not be loaded in the 80-bit parallel/serial register. in other words, while reading out with a clock cycle shorter than the monostable multivibrator time constant, the register will not be rewritten by crcok and others. fig. 2-3 shows timing chart. although a clock is input from sqck pin to actually perform these operations, the high and low intervals for this clock should be between 750ns and 120s. sein, a signal input to the cxd2507 from the ssp, is output. low while the auto sequencer is in operation, high when operation terminates. outputs the signal input to the fok pin. normally, fok (from rf) is input. high for "focus ok". sein, a signal input to cxd2507 from the ssp, is output. high when the played back frame sync is obtained with the correct timing. low when the efm signal, after passing through the sync detection filter, is lengthened by 64 channel clock pulses or more. the sens pin is fixed low. sein xbusy fok sein gfs ov64 low $0x, 1x, 2x, 3x $4x $5x $6x $ax $ex $7x, 8x, 9x, bx, cx, dx, fx microcomputer serial register value (latching not required) sens output meaning
?21 CXD2507AQ timing chart 2-1 interrel pll clock 4.3218 d mhz wfck scor exck sbso 400ns max s0-s1 q r wfck scor exck sbso s0-s1 q r s t u v w s0-s1 p1 q r s t u v w p1 p2 p3 same same subcode p.q.r.s.t.u.v.w read timing
?22 CXD2507AQ block diagram 2-2 subq sin a b c d e f g h (afram) h g f e d c b a (asec) (amin) 80bit s/p register addrs ctrl 8 8 8 order inversion 8 8 8 8 8 8 si ld ld ld ld ld ld ld ld 80bit s/p register so shift sqck crcf mix sqso mono/multi crcc subq shift
?23 CXD2507AQ timing chart 2-3 1 2 3 91 92 93 94 95 96 97 98 wfck scor sqso sqck mono/multi (interral) order inversion crcf1 determined by mode l crcf2 80 clock register load forbidder 270 to 400s for sqck = high 750ns to 120s 300ns max crcf adr0 adr1 adr2 adr3 ctl0 ctl1 ctl2 ctl3 sqck sqso 1 2 3
?24 CXD2507AQ 3. description of other functions 3-1. channel clock regeneration by digital pll circuit the channel clock is necessary for demodulating the efm signal regenerated by the optical system. assuming t as the channel clock cycle, the efm signal is modulated in an integer multiple of t from 3t to 11t. in order to read the information in the efm signal, this integer value must be read correctly. as a result, t, that is channel clock, is required. in an actual player, the fluctuation in the spindle rotation alters the width of the efm signal pulses, making a pll necessary for regenerating channel clock. the block diagram of this pll is shown in fig. 3-1. the cxd2507 has a built-in two-stage pll as shown in the diagram. the first-stage pll generates a high-frequency clock needed by the second-stage digital pll. the second-stage pll is a digital pll that regenerates actual channel clock, and has a 250khz (normal state) or more capture range. block diagram 3-1 x'tal osc 1/m 1/n phase comparator pco fili filo cltv v dd vco rfpll digital pll cxd2507 xtsl
?25 CXD2507AQ 3-2. frame sync protection in a cd player operating at normal speed, a frame sync is recorded approximately every 136s (7.35khz). this signal is used as a reference to know which data is the data within a frame. conversely, if the frame sync can not be recognized, the data is processed as error data because it can not be recognized what the data is. as a result, recognizing the frame sync properly is extremely important for improving playability. there are two window widths: one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (wsel = 0/1). in addition, the forward protection counter is fixed to 13, and the backward protection counter is fixed to 3. in other words, when the frame sync is being played back normally and then can not be detected due to scratches, a maximum of 13 frames are inserted. if frame sync can not be detected for 13 frames or more, the window is released and the frame sync is resynchronized. in addition, immediately after the window is released and resynchronization is executed, if a proper frame sync can not be detected within 3 frames, the window is released immediately. 3-3. error correction in the cd format, one 8-bit data contains two error correction codes, c1 and c2. for c1 correction, the code is created with 28-byte information and 4-byte c1 parity. for c2 correction, the code is created with 24-byte information and 4-byte parity. both c1 and c2 are reed-solomon codes with a minimum distance 5. the cxd2507 sec strategy provides excellent playability through powerful frame sync protection and c1 and c2 error corrections. the correction status can be monitored outside the lsi. see table 3-2. when the c2 pointer is high, the data in question was uncorrectable. either the pre-value was held for that data, or an average value interpolation was made. mnt3 0 0 0 1 1 1 mnt1 0 0 1 0 0 1 mnt0 0 1 1 0 1 0 description no c1 errors one c1 errors corrected c1 correction impossible no c2 errors one c2 errors corrected c2 correction impossible table 3-2
?26 CXD2507AQ timing chart 3-3 3-4. da interface the cxd2507 da interface is as described below. this interface includes 48 cycles of the bit clock within one lrck cycle, and is msb first. when lrck is high, the data is for the left channel. normal-speed pb 400 to 500ns rfck mnt3 mnt1 mnt0 t = dependent on error condition c1 correction c2 correction strobe strobe c4m mnt0, 1, 3 valid valid invalid
?27 CXD2507AQ timing chart 3-4 lrck (44.1k) bck (2.12m) wdck pcmd lrck (88.2k) bck (4.23m) wdck pcmd 48bit slot normal-speed playback 1 24 r0 lch msb (15) l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 rmsb lch msb (15) 24 rch msb 23456789101112 48bit slot double-speed playback 12 l0 r0
?28 CXD2507AQ 3-5. digital out there are three digital out formats: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. the cxd2507 supports type 2 form 1. sub q data which are matched twice in succession after a crc check are input to the first four bits (bit 0 to 3) of channel status. table 3-5 3-6. servo auto sequencer this function performs a series of controls, including auto focus and track jumps. when the auto sequence command is received from the cpu, auto focus, 1 track jump, 2n track jumps, and n track move are executed automatically. ssp (servo signal processor lsi) is used in an exclusive manner during the auto sequence execution (when xbusy = low), so that commands from the cpu are not transferred to the ssp, but they can be sent to the cxd2507. connect the cpu, rf and ssp as shown in fig. 3-6. when clok goes from low to high while xbusy is low, xbusy does not become high for a maximum of 100s after that point. this is designed to prevent the transfer of erroneous data to the ssp when xbusy changes from low to high by the monostable multivibrator, which is reset by clok being low (when xbusy is low). 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 id0 id1 copy emph 0 0 0 0 1 0 0 0 0 0 0 0 from sub q 0 16 32 48 176 digital out c bit 12 34 56 78 9101112131415 bit0 to 3 ?sub q control bits that matched twice with crcok
?29 CXD2507AQ (a) auto focus ($47) focus search up is performed, fok and fzc are checked, and the focus servo is turned on. if $47 is received from the cpu, the focus servo is turned on according to figure. 3-7. the auto focus is executed after focus search up, and the pickup should be lowered beforehand (focus search down). in addition, blind e of register 5 is used to eliminate fzc chattering. in other words, the focus servo is turned on at the falling edge of fzc after fzc has been continuously high for a longer time than e. connection diagram for using auto sequencer (example) rf fok ssp c. out sens data clk xlt cnin fok data clok xlat sens micro-computer cxd2507 sein dato clko xlto auto focus focus search up fok=h no yes fzc = h no yes fzc = l no yes end focus servo on (checks whether fzc has stayed high longer than the period of time e set in register 5) fig. 3-6. fig. 3-7-(a). auto focus flow chart
?30 CXD2507AQ fig. 3-7-(b). auto focus timing chart (b) track jump 1, 10, and 2n-track jumps are performed respectively. always use this when focus, tracking, and the sled servo are on. note that tracking gain up and braking on ($17) should be sent beforehand because they are not performed. 1-track jump when $48 ($49 for rev) is received from the cpu, an fwd (rev) 1-track jump is performed in accordance with fig. 3-8. set blind a and brake b with register 5. 10-track jump when $4a ($4b for rev) is received from the cpu, an fwd (rev) 10-track jump is performed in accordance with fig. 3-9. the principal difference between the 10-track jump and the 1-track jump is whether to kick the sled or not. in addition, after kicking the actuator, 5 tracks have been counted through cnin, and the brake is applied to the actuator. then, the actuator speed is found to have slowed up enough (determined by the cnin cycle becoming longer than the overflow c set in register 5), and the tracking and sled servos are turned on. 2n-track jump when $4c ($4d for rev) is received from the cpu, an fwd (rev) 2n-track jump is performed in accordance with fig. 3-10. the track jump count "n" is set in register 7. although n can be set to 2 16 tracks, note that the setting is actually limited by the actuator. cnin is used for counting the number of jumps. although the 2n-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "d", set in register 6. n-track move when $4e ($4f for rev) is received from the cpu, an fwd (rev) n-track move is performed in accordance with fig. 3-11. n can be set to a maximum of 2 16 tracks. cnin is used for counting the number of jumps. this n-track move uses a method in which only the sled is moved, and is suited for moves over thousands of tracks. xlt $47latch $03 blind e $08 fok sein (fzc) busy command for ssp
?31 CXD2507AQ fig. 3-8-(a). 1-track jump flow chart track no yes end track kick sled servo wait (blind a) cnin = track rev kick wait (brake b) track, sled servo on (fwd kick for rev jump) (rev kick for rev jump) fig. 3-8-(b). 1-track jump timing chart xlt cnin busy $48 (rev = $49) latch $28 ($2c) blind a brake b $2c ($28) $25 command for ssp
?32 CXD2507AQ fig. 3-9-(a). 10-track jump flow chart 10 track no yes end track, sled fwd kick wait (blind a) cnin = 5 ? track, rev kick track, sled servo on no yes c = overflow ? (checks whether the cnin cycle is longer than overflow c) (counts cnin 5) fig. 3-9-(b). 10-track jump timing chart cnin $4a (rev = $4b) latch blind a $2a ($2f) cnin 5count $2e ($2b) overflow c $25 xlt busy command for ssp
?33 CXD2507AQ fig. 3-10-(a). 2n-track jump flow chart 2n track no yes end track, sled fwd kick wait (blind a) cnin = n track rev kick track servo on no yes c = overflow wait (kick d) sled servo on fig. 3-10-(b). 2n-track jump timing chart xlt blind a $2a ($2f) cnin n count $2e ($2b) overflow kick d $26 ($27) $25 $4c (rev = $4d) latch cnin busy command for ssp
?34 CXD2507AQ fig. 3-11-(a). n-track move flow chart n track move no yes end track servo off sled fwd kick wait (blind a) cnin = n end track, sled servo on fig. 3-11-(b). n-track move timing chart xlt $22 ($23) blind a cnin n count $25 $4e (rev = $4f) latch cnin busy command for ssp
?35 CXD2507AQ 3-7. digital clv fig. 3-12 shows the block diagram. digital clv makes pwm output in clvs and clvp with the mds error and mdp error signal sampling frequency increased to 130khz during normal speed operation. in addition, the digital spindle servo can set the gain. digital clv clvs u/d gain mds error mdp error clv p/s 0, ?db measure measure 2/1 mux over sampling filter-1 gs (gain) gp (gain) clv p clv s 1/2 mux clv ?p/s over sampling filter-2 noise shape modulation kick, brake stop dclvmd mdp mds mode select fig. 3-12. block diagram
?36 CXD2507AQ 3-8. asymmetry compensation fig. 3-13 shows the block diagram and circuit example. fig. 3-13. example of asymmetry correction application circuit asye rf r1 r1 asyo asyi r 1 2 r 2 5 = bias r1 r1 r2 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
?37 CXD2507AQ application circuit gnd gnd 2 3 4 5 6 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 1 lrck pcmd bck gtop xugf xpck v dd gfs rfck c2po xrof mnt3 mnt1 xlon spod spoc spob spoa clko v dd xlto dato cnin sein clok xlat data xrst sens mute sqck sqso exck sbso scor vss wfck emph dout c4m fstt xtsl xtao xtai mnt0 fok mon mdp mds lock test filo fili pco vss avss cltv av dd rf bias asyi asyo asye wdck gnd wdck lrck pcmd bck c2po emph mute gtop xugf xpck rfck xrof to d/a converter gnd gfs c2po gnd gnd gnd mnt0 mnt1 mnt2 mnt3 gnd to error rate counter gnd open gnd gnd rf gnd rf driver gnd v dd mute scor sqck subq qfs clk xlt data xrst sens fok ldon to cpu ssp ldon gnd 7 9 gnd application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
?38 CXD2507AQ package outline unit: mm sony code eiaj code jedec code 23.9??.4 20.0?.1 1.0 0.4 ?0.1 + 0.15 14.00.1 1 19 20 32 33 51 52 64 0.15 ?0.05 + 0.1 2.75 ?0.15 16.3 0.1 ?0.05 + 0.2 0.8 0.2 m 0.12 0.15 +?.4 17.9??.4 +0.4 + 0.35 64pin qfp(plastic) qfp?4p?01 * qfp064??420 package material lead treatment lead material package weight epoxy resin solder/palladium copper /42 alloy package structure plating 1.5g sony code eiaj code jedec code package structure package material lead treatment lead material package weight epoxy resin solder plating 42 alloy 64pin qfp (plastic) 24.98 0.4 20.20 max 1.0 0.55 max 1 19 20 32 33 51 52 64 14.20 max 19.00 0.4 (16.4) 0.15 0.05 0.1 ?0.05 + 0.1 2.1 max 1.3 0.2 qfp-64p-l121 * qfp064-p-1420-ax 0.15 m 0.12 1.5g

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