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www.gennum.com gs9024 genlinx? automatic cable equalizer gs9024 data sheet 521-70-10 february 2005 1 of 16 features ? automatic cable equalization ? fully compatible with smpte 259m ? typically equalizes greater than 350m of high quality cable at 270mb/s ? signal strength indicator ? output data muting when input data is lost ? output 'eye' monitor (oem) with large signal amplitude and power down option ? low power: 240mw at 5v ? 14 pin soic package ? programmable output data squelch for max cable length limiting ? carrier detect with programmable threshold level ? serial data output "high z" select to allow muxing of eq inputs ? pb-free and green applications front-end cable equalization for digital video systems; input equalization for serial digital distribution amplifiers, routers, production switchers and other receiving equipment. description the gs9024 is a high performance automatic cable equalizer designed for serial digital data rates from 143 mb/s to 540mb/s. the gs9024 receives either single-ended or differential serial data and outputs equalized differential signals at pecl levels (800mv). the gs9024 provides up to 40db of gain at 200mhz which will typically result in equalization of greater than 350m at 270mb/s of belden 8281 cable. the gs9024 incorporates an analog signal strength indicator/carrier detect (ssi/c d) output indicating both the presence of a carrier a nd the amount of equalization applied to the signal. optional external resistors allow the carrier detect threshold level to be customized to the user's requirement. the gs9024 also features selectable high z serial data outputs eliminating the need for input muxing circuitry in routers. in addition, the gs9024 provides an 'output eye monitor' (oem) which a llows the verification of signal integrity after equaliz ation, prior to reslicing. the gs9024 operates from a single +5v or -5v power supply and consumes only 240mw of power. packaged in a small 14 pin soic, the gs9024 is ideal for router applications where high de nsity component placement is required. block diagram sdi sdi oem agc cd_adj + - + - + - + - high z sdo sdo ssi/cd variable gain eq stage auto eq control eye monitor
gs9024 data sheet 521-70-10 february 2005 2 of 16 contents 1. electrical characteristics ...........................................................................................3 1.1 dc electrical characteristics ............... ...........................................................3 1.2 ac electrical characteristics .............. .............................................................4 2. test setup................................................................................................................5 3. pin connections ........................................................................................................6 4. typical performance curves .....................................................................................7 5. detailed description .................................. ..............................................................11 5.1 output high z ..............................................................................................11 5.2 signal strength indication/carrier dete ct ......................................................11 5.3 carrier detect threshold adjust ....................................................................12 5.4 output eye monitor .......................................................................................12 5.5 i/o description ..............................................................................................13 5.5.1 high speed analog inputs (sdi/sdi)... .............. .............. ........... .........13 5.5.2 high speed outputs (sdo/sdo) ........ .............. .............. ........... .........13 6. applications information..........................................................................................14 7. typical application circuit .......................................................................................14 8. package dimensions ..............................................................................................15 9. ordering information ...............................................................................................15 10. revision history ...................................... ..............................................................16
gs9024 data sheet 521-70-10 february 2005 3 of 16 1. electrical characteristics 1.1 dc electrical characteristics table 1-1: absolute maximum ratings parameter value supply voltage 5.5v input voltage range (any input) v cc +0.5 to v ee -0.5v operating temperature range 0c t a 70c storage temperature range -65c t s 150c lead temperature (soldering, 10 sec) 260c table 1-2: dc electrical characteristics v cc = 5v, v ee = 0v, t a = 0c to 70c unless otherwise shown. parameter symbol conditions min typ 1 max units notes test level supply voltage v cc ? 4.75 5.0 5.25 v power consumption p d ? ? 240 ? mw 3 with oem active ? 340 ? mw 3 supply current s ??44?ma1 with oem active ? 58 ? ma 1 serial data o/p current sdo r l = 75 ? ?11 ? ma 3 sdi/sdi common mode voltage ?? ? 2.5 ? v 1 agc+/agc- mode voltage ?? ? 2.7 ? v 1 oem bias potential ? ? ? 4.5 ? v 1 ssi/cd output current source c lm ax = 50pf r l = ??18a c lm ax = 50pf r l = 5k ? ??110a i sink ??1.01.5ma high z input voltage v high ?2.4??v1 v low ???0.8v1 test levels 1. 100% tested at 25c. 2. guaranteed by design. 3. inferred or co-related value. notes 1. typical values are parametric norms at 25c.
gs9024 data sheet 521-70-10 february 2005 4 of 16 1.2 ac electrical characteristics table 1-3: ac electrical characteristics v cc = 5v, v ee = 0v, t a = 0c to 70c unless otherwise shown. parameter symb ol conditions min typ 1 max units notes test level data rate 143 ? 540 mb/s 1 output signal swing v sdo r l = 75 ? 700 850 1000 mv 1 additive jitter t j 270mb/s, 300m ? 275 ? ps p-p see fig 5 5 540mb/s, 100m ? 200 ? ps p-p see fig 5 5 output rise and fall times (20-80%) t r , t f ? 0.5 0.65 ? ns 3 output duty cycle distortion ?? ? 30 ? ps 2 input resistance r in sdi, sdi ?10 ? k ? 2 input capacitance c in sdi, sdi ?1.0 ? pf 2 carrier detect response time t cdon carrier applied r l = , c l 50pf on ssi/cd ?3 ?s 2 t cdoff carrier removed r l = , c l 50pf on ssi/cd ?30 ? s 2 high z response time t r highz ??17?ns2 input return loss at 270mhz 15 20 ? db see fig 8 3 maximum equalizer gain a eq at 200mhz ? 40 ? db see fig 4 3, 5 test levels 1. 100% tested at 25c. 2. guaranteed by design. 3. inferred or co-related value. 4. evaluated using test setup figure 2-1 . 5. evaluated using test setup figure 2-2 . notes 1. typical values are parametric norms at 25c.
gs9024 data sheet 521-70-10 february 2005 5 of 16 2. test setup figure 2-1: test setup for figure 4-1 . figure 2-2: test setup for figure 4-2 , figure 4-3 , figure 4-4 , figure 4-5 , figure 4-8 , and figure . eb9024 board gs9028 cable driver tektronix gigabert 700 analyzer tektronix gigabert 700 transmitter belden 8281 cable data data clock trigger gs9028 cable driver vertical in trigger in oscilloscope anritsu me522a or gigabert 700 transmitter belden 8281 cable data data clock eb9024 board ssi/cd cd_adj v v
gs9024 data sheet 521-70-10 february 2005 6 of 16 3. pin connections agc- v ee v cc sdi sdi high z sdo v ee v cc sdo cd_adj oem agc+ ssi/cd gs9024 top view 1 2 3 4 5 6 7 14 13 12 11 10 9 8 table 3-1: pin descriptions number symbol type description 1, 14 agc-, agc+ i external agc capacitor. 4, 5 sdi/sdi i differential serial digital data inputs. 8 oem o output ?eye? monitor. oem is a single ended current mode output and requires an external 50 ? pullup resistor. 9 cd_adj i carrier detect threshold adjust. 10, 11 sdo /sdo o equalized serial digital data outputs. 12 ssi/cd o signal strength indicator/carrier detect. 13 high z i the sdo /sdo outputs are high z when this pin is high. if high z functionality is not used, this input can be left floating or tied low.
gs9024 data sheet 521-70-10 february 2005 7 of 16 4. typical performance curves (v s = 5v, t a = 25c unless otherwise shown.) figure 4-1: maximum data rate vs . cable length - belden 8281n (see test setup in figure 2-1 ) figure 4-2: equalizer gain vs. frequency data rate (mb/s) cable length (m) 500 400 300 200 100 0 90 180 270 360 450 540 630 0.5 ui output additive jitter 0.2 ui output additive jitter 0 5 10 15 20 25 30 35 40 45 50 1 10 100 1000 gain (db) frequency (mhz)
gs9024 data sheet 521-70-10 february 2005 8 of 16 figure 4-3: additive jitter vs. input cable length ? belden 8281 figure 4-4: ssi/cd voltage vs. cable length ? belden 8281 (cd_adj = 0v) figure 4-5: carrier detect adjust voltage threshold characteristics 0 200 400 600 800 1000 1200 1400 1500 0 50 100 150 200 250 300 350 additive jitter (ps p-p) cable length (m) 540mb/s 270mb/s 5.00 4.50 4.00 3.50 3.00 2.50 0 50 100 150 200 250 300 350 400 450 500 ssi/cd output voltage (v) cable length (m) 200 250 300 350 400 cd_adj voltage (v) cable length (m) 2.0 3.0 3.5 4.0 4.5 5.0 2.5
gs9024 data sheet 521-70-10 february 2005 9 of 16 figure 4-6: input impedance figure 4-7: output data waveform at 270mb/s, 300m 3000 1620 810 720 -j1 -j2 -j5 j2 j5 j1 j0.5 j0.2 -j0.2 -j0.5 frequencies in mhz, impedances normalized to 50 ? .
gs9024 data sheet 521-70-10 february 2005 10 of 16 figure 4-8: output data waveform at 540mb/s, 200m
gs9024 data sheet 521-70-10 february 2005 11 of 16 5. detailed description the gs9024 automatic cable equalizer is a bipolar integrated circuit designed to equalize serial digital data signals between 30mbps and 622mbps. powered from a single +5v or -5v supply, the device consumes approximately 240mw of power. the serial data signal is connected to the input pins (sdi/sdi ) either differentially or single ended. the input signal passes through a variable gain equalizing stage whose frequency response closely matches the inverse cable loss characteristic. in addition, the variation of the frequency response with control voltage imitates the variation of the inverse cable loss characteristic with cable length. the gain stage provides up to 40db of gain at 200mhz wh ich will typically result in equalization of greater than 350m at 270mb/s of belden 8281 cable. the edge energy of the equalized signal is monitored by a detector circuit which produces an error signal corresponding to the difference between the desired edge energy and the actual edge energy. this er ror signal is integrated by an external differential agc filter capacitor (agc+/ag c-) providing a steady control voltage for the gain stage. as the frequency response of the gain stage is automatically varied by the application of negative feedback, th e edge energy of the equalized signal is kept at a constant level which is representative of the original edge energy at the transmitter. the equalized signal is dc restored, ther eby restoring its logi c threshold to its corrective level regardless of shifts due to ac coupling. the digital output signals have pecl voltage levels (800mv) and are available at pins sdo and sdo. 5.1 output high z a high z pin allows the data outputs to be put into a high impedance state which disconnects them from the ou tput traces. this feature is ideal for input expansion in router applications as it eliminates the need for input muxes or crosspoints. note: the high impedance feature will only take effect if the device outputs are not muted. 5.2 signal strength indication/carrier detect the gs9024 incorporates an analog signal strength indicator/carrier detect output (ssi/cd) which indicates both the presence of a carrier and the amount of equalization applied to the signal. the voltage output of this pin versus cable length (signal strength) is shown in figure . with 0m of cable (800mv input signal levels), the ssi/cd output voltage is approximately 4.5v. as the cable length increases, the ssi/c d voltage decreases linearly providing accurate correlation between the ssi/cd voltage and cable length.
gs9024 data sheet 521-70-10 february 2005 12 of 16 when the signal strength decreases to th e level set at the "carrier detect threshold adjust" pin, the ssi/cd voltage go es to a logic "0" state (0.8v) and can be used to drive other ttl/cmos compatible logic inputs. in addition, when loss of carrier is detected the sdo /sdo outputs are muted (set to a known static state). 5.3 carrier detect threshold adjust the threshold level at which loss of carrier is detected is adjustable via external resistors at the cd_adj pin. the control voltage at the cd_adj pin is set by a simple resistor divider circui t. the threshold level is adjustable from 200m to 350m. by default (no external resistors), the th reshold is typically 320m. connecting this pin to ground disables the sdo /sdo muting function and allows for maximum possible cable length equalization. this feature is designed for use in app lications such as routers where signal crosstalk and circuit noise cause the equaliz er to output erroneous data when no input signal is present. this problem is not solved by using a carrier detect function with a fixed internal reference because the si gnal to noise ratio on the circuit board may be significantly less than the default signal detection level set by the on- chip reference. to solve this problem, the gs9 024 provides a user adjustable threshold to meet the unique conditions that exist in each user's application. override and internal default settings are provided to give the user total flexibility. 5.4 output eye monitor the gs9024 provides an 'output eye monito r' (oem) which allows the verification of signal integrity after equalization, prio r to reslicing. the oem pin is an open collector current output that requires an external 50 ? pullup resistor. when the pullup resistor is not used, the oem block is disabled and the internal oem circuit is powered down. the oem provides a 0.25vp-p signal when driving a 5 0? oscilloscope input. 0 1 2 3 4 5 50 100 150 200 250 300 350 400 450 500 ssi/cd output voltage (v) cable length (m) 0 cd_adj control range
gs9024 data sheet 521-70-10 february 2005 13 of 16 5.5 i/o description 5.5.1 high speed analog inputs (sdi/sdi ) sdi/sdi are high impedance inputs which acce pt differential or single-ended input drive. figure shows the recommended interface when a single-ended serial digital signal is used. 5.5.2 high speed outputs (sdo /sdo) sdo /sdo are current mode outputs that require external pullups (see figure ). the output signal swings are 800mv when 75 ? resistors are used. a diode can be placed between v cc and the pullups to shift the signal levels down by approximately 0.7 volts. wh en the output traces are longer than 1 inch, controlled impedance traces should be used. the pull up resistors should be placed at the end of the output traces as th ey terminate the trace in its characteristic impedance (75 ? ). sdi gs9024 sdi 75 ? 37.5 ? 75 ? 10nf 10nf 75 ? sdo sdo gs9024 75 ? 75 ? v cc
gs9024 data sheet 521-70-10 february 2005 14 of 16 6. applications information the typical applicatio n circuit shown on page 14 is useful for both smpte and dvb-asi signals. the two agc capacitors shown however increase the agc time constant from the original times shown in earlier smpte-only application circuits. in this case a minimum off-time of 50ms is needed when break-before-make switching is used at the input in order for the agc voltage to recover. 7. typical application circuit high z sdo sdo cd_adj oem agc+ ssi/cd agc- v ee v cc sdi sdi v ee v cc v cc v cc v cc v cc data out data out 1 2 3 4 5 6 7 v cc 1n 10n 10n 50 75 37.5 75 75 75 75 100k pot (optional) 100n sdi input 30 - 622mb/s eye monitor output 14 13 12 11 10 9 8 gs9024 all resistors in ohms, all capacitors in farads, unless otherwise shown. 100n
gs9024 data sheet 521-70-10 february 2005 15 of 16 8. package dimensions all dimensions in millimeters. 9. ordering information 0.49 max 4.0 max 6.20 max 1 7 8 14 7.62 0.05 6 spaces@ 1.27 0.05 0.25 max 1.91 max 1.27 max 0.25 max 8.75 max o.56 max = = = = = = part number package temperature pb-free and green gs9024-ckb 14 pin soic 0c to 70c no gs9024-ctb 14 pin soic tape 0c to 70c no gs9024-ckbe3 14 pin soic 0c to 70c yes GS9024-CTBE3 14 pin soic tape 0c to 70c yes
caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 gennum japan corporation shinjuku green tower building 27f, 6-14-1, nish i shinjuku, shinjuku-ku, tokyo, 160-0023 japan tel. +81 (03) 3349-5501, fax. +81 (03) 3349-5505 gennum uk limited 25 long garden walk, farnham, surrey, england gu9 7hx tel. +44 (0)1252 747 000 fax +44 (0)1252 726 523 gennum corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. the sale of the circuit or device described herein does not imply any patent license, and gennum makes no representation that the circuit or device is free from patent infringement. gennum and the g logo are registered trademarks of gennum corporation. ? copyright 1996 gennum corporation. all rights reserved. printed in canada. www.gennum.com gs9024 data sheet 521-70-10 february 2005 16 16 of 16 document identification data sheet the product is in production. gennum reserves the right to make changes to the product at any time wit hout notice to improve reliability, function or design, in order to provide the best product possible. 10. revision history version ecr date changes 10 135403 february 2005 added note to clarify that the high impedance feature is available only when the device outputs are not muted.

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