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a adf4217l/adf4218l/adf4219l information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. rev. c dual low power frequency synthesizers functional block diagram n = bp + a 11(13)-bit if b counter 6(5)-bit if a counter if prescaler output mux if lock detect charge pump rf lock detect charge pump 14(15)-bit rf r counter 14(15)-bit if r counter bu ffer 22-bit data register sdout n = bp + a 11(13)-bit rf b counter 6(5)-bit rf a counter rf prescaler phase comparator phase comparator adf4217l/ adf4218l/ adf4219l v p 2 v p 1 v dd 2 v dd 1 adf4219l only nc if in a if in b adf4217l adf4218l only ref in clock data le rf in a rf in b dgnd rf a gnd rf dgnd if a gnd if cp rf muxout cp if features in ( ) refer to adf4219l nc = no connect features total i dd : 7.1 ma bandwidth/rf 3.0 ghz adf4217l/adf4218l, if 1.1 ghz adf4219l, if 1.0 ghz 2.6 v to 3.3 v power supply 1.8 v logic compatibility separate v p allows extended tuning voltage selectable dual modulus prescaler selectable charge pump currents charge pump current matching of 1% 3-wire serial interface power-down mode applications wireless handsets (gsm, pcs, dcs, cdma, wcdma) base stations for wireless radio (gsm, pcs, dcs, wcdma) wireless lans communications test equipment cable tv tuners (catv) general description the adf4217l/adf4218l/adf4219l are low power dual frequency synthesizers that can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. they can provide the lo for both the rf and if sections. they consist of a low noise digital pfd (phase frequency detector), a precision charge pump, a programmable reference divider, programmable a and b counters, and a dual modulus prescaler (p/p + 1). the a and b counters, in conjunction with the dual modulus prescaler (p/p + 1), implement an n divider (n = bp + a). in addition, the 14-bit reference counter (r counter) allows selectable refin fre- quencies at the pfd input. a complete pll (phase-locked loop) can be implemented if the synthesizers are used with an external loop filter and vcos (voltage controlled oscillators). control of all the on-chip registers is via a simple 3-wire interface with 1.8 v compatibility. the devices operate with a power supply ranging from 2.6 v to 3.3 v and can be powered down when not in use.
rev. c e2e adf4217l/adf4218l/adf4219lespecifications 1 (v dd 1 = v dd 2 = 2.6 v to 3.3 v; v p 1, v p 2 = v dd to 5.5 v; agnd = dgnd = 0 v; t a = t min to t max , unless otherwise noted.) bchips 2 par ameter b version 1 (t ypic al) u nit test co nditions/comments rf characteristics use a square wave for operation below minimum frequency spec. rf input frequency (rf in ) adf4217l, adf4218l 0.15/3.0 0.15/3.0 ghz min/max e10 dbm minimum input signal adf4217l, adf4218l 0.15/2.5 0.15/2.5 ghz min/max e15 dbm minimum input signal adf4219l 0.8/2.2 0.8/2.2 ghz min/max e20 dbm minimum input signal rf input sensitivity adf4217l, adf4218l e15/0 e15/0 dbm min/max adf4219l e20/0 e20/0 dbm min/max if input frequency (if in ) adf4217l/adf4218l 0.045/1.1 0.045/1.1 ghz min/max e15 dbm minimum input signal adf4219l p = 16/17 0.045/1.0 0.045/1.0 ghz min/max e10 dbm minimum input signal adf4219l p = 8/9 0.045/0.55 0.045/0.55 ghz min/max e10 dbm minimum input signal if input sensitivity e15/0 e15/0 dbm min/max maximum allowable prescaler output frequency 3 188 188 mhz max refin characteristics reference input frequency 10/110 10/110 mhz min/max for f < 10 mhz, use dc-coupled square wave, (0 to v dd ). reference input sensitivity 0.5 0.5 v p-p min ac-coupled. when dc-coupled, 0 to v dd max. refin input capacitance 10 10 pf max (cmos compatible) refin input current = = = ( + ) ( ) ( ) ( + ) =
rev. c e3e adf4217l/adf4218l/adf4219l clock data le le t 3 t 1 t 2 t 4 t 5 t 6 db21 (msb) db20 db2 db1 (control bit c2) db0 (lsb) (control bit c1) figure 1. timing diagram bchips 2 par ameter b version 1 (t ypic al) u nit test co nditions/comments noise characteristics 6 rf phase noise floor 7 e171 e171 dbc/hz typ @ 30 khz pfd frequency e163 e163 dbc/hz typ @ 200 khz pfd frequency if phase noise floor 7 e167 e167 dbc/hz typ @ 30 khz pfd frequency e159 e159 dbc/hz typ @ 200 khz pfd frequency phase noise performance 8 @ vco output rf 9 e75 e75 dbc/hz typ 1.95 ghz output; 30 khz pfd rf 10 e90 e90 dbc/hz typ 900 mhz output; 200 khz pfd if 11 e77 e77 dbc/hz typ 900 mhz output; 30 khz pfd if 12 e86 e86 dbc/hz typ 900 mhz output; 200 khz pfd spurious signals measured at offset of f pfd /2f pfd rf 9 e78/e85 e78/e85 dbc typ rf 10 e80/e84 e80/e84 dbc typ if 11 e79/e86 e79/e86 dbc typ if 12 e80/e84 e80/e84 dbc typ notes 1 operating temperature range is as follows: b version: e40 + = = = ( ) ( = ) = = = = = = = = = = = = = = = = = = = = = = = = ( ) ( = = 10%, 5 v 10%; v dd 1, v dd 2 = = = = = )
rev. c adf4217l/adf4218l/adf4219l e4e absolute maximum ratings 1, 2 ( t a = 25 ) + + + + + + ( ) ( ) + ( ) + + ja thermal impedance . . . . . . . . . . . . . 150.4 ja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 ( ) ( ) ( ) ( ) = = = ( ) + () + ()
rev. c adf4217l/adf4218l/adf4219l e5e tssop ref in clk data le muxout rf in a cp rf agnd rf rf in b v dd 1 dgnd rf v dd 2 v p 1 adf4217l/ adf4218l dgnd if if inb if ina dgnd if cp if v p 2 1 10 11 20 agnd if 2 3 4 5 6 7 8 9 12 13 14 15 16 17 18 19 chip scale ref in clk muxout dgnd if 10 data le rf in a cp rf 1 9 agnd rf rf in b v dd 1 dgnd rf v dd 2 v p 1 adf4217l/ adf4218l agnd if if in a dgnd if cp if v p 2 21 13 24 nc nc nc nc if in b 2 3 4 5 6 7 8 11 12 23 22 20 19 18 17 16 15 14 nc = no internal connect tssop ref in clk data le muxout rf in a cp rf agnd rf rf in b v dd 1 dgnd rf v dd 2 v p 1 adf4219l dgnd if agnd if if in dgnd if cp if v p 2 1 10 11 20 nc 2 3 4 5 6 7 8 9 12 13 14 15 16 17 18 19 chip scale ref in clk muxout dgnd if 10 data le rf in a cp rf 1 9 agnd rf rf in b v dd 1 dgnd rf v dd 2 v p 1 adf4219l nc if in dgnd if cp if v p 2 21 13 24 nc nc nc nc agnd if 2 3 4 5 6 7 8 11 12 23 22 20 19 18 17 16 15 14 nc = no internal connect pin configurations
rev. c adf4217l/adf4218l/adf4219l e6e pin function descriptions mnemonic function v dd 1p ositive power supply for the rf section. decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. v dd 1 should have a value of between 2.6 v and 3.3 v. v dd 1 must have the same potential as v dd 2. v p 1p ower supply for the rf charge pump. this should be greater than or equal to v dd . cp rf output from the rf charge pump. when enabled, this provides ? ( ) ( ) ( )
rev. c adf4217l/adf4218l/adf4219l e7e rf input frequency e ghz 0 0.5 1.5 2.5 1.0 2.0 3.0 0 e5 rf input power e dbm e10 e15 e20 e25 e30 e35 e40 v dd = 3v v p = 3v 3.5 t a = 25 c tpc 1. input sensitivity, rf input if input frequency e ghz 0 e5 0.1 0.6 1.1 1.6 if input power e dbm e10 e15 e20 e25 e30 e35 e40 v dd = 3v v p = 3v tpc 2. input sensitivity, if input e2khz e1khz 1960mhz 1khz 2khz v dd = 3v, v p = 5v i cp = 4.0ma pfd frequency = 200khz re s. bandwidth = 10hz v ideo bandwidth = 10hz sw eep = 1.9 seconds a verages = 20 r eference l evel = e11.2dbm output power e db e100 e90 e80 e70 e60 e50 e40 e30 e20 e10 0 e83dbc/hz frequency tpc 3. phase noise, rf side (1960 mhz, 200 khz, 20 khz) e400khz frequency output power e db v dd = 3v, v p = 5v i cp = 4ma pfd frequency = 200khz res. bandwidth = 1khz video bandwidth = 1khz sweep = 2.5 seconds averages = 10 0 e60 e100 e10 e50 e70 e90 e30 e40 e80 e20 r eference l evel = e11.2dbm e78dbc e200khz 1960mhz 200khz 400khz tpc 4. reference spurs, rf side (1960 mhz, 200 khz, 20 khz) 10db/division r l = e40dbc/hz rms noise = 1.2 100hz frequency offset from 1960mhz carrier 1mhz 1.2 rms phase noise e dbc/hz e90 e80 e70 e60 e50 e40 e100 e110 e120 e130 e140 tpc 5. integrated phase noise, rf side (1960 mhz, 200 khz, 20 khz) e2khz e1khz 900mhz 1khz 2khz frequency output power e db v dd = 3v, v p = 5v i cp = 4ma pfd frequency = 200khz res. bandwidth = 10hz video bandwidth = 10hz sweep = 1.9 seconds averages = 20 0 e60 e100 e10 e50 e70 e90 e30 e40 e80 e20 reference level = e4.2dbm e87dbc/hz tpc 6. phase noise, if side (900 mhz, 200 khz, 20 khz) t ypical performance characteristicse
rev. c adf4217l/adf4218l/adf4219l e8e e400khz e200khz 900mhz 200khz 400khz v dd = 3v, v p = 5v i cp = 4.0ma pfd frequency = 200khz l oop bandwidth = 20khz re s. bandwidth = 10khz v ideo bandwidth = 10khz sw eep = 1.9 seconds a verages = 20 r eference l evel = e4.2dbm e83dbc output power e db e100 e90 e80 e70 e60 e50 e40 e30 e20 e10 0 frequency tpc 7. reference spurs, if side (900 mhz, 200 khz, 20 khz) 10db/division r l = e40dbc/hz rms noise = 0.9 100hz frequency offset from 900mhz carrier 1mhz phase noise e dbc/hz e90 e80 e70 e60 e50 e40 e100 e110 e120 e130 e140 tpc 8. integrated phase noise, if side (900 mhz, 200 khz, 20 khz) phase detector frequency e khz 1 10000 100 1000 e180 phase noise e dbc/hz e140 e150 e160 e170 e120 e130 10 v dd = 3v v p = 5v tpc 9. phase noise referred to cp output vs. pfd frequency, rf side phase detector frequency e khz 1 10000 100 1000 e180 phase noise e dbc/hz e140 e150 e160 e170 e120 e130 10 v dd = 3v v p = 5v tpc 10. phase noise referred to cp output vs. pfd frequency, if side temperature e c e60 e70 e100 e40 100 e20 phase noise e dbc/hz 020406080 e80 e90 v dd = 3v v p = 5v tpc 11. phase noise vs. temperature, rf side (1960 mhz, 200 khz, 20 khz) temperature e c e60 e70 e100 e40 100 e20 phase noise e dbc/hz 020406080 e80 e90 v dd = 3v v p = 5v tpc 12. phase noise vs. temperature, if side (900 mhz, 200 khz, 20 khz)
rev. c adf4217l/adf4218l/adf4219l e9e circuit description reference input section the reference input stage is shown in figure 2. sw1 and sw2 are normally closed switches; sw3 is normally open. when power-down is initiated, sw3 is closed and sw1 and sw2 are opened. this ensures that there is no loading of the ref in pin on power-down. power-down control ref in nc nc no sw3 sw2 sw1 50k bu ffer to r counter nc = normally closed no = normally open figure 2. reference input stage if/rf input stage the if/rf input stage is shown in figure 3. it is followed by a tw o -stage limiting amplifier to generate the cml clock levels needed for the prescaler. 500 500 1.6v bias generator rf in a rf in b av dd a gnd figure 3. if/rf input stage prescaler the dual modulus prescaler (p/p + 1), along with the a and b counters, enables the large division ratio, n, to be realized (n = bp + a). this prescaler, operating at cml levels, takes the clock from the if/rf input stage and divides it down to a manageable frequency for the cmos a and b counters. it is based on a synchronous 4/5 core. the prescaler is selectable. on the if side, it can be set to either 8/9 (db20 of the if ab counter latch set to 0) or 16/17 (db20 set to 1). on the rf side of the adf4217l/adf4218l, it can be set to 64/65 or 32/33. on the adf4219l, the rf prescaler can be set to 16/17 or 32/33. see tables v, vi, viii, and ix. a and b counters the a and b cmos counters combine with the dual modulus prescaler to allow a wide ranging division ratio in the pll feed- back counter. the devices are guaranteed to work when the prescaler output is 188 mhz or less. typically they will work with 250 mhz output from the prescaler. to pfd n = bp + a load load modulus control from if/rf input stage 11(13)-bit b counter 6(5)-bit a counter prescaler p/p+1 figure 4. reference input stage, a and b counters v cp e v 6 0 e6 0 5.0 0.5 i cp e ma 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 4 2 e2 e4 v p = 5v i cp = 4ma tpc 13. charge pump output characteristics
rev. c adf4217l/adf4218l/adf4219l e10e the a and b counters, in conjunction with the dual modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by r . the equation for the vco frequency is as follows: fpbafr vco ref in = () + [] f vco = output frequency of external voltage controlled oscillator (vco). p = preset modulus of dual modulus prescaler (8/9, 16/17, and so on). b = preset divide ratio of binary 11-bit counter (adf4217l/ adf4218l), binary 13-bit counter (adf4219l). a = preset divide ratio of binary 6-bit a counter (adf4217l/ adf4218l), binary 5-bit counter (adf4219l). f ref in =o utput frequency of the external reference frequency oscillator. r = preset divide ratio of binary 14-bit programmable reference counter (1 to 16383). the adf4219l has an r divide of 15 bits. r counter the 14-bit r counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (pfd). division ratios from 1 to 16,383 are allowed. the extra r15 bit on the adf4219l allows ratios from 1 to 32767. phase frequency detector (pfd) and charge pump the pfd takes inputs from the r counter and n counter and produces an output proportional to the phase and frequency difference between them. figure 5 is a simplited schematic. r divider n divider cp output r divider n divider d1 q1 clr1 u1 u3 delay element hi up d2 q2 clr2 u2 hi down v p charge pump cp cpgnd figure 5. pfd simplified schematic muxout and lock detect the output multiplexer on the adf4217l family allows the user to access various internal points on the chip. the state of muxout is controlled by p3, p4, p11, and p12. see tables iv and vii. figure 6 shows the muxout section in block diagram form. if analog lock detect if r counter output if n counter output if/rf analog lock detect rf r counter output rf n counter output rf analog lock detect mux control muxout dv dd dgnd figure 6. muxout circuit lock detect muxout can be programmed for analog lock detect. the n-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 k ? ( ) ( ) ( )
rev. c adf4217l/adf4218l/adf4219l e11e table ii. adf4217l/adf4218l family latch summary 14-bit reference counter, r control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 c1 (0) c2 (0) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 p5 p2 p3 p4 if f o if lock detect if reference counter latch three-state cp if if cp gain if pd polarity not used p1 11-bit b counter control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 c1 (1) c2 (0) a1 a2 a3 a4 a5 a6 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 p6 p7 if power-down if prescaler if ab counter latch 6-bit a counter not used 14-bit reference counter, r control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 rf reference counter latch rf f o rf lock detect three-state cp if rf cp gain rf pd polarity not used c1 (0) c2 (1) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 p13 p10 p11 p12 p9 11-bit b counter control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 rf ab counter latch 6-bit a counter c1 (1) c2 (1) a1 a2 a3 a4 a5 a6 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 p14 p16 rf power-down rf prescaler not used
rev. c adf4217l/adf4218l/adf4219l e12e table iii. adf4219l family latch summary 15-bit reference counter, r control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 c1 (0) c2 (0) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 p5 p2 p3 p4 if f o if lock detect if reference counter latch three-state cp if if cp gain if pd polarity p1 r15 13-bit b counter control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 c1 (1) c2 (0) a1 a2 a3 a4 a5 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 p6 p7 if power-down if prescaler if ab counter latch 5-bit a counter 15-bit reference counter, r control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 rf reference counter latch c1 (0) c2 (1) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 p13 p10 p11 p12 rf f o rf lock detect three-state cp if rf cp gain rf pd polarity p9 control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 rf ab counter latch 13-bit b counter c1 (1) c2 (1) a1 a2 a3 a4 a5 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 p14 p16 rf power-down rf prescaler 5-bit a counter r15
rev. c adf4217l/adf4218l/adf4219l e13e table iv. adf4217l/adf4218l/adf4219l if reference counter latch map 14-bit reference counter, r control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 c1 (0) c2 (0) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 p1 p5 p2 p3 p4 if f o if lock detect if reference counter latch three-state cp if if cp gain if pd polarity 0 1 negative positive p1 pd polarity 0 1 1.0ma 4.0ma p5 i cp 0 1 normal three-state p2 charge pump output 0 0 0 0 0 0 1 1 1 1 1 1 0 0 x x 1 1 x x 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 logic low state if analog lock detect if reference divider output if n divider output rf analog lock detect rf/if analog lock detect rf reference divider rf n divider fa st lock output switch on and connected to muxout if counter reset rf counter reset if and rf counter reset p12 p11 p4 p3 muxout from rf r latch .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... 0 1 1 0 . . . 0 0 1 1 . 1 1 2 3 4 . . . 16380 16381 16382 16383 . 32767 r14 r13 r12 .......... r3 r2 r1 divide ratio r15 1 0 1 0 . . . 0 1 0 1 . 1 0 0 0 1 . . . 1 1 1 1 . 1 0 0 0 0 . . . 1 1 1 1 . 1 0 0 0 0 . . . 1 1 1 1 . 1 0 0 0 0 . . . 1 1 1 1 . 1 0 0 0 0 . . . 0 0 0 0 . 1 r15 adf4219l only
rev. c adf4217l/adf4218l/adf4219l e14e table v. adf4217l/adf4218l if ab counter latch map 11-bit b counter control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 c1 (1) c2 (0) a1 a2 a3 a4 a5 a6 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 p6 p7 if power-down if prescaler if ab counter latch 6-bit a counter 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... not allowed not allowed 3 . . . 2044 2045 2046 2047 b11 b10 b9 .......... b3 b2 b1 b counter divide ratio 0 0 0 . . . 1 1 1 1 0 0 0 . . . 1 1 1 1 0 0 0 . . . 1 1 1 1 0 1 1 . . . 0 0 1 1 1 0 1 . . . 0 1 0 1 0 1 8/9 16/17 p6 if prescaler 0 1 normal operation power-down p7 if section n = bp + a, p is prescaler value set by p6. b must be greater than or equal to a. to ensure continuously adjacent values of n, n min is (p 2 e p). a6 0 0 0 0 . . . 1 1 0 0 0 0 . . . 1 1 0 0 0 0 . . . 1 1 0 0 1 1 . . . 1 1 0 1 0 1 . . . 0 1 0 1 2 3 . . . 62 63 a5 a4 a3 a2 a1 a counter divide ratio 0 0 0 0 . . . 1 1 not used
rev. c adf4217l/adf4218l/adf4219l e15e table vi. adf4219l if ab counter latch map 13-bit b counter control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 c1 (1) c2 (0) a1 a2 a3 a4 a5 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 p6 p7 if power-down if prescaler if ab counter latch 5-bit a counter 0 1 8/9 16/17 p6 if prescaler 0 0 0 0 . 1 1 0 0 0 0 . 1 1 0 0 0 0 . 1 1 0 0 1 1 . 1 1 0 1 0 1 . 0 1 0 1 2 3 . 30 31 a5 a4 a3 a2 a1 a counter divide ratio 0 1 normal operation power-down p7 if section n = bp + a, p is prescaler value set by p6. b must be greater than or equal to a. for contiguous values of n, n min is (p 2 e p). 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... not allowed not allowed 3 . . . 8188 8189 8190 8191 b13 b12 b11 .......... b3 b2 b1 b counter divide ratio 0 0 0 . . . 1 1 1 1 0 0 0 . . . 1 1 1 1 0 0 0 . . . 1 1 1 1 0 1 1 . . . 0 0 1 1 1 0 1 . . . 0 1 0 1
rev. c adf4217l/adf4218l/adf4219l e16e table vii. rf reference counter latch map 14-bit reference counter, r control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 c1 (0) c2 (1) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 p13 p10 p11 p12 rf reference counter latch rf f o rf lock detect three-state cp if rf cp gain rf pd polarity p9 0 1 negative positive p9 pd polarity 0 1 1.0ma 4.0ma p13 i cp 0 1 normal three-state p10 charge pump output r15 adf4129l only 0 0 0 0 0 0 1 1 1 1 1 1 0 0 x x 1 1 x x 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 logic low state if analog lock detect if reference divider output if n divider output rf analog lock detect rf/if analog lock detect rf reference divider rf n divider fa st lock output switch on and connected to muxout if counter reset rf counter reset if and rf counter reset p12 p11 p4 p3 muxout from rf r latch .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... 0 1 1 0 . . . 0 0 1 1 . 1 1 2 3 4 . . . 16380 16381 16382 16383 . 32767 r14 r13 r12 .......... r3 r2 r1 divide ratio r15 1 0 1 0 . . . 0 1 0 1 . 1 0 0 0 1 . . . 1 1 1 1 . 1 0 0 0 0 . . . 1 1 1 1 . 1 0 0 0 0 . . . 1 1 1 1 . 1 0 0 0 0 . . . 1 1 1 1 . 1 0 0 0 0 . . . 0 0 0 0 . 1
rev. c adf4217l/adf4218l/adf4219l e17e table viii. adf4217l/adf4218l rf ab counter latch map 11-bit b counter control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 c1 (1) c2 (1) a1 a2 a3 a4 a5 a6 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 p14 p16 rf power-down rf prescaler rf ab counter latch 6-bit a counter 0 1 64/65 32/33 p14 rf prescaler adf4217l 32/33 64/65 rf prescaler adf4218l a6 0 0 0 0 . . . 1 1 0 0 0 0 . . . 1 1 0 0 0 0 . . . 1 1 0 0 1 1 . . . 1 1 0 1 0 1 . . . 0 1 0 1 2 3 . . . 62 63 a5 a4 a3 a2 a1 a counter divide ratio 0 0 0 0 . . . 1 1 0 1 normal operation power-down p16 rf section n = bp + a, p is prescaler value set by p6, b must be greater than or equal to a. to ensure continuously adjacent values of n f ref , n min is (p 2 e p). 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... not allowed not allowed 3 4 . . . 2044 2045 2046 2047 b11 b10 b9 .......... b3 b2 b1 b counter divide ratio 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 0 1 . . . 1 1 1 1 0 1 1 0 . . . 0 0 1 1 1 0 1 0 . . . 0 1 0 1 not used
rev. c adf4217l/adf4218l/adf4219l e18e table ix. adf4219l rf ab counter latch map 13-bit b counter control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 db21 c1 (1) c2 (1) a1 a2 a3 a4 a5 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 p14 p16 rf power-down rf prescaler rf ab counter latch 5-bit a counter 0 1 normal operation power-down p16 if section n = bp + a, p is prescaler value set by p14. b must be greater than or equal to a. for contiguous values of n, n min is (p 2 ep). a must be less than p. 0 1 16/17 32/33 p14 if prescaler 0 0 0 0 . 1 1 0 0 0 0 . 1 1 0 0 0 0 . 1 1 0 0 1 1 . 1 1 0 1 0 1 . 0 1 0 1 2 3 . 30 31 a5 a4 a3 a2 a1 a counter divide ratio 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... not allowed not allowed 3 4 . . . 8188 8189 8190 8191 b13 b12 b11 .......... b3 b2 b1 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 0 1 . . . 1 1 1 1 0 1 1 0 . . . 0 0 1 1 1 0 1 0 . . . 0 1 0 1 b counter divide ratio
rev. c adf4217l/adf4218l/adf4219l e19e program modes tables iv and vii show how to set up the program modes in the adf4217l family. the following should be noted: 1. if and rf analog lock detect indicate when the pll is in lock. when the loop is locked, and either if or rf analog lock detect is selected, the muxout pin will show a logic high with narrow low-going pulses. when the if/rf analog lock detect is chosen, the locked condition is indicated only when both if and rf loops are locked. 2. the if counter reset mode resets the r and n counters in the if section and also puts the if charge pump into three- state. the rf counter reset mode resets the r and n counters in the rf section and also puts the rf charge pump into three-state. the if and rf counter reset mode does both of the above. upon removal of the reset bits, the n counter resumes counting in close alignment with the r counter (maximum error is one prescaler output cycle). 3. the fastlock mode uses muxout to switch a second loop filter damping resistor to ground during fastlock operation. activation of fastlock occurs whenever rf cp gain in the rf reference counter is set to 1. power-down it is possible to program the adf4217l family for either synchro- nous or asynchronous power-down on either the if or rf side. synchronous if power-down programming a 1 to p7 of the adf4217l family will initiate a power-down. if p2 of the adf4217l family has been set to 0 (normal operation), then a synchronous power-down is conducted. the device will automatically put the charge pump into three- state and then complete the power-down. asynchronous if power-down if p2 of the adf4217l family has been set to 1 (three-state the if charge pump) and p7 is subsequently set to 1, an asynchro- nous power-down is conducted. the device will go into power-down on the rising edge of le, which latches the 1 to the if power- down bit (p7). synchronous rf power-down programming a 1 to p16 of the adf4217l family will initiate a power-down. if p10 of the adf4217l family has been set to 0 (normal operation), a synchronous power-down is conducted. the device will automatically put the charge pump into three-state and then complete the power-down. asynchronous rf power-down if p10 of the adf4217l family has been set to 1 (three-state the rf charge pump) and p16 is subsequently set to 1, an asynchronous power-down is conducted. the device will go into power-down on the rising edge of le, which latches the 1 to the rf power-down bit (p16). activation of either synchronous or asynchronous power-down forces the if/rf loop?s r and n dividers to their load state conditions, and the if/rf input section is debiased to a high impedance state. the ref in oscillator circuit is only disabled if both the if and rf power-downs are set. the input register and latches remain active and are capable of loading and latching data during all the power-down modes. the if/rf section of the devices will return to normal powered-up operation immediately upon le latching a 0 to the appropriate power-down bit. if section programmable if reference (r) counter if control bits c2, c1 are 0, 0, then the data is transferred from the input shift register to the 14-bit if r counter. table iv shows the input shift register data format for the if r counter and the possible divide ratios. if phase detector polarity p1 sets the if phase detector polarity. when the if vco char- acteristics are positive, this should be set to 1. when they are negative, it should be set to 0. see table iv. if charge pump three-state p2 puts the if charge pump into three-state mode when programmed to a 1. it should be set to 0 for normal operation. see table iv. if charge pump currents p5 sets the if charge pump current. with p5 set to 0, i cp is 1.0 ma. with p5 set to 1, i cp is 4.0 ma. see table iv. programmable if ab counter if control bits c2, c1 are 0, 1, the data in the input register is used to program the if ab counter. for the adf4217l/adf4218l, the ab counter consists of a 6-bit swallow counter (a counter) and 11-bit programmable counter (b counter). table v shows the input register data format for programming the if ab counter and the possible divide ratios. the adf4219l n counter consists of an 13-bit b counter and 5-bit a counter. table vi shows the input register data format for programming the adf4219l. if prescaler value p6 in the if ab counter latch sets the if prescaler value. for the adf4217l family, 8/9 or 16/17 prescalers are available. see table v and table vi. if power-down tables iv, v, and vi show the power-down bits in the adf4217l family. see the power-down section for a functional description. rf section programmable rf reference (r) counter if control bits c2, c1 are 1, 0, the data is transferred from the input shift register to the 14-bit rf r counter. table vii shows the input shift register data format for the rf r counter and the possible divide ratios. rf phase detector polarity p9 sets the rf phase detector polarity. when the rf vco characteristics are positive, this should be set to 1. when they are negative, it should be set to 0. see table vii. rf charge pump three-state p10 puts the rf charge pump into three-state mode when programmed to a 1. it should be set to 0 for normal operation. see table vii.
rev. c adf4217l/adf4218l/adf4219l e20e spi compatible serial bus lock detect vco190-1068u v cc cp if if in ref in dgnd rf a gnd rf dgnd if a gnd if clk data le rf in muxout cp rf v p 1 v p 2v dd 2v dd 1 adf4217l/ adf4218l/ adf4219l vco190-125t v cc 10mhz tcxo decoupling capacitors (22 f/10pf) on v dd , v p of the adf4217l/adf4218l/adf4219l. the tcxo and on v cc of the vcos have been omitted from the diagram to aid clarity. 400pf 620pf 3.9nf 100pf 100pf 100pf 620pf 6nf 620pf 100pf 100pf 100pf 3.3k 18 18 18 51 9k 18 18 18 51 3.3k rf out v p v dd v p if out 5.8k v dd figure 7. local oscillator design for gsm receiver rf program modes tables iv and vii show how to set up the rf program modes. rf charge pump currents p13 sets the rf charge pump current. with p13 set to 0, i cp is 1.0 ma. with p13 set to 1, i cp is 4.0 ma. see table vii. programmable rf ab counter if control bits c2, c1 are 1, 1, the data in the input register is used to program the rf ab counter. for the adf4217l/adf4218l, the ab counter consists of a 6-bit swallow counter (a counter) and 11-bit programmable counter (b counter). table viii shows the input register data format for programming the rf ab counter and the possible divide ratios. the adf4219l n counter consists of a 13-bit b counter and 5-bit a counter. table ix shows the input register data format for programming the adf4219l. rf prescaler value p14 in the rf ab counter latch sets the rf prescaler value. for the adf4217l and adf4218l family, 32/33 or 64/65 prescalers are available. see table viii. for the adf4219l, the prescaler may be 16/17 or 32/33. see table ix. rf power-down tables vii, viii, and ix show the power-down bits (charge pump bit used for asynchronous in the adf4217l family). see the power-down section for a functional description. rf fastlock the rf cp gain bit (p13) of the rf n register in the adf4217l family is the fastlock enable bit. the loop filter should be designed for the lower current setting. when fastlock is enabled, the rf cp current is set to maximum value. also, an extra loop filter damping resistor to ground is switched in using the muxout pi n, thus compensating for the change of loop dynamics when in fastlock mode. since the rf cp gain bit is contained in the rf n counter, only one write is needed to program the new frequency and to initiate fastlock. to come out of fastlock, the rf cp gain bit should be returned to 0 and the extra damping resistor switched out. applications section local oscillator for gsm handset receiver the diagram in figure 7 shows the adf4217l/adf4218l/ adf4219l being used in a classic superheterodyne receiver to provide the required los (local oscillators). in this circuit, the reference input signal is applied to the circuit at f ref in and is being generated by a 13 mhz temperature controlled crystal oscillator. in order to have a channel spacing of 200 khz (the gsm standard), the reference input must be divided by 65, using the on-chip reference counter. the rf output frequency range is 1050 mhz to 1085 mhz. loop filter component values are chosen so that the loop band- width is 20 khz. the synthesizer is set up for a charge pump current of 4.0 ma, and the vco sensitivity is 15.6 mhz/v. the if output is fixed at 125 mhz. the if loop bandwidth is chosen to be 20 khz with a channel spacing of 200 khz. loop filter component values are chosen accordingly. local oscillator for wcdma receiver figure 8 shows the adf4217l/adf4218l/adf4219l being used to generate the local oscillator frequencies in a wideband cdma (wcdma) system. the rf output range needed is 1720 mhz to 1780 mhz. the vco190-1750t from varil-l will accomplish that. channel spacing is 200 khz, the loop bandwidth of the loop filter is 20 khz, and the vco sensitivity is 32 mhz/v. a charge pump current of 4.0 ma is used and the desired phase margin for the loop is 45 degrees. the if output is fixed at 200 mhz. the vco190-200t is used. it has a sensitivity of 11.5 mhz/v. channel spacing and loop bandwidth are chosen the same as the rf side.
rev. c adf4217l/adf4218l/adf4219l e21e spi compatible serial bus lock detect vco190-1750t v cc cp if if in ref in dgnd rf a gnd rf dgnd if a gnd if clk data le rf in muxout cp rf v p 1 v p 2v dd 2v dd 1 adf4217l/ adf4218l/ adf4219l vco190-200t v cc 10mhz tcxo decoupling capacitors (22 f/10pf) on v dd , v p of the adf4217l/adf4218l/adf4219l. the tcxo and on v cc of the vcos have been omitted from the diagram to aid clarity. 2.4pf 450pf 24nf 100pf 100pf 100pf 760pf 7.5nf 690pf 100pf 100pf 100pf 3.3k 18 18 18 51 1.5k 18 18 18 51 3.3k rf out v p v dd v p if out 4.7k figure 8. local oscillator design for wcdma system in this circuit, the reference input signal is applied to the circuit at ref in by a 10 mhz tcxo (temperature controlled crystal oscillator). interfacing the adf4217l/adf4218l/adf4219l family has a simple spi compatible serial interface for writing to the device. sclk, sdata, and le control the data transfer. when le (latch enable) goes high, the 22 bits that have been clocked into the input register on each rising edge of sclk will get transferred to the appropriate latch. see figure 1 for the timing diagram and table i for the latch truth table. the maximum allowable serial clock rate is 20 mhz. this means that the maximum update rate possible for the device is 909 khz or one update every 1.1 = ( ) ( ) ( )
rev. c adf4217l/adf4218l/adf4219l e22e outline dimensions 20-lead thin shrink small outline package [tssop] (ru-20) dimensions shown in millimeters 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 compliant to jedec standards mo-153ac coplanarity 0.10 24-leadless chip array cason [lga] (cc-24) dimensions shown in millimeters 3.50 bsc 1.20 max seating plane view a top view view a 0.50 bsc typ 1 24 bottom view 0.10 typ 0.05 max pin 1 index area 4.50 bsc 0.60 0.40 1.15 0.90 0.33 0.30 0.25 compliant to jedec standards mo-208, ecea-1
rev. c adf4217l/adf4218l/adf4219l ?3 revision history location page 5/03?ata sheet changed from rev. b to rev. c. change to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 change to tpc 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 change to outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7/02?ata sheet changed from rev. a to rev. b. change to adf4219l sensitivity specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6/02?ata sheet changed from rev. 0 to rev. a. changes to functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to cason package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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