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? sunplus technology co., ltd. 1 rev. : 1.1 1998.07.19 SPL10A1 7.5kb lcd controller/driver general description the SPL10A1 is a cmos 8-bit single chip micro-controller which contains lcd drivers, rom, sram, i/o, timer/counter and audio output on a single chip. the SPL10A1 is designed to drive lcd directly and perform efficient controller function as well as arithmetic function. with the on chip crystal oscillator, the clock function is easily realized. for power saving, a software controllable standby switch is also built-in. the SPL10A1 is widely used in electronic products requiring very low power operation, for example, multi-function watch, calendar, calculator, thermometer or lcd game with audio output. features ? cpu: 8-bit sunplus risc cpu ? operating voltage : 2.4v to 5.5v ? maximum cpu clock: 2 mhz @ 3v ? rom capacity: 7.5 k x 8 bits ? ram capacity: 96 x 8 bits ? direct driver for lcd : 4 commons x 32 segments (1/2, 1/3 bias, 1/2, 1/3, 1/4 duty) ? input port : 6 input pins with key wakeup function with 4 different configurations (mask option) ? i/o port : 2 general i/o pins and 4 special i/o pins that can implement thermometer and.. ? timer/counter: one 12-bit timer/counter ? 6 interrupt sources : external interrupt timer interrupt 2 khz interrupt lcd service interrupt (in lcd share mode) 128 hz interrupt 2 hz interrupt ? dual clock system : one built-in rc oscillator (only one resistor is needed) for cpu and one built-in crystal oscillator or rc oscillator ( mask option ) for lcd scanning. ? audio or tone output : one 7-bit da single tone melody or speech that can drive transistor or tone output that can drive buzzer. ? low operating current : typical current < 3 m a @ 3v for timepiece product
SPL10A1 2 block diagram rosc x32i x32o rosc gen 12 8 bit time base i/o ioab0-1(i/o) risc & p iocd0-3(i/o) processor interrupt o ioef0-5(input) logic r t 7.5k 8 one rom 12 bits da aud auto 96 8 reload tone sram timer 32 segments 4 commons lcd driver seg0 - seg31 com0 - com3
SPL10A1 3 pin description pin name i/o description seg0 - seg31 o lcd driver segment output com0 - com3 o lcd driver common output ioab0 - ioab1 i/o i/o port ioef0 - ioef5 i input port (also for key wake input) iocd0 - iocd3 i/o i/o port rosc i r-osc input, connect to vdd through resistor reset i system reset input aud o current da output /tone output x32i i 32.768khz crystal input/r oscillator input (provide lcd frequency) x32o o 32.768khz crystal output test i test input vdd i power input vss i ground input vdd1 i inputs for setting lcd bias vdd2 i inputs for setting lcd bias cup1 i input for maintaining 1/3 bias lcd cup2 i input for maintaining 1/3 bias lcd function description ? rom the SPL10A1 has 7.5k bytes rom size. the user can has 7k bytes for program and data. the other 0.5k bytes are for suplus internal test use. the rom address is from $0200 to $1fff. ? ram the SPL10A1 has 96 bytes ram size. this area is all for data storage. the ram address is from $00a0 to $00ff.
SPL10A1 4 ? memory and i/o map $0000 $001f $00a0 $00ff $0100 $01ff $0200 $03ff $0400 $1fff sunplus test program $05ff $0600 h/w register,i/os user ram and stack dummy for ice debug user's program data area rom user's program data area rom ? oscillators the SPL10A1 has dual clock system that one is for the cpu and system and the other is for the lcd scanning and interrupt sources. 1. r oscillator for the cpu and system clock 1.1 normal case 1.2 noise environment +v dd +v dd note: length of the wiring for rosc pin should be minimized because the oscillator frequency varies due to coupling from other signal lines.
SPL10A1 5 2 . 32768hz crystal oscillator or r oscillator (mask option) for lcd scanning and interrupt sources (2 khz, lcdl for lcd service,128 hz, 2hz). it is suggested to enable 32768hz crystal in strong mode for a few seconds and then switch to weak mode when reset occurs. x32i x32o c1 c2 32768hz 32768hz crystal 20p 20p +v dd x32i r oscillator r note: length of the wiring for x32i and x32o should be as short as possible. ? stop clock mode the SPL10A1 supports the power saving mode for those applications needed very low standby current. the user can simply enable the wake-up sources then stop the cpu clock by writing the stop clock register ($09). the cpu will go to stand-by and the ram and i/o remains their previous states until wake-up. there are three sources of wake-up in this chip, port ioef wake-up, timer 0 wake-up and 2 hz wake-up. after the chip being waken up, the internal cpu will go to the reset state the ram and i/o are not affected by the wake-up reset. the standby current of timepiece product typically is less than 3 m a@3v by using this mode and 32768hz clock source in weak mode. for non-timepiece products, 32768hz crystal driver or r oscillator (mask option) that generates the 32768hz clock source also can be turned off, then the whole chip stops. the standby current of the SPL10A1 is less than 1 m a@3v. in this mode, ioef port can be used to wake up this chip. ? timer/counter the SPL10A1 contains one 12-bit timer/counter,tm0.in timer mode,tm0 is reloadable up-counter. when timer overflows from 0fff to 0000, the carry signal will generate the interrupt signal if the corresponding bit is enabled in int enable register ($0d),and the timer will be auto reloaded to the users setup value and upcount again. if tm0 being specified as a counter, the user may reset the counter by loading 0 into register $14 and $1c. after the counter being activated, the count value can also be read from above registers on-the-fly, the read instruction will not affect the counter's value or reset it.
SPL10A1 6 the clock source of the timer/counter are selectable as the following: timer/counter addr. clock source tm0 12 bit timer $0014 cpu clock (t) or t/4 $001c 12 bit counter $0014 t/128, t/256, t/2048 or ext clk $001c mode select register $000b select tm0 timer or counter timer clock selector $001c select t or t/4 ? interrupts the SPL10A1 has six interrupt sources. they are int0 ( interrupt fromtimer 0 ), 2 khz int, lcdl int (lcd service in share mode, due to lcd registers is shared with the timer/counter ), 128 hz int, ext int ( external interrupt from iocd1 ), 2 hz int. the 2khz int, lcdl int (256 hz in 1/3, 1/4 bias;128 hz in 128 hz), 128 hz int, 2hz int, all are divided from 32768 hz crystal oscillator. ? audio (melody/speech) / tone output the SPL10A1 provides both speech and single tone melody output in current da type that can drive speaker through transistor. also, the SPL10A1 provides tone output that can directly drive buzzer. the two modes, current da and tone, share the same aud pin. in current da mode, it should smoothly switch current da output current to zero by using speech mode to reduce noise to turn off current da. the current da should be turned off when not used due to the current consumption. the tone output is a full-swing (vdd and vss) signal and its frequency source is the frequency of timer carry divided by 2.
SPL10A1 7 the block diagram is shown as below: 2 tone driver mix enve lope da aud pitch timer carry speech melody tone ? liquid crystal display the SPL10A1 can directly drive the liquid crystal display (lcd) panel of 1/2 duty, 1/3 duty, and 1/4 duty with 1/2 bias or 1/3 bias. it has 4 commons and 32 segments signal pins. in share mode (timer/counter is used), the lcd being refresh by lcdl interrupt. the int routine will read the number of common which is under serving, and send the next common's pattern to lcd port ($10 - $13) from ram buffer. if the timer/the counter is not used, hardware mechanism will auto refresh the lcd after writing option register ($1f). the power connections for lcd (1/2 bias,1/3bias) are shown as below: vdd2 0.1u 1 / 2 bias vdd1 1 / 3 bias vdd2 cup2 cup1 0.01u vdd 0.01u 0.01u
SPL10A1 8 ? output waveform of the lcd driver vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vss vdd vss com0 com1 com2 com3 normal operation 1/2 bias , 1/2 duty lighting format at the initial clear ( reset ) com0 ~ com3 lcd display on mode lcd segments display on lcd driver output: com0 lcd segments display on lcd driver output: com1 lcd driver output:all the lcd segments display off lcd driver output:all the lcd segments display on
SPL10A1 9 com0 com1 com2 com3 normal operation vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss at the initial clear ( reset ) com0 ~ com3 lcd display on mode 1/2 bias , 1/3 duty lighting format vdd vss vdd vss lcd segments display on lcd driver output: com0 lcd segments display on lcd driver output: com1 lcd segments display on lcd driver output: com2 lcd segments display on lcd driver output : com1 and com1 lcd segments display on lcd driver output : com1 and com2 lcd segments display on lcd driver output : com2 and com2 lcd driver output:all the lcd segments display off lcd driver output:all the lcd segments display on
SPL10A1 10 com0 com1 com2 com3 normal operation vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss vdd vdd2 vss at the initial clear ( reset ) com0 ~ com3 lcd display on mode 1/2 bias , 1/4 duty li g htin g format vdd vss vdd vss lcd segments display on lcd driver output: com0 lcd segments display on lcd driver output: com1 lcd segments display on lcd driver output: com2 lcd segments display on lcd driver output: com3 lcd segments display on lcd driver output : com1 and com1 lcd segments display on lcd driver output : com1 and com2 lcd segments display on lcd driver output : com2 and com2 lcd segments display on lcd driver output : com2 and com3 lcd driver output:all the lcd segments display off
SPL10A1 11 1/3 bias , 1/2 duty li g htin g format com0 com1 com2 com3 normal operation at the initial clear ( reset ) com0 ~ com3 lcd display on mode lcd segments display on lcd driver output: com1 lcd driver output:all the lcd segments display on lcd segments display on lcd driver output: com0 lcd driver output:all the lcd segments display off vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd2 vdd1 vdd2 vdd1 vdd2 vdd1 vdd vss vdd vss vss vdd
SPL10A1 12 com0 com1 com2 com3 lcd segments display on lcd driver output: com1 lcd segments display on lcd driver output: com2 lcd segments display on lcd driver output : com1 and com1 lcd segments display on lcd driver output : com1 and com2 lcd segments display on lcd driver output : com2 and com2 lcd segments display on lcd driver output: com0 lcd driver output:all the lcd segments display off vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd2 vdd1 vdd2 vdd1 normal operation at the initial clear ( reset ) 1/3 bias , 1/3 duty lighting format com0 ~ com3 lcd display on mode vdd vss vdd vss
SPL10A1 13 com0 normal operation vdd vdd2 vdd1 vss at the initial clear ( reset ) 1/3 bias , 1/4 duty li g htin g format com0 ~ com3 lcd display on mode vdd vss vdd vss com1 vdd vdd2 vdd1 vss com2 vdd vdd2 vdd1 vss com3 vdd vdd2 vdd1 vss lcd segments display on lcd driver output: com1 lcd segments display on lcd driver output: com2 lcd segments display on lcd driver output : com1 and com2 lcd segments display on lcd driver output : com2 and com3 lcd segments display on lcd driver output: com0 vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss vdd vdd2 vdd1 vss lcd segments display on lcd driver output: com3 lcd driver output:all the lcd segments display off vdd2 vdd1
SPL10A1 14 ? reset function the SPL10A1 can be reset by setting the reset pin to ground voltage and its operation starts when this pin is set to power voltage. also an automatic reset function (internal reset function) operates when power is turned on. ? watch dog function the SPL10A1 provides a watch dog timer. the watch dog timer must be reset when 2 hz wake-up by writing $0f, otherwise it will reset the system. ? mask option the following type mask option is available. ioef0 to ioef5 ............ select one of a, b, c, d(refer to input/output) a. without fixed pull low resistor 200k w , with feedback mos b. with fixed pull low resistor 200k w , without feedback mos c. with fixed pull low resistor 200k w , with feedback mos d. without fixed pull low resistor 200k w , without feedback mos 32768 hz clock source ................ select one of a, b (refer to r oscillator) a. 32768 crystal oscillator b. r oscillator i/o port configuration input ioef port: ioef0 to ioef5 there are 4 different configurations in ioef port. they are shown as following: ef port ( mask option ) : ef port write gnd pl gnd type a input d q 50k 30k ck 30k d q 200k gnd gnd type b input pl 200k 30k gnd ck d q 50k gnd pl gnd type c input ck gnd 30k d q ck type d input pl
SPL10A1 15 input/output ioab port: ioab0 and ioab1 these two ports can be programmed to be input or output pins. the configurations are shown as below: d q output input 100k gnd input data ck : ab port write ab port * input/output iocd port: iocd0 to iocd3 these four iocd ports can be programmed to be input or output pins independently. these pins also can be used to implement a thermometer by sense mode. their configurations are shown as belows: d q output input 100k gnd input data ck : cd port write cd port the application circuit for sense mode: thermo-resistor iocdb1 iocdb2 iocdb3
SPL10A1 16 absolute maximum ratings characteristics symbol ratings dc supply voltage v+ < 7v input voltage range v in -0.5v to v+ + 0.5v operating temperature t a 0 : to +60 : storage temperature t sto -50 : to +150 : dc characteristics limit characteristics symbol min typ max unit test condition operating voltage vdd 2.4 - 5.0 v operating current i op - 350 - m af cpu = 600khz/3.0v standby current i stby --1 m a vdd = 3.0 v current da output i oh - -1 - ma vdd = 3.0 v input high level v ih 2.0 - - v vdd = 3.0 v input low level v il - - 0.8 v vdd = 3.0 v output high i (i/o) i oh -300 - - m a vdd = 3.0 v, v oh = 2.4v output sink i (i/o) i ol 600 - - m a vdd = 3.0 v, v ol = 0.8v lcd display voltage v lcd --vddv lcd drive vdd 2.8 - 3.0 v v lcd =3v, i o = 6 m a output voltage vdd2 1.8 - 2.2 v v lcd =3v, i o = 3.5 m a vdd1 0.8 - 1.2 v v lcd =3v, i o = 3.5 m a vss 0 - 0.2 v v lcd =3v, i o = 6 m a osc resistor r osc - 50k - ohm
SPL10A1 17 ac characteristics limits characteristics symbol min typ max unit test condition osc frequency f osc - - 4.0 mhz vdd = 3.0 v cpu clock f cpu 0.01 - 2.0 mhz f cpu =f osc / 2@3v frame frequency - 64 - hz 1/2 duty of the lcd drive - 85 - hz 1/3 duty ffm1 - 64 - hz 1/4 duty wake-up time tw 6t1 - - hz t1= 1/(fosc), tw = 3 x t1, f cpu = f osc /2 sleep system clock cpu clock wake-up t1 tw
SPL10A1 18 the relationship between the rosc and the f cpu vdd = 3.0v, ta = 25 : vdd = 4.5v, ta = 25 : 0.0 0.5 1.0 1.5 2.0 0 200 400 600 800 rosc ( kohms ) f cpu ( mhz ) 0.0 0.5 1.0 1.5 2.0 0 200 400 600 800 rosc ( kohms ) f cpu ( mhz )
SPL10A1 19 frequency vs. v dd 010203040506070 0.96 1.00 0.98 1.02 1.04 temperature ( : ) f cpu /f cpu (25 : ) frequency normalized to 25 : frequency vs. temperature rosc=560kohms v dd =4.5v v dd =3.0v 0 0.5 1 1.5 2.5 3.5 4.5 5.5 v dd ( volts ) f cpu ( mhz ) rosc = 100 kohms rosc = 430 kohms
SPL10A1 20 operating current vs. frequency vs. v dd 0.0 200.0 400.0 600.0 800.0 1000.0 0.0 0.5 1.0 1.5 2.0 f cpu ( mhz ) i op ( m a ) vdd = 4.5v vdd = 3v
SPL10A1 21 application notes ? SPL10A1 application circuit SPL10A1 vdd2 vdd1 vss com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 ioef1 ioef2 ioef3 ioef4 ioef5 ioab0 ioab1 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 cup1 cup2 aud vdd x32i x32o iocd0 iocd1 iocd2 iocd3 reset rosc test ioef0 io device lcd module i/o inputs c1 20p c2 20p 32768hz common segment bias option 1/2 bias vdd1 vdd2 cup1 cup2 0.1uf 1/3 bias vdd1 vdd2 cup1 cup2 0.01uf vdd 0.01uf 0.01uf vdd bias option reset c5 0.1uf com ? 3:0 ? seg ? 31:0 ? audio ckt vdd 100uf seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg23
SPL10A1 22 ? audio driver/amplifier for da mode *aud in current da mode *aud in tone mode buzzer aud gnd aud vdd speaker 8050 gnd
SPL10A1 23 pad assignment and locations ? pad assignment chip size: 2100 m m x 2380 m m this ic substrate should be connected to vss ordering information product number package type SPL10A1-nnnnv-c chip form note: 1.code number (nnnnv) is assigned for customer. 2.code number ( nnnn = 0000 ~ 9999 ); version ( v = a ~ z ).
SPL10A1 24 ? pad locations pad no pad name xypad no pad name xy 1 ioef1 -913 1028 31 seg8 912 -1028 2 ioef2 -913 882 32 seg7 912 -881 3 ioef3 -913 756 33 seg6 912 -755 4 ioef4 -913 630 34 seg5 912 -629 5 ioef5 -913 504 35 seg4 912 -503 6 ioab0 -913 378 36 seg3 912 -377 7 ioab1 -913 252 37 seg2 912 -251 8 seg31 -913 126 38 seg1 912 -125 9 seg30 -913 0 39 seg0 912 0 10 seg29 -913 -125 40 com3 912 125 11 seg28 -913 -251 41 com2 912 251 12 seg27 -913 -377 42 com1 912 377 13 seg26 -913 -503 43 com0 912 503 14 seg25 -913 -629 44 vss 912 629 15 seg24 -913 -755 45 vdd1 912 755 16 seg23 -913 -881 46 vdd2 912 881 17 seg22 -913 -1028 47 cup1 912 1028 18 seg21 -759 -1028 48 cup2 752 1028 19 seg20 -633 -1028 49 aud 626 1028 20 seg19 -507 -1028 50 vdd 500 1028 21 seg18 -381 -1028 51 x32i 374 1028 22 seg17 -255 -1028 52 x32o 248 1028 23 seg16 -129 -1028 53 iocd0 122 1028 24 seg15 -3 -1028 54 iocd1 -3 1028 25 seg14 122 -1028 55 iocd2 -129 1028 26 seg13 248 -1028 56 iocd3 -255 1028 27 seg12 374 -1028 57 reset -381 1028 28 seg11 500 -1028 58 rosc -507 1028 29 seg10 626 -1028 59 test -633 1028 30 seg9 752 -1028 60 ioef0 -759 1028

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