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dram module kmm372v320(8)0cs1 i cc1 , i cc3 , i cc4 and i cc6 are dependent on output loading and cycle rates. specified values are obtained with the output open. i cc is specified as an average current. in i cc1 and i cc3 , address can be changed maximum once while ras =v il . in i cc4 , address can be changed maximum once within one fast page mode cycle time, t pc . * note : dc and operating characteristics (recommended operating conditions unless otherwise noted) i cc1 * i cc2 i cc3 * i cc4 * i cc5 i cc6 * i( il) i( ol) v oh v ol symbol speed KMM372V3200CS1 kmm372v3280cs1 unit min max min max i cc1 -5 -6 - - 1998 1818 - - 1458 1278 ma ma i cc2 don t care - 100 - 100 ma i cc3 -5 -6 - - 1998 1818 - - 1458 1278 ma ma i cc4 -5 -6 - - 1098 918 - - 1098 918 ma ma i cc5 don t care - 30 - 30 ma i cc6 -5 -6 - - 1998 1818 - - 1998 1818 ma ma i i(l) i o(l) don t care -10 -10 10 10 -10 -10 10 10 ua ua v oh v ol don t care 2.4 - - 0.4 2.4 - - 0.4 v v : operating current * ( ras , cas , address cycling @ t rc =min) : standby current ( ras = cas = w =v ih ) : ras only refresh current * ( cas =v ih , ras cycling @ t rc =min) : fast page mode current * ( ras =v il , cas cycling : t pc =min) : standby current ( ras = cas = w =vcc-0.2v) : cas -before- ras refresh current * ( ras and cas cycling @ t rc =min) : input leakage current (any input 0 v in vcc+0.3v, all other pins not under test=0 v) : output leakage current(data out is disabled, 0v v out vcc) : output high voltage level (i oh = -2ma) : output low voltage level (i ol = 2ma) recommended operating conditions (voltage referenced to v ss , t a = 0 to 70 c) *1 : v cc +1.3v at pulse width 15ns, which is measured at v cc . *2 : -1.3v at pulse width 15ns, which is measured at v ss . item symbol min typ max unit supply voltage ground input high voltage input low voltage v cc v ss v ih v il 3.0 0 2.0 -0.3 *2 3.3 0 - - 3.6 0 v cc +0.3 *1 0.8 v v v v absolute maximum ratings * * permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for in tended periods may affect device reliability. item symbol rating unit voltage on any pin relative v ss voltage on v cc supply relative to v ss storage temperature power dissipation short circuit output current v in , v out v cc t stg p d i os -0.5 to +4.6 -0.5 to +4.6 -55 to +125 36 50 v v c w ma
dram module kmm372v320(8)0cs1 capacitance (t a = 25 c, f = 1mhz) item symbol min max unit input capacitance[a0, b0, a1 - a12] input capacitance[ w0 , w2 , oe0 , oe2 ] input capacitance[ ras0 - ras3 ] input capacitance[ cas0 , 1, 4, 5] input/output capacitance[dq0 - 71] c in1 c in2 c in3 c in4 c dq - - - - - 20 20 73 20 24 pf pf pf pf pf test condition : v ih /v il =2.2/0.7v, v oh /v ol =2.0/0.8v, output loading cl=100pf parameter symbol -5 -6 unit note min max min max random read or write cycle time t rc 90 110 ns read-modify-write cycle time t rwc 133 155 ns access time from ras t rac 50 60 ns 3,4,10 access time from cas t cac 18 20 ns 3,4,5,11 access time from column address t aa 30 35 ns 3,10,11 cas to output in low-z t clz 5 5 ns 3,11 output buffer turn-off delay t off 5 18 5 20 ns 6,11 transition time(rise and fall) t t 1 50 1 50 ns 2 ras precharge time t rp 30 40 ns ras pulse width t ras 50 10k 60 10k ns ras hold time t rsh 18 20 ns 11 cas hold time t csh 48 58 ns 11 cas pulse width t cas 13 10k 15 10k ns ras to cas delay time t rcd 18 32 18 40 ns 4,11 ras to column address delay time t rad 13 20 13 25 ns 10,11 cas to ras precharge time t crp 10 10 ns 11 row address set-up time t asr 5 5 ns 11 row address hold time t rah 8 8 ns 11 column address set-up time t asc 0 0 ns column address hold time t cah 10 10 ns column address to ras lead time t ral 30 35 ns 11 read command set-up time t rcs 0 0 ns read command hold referencde to cas t rch 0 0 ns 8 read command hold referenced to ras t rrh -2 -2 ns 8,11 write command hold time t wch 10 10 ns write command pulse width t wp 10 10 ns write command to ras lead time t rwl 20 20 ns 11 write command to cas lead time t cwl 13 15 ns data in set-up time t ds -2 -2 ns 9,11 data in hold time t dh 15 15 ns 9,11 refresh period(4k & 8k) t ref 64 64 ms write command set-up time t wcs 0 0 ns 7 cas to w delay time t cwd 36 40 ns 7 column address to w delay time t awd 48 55 ns 7 cas prechange to w delay time t cpwd 53 60 ns 7 ras ro w delay time t rwd 71 83 ns 7,11 ac characteristics (0 c t a 70 c, v cc =3.3v 0.3v. see notes 1,2.)
dram module kmm372v320(8)0cs1 ac characteristics (0 c t a 70 c, v cc =3.3v 0.3v. see notes 1,2.) parameter symbol -5 -6 unit note min max min max cas setup time( cas -before- ras refresh) t csr 10 10 ns 11 cas hold time( cas -before- ras refresh) t chr 8 8 ns 11 ras to cas precharge time t rpc 3 3 ns 11 access time from cas precharge t cpa 35 40 ns 3,11 fast page mode cycle time t pc 35 40 ns fast page mode read-modify-write cycle time t prwc 76 85 ns cas precharge time(fast page cycle) t cp 10 10 ns ras pulse width(fast page cycle) t rasp 50 200k 60 200k ns ras hold time from cas precharge t rhcp 35 40 ns 11 w to ras precharge time(c-b-r refresh) t wrp 15 15 ns 11 w to ras hold time(c-b-r refresh) t wrh 8 8 ns 11 oe access time t oea 18 20 ns 11 oe to data delay t oed 18 20 ns 11 output buffer turn off delay time from oe t oez 5 18 5 20 ns 11 oe command hold time t oeh 13 15 ns pde to valid pd bit t pd 10 10 ns pde to pd bit inactive t pdoff 2 7 2 7 ns present detect read cycle notes an initial pause of 200us is required after power-up followed by any 8 ras -only or cas -before- ras refresh cycles before proper device operation is achieved. input voltage levels are v ih /v il . v ih (min) and v il (max) are ref- erence levels for measuring timing of input signals. transi- tion times are measured between v ih (min) and v il (max) and are assumed to be 5ns for all inputs. measured with a load equivalent to 1 ttl loads and 100pf. operation within the t rcd (max) limit insures that t rac (max) can be met. t rcd (max) is specified as a reference point only. if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . assumes tha t rcd 3 t rcd (max). this parameter defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . t wcs , t rwd , t cwd , t awd and t cpwd are not restrictive operat- ing parameter. they are included in the data sheet as electri- cal characteristics only. if t wcs 3 t wcs (min) the cycle is an early write cycle and the data out pin will remain high imped- ance for the duration of the cycle. if t rwd 3 t rwd (min), t cwd 3 t cwd (min), t awd 3 t awd (min) and t cpwd 3 t cpwd (min). the cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. if neither of the above sets of conditions is satisfied, the condition of data out(at access time) is indeterminate. either t rch or t rrh must be satisfied for a read cycle. these parameters are referenced to the cas leading edge in early write cycles. operation within the t rad (max) limit insures that t rac (max) can be met. t rad (max) is specified as reference point only. if t rad is greater than the specified t rad (max) limit, then access time is controlled by t aa . the timing skew from the dram to the dimm resulted from the addition of buffers. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11.
dram module kmm372v320(8)0cs1 t crp ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v oh - v ol - dq read cycle column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t aa t oea t cac t clz t rac open data-out t oez t rrh t rch don t care undefined t rcs t off
dram module kmm372v320(8)0cs1 t wcs write cycle ( early write ) note : d out = open ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp t wp t ds t dh t wch t cwl t rwl don t care data-in undefined
dram module kmm372v320(8)0cs1 t oed ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp data-in t wp don t care write cycle ( oe controlled write ) note : d out = open t cwl t rwl t ds t dh t oeh undefined
dram module kmm372v320(8)0cs1 ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v i/oh - v i/ol - dq row addr t ras t rwc t rp t rsh t rcd t cas t csh t rad t asr t rah t asc t cah t crp valid t wp don t care read - modify - wrtie cycle t rwl t cwl t oez t oea t oed t awd t cwd t rwd data-out undefined valid data-in t rac t aa t cac t clz t ds t dh column address
dram module kmm372v320(8)0cs1 t rch t oez t clz ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v oh - v ol - dq column address row addr t rhcp t rasp t cas t asc t rad t asr t rah t asc t cah t crp valid don t care fast page read cycle t oez t rrh data-out undefined valid data-out note : d out = open column address column address t rsh t cas t rcd t pc ? t csh t cah t asc t cah ? ? ? t rch ? t rcs t rcs t rcs t oea t cac t oea t cac t oea t cac valid data-out t clz t off t aa t off t aa t clz t off t oez t rac t aa ? ? t cp t cas t rp t cp
dram module kmm372v320(8)0cs1 t asc t cah ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq column address row addr t rhcp t rasp t cas t rad t asr t rah t asc t crp valid don t care fast page write cycle ( early write ) data-in undefined valid data-in t ds note : d out = open column address column address t rsh t cas t rcd t pc ? t csh t cah t asc t cah ? ? ? t wcs t wch t wcs valid data-in ? ? t wp t cwl t wp t wch t wp t wcs t wch t cwl t rwl t cwl t dh t ds t dh t ds t dh ? ? ? t rp t cp t cp t cas t pc
dram module kmm372v320(8)0cs1 t cac t asc t asc ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v i/oh - v i/ol - dq row addr t csh t rasp t asr valid don t care fast page read - modify - write cycle data-out undefined t rcd t cp t rad t cah t wp t dh col. addr col. addr t cas t cas t crp t cah t ral t prwc t rcs t cwl t cwd t awd t rwd t wp t cwd t awd t cwl t aa t rac t oea t clz t cac t oez t cpwd t oed valid data-in valid data-out valid data-in t clz t ds t oea t aa t dh t ds t oez t oed t rwl t rp t rsh t rah
dram module kmm372v320(8)0cs1 ras v ih - v il - cas v ih - v il - a v ih - v il - row addr t ras t rc t rp t asr t rah t crp don t care ras - only refresh cycle undefined note : w , oe , d in = don t care d out = open t rpc t crp cas - before - ras refresh cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t ras t rc t rp t wrp t rpc t rp t cp t chr t csr w v ih - v il - t wrh t off t rpc v oh - v ol - dq open
dram module kmm372v320(8)0cs1 t wrh t off ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v oh - v ol - dq hidden refresh cycle ( read ) column address row address t ras t rc t chr t rcd t rad t asr t rah t asc t cah t crp t rcs t aa t oea t cac t clz t rac open t rrh don t care t rsh t oez t wrp undefined t rc data-out t rp t rp t ras
dram module kmm372v320(8)0cs1 ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq hidden refresh cycle ( write ) column address row address t ras t rc t chr t rcd t rad t asr t rah t asc t cah t crp don t care t rsh data-in t wrp t wrh undefined t rc note : d out = open t wch t wp t dh t rp t rp t ras t ds t wcs
dram module kmm372v320(8)0cs1 cas -before- ras refresh counter test cycle ras v ih - v il - cas v ih - v il - a v ih - v il - column address t ras t rsh t chr t ral t csr t cpt t rp t cas t asc t cah read cycle v oh - v ol - data-out dq t off t clz write cycle v ih - v il - data-in dq t dh t ds w v ih - v il - t wp t cwd t cwl t rwl read-modify-write t awd v ih - v il - oe t oea t aa t cac t ds t dh valid data-out v i/oh - v i/ol - dq don t care undefined v ih - v il - oe t oea t oez oe v ih - v il - t rcs t clz t oez t oed t wrp t wrh t rrh t rch t rcs t cac t aa v ih - v il - w t wrp t wrh t wcs t wch t cwl v ih - v il - w t wp t rwl t wrp t wrh valid data-in note : this timing diagram is applied to all devices besides 16m dram 4th & 64m dram.
dram module kmm372v320(8)0cs1 don t care undefined cas - before - ras self refresh cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t rass t rps t rpc t wrp t chs t rp t cp t csr w v ih - v il - t wrh t off t rpc open v oh - v ol - dq test mode in cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t ras t rc t rp t rpc t wts t rpc t rp t cp t chr t csr w v ih - v il - t wth t off open v oh - v ol - dq
dram module kmm372v320(8)0cs1 tolerances : .005(.13) unless otherwise specified the used device is 16mx4 dram with fast page mode, tsop ii dram part no. : KMM372V3200CS1 - km44v16100cs. kmm372v3280cs1 - km44v16000cs. package dimensions units : inches (millimeters) 0.050 0.039 .002 0.01max (0.25 max) (1.000 . 050) (1.270 ) 0 . 1 0 0 m i n ( 2 . 5 4 0 m i n ) detail c 0.250 (6.350 ) detail a 0.1230 .0050 (3.125 .125) 0.250 (6.350 ) detail b 0.1230 .0050 (3.125 .125) 0.079 .0040 (2.000 .100) 0.079 .0040 (2.000 .100) 5.250 5.014 0.050 0.0039 (1.270 0.10) r 0.079 (r 2.000) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 0.350 0 . 1 0 0 m i n ( 2 . 5 4 0 m i n ) 0 . 7 0 0 ( 1 7 . 7 8 0 ) .118dia .004 (3.000dia .100) (8.890) a b c 0.250 (6.350) .450 (11.430) 4.550 (115.57) 0.157 0.004 (4.000 0.100 ) 0.054 (1.372) (127.350) (133.350) 2 . 1 0 0 ( 5 3 . 3 4 ) 0.118 (3.000) 0.150max (3.81max ) 0 . 1 1 8 ( 3 . 0 0 0 ) 0 . 1 6 5 m i n ( 4 . 1 9 m i n ) ( back view ) ( front view )

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