? semiconductor components industries, llc, 2010 june, 2010 -- rev. 4 1 publication order number: ntd4805n/d ntd4805n power mosfet 30 v, 88 a, single n--channel, dpak/ipak features ? low r ds(on) to minimize conduction losses ? low capacitance to minimize driver losses ? optimized gate charge to minimize switching losses ? these are pb--free devices applications ? cpu power delivery ? dc--dc converters ? low side switching maximum ratings (t j =25 c unless otherwise noted) parameter symbol value unit drain--to--source voltage v dss 30 v gate--to--source voltage v gs ? 20 v continuous drain current (r ja )(note1) steady state t a =25 c i d 16 a t a =85 c 12.6 power dissipation (r ja )(note1) t a =25 c p d 2.24 w continuous drain current (r ja )(note2) t a =25 c i d 12.6 a t a =85 c 9.8 power dissipation (r ja )(note2) t a =25 c p d 1.35 w continuous drain current (r jc ) (note 1) t c =25 c i d 88 a t c =85 c 68 power dissipation (r jc )(note1) t c =25 c p d 66 w pulsed drain current t p =10 m s t a =25 c i dm 175 a current limited by package t a =25 c i dmaxpkg 45 a operating junction and storage temperature t j ,t stg -- 5 5 t o 175 c source current (body diode) i s 55 a source current (body diode) pulsed t p =20 m s i sm 175 a drain to source dv/dt dv/dt 6.0 v/ns single pulse drain--t o--source avalanche energy (v dd =24v,v gs =10v, l=1.0mh,i l(pk) =24a,r g =25 ) e as 288 mj lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. f unctional operation above the recommended operating conditions is not implied. ex tended exposure to stresses above the recommended operating conditions may affect device reliability. case 369aa dpak (bent lead) style 2 marking diagrams & pin assignments case 369d ipak (straight lead dpak) 30 v 5.0 m @10v r ds(on) max 88 a i d max v (br)dss 7.4 m @4.5v http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. ordering information 1 2 3 4 case 369ac 3ipak (straight lead) 1 2 3 4 n--channel d s g yww 48 05ng 1 gate 2 drain 3 source 4 drain 4 drain 2 drain 1 gate 3 source 4 drain 2 drain 1 gate 3 source yww 48 05ng yww 48 05ng y = year ww = work week 4805n = device code g = pb--free package 1 2 3 4
ntd4805n http://onsemi.com 2 thermal resistance maximum ratings parameter symbol value unit junction--to--case (drain) r jc 2.25 c/w junction--to--tab (drain) r jc--tab 3.5 junction--to--ambient -- steady state (note 1) r ja 67 junction--to--ambient -- steady state (note 2) r ja 111 1. surface--mounted on fr4 board using 1 in sq pad size, 1 oz cu. 2. surface--mounted on fr4 board using the minimum recommended pad size. electrical characteristics (t j =25 c unless otherwise noted) parameter symbol test condition min typ max unit off characteristics drain--to--source breakdown voltage v (br)dss v gs =0v,i d = 250 m a 30 v drain--to--source breakdown voltage temperature coefficient v (br)dss /t j 27 mv/ c zero gate voltage drain current i dss v gs =0v, v ds =24v t j =25 c 1.0 m a t j = 125 c 10 gate--to--source leakage current i gss v ds =0v,v gs = ? 20 v ? 100 na on characteristics (note 3) gate threshold voltage v gs(th) v gs =v ds ,i d = 250 m a 1.5 2.5 v negative threshold temperature coefficient v gs(th) /t j 5.86 mv/ c drain--to--source on resistance r ds(on) v gs =10to 11.5 v i d =30a 4.3 5.0 m i d =15a 4.2 v gs =4.5v i d =30a 6.0 7.4 i d =15a 5.8 forward transconductance gfs v ds =15v,i d =15a 17 s charges and capacitances input capacitance c iss v gs =0v,f=1.0mhz, v ds =12v 2865 pf output capacitance c oss 610 reverse transfer capacitance c rss 338 total gate charge q g(tot) v gs =4.5v,v ds =15v, i d =30a 20.5 26 nc threshold gate charge q g(th) 4.05 gate--to--source charge q gs 8.28 gate--to--drain charge q gd 8.36 total gate charge q g(tot) v gs =11.5v,v ds =15v, i d =30a 48 nc switching characteristics (note 4) turn--on delay time t d(on) v gs =4.5v,v ds =15v, i d =15a,r g =3.0 17.2 ns rise time t r 20.3 turn--off delay time t d(off) 20.8 fall time t f 8.0 turn--on delay time t d(on) v gs =11.5v,v ds =15v, i d =15a,r g =3.0 10.8 ns rise time t r 20.5 turn--off delay time t d(off) 30.8 fall time t f 4.4 3. pulse test: pulse width 300 m s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperatures.
ntd4805n http://onsemi.com 3 electrical characteristics (t j =25 c unless otherwise noted) parameter symbol test condition min typ max unit drain--source diode characteristics forward diode voltage v sd v gs =0v, i s =30a t j =25 c 0.87 1.2 v t j = 125 c 0.76 reverse recovery time t rr v gs = 0 v, dis/dt = 100 a/ m s, i s =30a 25.7 ns charge time ta 13.1 discharge time tb 12.6 reverse recovery time q rr 18 nc package parasitic values source inductance l s t a =25 c 2.49 nh drain inductance, dpak l d 0.0164 drain inductance, ipak l d 1.88 gate inductance l g 3.46 gate resistance r g 0.8
ntd4805n http://onsemi.com 4 typical performance curves 4v 10 v 50 0.01 60 0.001 0 90 2.0 1.5 1.0 0.5 10,000 100,000 05 30 2 1 v ds , drain--to--source voltage (volts) i d , drain current (amps) 0 v gs , gate--to--source voltage (volts) figure 1. on--region characteristics figure 2. transfer characteristics i d , drain current (amps) 3 0.045 4 0.020 0.010 0 5 figure 3. on--resistance vs. gate--to--source voltage v gs , gate--to--source voltage (volts) figure 4. on--resistance vs. drain current and gate voltage i d , drain current (amps) r ds(on) , drain--to--source resistance ( ) r ds(on) , drain--to--source resistance ( ) figure 5. on--resistance variation with temperature t j , junction temperature ( c) figure 6. drain--to--source leakage current vs. drain voltage v ds , drain--to--source voltage (volts) r ds(on) , drain--to--source resistance (normalized) i dss , leakage (na) --50 50 25 0 --25 75 125 100 23 15 10 25 5 3 v ds 10 v t j =25 c t j =--55 c t j = 125 c v gs =4.5v 175 v gs =0v i d =30a v gs =10v 50 t j = 175 c t j = 125 c 40 0 180 80 45 t j =25 c 20 10 5v 2.8 v 6v 6 1000 4 90 1 0 120 610 0.030 70 0.005 80 3.2 v 4.5 v 3.4 v 3.6 v 3.8 v 110 40 10 20 60 80 70 20 140 60 100 i d =30a t j =25 c 789 0.005 0.015 0.025 0.040 0.035 55 65 75 85 v gs =11.5v 150 100 100 3v 160 0.002 0.006 0.003 0.007 0.004 0.008 0.009 30 40 35 45
ntd4805n http://onsemi.com 5 typical performance curves c rss 10 0 10 15 25 gate--to--source or drain--to--source voltage (volts) c, capacitance (pf) figure 7. capacitance variation 1000 0 v gs v ds 2000 55 v gs =0v v ds =0v t j =25 c c iss c oss c rss c iss 3000 5000 figure 8. gate--to--source and drain--to--source voltage vs. total charge v gs , gate--to--source voltage (volts) 0 2 0 q g , total gate charge (nc) 7 4 10 5 i d =30a v gs =4.5v t j =25 c q 2 q 1 q t 25 15 0 0.5 v sd , source--to--drain voltage (volts) i s , source current (amps) figure 9. resistive switching time variation vs. gate resistance r g , gate resistance (ohms) 1 10 100 1000 1 t, time (ns) v gs =0v figure 10. diode forward voltage vs. current 100 0.6 0.7 1.0 5 10 15 t r t d(off) t d(on) t f 10 v dd =15v i d =30a v gs =11.5v 0.8 0.9 20 30 25 t j =25 c figure 11. maximum rated forward biased safe operating area 0.1 1 100 v ds , drain--to--source voltage (volts) 0.1 1000 i d , drain current (amps) r ds(on) limit thermal limit package limit 10 10 v gs =20v single pulse t c =25 c 1ms 100 m s 10 ms dc 10 m s 20 6 1 100 0 25 t j , junction temperature ( c) i d =29a figure 12. maximum avalanche energy vs. starting junction temperature 50 75 175 50 100 150 100 125 200 250 eas, single pulse drain--to--source avalanche energy (mj) 150 4000 1 3 5 20 300 350 400 450
ntd4805n http://onsemi.com 6 typical performance curves figure 13. avalanche characteristics 1000 1 100 pulse width ( m s) i d , drain current (amps) 10 10 125 c 1 100 100 c 25 c figure 14. thermal response r(t), effective transient thermal resistance (normalized) t, time ( m s) 0.1 1.0 0.01 0.1 0.2 0.02 d=0.5 0.05 0.01 single pulse r jc (t) = r(t) r jc d curves apply for power pulse train shown read time at t 1 t j(pk) -- t c =p (pk) r jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 1.0e+00 1.0e+01 1.0e--01 1.0e--02 1.0e--03 1.0e--04 1.0e--05 ordering information order number package shipping ? ntd4805nt4g dpak (pb--free) 2500 tape & reel ntd4805n--1g ipak (pb--free) 75 units/rail ntd4805n--35g ipak trimmed lead (3.5 ? 0.15 mm) (pb--free) 75 units/rail ?for information on tape and reel specificat ions, including part orientation and tape si zes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ntd4805n http://onsemi.com 7 package dimensions dpak (single guage) case 369aa--01 issue b b d e b3 l3 l4 b2 e m 0.005 (0.13) c c2 a c c z dim min max min max millimeters inches d 0.235 0.245 5.97 6.22 e 0.250 0.265 6.35 6.73 a 0.086 0.094 2.18 2.38 b 0.025 0.035 0.63 0.89 c2 0.018 0.024 0.46 0.61 b2 0.030 0.045 0.76 1.14 c 0.018 0.024 0.46 0.61 e 0.090 bsc 2.29 bsc b3 0.180 0.215 4.57 5.46 l4 -- -- -- 0 . 0 4 0 -- -- -- 1 . 0 1 l 0.055 0.070 1.40 1.78 l3 0.035 0.050 0.89 1.27 z 0.155 ------ 3.93 ------ notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. thermal pad contour optional within dimensions b3, l3 and z. 4. dimensions d and e do not include mold flash, protrusions, or burrs. mold flash, protrusions, or gate burrs shall not exceed 0.006 inches per side. 5. dimensions d and e are determined at the outermost extremes of the plastic body. 6. datums a and b are determined at datum plane h. 12 3 4 h 0.370 0.410 9.40 10.41 a1 0.000 0.005 0.00 0.13 l1 0.108 ref 2.74 ref l2 0.020 bsc 0.51 bsc a1 h detail a seating plane a b c l1 l h l2 gauge plane detail a rotated 90 cw style 2: pin 1. gate 2. drain 3. source 4. drain 5.80 0.228 2.58 0.102 1.60 0.063 6.20 0.244 3.00 0.118 6.17 0.243 ? mm inches ? scale 3:1 *for additional information on our pb--free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
ntd4805n http://onsemi.com 8 package dimensions 3 ipak, straight lead case 369ac--01 issue o d a k b r v f g 3pl e c j h dim min max min max millimeters inches a 0.235 0.245 5.97 6.22 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.043 0.94 1.09 g 0.090 bsc 2.29 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.134 0.142 3.40 3.60 r 0.180 0.215 4.57 5.46 v 0.035 0.050 0.89 1.27 w 0.000 0.010 0.000 0.25 notes: 1.. dimensioning and tolerancing per ansi y14.5m, 1982. 2.. controlling dimension: inch. 3. seating plane is on top of dambar position. 4. dimension a does not include dambar position or mold gate. w seating plane 0.13 (0.005) w ipak (straight lead dpak) case 369d--01 issue b style 2: pin 1. gate 2. drain 3. source 4. drain 123 4 v s a k -- t -- seating plane r b f g d 3pl m 0.13 (0.005) t c e j h dim min max min max millimeters inches a 0.235 0.245 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.090 bsc 2.29 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.350 0.380 8.89 9.65 r 0.180 0.215 4.45 5.45 s 0.025 0.040 0.63 1.01 v 0.035 0.050 0.89 1.27 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. z z 0.155 ------ 3.93 ------ on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further noti ce to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation speci al, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performa nce may vary over time. all operating parameters, including ?typicals? must be validated for each custo mer application by customer?s technical experts. scillc does not conve y any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant int o the body, or other applications intended to support or sustain life, or for any other application in which the f ailure of the scillc product could create a situation where personal inj ury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthoriz ed application, buyer shall indemnify and hold scillc and its officers, em ployees, subsidiaries, affiliates, and distributors harmless against all claims, cos ts, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, an y claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the p art. scillc is an equal opportunity/affirmative action employer. this literature is subj ect to all applicable copyright la ws and is not for resale in any manner. ntd4805n/d publication ordering information n. american technical support : 800--282--9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81--3--5773--3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303--675--2175 or 800--344--3860 toll free usa/canada fax : 303--675--2176 or 800--344--3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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