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pwm, step-down dc-to-dc controller with margining and tracking adp1822 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006C2007 analog devices, inc. all rights reserved. 6 features the adp1822 regulated output can track another power supply and can be dynamically adjusted up or down with the controllers margining-control inputs, making it ideal for high reliability applications. it is well suited for a wide range of high power applications, such as dsp power and processor core power in telecommunications, medical imaging, high performance servers, and industrial applications. it operates from a 3.7 v to 5.5 v supply with power input voltage ranging from 1.0 v to 24 v. wide power input voltage range: 1 v to 24 v chip supply voltage range: 3.7 v to 5.5 v wide output voltage range: 0.6 v to 85% of input voltage 1% accuracy, 0.6 v reference voltage output voltage margining control output voltage tracking all n-channel mosfet the adp1822 can operate at any frequency between 300 khz and 1.2 mhz, either by synchronizing with an external source or an internally generated, logic-controlled clock of 300 khz or 600 khz. it includes an adjustable soft start to allow sequencing and quick power-up while preventing input inrush current. output reverse-current protection at startup prevents excessive output voltage excursions. the adjustable, virtually lossless current- limit scheme reduces external part count and improves efficiency. 300 khz, 600 khz, or up to 1.2 mhz synchronized frequency no current sense resistor required power-good output programmable soft start with reverse current protection current-limit protection thermal overload protection overvoltage protection undervoltage lockout 1 a shutdown supply current the adp1822 operates over the ?40c to +125c junction temperature range and is available in a 24-lead qsop package. small, 24-lead qsop package applications 97 87 01 load current (a) efficiency (%) 96 95 94 93 92 91 90 89 88 2 4 6 8 10 12 14 1.8v output 3.3v output 05311-006 telecommunications and networking systems high performance servers medical imaging systems dsp core power supplies microprocessor core power supplies mobile communication base stations distributed power general description the adp1822 is a versatile and inexpensive synchronous voltage- mode pwm step-down controller. it drives an all n-channel power stage to regulate an output voltage as low as 0.6 v. figure 1. efficiency vs. load current, 5 v input bias input 5v 1f 10 ? freq sync mar msel comp ss 100nf irf3711 irf3711 1h 180f 20v 1000f 4v dh bst sw dl pgnd trkp trkn fb mdn mup 0.1f pvcc adp1822 6.18k ? power input 2.25v to 24v 05311-001 output 1.8v, 15a 1f 80.6k ? 309pf agnd dgnd tracking signal input 2.2pf 1nf 15pf 158k ? 316k ? cmosh-3 20k ? 10k ? vcc pwgd csl shdn figure 2. typical operating circuit
adp1822 rev. c | page 2 of 24 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 absolute maximum ratings............................................................ 5 esd caution.................................................................................. 5 simplified block diagram ............................................................... 6 pin configuration and function descriptions............................. 7 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 12 current-limit scheme............................................................... 12 output voltage margining ........................................................ 12 output voltage tracking ........................................................... 12 soft start ...................................................................................... 12 high-side driver (bst and dh).............................................. 13 low-side driver (dl) ................................................................ 13 input voltage range ................................................................... 13 setting the output voltage ........................................................ 13 switching frequency control ................................................... 13 compensation............................................................................. 13 power-good indicator............................................................... 13 shutdown control...................................................................... 13 application information................................................................ 14 selecting the input capacitor ................................................... 14 output lc filter ......................................................................... 14 selecting the mosfets ............................................................ 15 setting the current limit .......................................................... 15 feedback voltage divider ......................................................... 16 setting the voltage margin........................................................ 16 compensating the regulator .................................................... 16 setting the soft start period...................................................... 18 synchronizing the converter.................................................... 19 setting the output voltage tracking ....................................... 19 application circuits ....................................................................... 20 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 21 revision history 5/07rev. b to rev. c changes to features.......................................................................... 1 changes to general description .................................................... 1 changes to specifications section.................................................. 3 changes to table 2............................................................................ 5 changes to theory of operation section.................................... 12 changes to current limit scheme section ................................. 12 changes to setting the current limit section............................ 15 changes to ordering guide .......................................................... 21 8/06rev. a to rev. b change to title.................................................................................. 1 change to general description ...................................................... 1 changes to figure 6.......................................................................... 9 changes to output voltage margining section.......................... 12 changes to table 4.......................................................................... 12 1/06rev. 0 to rev. a changes to figure 1...........................................................................1 changes to table 1.............................................................................3 changes to input voltage range section .................................... 13 changes to selecting the input capacitor section..................... 14 added equation 1; renumbered sequentially ........................... 14 changes to equation 7 and equation 8 ....................................... 15 changes to selecting the mosfets section.............................. 15 added equation 9; renumbered sequentially ........................... 15 changes to equation 10................................................................. 15 changes to equation 22................................................................. 17 changes to compensating the regulator section...................... 17 changes to figure 19 and figure 20............................................. 17 changes to equation 27................................................................. 17 changes to equation 34................................................................. 18 7/05revision 0: initial version
adp1822 rev. c | page 3 of 24 specifications v vcc = v pvcc = v shdn = v freq = v trkn = 5 v, sync = mar = msel = gnd. all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). t j = ?40c to +125c, unless otherwise specified. typical values are at t a = 25c. table 1. parameter conditions min typ max unit power supply input voltage 3.7 5.5 v undervoltage lockout threshold v vcc rising, t j = ?40c to +125c 2.4 2.7 3.0 v v vcc rising, t a = 25c 2.5 2.7 2.9 v undervoltage lockout hysteresis v vcc 0.1 v quiescent current i vcc + i vcc , not switching 1 2 ma shutdown current shdn = gnd 10 a power stage supply voltage 1.0 24 v error amplifer fb regulation voltage t j = ?40c to +85c 594 600 606 mv t j = ?40c to +125c 588 600 606 mv fb input bias current C100 +1 +100 na error amplifier open-loop voltage gain 70 db comp output sink current 600 a comp output source current 110 a pwm controller pwm peak ramp voltage 1.25 v dl minimum on time freq = vcc (300 khz) 120 170 220 ns freq = vcc (300 khz), t a =25c 140 170 200 ns soft start ss pull-up resistance ss = gnd 95 k ss pull-down resistance v ss = 0.6 v 1.65 2.5 4.2 k oscillator oscillator frequency freq = gnd 250 310 375 khz freq = vcc 470 570 720 khz synchronization range freq = gnd 300 600 khz freq = vcc 600 1200 khz sync minimum pulse width 80 ns current sense csl threshold voltage relative to pgnd ?30 0 +30 mv csl output current v csl = 0 v 42 50 54 a current sense blanking period 160 ns gate drivers dh rise time c gate = 3 nf, v dh = v in , v bst ? v sw = 5 v 16 ns dh fall time c gate = 3 nf, v dh = v in , v bst ? v sw = 5 v 12 ns dl rise time c gate = 3 nf, v dl = v in 19 ns dl fall time c gate = 3 nf, v dl = 0 v 13 ns driver r on , sourcing current 1 a, 0.7 s pulse 2 driver r on , sinking current 1 a, 0.7 s pulse 1.5 dl low to dh high dead time 33 ns dh low to dl high dead time 42 ns voltage margining high output voltage margin resistance mup to fb, v mar = v msel = 5 v 20 low output voltage margin resistance mdn to fb, v mar = 5 v, v msel = 0 v 20
adp1822 rev. c | page 4 of 24 parameter conditions min typ max unit tracking tracking comparator input offset C200 +200 mv tracking comparator delay 100 ns tracking comparator common-mode input voltage range 0 v vcc v trkp pull-up resistance pull-up to vcc 200 k trkn pull-down resistance 200 k logic thresholds ( shdn , sync, freq, mar, msel) input high voltage v vcc = 3.7 v to 5.5 v 2.0 v input low voltage v vcc = 3.7 v to 5.5 v 0.8 v sync, freq input leakage current sync = freq = gnd 0.1 1 a shdn , mar, msel pull-down resistance 100 k thermal shutdown thermal shutdown threshold 145 c thermal shutdown hysteresis 10 c pwgd output fb overvoltage threshold v fb rising 750 mv fb overvoltage hysteresis 35 mv fb undervoltage threshold v fb rising 550 mv fb undervoltage hysteresis 35 mv pwgd off current v pwgd = 5 v 1 a pwgd low voltage i pwgd = 10 ma 150 500 mv
adp1822 rev. c | page 5 of 24 absolute maximum ratings table 2. parameter rating stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. vcc, shdn ?0.3 v to +6 v , sync, freq, comp, ss, fb, trkp, trkn, mar, msel, mup, and mdn to gnd; pvcc to pgnd; bst to sw bst to gnd ?0.3 v to +30 v csl to gnd ?1 v to +30 v dh to gnd (v sw ? 0.3 v) to (v bst + 0.3 v) absolute maximum ratings apply individually only, not in combination. unless otherwise specified, all other voltages are referenced to gnd. dl to pgnd ?0.3 v to (v pvcc + 0.3 v) sw to gnd ?2 v to +30 v pgnd to gnd 2 v esd caution ja , 2-layer (semi standard board) 122c/w ja , 4-layer (jedec standard board) 82c/w operating ambient temperature range ?40c to +85c operating junction temperature range ?55c to +125c storage temperature range ?65c to +150c maximum soldering lead temperature 260c
adp1822 rev. c | page 6 of 24 simplified block diagram thermal shutdown logic uvlo oscillator fault s r q q pwm vcc fault reference thsd uvlo ov v ref uv 0.8v 100k ? 2.5k ? bst dh sw pvcc dl pgnd csl pwgd fb mar msel mup dgnd mdn ss comp sync freq gnd vcc shdn adp1822 05311-002 decode trkn trkp figure 3. simplified block diagram
adp1822 rev. c | page 7 of 24 pin configuration and fu nction descriptions 05311-005 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 19 18 17 16 15 14 13 12 11 nc = no connect dh sw sync trkn mar freq bst pvcc dl pgnd mup vcc csl trkp shdn gnd dgnd pwgd mdn msel ss fb comp nc adp1822 top view (not to scale) figure 4. adp1822 pin configuration table 3. pin function descriptions pin o. mneonic description 1 bst high-side gate driver boost capacitor input. a capacitor between sw and bst powers the high-side gate driver dh. the capacitor is charged through a diode from pvcc when the low-side mosfet is on. connect a 0.1 f or greater ceramic capacitor from bst to sw and a schottky diode from pvcc to bst to power the high-side gate driver. 2 dh high-side gate driver output. connect dh to the gate of the external high-side n-channel mosfet switch. dh is powered from the capacitor between sw and bst and its voltage swings between v sw and v bst . 3 sw power switch node. sw is the power switching node. co nnect the source of the high-side n-channel mosfet switch and the drain of the low-side n-channel mosfet synchronous rectifier to sw. sw powers the output through the output lc filter. 4 sync frequency synchronization input. drive sync with an external 300 khz to 1.2 mhz signal to synchronize the converter switching frequency to the applied signal. the maximum sync frequency is limited to 2 the nominal internal frequency selected by freq. do not leave sync unconnected; when not used, connect sync to gnd. 5 freq frequency select input. freq selects the converter switching frequency. drive freq low to select 300 khz, or high to select 600 khz. do not leave freq unconnected. 6 mar margin control input. mar is used with msel to co ntrol output voltage margining. mar chooses between high voltage and low voltage margining when msel is driven high. if not used, connect mar to gnd. 7 trkn tracking comparator negative input. drive trkn from the voltage that the adp1822 output voltage tracks. trkn voltage is limited to vcc. see the output voltage tracking section. 8 trkp tracking comparator positive input. drive trkp from the output voltage. trkp voltage is limited to vcc. see the output voltage tracking section. 9 shdn active low dc-to-dc shutdown input. drive shdn high to turn on the converter. drive it low to turn it off. connect shdn to vcc for automatic startup. 10 pwgd open-drain power-good output. pwgd sinks current to gnd when the output voltage is above or below the regulation voltage. connect a pull-up resistor from pwgd to vdd for a logical power-good indicator. 11 dgnd digital ground. connect dgnd to gnd at a single point as close as possible to the ic. 12 gnd analog ground. connect gnd to pgnd at a single point as close as possible to the ic. 13 ss soft start control input. a capacitor from ss to gnd controls the soft start period. when the output is overloaded, ss is discharged to prevent excessive input current while the output recovers. connect a 1 nf to 1 f capacitor from ss to gnd to set the soft start period. see the soft start section. 14 fb voltage feedback input. connect to a resistive voltage di vider from the output to fb to set the output voltage. see the setting the output voltage section. 15 comp compensation node. connect a resistor-capacitor networ k from comp to fb to compensate the regulation control system. see the compensation section. 16 msel margin select input. drive msel high to activate the voltage margining feature. drive msel low to regulate the output voltage to the nominal value. if not used, connect msel to gnd.
adp1822 rev. c | page 8 of 24 pin no. mnemonic description 17 mdn margin down input. connect a resistor from mdn to th e output voltage to set the low margining voltage. see the setting the voltage margin section. 18 mup margin up input. connect a resistor from mup to gnd to set the high margining voltage. see the setting the voltage margin section. 19 vcc internal power supply input. vcc powers the internal circuitry. bypass vcc to gnd with 0.1 f or greater capacitor connected as close as possible to the ic. 20 csl low-side current sense input. connect csl to sw th rough a resistor to set the current limit. see the setting the current limit section. 21 pgnd power ground. connect gnd to pgnd at a single point as close as possible to the ic. 22 dl low-side gate driver output. connect dl to the gate of the low-side n-channel mosfet synchronous rectifier. the dl voltage swings between pgnd and pvcc. 23 pvcc internal gate driver power supply input. pvcc powers the low-side gate driver dl. bypass pvcc to pgnd with 1 f or greater capacitor connected as close as possible to the ic. 24 nc no connection. not internally connected.
adp1822 rev. c | page 9 of 24 load current (a) efficiency (%) typical performance characteristics 97 87 01 6 0.6003 0.5996 ?50 110 temperature (c) feedback voltage (v) 96 95 94 93 92 91 90 89 88 0.6002 0.6001 0.6000 0.5999 0.5998 0.5997 2 4 6 8 10 12 14 1.8v output 3.3v output load current (a) efficiency (%) 05311-106 ?30 ?10 10 30 50 70 90 figure 5. efficiency vs. load current, v in = 5 v, v out = 3.3 v, 1.8 v 94 80 01 6 05311-009 700 0 ?50 100 temperature (c) switching frequency (khz) figure 8. fb regulation voltage vs. temperature 92 90 88 86 84 82 600 500 400 300 200 100 2 4 6 8 10 12 14 1.8v output 3.3v output 300khz 600khz 05311-010 05311-007 05 0 figure 6. efficiency vs. load current, v in = 12 v, v out = 3.3 v, 1.8 v figure 9. switching frequency vs. temperature 1400 0 06 vcc voltage (v) vcc current (a) 1200 1000 800 600 400 200 12345 05311-008 output voltage (20mv/div) load current (5a/div) 05311-011 figure 10. load transient response, 1.5 a to 15 a figure 7. vcc supply current vs. voltage
adp1822 rev. c | page 10 of 24 output voltage (1v/div) shdn (5v/div) pwgd (5v/div) 05311-012 output voltage (50mv/div) input voltage (5v/div) 05311-015 figure 11. power-on response figure 14. line transient response, 10 v to 16 v output voltage (1v/div) shdn (5v/div) pwgd (5v/div) 05311-013 05311-016 output voltage (100mv/div) mar voltage (5v/div) figure 12. power-on response, prebiased output figure 15. output voltage margin-down response output voltage (1v/div) load current (10a/div) 05311-014 05311-017 output voltage (100mv/div) mar voltage (5v/div) figure 13. output short-circ uit response and recovery figure 16. output voltage margin-up response
adp1822 rev. c | page 11 of 24 05311-018 tracking voltage (1v/div) output voltage (1v/div) figure 17. output voltage tracking response
adp1822 rev. c | page 12 of 24 theory of operation the adp1822 is a versatile, economical, synchronous-rectified, fixed frequency, voltage-mode, pulse-width modulated (pwm) step-down controller capable of generating an output voltage as low as 0.6 v. it is ideal for a wide range of high power applications, such as dsp and processor core power in telecommunications, medical imaging, and industrial applications. the adp1822 controller runs from 3.7 v to 5.5 v and accepts a power input voltage between 1.0 v and 24 v. the adp1822 includes circuitry to implement output voltage margining and can track an external voltage, making it ideal for high reliability applications with multiple dc-to-dc converters. it operates at a fixed, internally set 300 khz or 600 khz switching frequency that is controlled by the state of the freq input. the high frequency reduces external component size and cost while maintaining high efficiency. for noise sensitive applications where the switching frequency needs to be more tightly con- trolled, synchronize the adp1822 to an external signal whose frequency is between 300 khz and 1.2 mhz. the adp1822 includes adjustable soft start with output reverse- current protection, and a unique, adjustable, lossless current limit. it operates over the ?40c to +125c junction tempera- ture range and is available in a space-saving, 24-lead qsop package. current-limit scheme the adp1822 employs a unique, programmable cycle-by-cycle lossless current-sensing scheme that uses an inexpensive resistor to set the current limit. a 50 a current source is forced out of csl to a programming resistor connected to sw. the resulting voltage across the current sense resistor sets the current-limit threshold. when on-state voltage of the low-side mosfet synchronous rectifier exceeds the programmed threshold, the low-side mosfet remains on, preventing another on cycle and reducing the inductor current. once the mosfet voltage, and thus the inductor current, is below the current-sense threshold, the synchronous rectifier is allowed to turn off, and another cycle begins. when the adp1822 senses an overcurrent condition, ss sinks current from the soft start capacitor through an internal 2.5 k resistor, reducing the voltage at ss and thus reducing the regulated output voltage. the output behaves like a constant current source around the preset current limit in the event of an overcurrent condition. the adp1822 remains in this mode for as long as the overcurrent condition persists. when the overcurrent condition is removed, operation resumes in soft start mode. this ensures that when the overload condition is removed, the output voltage smoothly transitions back to regulation while providing protection for overload and short-circuit conditions. the adp1822 also offers a technique for implementing a current limit foldback in the event of a short circuit with the use of an additional resistor. see the setting the current limit section for more information. output voltage margining the adp1822 features output voltage margining. mar enables voltage margining, and msel controls whether the voltage is margined up or down. the voltage is margined by switching a resistor from fb to gnd (for the high margin) or from fb to the output voltage (for the low margin). the switches from fb are internal to the adp1822 through the mup and mdn terminals. table 4 shows the states of mar and msel and the resulting voltage margin setting. see the setting the voltage margin section for more information. table 4. voltage margining control msel mar voltage margin x l none (fb not changed) h h high margin (fb connected to mup) l h low margin (fb connected to mdn) output voltage tracking the adp1822 features an internal comparator that forces the output voltage to track an external voltage at startup, which prevents the output voltage from exceeding the tracking voltage. the comparator turns off the high-side switch if the positive tracking (trkp) input voltage exceeds the negative tracking (trkn) input voltage. connect trkp to the output voltage and drive trkn with the voltage to be tracked. if the voltage at trkn is below the regulation voltage, the output voltage is limited to the voltage at trkn. if the voltage at trkn is above the regulation voltage, the output voltage regulates the desired voltage set by the voltage divider. for more information, see the setting the output voltage tracking section. soft start when powering up or resuming operation after shutdown, overload, or short-circuit conditions, the adp1822 employs an adjustable soft start feature that reduces input current transients and prevents output voltage overshoot at start-up and overload conditions. the soft start period is set by the value of the soft start capacitor, c ss , between ss and gnd. when starting the adp1822, c ss is initially discharged. it is enabled by either driving shdn high or by bringing vcc above the undervoltage lockout threshold, and c ss begins charging to 0.8 v through an internal 100 k resistor. as c ss charges, the regulation voltage at fb is limited to the lesser of either the voltage at ss or the internal 0.6 v reference voltage. as the voltage at ss rises, the output voltage rises proportionally until the voltage at ss exceeds 0.6 v. at this time, the output voltage is regulated to the desired voltage.
adp1822 rev. c | page 13 of 24 if the output voltage is precharged prior to turn-on, the adp1822 prevents reverse inductor current that would discharge the output voltage. once the voltage at ss exceeds the 0.6 v regulation voltage, the reverse current is re-enabled to allow the output voltage regulation to be independent of load current. to override the soft start feature, leave ss unconnected. this allows the output voltage to rise as quickly as possible and eliminates the soft start period. high-side driver (bst and dh) gate drive for the high-side power mosfet is generated by a flying capacitor boost circuit. this circuit allows the high-side n-channel mosfet gate to be driven above the input voltage, allowing full enhancement of and a low voltage drop across the mosfet. the circuit is powered from a flying capacitor from sw to bst that in turn is powered from the pvcc gate driver voltage. when the low-side switch is turned on, sw is driven to pgnd, and the flying capacitor is charged from pvcc through an external schottky rectifier. the capacitor stores sufficient charge to power bst to drive dh high and to fully enhance the high-side n-channel mosfet. use a flying capacitor value greater than 100 the high-side mosfet input capacitance. low-side driver (dl) dl is the gate drive for the low-side power mosfet synchronous rectifier. synchronous rectification reduces conduction losses developed by a conventional rectifier by replacing it with a low resistance mosfet switch. dl turns on the synchronous rectifier by driving the gate voltage to pvcc. the mosfet is turned off by driving the gate voltage to pgnd. an active dead time reduction circuit reduces the break-before- make time of the switching to limit the losses due to current flowing through the synchronous rectifier body diode or external schottky rectifier. input voltage range the adp1822 takes its internal power from the vcc and pvcc inputs. pvcc powers the low-side mosfet gate drive (dl), and vcc powers the internal control circuitry. both of these inputs are limited to between 3.7 v and 5.5 v. bypass pvcc to pgnd with a 1 f or greater capacitor. bypass vcc to gnd with a 0.1 f or greater capacitor. the power input to the dc-to-dc converter can range between 1.2 the output voltage up to 24 v. bypass the power input to pgnd with a suitably large capacitor. see the selecting the input capacitor section. setting the output voltage the output voltage is set using a resistive voltage divider from the output to fb. the voltage divider drops the output voltage to the 0.6 v fb regulation voltage to set the regulation output voltage. the output voltage is set to voltages as low as 0.6 v and as high as 85% of the minimum power input voltage (see the feedback voltage divider section). switching frequency control the adp1822 has a logic-controlled frequency select input, freq, which sets the switching frequency to 300 khz or 600 khz. drive freq low for 300 khz and drive it high for 600 khz. the sync input is used to synchronize the converter switching frequency to an external signal. the synchronization range is 300 khz to 1.2 mhz. the acceptable synchronization frequency range is limited to twice the nominal switching frequency set by freq. for lower frequency synchronization, between 300 khz and 600 khz, connect freq to gnd. for higher frequency synchronization, between 480 khz and 1.2 mhz, connect freq to vcc (see the synchronizing the converter section for more information). compensation the control loop is compensated by an external series rc network from comp to fb and sometimes requires a series rc in parallel with the top voltage divider resistor. comp is the output of the internal error amplifier. the internal error amplifier compares the voltage at fb to the internal 0.6 v reference voltage. the difference between the two (the feedback voltage error) is amplified by the error amplifier. to optimize the adp1822 for stability and transient response for a given set of external components and input/output voltage conditions, choose the compensation components. for more information on choosing the compensation components, see the compensating the regulator section. power-good indicator the adp1822 features an open-drain power-good output, pwgd, that sinks current when the output voltage drops 8.3% below or 25% above the nominal regulation voltage. two comparators measure the voltage at fb to set these thresholds. the pwgd output also sinks current if overtemperature or input undervoltage conditions are detected. it is operational with v cc voltage as low as 1.0 v. use this output as a simple power-good signal by connecting a pull-up resistor from pwgd to an appropriate supply voltage. shutdown control the adp1822 dc-to-dc converter features a low power shut- down mode that reduces quiescent supply current to 1 a. to shut down the adp1822, drive shdn low. to turn it on, drive shdn high. for automatic startup, connect shdn to vcc.
adp1822 rev. c | page 14 of 24 application information selecting the input capacitor the output ripple voltage is a function of the inductor ripple current and the capacitor impedance at the switching frequency. for high esr capacitors, the impedance is dominated by the esr, while for low esr capacitors, the impedance is dominated by the capacitance. determine if the capacitor is high esr or low esr by comparing the zero frequency formed by the capacitance and the esr to the switching frequency: the input capacitor absorbs the switched input current of the dc-to-dc converter, allowing the input source to deliver smooth dc current. choose an input capacitor whose impedance at the switching frequency is lower than the input source impedance. use low equivalent series resistance (esr) capacitors, such as low esr tantalum, ceramic, or organic electrolyte (such as sanyo os-con) types. for all types of capacitors, make sure that the current rating of the capacitor is greater than the input rms ripple current, which is approximately () () esrc f out esrz 2 1 = (3) 1 v v v v ii out in in out load in_rms ?? (1) where: f esrz is the frequency of the output capacitor esr zero. c out is the output capacitance. esr is the equivalent series resistance of the capacitor. output lc filter if f esrz is much less than the switching frequency, then the capacitor is high esr, and the esr dominates the impedance at the switching frequency. if f esrz is much greater than the switching frequency, the capacitor is low esr, and the impedance is dominated by the capacitance at the switching frequency. the output lc filter smoothes the switched voltage at sw, making the output an almost dc voltage. choose the output lc filter to achieve the desired output ripple voltage. since the output lc filter is part of the regulator negative-feedback control loop, the choice of the output lc filter components affects the regulation control-loop stability. when using capacitors whose impedance is dominated by esr at the switching frequency (such as tantalum or aluminum electrolytic capacitors), approximate the output voltage ripple current by choose an inductor value such that the inductor ripple current is approximately 1/3 of the maximum dc output load current. using a larger value inductor results in a physical size larger than required, and using a smaller value results in increased losses in the inductor and/or mosfet switches. )(? esriv l out ? (4) choose the inductor value by ? ? ? ? ? ? ? = in out out l sw v v v if l 1 ))(( 1 (2) where: v out is the output ripple voltage. i l is the inductor ripple current. esr is the total equivalent series resistance of the output capacitor (or the parallel combination of esr of all parallel- connected output capacitors). where: l is the inductor value. f sw is the switching frequency. v out is the output voltage. v in is the input voltage. i l is the inductor ripple current, typically 1/3 of the maximum dc load current. make sure that the ripple current rating of the output capacitor(s) is greater than the maximum inductor ripple current. for output capacitors whose esr is much lower than the capacitive impedance at the switching frequency, the capacitive impedance dominates the output ripple current. in this case, determine the ripple voltage by choose the output capacitor to set the desired output voltage ripple. the adp1822 functions with output capacitors that have both high and low esr. for high esr capacitors, such as tantalum or electrolytic types, many parallel connected capacitors may be required to achieve the desired output ripple voltage. when choosing an output capacitor, consider ripple current rating, capacitance, and esr. make sure that the ripple current rating is higher than the maximum inductor ripple current (i l ). () ( ) sw out l out fc i v 8 ? (5) where: f sw is the switching frequency. c out is the output capacitance.
adp1822 rev. c | page 15 of 24 when f esrz is approximately the same as the switching frequency, the square-root sum of the squares of the two ripples applies, or [] () () 2 2 8 )( ? ? ? ? ? ? + ? sw out l l out fc i esriv (6) selecting the mosfets the choice of mosfet directly affects the dc-to-dc converter performance. the mosfet must have low on resistance to reduce i 2 r losses and low gate charge to reduce transition losses. in addition, the mosfet must have low thermal resistance to ensure that the power dissipated in the mosfet does not result in excessive mosfet die temperature. the high-side mosfet carries the load current during on time and carries all the transitions losses of the converter. typically, the lower the mosfet on resistance, the higher the gate charge and vice versa. therefore, it is important to choose a high-side mosfet that balances the two losses. the conduction loss of the high-side mosfet is determined by ()() ? ? ? ? ? ? ? ? ? in out on load c v v rip 2 (7) where: p c is the conduction power loss. r on is the mosfet on resistance. the gate-charging loss is approximated by ( ) ( ) ( ) swg pvcc t fqvp ? (8) where: p t is the gate-charging loss power. v pvcc is the gate driver supply voltage. q g is the mosfet total gate charge. f sw is the converter switching frequency. the high-side mosfet transition loss is approximated by () 2 sw fr load in sw fttiv p + = (9) where: p sw is the high-side mosfet switching loss power. t r is the mosfet rise time. t f is the mosfet fall time. the total power dissipation of the high-side mosfet is the sum of all the previous losses, or ( ) ( ) ( ) sw t chs pppp ++? (10) where p hs is the total high-side mosfet power loss. the low-side mosfet does not carry the transition losses but does carry the inductor current when the high-side mosfet is off. for high input and low output voltages, the low-side mosfet carries the current most of the time, and therefore to achieve high efficiency, it is critical to optimize the low-side mosfet for low on resistance. in some cases, where the power loss exceeds the mosfet rating, or lower resistance is required than is available in a single mosfet, connect multiple low-side mosfets in parallel. the equation for low-side mosfet power loss is ()() ? ? ? ? ? ? ? ? in out on load ls v v rip 1 2 (11) where: p ls is the low-side mosfet on resistance. r on is the total on resistance of the low-side mosfet(s). if multiple low-side mosfets are used in parallel, use the parallel combination of the on resistances for determining r on to solve this equation. setting the current limit the internal current-limit circuit measures the voltage across the low-side mosfet to determine the load current. when the low-side mosfet current exceeds the current limit, the high- side mosfet is not allowed to turn on until the current drops below the current-limit. the current limit is set through the current-limit resistor, r cl . the current-sense pin, csl, sources 50 a through r cl . this creates an offset voltage of resistance of r cl multiplied by the 50 a csl current. when the low-side mosfet voltage is equal to or greater than the offset voltage, the adp1822 is in current limit mode and prevents additional on-time cycles. choose the current-limit resistor by the equation ( ) ( ) a42 onwc lpk cl ri r = (12) where: i lpk is the peak inductor current. r onwc is the worst-case (maximum) low-side mosfet on resistance. the worst-case, low-side mosfet on resistance can be found in the mosfet data sheet. note that mosfets typically increase on resistance with increasing die temperature. to determine the worst-case mosfet on resistance, calculate the worst-case mosfet temperature (based on the mosfet power loss) and multiply by the ratio between the typical on resistance at that temperature and the on resistance at 25c as listed in the mosfet data sheet. in addition, the adp1822 offers a technique for implementing a current-limit foldback in the event of a short circuit with the use of an additional resistor, as shown in figure 18 . the resistor r lo is largely responsible for setting the foldback current limit during a short circuit, and r hi is mainly responsible for setting up the normal current limit. r lo is lower than r hi . these current-limit sense resistors can be calculated as ( )( ) a42 onwc pkfoldback lo r i r = (13)
adp1822 rev. c | page 16 of 24 a42 ? = lo onwc lpk out hi r r i v r (14) choose the low margin resistor by the equation ? ? ? ? ? ? ?? ? ? ? ? ? ? = mdn out fb mdn top dn k v v k r r 1 (17) where: i pkfoldback is the desired short-circuit peak inductor current limit. i lpk is the peak inductor current limit during normal operation and is also used in equation 12. where: r dn is the down-margin resistor. r top is the top voltage divider resistor from fb to the output voltage. v fb is the 0.6 v feedback voltage. v out is the nominal output voltage setting. k mdn is the down-margin as a ratio of the nominal output voltage (for example, margining 4% down would be k mdn = 0.04). 05311-118 + v in m1 lv out c out m2 dh dl csl adp1822 r lo r hi for example, for an output voltage of 1.0 v and a 5% margin, choose r bot = 10 k (18) thus, figure 18. short-circuit current foldback scheme feedbac voltae divider k 67.6 = ? ? ? ? ? ? ? = fb fb out bot top v vv rr (19) the output regulation voltage is set through the feedback voltage divider. the output voltage is reduced through the voltage divider and drives the fb feedback input. the regulation threshold at fb is 0.6 v. for the low-side resistor of the voltage divider, r bot , use 10 k. a larger value resistor can be used but results in a reduction in output voltage accuracy. choose r top to set the output voltage by and ( ) ( ) k k rr rr r m up bot top bot top up 80 = ? ? ? ? ? ? ? ? + = (20) ? ? ? ? ? ? ? ? ? = fb fb out bot top v vv rr (15) and k k v v k r r mdn out fb mdn top dn 7.46 1 = ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? = (21) where: r top is the high-side voltage divider resistance. r bot is the low-side voltage divider resistance. v out is the regulated output voltage. v fb is the feedback regulation threshold, 0.6 v. compensating the regulator the output of the error amplifier at comp is used to compensate the regulation control system. connect a resistor capacitor (rc) network from comp to fb to compensate the regulator. setting the voltage margin the first step of selecting the compensation components is determining the desired regulation-control crossover frequency, f co . choose a crossover frequency approximately 1/10 of the switching frequency, or the output voltage is margined by connecting a resistor from fb to gnd (for the high margin voltage) or fb to the output voltage (for low margin voltage). the switches for margining are supplied inside the adp1822 and are controlled by the mar and msel inputs (see 10 sw co f f = tabl e 1 ). (22) choose the high margin resistor by ()() m u p bot top bot top up k rr rr r ? ? ? ? ? ? + = (16) the characteristics of the output capacitor affect the compensation required to stabilize the regulator. the output capacitor acts with its esr to form a zero. calculate the esr zero frequency by () () esrc f out esrz 2 1 = (23) where: r up is the up-margin resistor from mup to gnd. r bot is the bottom voltage divider resistor from fb to gnd. r top is the top voltage divider resistor from fb to the output voltage. k mup is the high voltage margin as a ratio of the output voltage (for example, margining 4% up would be k mup = 0.04). note that as similar capacitors are placed in parallel, the esr zero frequency remains the same. if f esrz f co /2, use the esr zero to stabilize the regulator (see the compensation using the esr zero section). if f esrz 2 f co , use a feed-forward network to stabilize the regulator (see the section). if f co /2 < f esrz < 2 f co , compensation using feed-forward
adp1822 rev. c | page 17 of 24 or then use both the esr zero and feed-forward zeros to stabilize the regulator (see the compensation using both the esr and feed-forward zeros section). in all three cases, it is sometimes beneficial, although not required, to add an additional compensation capacitor, c c2 , from comp to fb to reduce high frequency noise. this capacitor forms an extra pole in the loop response. choose this capacitor such that the pole occurs at approximately 1/2 of the switching frequency, or () ( ) comp c comp sw pc rcc f f 2 2 //2 1 2 == (24) assuming c comp >> c c2 , then solving for c c2 , ()( ) comp sw c rf c 2 2 2 = (25) compensation using the esr zero v out to pwm comp fb 0.6v r comp c comp c c2 r top r bot internal error amplifier 05311-003 figure 19. compensation using the esr zero if the output capacitor esr zero is sufficiently low (less than or equal to 1/2 of the crossover frequency), use the esr to stabilize the regulator. in this case, use the circuit shown in figure 19 . choose the compensation resistor to set the desired crossover frequency, typically 1/10 of the switching frequency or () ( ) () () () 2 lc in co esrz ramp top comp fv ffvr r = (26) where: r comp is the compensation resistor. v ramp is the internal ramp peak voltage, 1.25 v. f esrz and f co are the esr zero and crossover frequencies. v in is the dc input voltage. f lc is the characteristic frequency of the output lc filter, or lc f lc 2 1 = (27) using known constants ( ) ( ) ( ) () () i n sw esrz top comp v clffr r 9.4 ? (28) choose the compensation capaci tor to set the compensation zero, f zc , to the lesser of 1/4 of the crossover frequency or 1/2 of the lc resonant frequency, or ()( ) comp comp sw co zc rc ff f 2 1 404 === (29) ()( ) comp comp lc zc rc f f 2 1 2 == (30) solving for c comp , ()( ) comp co comp rf c 2 4 = (31) in terms of the switching frequency and combining the constants, ()( ) comp sw comp rf c 37.6 ? (32) or ()( ) comp lc comp rf c 2 2 = (33) or whichever is greater. compensation using feed-forward v out to pwm comp fb 0.6v r comp c comp r top r bot r ff c ff internal error amplifier 05311-004 c c2 figure 20. compensation using feed-forward if the esr zero is at too high a frequency to be useful in stabilizing the regulator, add a series rc network, as shown in figure 20 , in parallel with the top side voltage divider resistor, r top . this adds an additional zero and pole pair that is used to increase the phase at crossover, thus improving stability. choose the feed-forward zero frequency for 1/7 of the crossover frequency, and the feed-forward pole at 7 the crossover frequency. this sets the ratio of pole-to-zero frequency of approximately 50:1 for optimum stability. choose the compensation resistor, r comp , to set the crossover frequency by ( ) ( )( )( ) () 2 lc in co zff ramp top comp fv ffvr r = (34) where f zff is the feed-forward zero frequency and is 1/7 of the crossover frequency. simplify the following equation: ( ) () () () in sw top comp v clfr r 2 0705.0 ? (35)
adp1822 rev. c | page 18 of 24 ( ) ( ) ( )( ) () 2 lc in co zff ramp top comp fv ffvr r = choose the compensation capaci tor to set the compensation zero, f zc , to the lesser of 1/4 of the crossover frequency or 1/2 of the lc resonant frequency, or (46) ()( ) comp comp sw co zc rc ff f 2 1 404 === (36) where f zff is the feed-forward zero frequency and is 1/7 of the crossover frequency. simplify the following equation: ( ) ( ) () () in sw top comp v clfr r 2 0705.0 ? (47) or ()( ) comp comp lc zc rc f f 2 1 2 == (37) choose the compensation capaci tor to set the compensation zero, f zc , to 1/2 of the lc resonant frequency, or solving for c comp , ()( ) comp co comp rf c 2 4 = (38) in terms of the switching frequency and combining the constants, ()( ) comp sw comp rf c 37.6 ? (39) or ()( ) comp lc comp rf c 2 2 = (40) or whichever is greater. choose the feed-forward capacitor, c ff , to set the feed-forward zero at 1/7 of the crossover frequency 7 co zff f f = (41) or () () ff top co cr f 2 7 = (42) simplifying and solving for c ff , () ( ) sw top ff fr c 14.11 = (43) choose the feed-forward resistor, r ff , to set the condition () ()() ffff co cr f 27 1 = (44) simplifying and solving for r ff , () () ff sw ff cf r 227.0 = (45) compensation using both the esr and feed-forward zeros if the output capacitor esr zero frequency falls between 1/2 of the crossover frequency to 2 the crossover frequency, use the circuit shown in figure 19 , such that the esr zero, along with a feed-forward network, stabilizes the regulator. in this case, the feed-forward zero is set to 1/7 of the crossover frequency, and the feed-forward pole is set to the same frequency as the esr zero. choose the compensation resistor, r comp , to set the crossover frequency by ()( ) comp comp lc zc rc f f 2 1 2 == (48) solving for c comp , ()( ) comp lc comp rf c 2 2 = (49) choose the feed-forward capacitor, c ff , to set the feed-forward zero at 1/7 of the crossover frequency 7 co zff f f = (50) or () () ff top co cr f 2 7 = (51) simplifying and solving for c ff , () ( ) sw top ff fr c 14.11 = (52) choose the feed-forward resistor, r ff , to set the condition () ()() ffff co cr f 27 1 = (53) simplifying and solving for r ff , () () ff sw ff cf r 227.0 = (54) setting the soft start period the adp1822 uses an adjustable soft start to limit the output voltage ramp-up period, limiting the input inrush current. the soft start is set by selecting the capacitor, c ss , from ss to gnd. the adp1822 charges c ss to 0.8 v through an internal resistor. the voltage on c ss while it is charging is ? ? ? ? ? ? ? ? ?= ss rc css e v 1 1v8.0 (55) where r is the internal 100 k resistor. the soft start period, t ss , is achieved when v css = 0.6 v, or ? ? ? ? ? ? ? ? ?= ) k 100 1v8.0v6.0 ss ss c t e (56)
adp1822 rev. c | page 19 of 24 or () 386 . 1 v 8 . 0 v 6 . 0 1 ln k 100 = ? ? ? ? ? ? ? ? ? ? = ss ss c t (57) solving for c ss and combining constants, c ss = (7.213 10 ?6 ) t ss (58) synchronizing the converter the dc-to-dc converter switching can be synchronized to an external signal. this allows multiple adp1822 converters to be operated at the same frequency to prevent frequency beating or other interactions. to synchronize the adp1822 switching to an external signal, drive the sync input with the synchronizing signal. the adp1822 can only synchronize up to 2 the nominal oscillator frequency. if the frequency is set to 300 khz (freq connected to gnd), it can synchronize up to 600 khz. if the frequency is set to 600 khz (freq connected to vcc), it can synchronize to 1.2 mhz. the high-side mosfet turn-on follows the rising edge of the sync input by approximately 320 ns. to prevent erratic switching frequency, make sure that the falling edge of the sync input signal does not coincide with the falling edge of the dc-to-dc converter switching, or () () [] in out sw sync v v f d + ns 320 (59) where d sync is the duty cycle of the synchronization waveform. make sure that in all combinations of frequency, input, and output voltages, the sync input fall time does not align with the dc-to-dc converter fall time. setting the output voltage tracking the adp1822 provides a tracking function that limits the output voltage to or below an external tracking voltage. this is useful in systems where multiple dc-to-dc converters are used to power different sections of a circuit, such as a microcontroller or a dsp that has separate i/o and core voltages. in similar circuits, if the nominally lower of the two voltages exceeds the nominally higher voltage at startup or shutdown, the circuit powered may experience problems. to prevent this, use the tracking feature of the adp1822 to limit the output voltage to or below the tracking voltage at all times. to use the tracking feature, connect trkp to the output voltage and drive trkn with the tracking voltage. to ensure that noise does not cause unstable operation, connect a 1 nf capacitor between trkn and trkp as close to the adp1822 as possible. if either the adp1822 output voltage or the tracking voltage at any time exceeds the voltage at vcc, use equal voltage dividers from the output voltage to trkp and from the tracking voltage to trkn to prevent overstress on the trkp and trkn inputs.
adp1822 rev. c | page 20 of 24 application circuits 1f 10? shdn vcc freq sync pwgd mar msel comp ss 100nf 3 irf3711 1h 2 180f 20v 4 1000f, 4v dh bst sw csl dl pgnd trkp trkn fb mdn mup 0.1f pvcc adp1822 3.01k ? input 5v 05311-019 output 1.8v, 15a 1f 80.6k ? 309pf agnd dgnd tracking signal input 2.2pf 1nf 15pf 158k ? 316k ? cmosh-3 20k ? 10k ? 10 ? figure 21. typical application circuit, 5 v input 1f 10? shdn vcc freq sync pwgd mar msel comp ss 100nf q1 irf3711 1h 2 180f 20v 4 1000f, 4v dh bst sw csl dl pgnd trkp trkn fb mdn mup 0.1f pvcc adp1822 3.01k ? input 12v 05311-020 output 1.8v, 15a 1f 80.6k ? 309pf agnd dgnd tracking signal input 2.2pf 1nf 15pf 158k? 316k ? cmosh-3 20k ? 10k ? cmoz5v6 1.2k ? cmst2222a 2 irf3711 figure 22. typical application circuit, 12 v input
adp1822 rev. c | page 21 of 24 outline dimensions compliant to jedec standards mo-137ae 24 13 12 1 pin 1 seating plane 0.010 0.004 0.012 0.008 0.025 bsc 0.069 0.053 0.010 0.006 0.050 0.016 8 0 0.065 0.049 coplanarity 0.004 0.345 0.341 0.337 0.158 0.154 0.150 0.244 0.236 0.228 figure 23. 24-lead shrink small outline package [qsop] (rq-24) dimensions shown in inches ordering guide model temperature range package description package option 1 ADP1822ARQZ-R7 ?40c to +85c 24-lead shrink small outline package [qsop] rq-24 2 adp1822-eval evaluation board 1 operating junction temper ature is C40 c to +125c. 2 z = rohs compliant part.
adp1822 rev. c | page 22 of 24 notes
adp1822 rev. c | page 23 of 24 notes
adp1822 rev. c | page 24 of 24 notes ?2006C2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05311-0-5/07(c)

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