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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD9816 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 complete 12-bit 6 msps ccd/cis signal processor functional block diagram vinr vinb offset clamp/cds avdd avss capt capb cml pgaout vref dvdd dvss drvdd drvss oeb dout 11:0 sclk sload sdata cdsclk2 adcclk clamp/cds + dac dac + dac pga pga bandgap reference mux register configuration register r g b 8 offset registers r g b gain registers digital control port 12 6 100mv 1xC6x mux pga + clamp/cds ving 12-bit adc cdsclk1 AD9816 8 features 12-bit 6 msps a/d converter no missing codes guaranteed 3-channel or 1-channel operation correlated double sampling 8-bit programmable gain 8-bit offset adjustment pga output monitor input clamp circuitry internal voltage reference 3-wire serial interface +3.3 v/+5 v digital output compatibility 44-lead mqfp package low power cmos: 420 mw typ product description the AD9816 is a complete analog signal processor for ccd and cis applications. included is all the necessary circuitry to perform three-channel conditioning and sampling for a variety of imaging applications. the signal chain consists of an input clamp, correlated double sampler (cds), offset adjust dac, programmable gain ampli- fier and a 12-bit a/d converter. the cds and input clamp may be disabled for cis applications. the internal registers are programmed using a 3-wire serial interface and provide adjustment of the gain, offset and operat- ing mode. the AD9816 operates from a +5 v supply, typically consumes 420 mw of power and is packaged in a 44-lead mqfp.
C2C rev. a AD9816Cspecifications analog specifications (t min to t max with avdd = +5.0 v, dvdd = +5.0 v, drvdd = +5.0 v, cds mode, f adcclk = 6 mhz, f cdsclk1 = 2 mhz, f cdsclk2 = 2 mhz, pga gain = 1, input range = 3 v p-p, input capacitor = 1200 pf, unless otherwise noted) parameter AD9816 AD9816-80010 units maximum conversion rate 3-channel mode with cds 6 6 msps min 1-channel mode with cds 6 6 msps min accuracy (includes entire signal path) adc resolution 12 12 bits min differential nonlinearity (dnl) 0.4 0.75 lsb typ 1.0 lsb max no missing codes 12 bits guaranteed integral nonlinearity (inl) 1.5 2.5 lsb typ 4.0 lsb max offset error 2.4 % fsr max gain error 1 4.3 % fsr max analog inputs input voltage range 2 0 0 v min 3 3 v max input limits 3 avss C 0.3 avss C 0.3 v min avdd + 0.3 avdd + 0.3 v max input capacitance 10 10 pf typ input current 10 10 na typ amplifiers pga gain range 1 1 v/v min 5.98 5.98 v/v max pga gain resolution 256 256 steps offset range C100 C100 mv min +100 +100 mv max offset resolution 256 256 steps noise and crosstalk total output noise at min pga gain 4 0.5 lsb rms typ total output noise at max pga gain 4 0.8 lsb rms typ channel-to-channel crosstalk 5 1lsb max power supply rejection (avdd = +5 v/ 0.25 v) 0.28 % fsr max voltage reference 0.75 v reference tolerance (@ +25 c) 20 mv max 1.5 v reference tolerance (@ +25 c) 34 mv max temperature range operating 0 0 c min +70 +70 c max power supplies operating voltages avdd, dvdd +4.75 +4.75 v min +5.25 +5.25 v max drvdd +3.3 +3.3 v min +5.25 +5.25 v max operating current 84 84 ma typ power consumption 420 420 mw typ 500 500 mw max notes 1 includes internal voltage reference error. 2 input voltage range is the linear region over which the input signal can be processed by the input stage of the AD9816. 3 the input limits are defined as the maximum tolerable input voltage into the AD9816. this is not intended to be the linear inpu t range of the device. signals beyond the input limits will turn on the overvoltage protection diodes. 4 the total output noise is measured with the inputs of the AD9816 grounded. 5 the channel-to-channel crosstalk is measured with one input grounded, and the other two inputs at full scale. specifications subject to change without notice.
C3C rev. a AD9816 digital specifications (t min to t max with avdd = +5.0 v, dvdd = +5.0 v, drvdd = +5.0 v, f adcclk = 6 mhz, f cdsclk1 = 2 mhz, f cdsclk2 = 2 mhz, c l = 10 pf unless otherwise noted) parameter symbol min typ max units logic inputs high level input voltage v ih 3.5 v low level input voltage v il 1.0 v high level input current i ih 10 m a low level input current i il 10 m a input capacitance c in 10 pf logic outputs high level output voltage v oh 4.5 v low level output voltage v ol 0.1 v high level output current i oh 50 m a low level output current i ol 50 m a specifications subject to change without notice. timing specifications (t min to t max with dvdd = +5.0 v, drvdd = +5.0 v) parameter symbol min typ max units clock parameters 3-channel conversion rate t cra 500 ns 1-channel conversion rate t crb 160 ns adcclk pulsewidth t adclk 80 ns cdsclk1 pulsewidth t c1 20 ns cdsclk2 pulsewidth t c2 60 2 t adclk C 30 ns cdsclk1 falling to cdsclk2 rising t c1c2 5ns adcclk falling to cdsclk2 rising t adc2 0ns cdsclk2 falling to adcclk falling t c2ad 30 ns cdsclk2 falling to cdsclk1 rising t c2c1 10 ns aperture delay for cds clocks t ad 10 ns serial interface maximum sclk frequency f sclk 10 mhz sload to sclk set-up time t ls 10 ns sclk to sload hold time t lh 10 ns sdata to sclk rising set-up time t ds 10 ns sclk rising to sdata hold time t dh 10 ns sclk falling to sdata valid t rdv 10 ns data output output delay t od 13 ns 3-state to data valid t dv 15 ns output enable high to 3-state t hz 5ns latency (pipeline delay) 3 (fixed) adcclk cycles
AD9816 C4C rev. a t ad pixel n (r, g, b) pixel (n+1) pixel (n+m) t c1 r(nC2) g(nC2) b(nC2) r(nC1) g(nC1) b(nC1) r(n) g(n) b(n) r(n+1) g(nC1) b(nC1) r(n) g(n) b(n) r(n+1) g(n+1) b(n+1) r(n+2) pixel (n+2) t ad t c2c1 t c2 t adclk t adc2 t c2ad t cra t c1c2 t adclk t od analog inputs cdsclk1 cdsclk2 adcclk output data d11:d0 pgaout_t pgaout_c figure 1. 3-channel cds mode timing t ad pixel n (r, g, b) pixel (n+m) r(nC2) g(nC2) b(nC2) r(nC1) g(nC1) b(nC1) r(n) g(n) b(n) r(n+1) g(nC1) b(nC1) r(n) g(n) b(n) r(n+1) g(n+1) b(n+1) r(n+2) pixel (n+2) pixel (n+1) t c2 t cra t adclk t adc2 t c2ad t adclk t od analog inputs cdsclk2 adcclk output data d11:d0 pgaout_t pgaout_c figure 2. 3-channel sha mode timing t ad pixel (nC1) pixel n pixel (n+1) t adclk t od pixel (n+2) pixel (nC4) pixel (nC3) pixel (nC2) pixel (nC1) pixel n pixel (n+m) pixel (n+2) pixel (n+1) t c1 t ad t c2c1 t c1c2 t c2 t adc2 t c2ad t adclk analog inputs cdsclk2 adcclk output data d11:d0 pgaout_t pgaout_c cdsclk1 t crb figure 3. 1-channel cds mode timing
AD9816 C5C rev. a analog inputs cdsclk2 output data , d11:d0 . pgaout_t pgaout_c adcclk pixel (nC1) pixel n pixel (n+1) pixel (n+2) pixel (nC4) pixel (nC3) pixel (nC2) pixel (nC1) pixel n pixel (n+m) t ad t crb t c2ad t adc2 t adclk t od pixel (n+2) pixel (n+1) t c2 t adclk figure 4. 1-channel sha mode timing optical black or dummy pixels effective pixels analog inputs cdsclk1 cdsclk2 adcclk figure 5. line clamp timing for 3-channel cds mode t od adcclk output data , d11:d0 . oeb t hz t dv figure 6. output enable timing
AD9816 C6C rev. a caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD9816 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings* with respect parameter to min max units vin, vref avss C0.3 avdd + 0.3 v pga outputs avss C0.3 avdd + 0.3 v clock inputs dvss C0.3 dvdd + 0.3 v avdd avss C0.5 +6.5 v dvdd dvss C0.5 +6.5 v drvdd drvss C0.5 +6.5 v avss dvss C0.3 +0.3 v digital outputs drvss C0.3 drvdd + 0.3 v digital inputs dvss C0.3 dvdd + 0.3 v junction temperature +150 c storage temperature C65 +150 c lead temperature (10 sec) +300 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. ordering guide temperature package package model range description option AD9816js 0 c to +70 c 44-lead mqfp (metric) plastic quad flatpack s-44 AD9816js-80010 0 c to +70 c 44-lead mqfp (metric) plastic quad flatpack s-44 AD9816-eb evaluation board warning! esd sensitive device
AD9816 C7C rev. a pin function descriptions pin pin name type description 1 avdd p +5 v analog supply. 2 avss p analog ground. 3, 4 capt ao reference decoupling. 5, 6 capb ao reference decoupling. 7 vref ao internal reference output. 8 cml ao internal bias level. 9 vinr ai analog input, red channel. 10 avss p analog ground. 11 ving ai analog input, green channel. 12 avss p analog ground. 13 vinb ai analog input, blue channel. 14 avss p analog ground. 15 avdd p +5 v analog supply. 16 offset ai clamp bias level in cds mode. offset adjustment input in sha mode. 17 cdsclk1 di cds reset level sampling clock. 18 cdsclk2 di cds data level sampling clock. 19 adcclk di a/d converter sampling clock. 20 dvss p digital ground. 21 dvdd p +5 v digital supply. 22 nc no connect. 23 sclk di clock input for serial interface. 24 sdata dio serial data input-output. 25 sload di load pulse for serial interface. 26 dvss p digital ground. 27 db0 do data output (lsb). 28C32 db1Cdb5 do data outputs. 33 drvss p digital driver ground. 34 drvdd p digital driver supply. 35C39 db6Cdb10 do data outputs. 40 db11 do data output (msb). 41 oeb di output enable, active low. 42 nc no connect. 43 pgaout_c ao pga output, negative. this pin should be left unconnected except during evaluation. 44 pgaout_t ao pga output, positive. this pin should be left unconnected except during evaluation. notes see applications information for circuit configurations. type: ai = analog input, ao = analog output, di = digital input, do = digital output, dio = digital input/output, p = power. pin configuration pin 1 identifier top view (not to scale) nc = no connect drvss db5 db4 db3 db2 db1 db0 (lsb) dvss sload sdata sclk avdd avss capt capt capb capb vref cml vinr avss ving pgaout_t pgaout_c nc oeb db11(msb) db10 db9 avss vinb avss avdd cdsclk1 cdsclk2 adcclk dvss dvdd nc offset db8 db7 db6 drvdd AD9816 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23
AD9816 C8C rev. a definitions of specifications integral nonlinearity (inl) integral nonlinearity error refers to the deviation of each indi- vidual code from a line drawn from zero scale through posi- tive full scale. the point used as zero scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. differential nonlinearity (dnl) an ideal adc exhibits code transitions which are exactly 1 lsb apart. dnl is the deviation from this ideal value. thus every code must have a finite width. no missing codes guaranteed to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating ranges. offset error the first adc code transition should occur at a level 1/2 lsb above the nominal zero scale voltage. the offset error is the deviation of the actual first code transition level from the ideal level. gain error the last code transition should occur for an analog value 1 1/2 lsb below the nominal full scale voltage. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between the first and last code transitions. total output noise an ideal adc outputs only one code value for a dc input voltage. a real converter has noise sources that will cause a spread of codes at the output for a dc input voltage. the total output noise is measured with a grounded input and is equal to the standard deviation of the histogram of output codes. channel-to-channel crosstalk in an ideal three-channel system, the signal in one channel will not influence the signal level of another channel. the channel- to-channel crosstalk specification is a measure of the change that occurs in one channel as the other two channels are varied. in the AD9816, one channel is grounded and the other two chan- nels are exercised with full-scale input signals. the change in the output codes from the first channel is measured and com- pared with the result when all three channels are grounded. the difference is the channel-to-channel crosstalk, stated in lsbs. aperture delay the aperture delay is the time delay that occurs from when a sampling edge is applied to the AD9816 until the actual sample of the input signal is held. for cdsclk1, the aperture delay represents the amount of time it takes for the clamp switch to open after cdsclk1 transitions from high to low. for cdsclk2, the aperture delay is the amount of time after the cdsclk2 falling edge that the input signal is sampled. power supply rejection power supply rejection specifies the maximum full-scale change that occurs from the initial value when the supplies are varied over the specified limits. functional description the AD9816 can be operated in several different modes: 3-channel cds mode, 3-channel sha mode, 1-channel cds mode, and 1-channel sha mode. each mode is selected by programming the configuration register through the serial interface. for more detail on cds or sha mode operation, see circuit descriptions section. 3-channel cds mode in 3-channel cds mode, the AD9816 simultaneously samples the red, green and blue input voltages from the ccd outputs. the sampling points for each correlated double sampler (cds) are controlled by cdsclk1 and cdsclk2. cdsclk1s fall- ing edge clamps the reference level of the ccd waveform at the analog inputs of the AD9816. cdsclk2s falling edge samples the data level of the ccd waveform. each cds amplifier out- puts the difference between the ccd reference and data levels. next, the output voltage of each cds amplifier is level-shifted by an offset dac. the voltages are then scaled by the three programmable gain amplifiers before being multiplexed to the common 12-bit adc. the adc sequentially samples the pga outputs on the falling edges of adcclk. timing for this mode is shown in figure 1, using a 2 master clock. although it is not required, it is recommended that the falling edge of cdsclk2 be aligned with the rising edge of adcclk. the rising edge of cdsclk2 should not occur before the previous falling edge of adcclk, as shown by t adc2 . the maximum allowable width of cdsclk2 will be dependent on the adcclk period, and equal to one adcclk period minus 30 ns. the output data latency is three clock cycles. the offset and gain values for the red, green, and blue channels are programmed using the serial interface. the order in which the channels are switched through the multiplexer is selected by programming the mux register. the rising edge of cdsclk2 always resets the multiplexer. 3-channel sha mode in 3-channel sha mode, the AD9816 simultaneously samples the red, green, and blue input voltages. the samp le-and-hold amplifiers sampling point is controlled by cdsclk2. cdsclk2s falling edge samples the input waveforms on each channel. the output voltages from the three shas are modified by the offset dacs and then scaled by the three pgas. the outputs of the pgas are then multiplexed through the 12-bit adc. the adc sequentially samples the pga outputs on the falling edges of adcclk. the input signal is sampled with respect to the voltage applied to the offset pin. with the offset pin grounded, a zero volt input corresponds to the adcs zero scale output. the input clamp is disabled in this mode. however, the offset pin may be used as a coarse offset adjust pin. a voltage applied to this pin will be subtracted from the voltages applied to the red, green and blue inputs in the first amplifier stage of the AD9816. for more information, see the circuit descriptions section. timing for this mode is shown in figure 2, using a 1 master clock. cdsclk1 should be grounded in this mode. although it is not required, it is recommended that the falling edge of cdsclk2 be aligned with the rising edge of adcclk. the rising edge of cdsclk2 should not occur before the previous falling edge of adcclk, as shown by t adc2 . the maximum allowable width of cdsclk2 will be dependent on the adcclk
AD9816 C9C rev. a period, and equal to one adcclk period minus 30 ns. the output data latency is three adcclk cycles. the offset and gain values for the red, green and blue channels are programmed using the serial interface. the order in which the channels are switched through the multiplexer is selected by programming the mux register. the rising edge of cdsclk2 always resets the multiplexer. 1-channel cds mode this mode operates in the same way as the 3-channel cds mode. the difference is that the multiplexer remains fixed in this mode, so only the channel specified in the mux register is processed. because the AD9816 is still sampling all three chan- nels, the unused inputs should be grounded through 1200 pf capacitors. timing for this mode is shown in figure 3, using a 3 master clock. although it is not required, it is recommended that the falling edge of cdsclk2 be aligned with the rising edge of adcclk. 1-channel sha mode this mode operates the same way as the 3-channel sha mode, except that the multiplexer remains stationary. only the channel specified in the mux register is processed. because the AD9816 is still sampling all three channels, the unused inputs should be grounded. the input signal is sampled with respect to the voltage applied to the offset pin. with the offset pin grounded, a zero volt input corresponds to the adcs zero scale output. the input clamp is disabled in this mode. however, the offset pin may be used as a coarse offset adjust pin. a voltage applied to this pin will be subtracted from the voltages applied to the red, green and blue inputs in the first amplifier stage of the AD9816. for more information, see the circuit descriptions section. timing for this mode is shown in figure 4, using a 1 master clock. cdsclk1 should be grounded in this mode of opera- tion. although it is not required, it is recommended that the falling edge of cdsclk2 be aligned with the rising edge of adcclk. table i. register map a2 a1 a0 register power-on default value 0 0 0 configuration register 0 0 1 1 0 1 0 0 (lsb) 0 0 1 mux register 0 0 1 0 0 0 0 1 (lsb) 0 1 0 red pga register undetermined 0 1 1 green pga register undetermined 1 0 0 blue pga register undetermined 1 0 1 red offset register undetermined 1 1 0 green offset register undetermined 1 1 1 blue offset register undetermined register overview the serial interface is used to program the eight internal regis- ters of the AD9816. the address bits a2Ca0 determine the register in the AD9816 where serial data d7Cd0 is written to or read from. the configuration register controls the operating mode of the AD9816. bits 7 (msb), 6 and 0 are test mode bits and should always be set to zero. bit 5 is set high to enable the cds mode. setting this bit low enables the sha mode. set bit 4 high to enable the 3 v input span. set bit 3 high to enable the 1.5 v span. bits 2 and 1 set the channel mode. bit 2 enables 3-chan- nel simultaneous sampling. bit 1 enables single channel mode, with the appropriate channel set in the mux register. at power-on, this register defaults to 3-channel cds mode with a 3 v input span, as shown in table i. 7 6 5 4 3 2 1 0 test mode (lsb) 1-channel mode 3-channel mode 1.5 v input span 3 v input span cds enable test mode test mode (msb) figure 7. configuration register the mux register determines the order of channels that the multiplexer will switch to in the different modes of operation. bit 7 and bit 1 are test modes and should be set to zero. bit 0 is a test mode bit and should be set high. in 3-channel mode, table ii shows how to set the order in which the channels are converted. the multiplexer is always reset on the rising edge of cdsclk2. in 1-channel mode, the multiplexer is stationary, and only converts the channel selected in table iii. at power- on, this register defaults to 3-channel rgb mode. 7 6 5 4 3 2 1 0 test mode (lsb) test mode 1-channel red 1-channel green 1-channel blue 3-channel bit 0 3-channel bit 1 test mode (msb) figure 8. mux register
AD9816 C10C rev. a table ii. 3-channel selection mux register bits 6 5 channel sequence 0 1 red, green, blue 1 0 blue, green, red table iii. 1-channel selection mux register bits 4 3 2 channel 0 0 1 red 0 1 0 green 1 0 0 blue the offset is variable from C100 mv to +100 mv, and is applied at the output of the cds, before the pga. the resolution is 8 bits, and a sign magnitude coding scheme is used. table iv shows the offset voltage that corresponds to the register value. 7 6 5 4 3 2 1 0 d0 (lsb) d1 d2 d3 d4 d5 d6 d7 (msb) figure 9. offset regist ers for red, green and blue channels table iv. offset adjustment offset register offset voltage 0111 1111 (lsb) +100 mv .. .. .. 0000 0001 +0.8 mv 0000 0000 0.0 mv 1000 0000 0.0 mv 1000 0001 C0.8 mv .. .. .. 1111 1111 C100 mv the pga is used for correcting color imbalance and for fine adjustment of the input span before the adc. gain is variable from 1 to 6 (0 db to 15.5 db) with 8-bit resolution. an all zeros word (00 . . . 0) corresponds to the minimum gain, and an all ones word (11 . . . 1) corresponds to the maximum gain. the gain of the pga increases linearly as the gain word increases, and can be calculated by the following equation: pga gain = 1 + ( gain code /51.2) where gain code varies from 0 to 255. for more information, refer to the circuit descriptions section. 7 6 5 4 3 2 1 0 d0 (lsb) d1 d2 d3 d4 d5 d6 d7 (msb) figure 10. pga registers for red, green and blue channels serial timing the 3-wire serial interface timing is shown below. to write to the AD9816, sload is first taken low. next, a total of 16 bits are sent to sdata, which get latched into the AD9816 on the rising edges of sclk. additional sclk pulses will be ignored. the first bit, r/ w , should be low to specify a write operation. the next three bits, a2Ca0, are the address bits to specify the destination register for the data word d7Cd0. after all 16 bits have been clocked, sload is taken high, which internally latches the data to the appropriate register. the read operation also starts by taking sload low. first, a one is written to r/ w , to specify a read operation. next, the three address bits a2Ca0 are written to specify the register that will be read. on the 8th sclk falling edge, sdata will begin to output the informa- tion from the desired register. after all eight data bits have been read, sload is taken back high. t dh t ds t ls t lh sdata sclk sload r/wb a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 figure 11. write operation timing t dh t ds t ls t lh sdata sclk sload r/wb a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 t rdv figure 12. read operation timing
AD9816 C11C rev. a circuit descriptions analog input configuration for cds and sha mode cds mode operation figure 13 shows the equivalent input circuit for the cds mode of operation. the ccd signal is connected to the AD9816s analog inputs through a coupling capacitor c in . the ccd reference level is clamped during the cdsclk1 pulse, when the clamp switch closes and connects the externally-generated 3 v bias to the analog input. after the clamp switch opens (cdsclk1 low), the ccd data level will be level shifted by the voltage held across c in , and the sha will sample the input signal when the cdsclk2 pulse goes low (see figures 1 and 3 for cds mode timing). in this sampling technique, the cds function is effectively performed across the input capacitor, c in . this cds method has two additional considerations. first, the ccd signal cannot be dc-coupled into the AD9816, because the input capacitor is required. second, the input clamp of the AD9816 is operating as a pixel clamp, and must be asserted on every pixel for true cds operation. if line clamp operation is desired, cdsclk1 may be used at the start of each line to set the proper dc voltage on c in . then, during the effective pixels of each line, cdsclk1 can be held low while cdsclk2 samples the data levels of each pixel. figure 5 shows the timing for line clamp operation. 11 sha buffer ving i bias c stray clamp switch 16 3v offset 1.0k v 1.5k v +5v 0.1 m f 1 m f 17 18 AD9816 c in r s ccd signal cdsclk1 cdsclk2 figure 13. cds mode input circuit (all channels identical) input signal range for cds mode an input dc bias level of 3 v allows a maximum 3 v p-p signal swing from the ccd. figure 14 shows a typical full-scale input waveform to the AD9816, illustrating the allowable input range. with a reference level of 3 v, the AD9816 can tolerate up to 2 v of reset feedthrough above the reference level. the inputs of the AD9816 can also handle an input signal down to avss C 0.3 v without any saturation recovery issues. although an input level below zero volts will be clipped to the adcs full- scale output code, the input stage can respond quickly enough to accurately process the next pixel that falls into the linear input range. any signals below avss C 0.3 v will turn on the input protection diodes, and recovery from the saturated condi- tion may take up to several milliseconds. input capacitor c in the recommended value for c in is 1200 pf. this value has been selected to provide the best overall performance when considering three factors: input attenuation, linearity and signal droop. the value of c in may be optimized for a particular ap- plication if these three factors are understood. 1. attenuation (gain error) the input voltage will be attenuated by the interaction of c in and c stray . c stray is less than 10 pf, which results in an attenuation of about 0.8% when c in is 1200 pf. the gain error will increase accordingly as the value of c in is decreased. 2. linearity the input capacitance of the AD9816 is shown in figure 8 as c stray . a small portion of this capacitance is junction capacitance, which will vary nonlinearly as the input voltage to the AD9816 changes. when the input voltage is attenu- ated by the combination of c in and c stray , there will be a small nonlinear component caused by the input junction capacitance. the magnitude of the junction capacitance will cause a 1 lsb (0.024%) nonlinearity over the 3 v input range when a 1200 pf c in is used. this nonlinearity will increase if a smaller c in is used. 3. droop the input bias current of the AD9816 is typically 10 na and is constant regardless of the AD9816s input voltage. the droop of the voltage across c in can be calculated with the following equation: dv = i bias c in ( t ) where t is the time between clamp intervals. between the adjacent pixels of a scanned line, this droop will be insignifi- cant. between scanned lines, a 1 ms delay will produce a droop of about 10 mv, which can be easily clamped on the first pixel of the next line. if the value of c in is reduced, the droop will increase accordingly. 5v max reset feedthrough 3v reference level (set by input clamp) 0v max data level C0.3v max saturated data level max peak-peak signal figure 14. ccd input signal clamped to 3 v
AD9816 C12C rev. a line clamp if a line clamp technique is implemented (see figure 5 for timing), the value of c in should be increased to more than 1200 pf. the main requirement for line clamp is to keep the signal droop below 1 lsb across a scanned line. for example, if a ccd with 5400 effective pixels is clocked at 2 mhz, then t = 2.7 ms. one lsb at 12 bits with a 3 v full scale is 732 m v. rearranging the above droop equation: c min = i bias dv t in this case, c min = 37 nf, and a convenient standard value of 0.047 m f will be adequate. sha mode operation when the AD9816 is configured for sha mode operation, the offset pin functions as an offset adjustment input. figure 15 shows a simplified diagram of the AD9816s inputs when sha mode is selected. a positive dc voltage may be applied to offset which will be subtracted from all three input channels in the input stage of the AD9816. the maximum input voltage to the analog input pins or the offset pin in sha mode is 3 v. the offset feature is provided to allow coarse offset adjust- ment of the input signal. if the signal is sampled with respect to ground, any positive offset on the input signal will subtract from the dynamic range of the adc. for example, an input signal that spans from 1.5 v to 2.5 v cannot utilize all of the available dynamic range, using either the 1.5 v or 3 v span. however, by applying a dc value of 1.5 v to the offset pin, the i nput signal will be level-shifted down to 0 v to 1 v. this would allow the use of the 3 v span and a pga gain of three to use the entire adc dynamic range. if no dc offset adjustment is desired, the offset pin should be grounded. the input signal will be sampled with respect to ground. sha buffer sha buffer sha buffer vinr ving vinb offset AD9816 cdsclk1 cdsclk2 12k v figure 15. sha mode input circuit programmable gain amplifiers the AD9816 has three programmable amplifiers, one for each channel. the gain is variable from 1 v/v (0 db) to 5.98 v/v (15.5 db) in 256 increments. figure 16 shows the pga gain transfer function. the gain of the pga can be calculated ac- cording to the equation: pga gain = 1 + gain code 51.2 ? ? ? ? gain register code C decimal pga gain C v/v 6 5 1 051 255 102 153 204 4 3 2 figure 16. pga gain transfer function the analog outputs of the three pgas are multiplexed to the input of the 12-bit adc. the differential output of the mux is also buffered and externally available at pins 43 and 44 (pgaout_c and pgaout_t, respectively). the timing diagrams, fig- ures 1 through 4, show the timing relationships between the analog inputs, cdsclk2, adcclk, and pgaout_t and pgaout_c. the cdsclk2 pulse resets the outputs of all three pgas to an internal bias level. the first rising edge of adcclk after the rising edge of cdsclk2 will switch the mux to the red pga output. the second adcclk rising edge switches the mux to the green pga output, and the third rising edge switches the mux to the blue pga output. pga outputs the pgaout_t and pgaout_c signals represent the differ- ential input to the adc, and are complementary. both signals will reset to 3.5 v while cdsclk2 is high. the voltage swing of each output is equal to one-half of the adcs full-scale volt- age, centered at 3.5 v. table v shows the relationship between the analog input voltage, the pga output voltage and the adc input voltage. figure 18 shows the pga output voltages for three different color pixel amplitudes. in this example, the red pixel has the largest amplitude, and the blue pixel has the smallest amplitude. because the pgaout_t and pgaout_c outputs are inter- nally buffered by source followers, they are not an exact r epre- sentation of the differential adc input signal. pgaout_t and pgaout_c should only be used during evaluation; perfor- mance of the AD9816 is only guaranteed with these two pins unconnected.
AD9816 C13C rev. a analog-to-digital converter the AD9816 uses a high speed 12-bit adc core. this cmos converter is designed to run at 6 msps with good linearity and noise performance. figure 19 shows the inl and dnl perfor- mance of a typical AD9816 device, running at 6 mhz in 3-channel cds mode using the timing shown in figure 1. the following timing parameters were used: t cra = 500 ns, t adclk = 83 ns, t c1 = 20 ns, t c1c2 = 170 ns, t c1 = 80 ns, t adc2 = 3 ns, t c2ad = 83 ns, and t c2c1 = 230 ns. the digital outputs of the AD9816 follow a straight binary coding scheme. table vi shows the digital output coding for the 3 v input span. 0.2 C1.6 0 4095 inl 0.0 C0.2 C0.4 C0.6 C0.8 C1.2 C1.4 1200 400 1600 800 1.0 0.5 C1.0 1.5 dnl 2000 2400 2800 3200 3600 0.0 C0.5 0 4095 1200 400 1600 800 2000 2400 2800 3200 3600 max inl 0.18 min inl C1.46 max dnl 0.31 min dnl C0.33 figure 19. typical linearity performance table vi. digital output format input voltage 1 digital outputs 3.0 C 1 lsb 1111 1111 1111 3.0 C 2 lsb 1111 1111 1110 0.0 + 1 lsb 0000 0000 0001 0.0 0000 0000 0000 note 1 analog input voltage in cds mode is the difference between the ccds reference and data levels. 3:1 diff mux red green blue pga pga pga select mux control 2 adcclk cdsclk2 12-bit adc pgaout_t pgaout_c figure 17. pga/mux circuit configuration analog inputs cdsclk2 adcclk pgaout_t pgaout_c pixel n blue green red reset green(nC1) blue(nC1) red(n) green(n) blue(n) reset 4.25v 3.5v 2.75v figure 18. pga output voltages (adc input range = 3 v) table v. voltage swing of pga outputs analog differential input adc voltage 1 pgaout_t pgaout_c input 0.00 2 2.75 4.25 1.5 1.50 2 3.50 3.50 0.0 3.00 2 4.25 2.75 +1.5 0.00 3 3.125 3.875 0.75 0.75 3 3.50 3.50 0.0 1.50 3 3.875 3.125 +0.75 notes 1 analog input voltage in cds mode is the difference between the ccds refer- ence and data levels. 2 3.0 v input range. 3 1.5 v input range.
AD9816 C14C rev. a applications information cds mode circuit the recommended circuit configuration for cds mode opera- tion is shown in figure 20. the input coupling capacitor value of 1200 pf is recommended, but this value may be adjusted to suit a particular application (see circuit descriptions). a single ground plane is recommended for the AD9816. a separate power supply may be used for drvdd, the digital dri ver supply, but this avdd avss capt capt capb capb vref cml vinr avss ving avss vinb avss avdd offset cdsclk1 cdsclk2 adcclk dvss dvdd nc drvss db5 db4 db3 db2 db1 db0 (lsb) dvss sload sdata sclk pgaout_t pgaout_c nc oeb db11 (msb) db10 db9 db8 db7 db6 drvdd AD9816 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 oeb db11(msb) db10 db9 db8 db7 db6 0.01 m f 0.1 m f v dd db5 db4 db3 db2 db1 db0 (lsb) sload sdata sclk 0.01 m f 0.1 m f v dd 1200pf 1200pf 1200pf red_in green_in blue_in 1.0 m f + 0.1 m f 10 m f + 10 m f 0.1 m f 0.1 m f 0.1 m f 0.01 m f 0.1 m f v dd v dd 0.1 m f 0.01 m f adcclk cdsclk2 cdsclk1 v dd 1k v 0.1 m f 1.0 m f 1.5k v nc = no connect figure 20. recommended circuit for cds mode supply pin should still be decoupled to the same ground plane as the rest of the AD9816. the loading of the digital outputs should be minimized, either by using short traces to the digital asic, or by using external digital buffers. all 0.01 m f and 0.1 m f decoupling capacitors should be located as close as pos- sible to the AD9816 pins. also, the 1200 pf input capacitors should be located close the AD9816s analog input pins.
AD9816 C15C rev. a avdd avss capt capt capb capb vref cml vinr avss ving avss vinb avss avdd offset cdsclk1 cdsclk2 adcclk dvss dvdd nc drvss db5 db4 db3 db2 db1 db0 (lsb) dvss sload sdata sclk pgaout_t pgaout_c nc oeb db11 (msb) db10 db9 db8 db7 db6 drvdd AD9816 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 oeb db11(msb) db10 db9 db8 db7 db6 0.01 m f 0.1 m f v dd db5 db4 db3 db2 db1 db0 (lsb) sload sdata sclk 0.01 m f 0.1 m f v dd red_in green_in blue_in 1.0 m f + 0.1 m f 10 m f + 10 m f 0.1 m f 0.1 m f 0.1 m f 0.01 m f 0.1 m f v dd v dd 0.1 m f 0.01 m f adcclk cdsclk2 cdsclk1 0.1 m f 1.0 m f v dd r1 r2 optional dc offset ground-referenced sampling nc = no connect figure 21. recommended circuit for sha mode sha mode circuit the circuit configuration for sha mode is identical to cds mode except for two differences: the analog inputs should be dc-coupled, and the offset pin is tied to ground or a desired dc voltage (see circuit descriptions). in cis applications, the reference black level of the cis can be connected to the off- set pin, to remove the dc offset. removing the coarse offset of the cis signal will allow the dynamic range of the AD9816 to be maximized.
AD9816 C16C rev. a outline dimensions dimensions shown in inches and (mm). c3324aC0C10/98 printed in u.s.a. 44-lead mqfp (s-44) 12 44 1 11 22 23 34 33 0.018 (0.45) 0.012 (0.30) 0.031 (0.80) bsc 0.333 (8.45) 0.327 (8.3) 0.529 (13.45) 0.510 (12.95) 0.398 (10.1) 0.390(9.90) top view (pins down) 0.083 (2.1) 0.077 (1.95) 0.009 (0.23) 0.005 (0.13) 0.01 (0.25) min seating plane 0.096 (2.45) max 0.041 (1.03) 0.029 (0.73)

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