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128k x 36 synchronous flow-through burst sram cy7c1345a/gvt71128e36 cypress semiconductor corporation ? 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-05123 rev. *a revised november 13, 2002 345a features ? fast access times: 7.5 and 8 ns fast clock speed: 117 and 100 mhz provide high-performance 2-1-1-1 access rate fast oe access times: 4.0 ns 3.3v ?5% and +10% power supply 2.5v or 3.3v i/o supply 5v tolerant inputs except i/os clamp diodes to v ssq at all inputs and outputs common data inputs and data outputs byte write enable and global write control three chip enables for depth expansion and address pipeline address, data, and control registers internally self-timed write cycle burst control pins (interleaved or linear burst se- quence) automatic power-down for portable applications low profile 119-lead, 14-mm x 22-mm bga (ball grid array) and 100-pin tqfp packages functional description the cypress synchronous burst sram family employs high- speed, low-power cmos designs using advanced triple-layer polysilicon, double-layer metal technology. each memory cell consists of four transistors and two high-valued resistors. the cy7c1345a/gvt71128e36 sram integrates 131,072x36 sram cells with advanced synchronous periph- eral circuitry and a 2-bit counter for internal burst operation. all synchronous inputs are gated by registers controlled by a pos- itive-edge-triggered clock input (clk). the synchronous in- puts include all addresses, all data inputs, address-pipelining chip enable (ce ), depth-expansion chip enables (ce2 and ce2), burst control inputs (adsc , adsp , and adv ), write enables (wel , weh , and bwe ), and global write (gw ). asynchronous inputs include the output enable (oe ) and burst mode control (mode), and sleep mode control (zz). the data outputs (dq), enabled by oe , are also asynchro- nous. addresses and chip enables are registered with either ad- dress status processor (adsp ) or address status controller (adsc ) input pins. subsequent burst addresses can be inter- nally generated as controlled by the burst advance pin (adv ). address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycle. write cycles can be one to four bytes wide as controlled by the write control inputs. indi- vidual byte write allows individual byte to be written. bw1 con- trols dq1 ? dq8 and dqp1. bw2 controls dq9 ? dq16 and dqp2. bw3 controls dq17 ? dq24 and dqp3. bw4 controls dq25 ? dq32 and dqp4. bw1 , bw2 , bw3 , and bw4 can be active only with bwe being low. gw being low causes all bytes to be written. the cy7c1345a/gvt71128e36 operates from a +3.3v pow- er supply and all outputs operate on a +2.5v supply. all inputs and outputs are jedec standard jesd8-5 compatible. the device is ideally suited for 486, pentium ? , 680x0, and power- pc ? systems and for systems that benefit from a wide syn- chronous data bus. selection guide 7c1345a-117 71128e36-7 7c1345a-100 71128e36-8 7c1345a-100 71128e36-9 7c1345a-100 71128e36-10 maximum access time (ns) 7.5 8 8 8 maximum operating current (ma) 370 320 320 320 maximum cmos standby current (ma) 10 10 10 10
cy7c1345a/gvt71128e36 document #: 38-05123 rev. *a page 2 of 16 note: 1. the functional block diagram illustrates simplified device operation. see truth table, pin descriptions, and timing diagrams for detailed information. 128k x 36 (cy7c1345a/gvt71128e36) functional block diagram [1] dq dq bw3# bw4# ce# ce2 ce2# byte 3 write byte 4 write enable oe# byte 3 write adsp# adsc# address register binary counter & logic clr a16-a2 a1-a0 adv# mode 128k x 9 x 4 sram array output buffers input register byte 4 write dq1-dq32, dqp1, dqp2 dqp3, dqp4 dq dq dq bw1# bwe# bw2# gw# byte 1 write byte 2 write clk byte 2 write byte 1 write power down logic zz
cy7c1345a/gvt71128e36 document #: 38-05123 rev. *a page 3 of 16 pin configurations 100-pin tqfp top view a5 a4 a3 a2 a1 a0 nc nc v ss v cc nc nc a10 a11 a12 a13 a14 a15 a16 dqp2 dq16 dq15 v ccq v ssq dq14 dq13 dq12 dq11 v ssq v ccq dq10 dq9 v ss nc v cc zz dq8 dq7 v ccq v ssq dq6 dq5 dq4 dq3 v ssq v ccq dq2 dq1 dqp1 dqp3 dq17 dq18 v ccq v ssq dq19 dq20 dq21 dq22 v ssq v ccq dq23 dq24 v cc nc v ss dq25 dq26 v ccq v ssq dq27 dq28 dq29 dq30 v ssq v ccq dq31 dq32 dqp4 a6 a7 ce ce 2 bw4 bw3 bw2 bw1 ce 2 v cc v ss clk gw bwe oe adsc adsp adv a8 a9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1345a/gvt71128e36 (128k x 36) nc
cy7c1345a/gvt71128e36 document #: 38-05123 rev. *a page 4 of 16 pin configurations (continued) 119-ball bump bga 1234567 a v ccq a6 a4 adsp a8 a16 v ccq b nc ce2 a3 adsc a9 ce 2 nc c nc a7 a2 v cc a12 a15 nc d dq17 dqp3 v ss nc v ss dqp2 dq16 e dq18 dq19 v ss ce v ss dq14 dq15 f v ccq dq20 v ss oe v ss dq13 v ccq g dq21 dq22 bw3 adv bw2 dq12 dq11 h dq23 dq24 v ss gw v ss dq10 dq9 j v ccq v cc nc v cc nc v cc v ccq k dq25 dq27 v ss clk v ss dq7 dq8 l dq26 dq28 bw4 nc bw1 dq5 dq6 m v ccq dq29 v ss bwe v ss dq4 v ccq n dq30 dq31 v ss a1 v ss dq3 dq2 p dq32 dqp4 v ss a0 v ss dqp1 dq1 r nc a5 mode v cc nc a13 nc t nc nc a10 a11 a14 nc zz u v ccq nc nc nc nc nc v ccq 128kx36 ? cy7c1345a/gvt71128e36 top view pin descriptions bga pins qfp pins pin name type description 4p, 4n, 2a, 3a, 5a, 6a, 3b, 5b, 2c, 3c, 5c, 6c, 2r, 6r, 3t, 4t, 5t 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49,50 a0 ? a16 input- synchronous addresses: these inputs are registered and must meet the set-up and hold times around the rising edge of clk. the burst counter generates internal addresses associated with a0 and a1, during burst cycle and wait cycle. 5l, 5g, 3g, 3l 93,94,95,96 bw1 , bw2 , bw3 , bw4 input- synchronous byte write: a byte write is low for a write cycle and high for a read cycle. bw1 controls dq1 ? dq8 and dqp1. bw2 controls dq9 ? dq16 and dqp2. bw3 controls dq17 ? dq24 and dqp3. bw4 controls dq25 ? dq32 and dqp4. data i/o are high imped- ance if either of these inputs are low, conditioned by bwe being low. 4m 87 bwe input- synchronous write enable: this active low input gates byte write operations and must meet the set-up and hold times around the rising edge of clk. 4h 88 gw input- synchronous global write: this active low input allows a full 36-bit write to occur independent of the bwe and bwn lines and must meet the set-up and hold times around the rising edge of clk. 4k 89 clk input- synchronous clock: this signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge. all synchronous inputs must meet set-up and hold times around the clock ? s rising edge.
cy7c1345a/gvt71128e36 document #: 38-05123 rev. *a page 5 of 16 4e 98 ce input- synchronous chip enable: this active low input is used to enable the device and to gate adsp . 6b 92 ce2 input- synchronous chip enable: this active low input is used to enable the device. 2b 97 ce2 input- synchronous chip enable: this active high input is used to enable the device. 4f 86 oe input output enable: this active low asynchronous input enables the data output drivers. 4g 83 adv input- synchronous address advance: this active low input is used to control the internal burst counter. a high on this pin generates wait cycle (no address advance). 4a 84 adsp input- synchronous address status processor: this active low input, along with ce being low, causes a new external address to be registered and a read cycle is initiated using the new address. 4b 85 adsc input- synchronous address status controller: this active low input causes device to be deselected or selected along with new external address to be registered. a read or write cycle is initiated depending upon write control inputs. 3r 31 mode input- static mode: this input selects the burst sequence. a low on this pin selects linear burst. a nc or high on this pin selects interleaved burst. 7t 64 zz input-asyn- chronous snooze: this active high input puts the device in low power con- sumption standby mode. for normal operation, this input has to be either low or nc (no connect). 7p, 7n, 6n, 6m, 6l, 7l, 6k, 7k, 7h, 6h, 7g, 6g, 6f, 6e, 7e, 7d, 1d, 1e, 2e, 2f, 1g, 2g, 1h, 2h, 1k, 1l, 2k, 2l, 2m, 1n, 2n, 1p 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72-75, 78, 79, 2, 3, 6-9, 12, 13, 18, 19, 22-25, 28, 29 dq1 ? dq32 input/ output data inputs/outputs: first byte is dq1 ? dq8. second byte is dq9 ? dq16. third byte is dq17 ? dq24. fourth byte is dq25 ? dq32. input data must meet set-up and hold times around the rising edge of clk. 6p, 6d, 2d, 2p 51, 80, 1, 30 dqp1 ? dqp4 input/ output parity inputs/outputs: dqp1 is parity bit for dq1 ? dq8 and dqp2 is parity bit for dq9 ? dq16. dqp3 is parity bit for dq17 ? dq24 and dqp4 is parity bit for dq25 ? dq32. 4c, 2j, 4j, 6j, 4r 15, 41,65, 91 v cc supply core power supply: +3.3v ? 5% and +10% 3d, 5d, 3e, 5e, 3f, 5f, 5g, 3h, 5h, 3k, 5k, 3l, 3m, 5m, 3n, 5n, 3p, 5p 17, 40, 67, 90 v ss ground ground: gnd 1a, 7a, 1f, 7f, 1j, 7j, 1m, 7m, 1u, 7u 4, 11, 20, 27, 54, 61, 70, 77 v ccq i/o supply output buffer supply: +2.5v (from 2.375v to v cc ) 5, 10, 21, 26, 55, 60, 71, 76 v ssq i/o ground output buffer ground: gnd 1b, 7b, 1c, 7c, 4d, 3j, 5j, 4l, 1r, 5r, 7r, 1t, 2t, 6t, 2u, 3u, 4u, 5u, 6u 14, 16, 38, 39, 42, 43, 66 nc - no connect: these signals are not internally connected. pin descriptions (continued) bga pins qfp pins pin name type description
cy7c1345a/gvt71128e36 document #: 38-05123 rev. *a page 6 of 16 burst address table (mode = nc/v cc ) first address (external) second address (internal) third address (internal) fourth address (internal) a...a00 a...a01 a...a10 a...a11 a...a01 a...a00 a...a11 a...a10 a...a10 a...a11 a...a00 a...a01 a...a11 a...a10 a...a01 a...a00 burst address table (mode = gnd) first address (external) second address (internal) third address (internal) fourth address (internal) a...a00 a...a01 a...a10 a...a11 a...a01 a...a10 a...a11 a...a00 a...a10 a...a11 a...a00 a...a01 a...a11 a...a00 a...a01 a...a10 truth table [2, 3, 4, 5, 6, 7, 8] operation address used ce ce2 ce2 adsp adsc adv write oe clk dq deselected cycle, power down none h x x x l x x x l-h high-z deselected cycle, power down none l x l l x x x x l-h high-z deselected cycle, power down none l h x l x x x x l-h high-z deselected cycle, power down none l x l h l x x x l-h high-z deselected cycle, power down none l h x h l x x x l-h high-z read cycle, begin burst external l l h l x x x l l-h q read cycle, begin burst external l l h l x x x h l-h high-z write cycle, begin burst external l l h h l x l x l-h d read cycle, begin burst external l l h h l x h l l-h q read cycle, begin burst external l l h h l x h h l-h high-z read cycle, continue burst next x x x h h l h l l-h q read cycle, continue burst next x x x h h l h h l-h high-z read cycle, continue burst next h x x x h l h l l-h q read cycle, continue burst next h x x x h l h h l-h high-z write cycle, continue burst next x x x h h l l x l-h d write cycle, continue burst next h x x x h l l x l-h d read cycle, suspend burst current x x x h h h h l l-h q read cycle, suspend burst current x x x h h h h h l-h high-z read cycle, suspend burst current h x x x h h h l l-h q read cycle, suspend burst current h x x x h h h h l-h high-z write cycle, suspend burst current x x x h h h l x l-h d write cycle, suspend burst current h x x x h h l x l-h d notes: 2. x means ? don ? t care. ? h means logic high. l means logic low. write = l means [bwe + bw1 *bw2 *bw3 *bw3 ]*gw equals low. write = h means [bwe + bw1 *bw2 *bw3 *bw3 ]*gw equals high. 3. bw1 enables write to dq1 ? dq8 and dqp1. bw2 enables write to dq9 ? dq16 and dqp2. bw3 enables write to dq17 ? dq24 and dqp3. bw4 enables write to dq25 ? dq32 and dqp4. 4. all inputs except oe must meet set-up and hold times around the rising edge (low to high) of clk. 5. suspending burst generates wait cycle. 6. for a write operation following a read operation, oe must be high before the input data required set-up time plus high-z time for oe and staying high throughout the input data hold time. 7. this device contains circuitry that will ensure the outputs will be in high-z during power-up. 8. adsp low along with chip being selected always initiates a read cycle at the l-h edge of clk. a write cycle can be performed by set ting write low for the clk l-h edge of the subsequent wait cycle. refer to write timing diagram for clarification.
cy7c1345a/gvt71128e36 document #: 38-05123 rev. *a page 7 of 16 maximum ratings (above which the useful life may be impaired. for user guide- lines only, not tested.) voltage on v cc supply relative to v ss ......... ? 0.5v to +4.6v v in .......................................................... ? 0.5v to +v cc +0.5v storage temperature (plastic)..................... ? 55 c to +125 c junction temperature ............................................... +125 c power dissipation.......................................................... 1.6w short circuit output current ....................................... 20 ma . partial truth table for read/write function gw bwe bw1 bw2 bw3 bw4 read hhxxxx read hlhhhh write one byte h l l h h h write all bytes hlllll write all bytes lxxxxx operating range range ambient temperature v cc [9,10] com ? l 0 c to + 70 c 3.3v ? 5%/+10% electrical characteristics over the operating range [11] parameter description test conditions min. max. unit v ihd input high (logic 1) voltage [12, 13] data inputs (dqxx) 1.7 v cc +0.3 v v ih all other 1.7 4.6 v v il input low (logic 0) voltage [12, 13] ? 0.3 0.7 v il i input leakage current [14] 0v < v in < v cc ? 2 2 a il o output leakage current output(s) disabled, 0v < v out < v cc ? 2 2 a v oh output high voltage [12, 15] i oh = ? 2.0 ma 1.7 v v ol output low voltage [12, 15] i ol = 2.0 ma 0.7 v v cc supply voltage [12] 3.135 3.6 v v ccq i/o supply voltage 2.375 v cc v parameter description conditions typ. -7 117 mhz -8 100 mhz -9 90 mhz -10 50 mhz unit i cc power supply current: operating [16, 17, 18] device selected; all inputs < v il or > v ih ; cycle time > t kc min.; v cc = max.; outputs open 150 370 320 290 200 ma i sb2 cmos standby [17, 18] device deselected; v cc = max.; all inputs < v ss + 0.2 or > v cc ? 0.2; all inputs static; clk frequency = 0 510 10 10 10ma i sb3 ttl standby [17, 18] device deselected; all inputs < v il or > v ih ; all inputs static; v cc = max.; clk frequency = 0 10 20 20 20 20 ma i sb4 clock running [17, 18] device deselected; all inputs < v il or > v ih ; v cc = max.; clk cycle time > t kc min. 40 80 70 60 40 ma notes: 9. please refer to waveform (c) 10. power supply ramp-up should be monotonic. 11. values in table are associated with the operating frequencies listed. 12. all voltages referenced to v ss (gnd). 13. overshoot: v ih < +6.0v for t < t kc /2. undershoot: v il < ? 2.0v for t < t kc /2. 14. mode pin has an internal pull-up and zz pin has an internal pull-down. these two pins exhibit an input leakage current of 3 0 a. 15. ac i/o curves are available upon request. 16. i cc is given with no output current. i cc increases with greater output loading and faster cycle times. 17. ? device deselected ? means the device is in power-down mode as defined in the truth table. ? device selected ? means the device is active. 18. typical values are measured at 3.3v, 25 c and 20-ns cycle time.
cy7c1345a/gvt71128e36 document #: 38-05123 rev. *a page 8 of 16 thermal consideration parameter description conditions tqfp typ. unit ja thermal resistance - junction to ambient still air, soldered on 4.25 x 1.125 inch 4-layer pcb 25 c/w jc thermal resistance - junction to case 9 c/w capacitance parameter description test conditions typ. max. unit c i input capacitance [19] t a = 25 c, f = 1 mhz, v cc = 3.3v 4 5 pf c o input/output capacitance (dq) [19] 7 8 pf typical output buffer characteristics output high voltage pull-up current output low voltage pull-down current v oh (v) i oh ( ma ) min. i oh (ma) max. v ol (v) i ol (ma) min. i l ( ma ) max. ? 0.5 ? 38 ? 105 ? 0.5 0 0 0 ? 38 ? 105 0 0 0 0.8 ? 38 ? 105 0.4 10 20 1.25 ? 26 ? 83 0.8 20 40 1.5 ? 20 ? 70 1.25 31 63 2.3 0 ? 30 1.6 40 80 2.7 0 ? 10 2.8 40 80 2.9 0 0 3.2 40 80 3.4 0 0 3.4 40 80 ac test loads and waveforms note: 19. this parameter is sampled. 20. overshoot: vih(ac) cy7c1345a/gvt71128e36 document #: 38-05123 rev. *a page 9 of 16 switching characteristics over the operating range [21] description -7 117 mhz -8 100 mhz -9 90 mhz -10 50 mhz parameter min. max. min. max. min. max. min. max. unit clock t kc clock cycle time 8.5 10 11 20 ns t kh clock high time 3 4 4.5 4.5 ns t kl clock low time 3 4 4.5 4.5 ns output times t kq clock to output valid 7.5 8 8.5 10 ns t kqx clock to output invalid 2 2 2 2 ns t kqlz clock to output in low-z [19, 22, 23] 0 0 0 0 ns t kqhz clock to output in high-z [19, 22, 23] 2 3.5 2 3.5 2 3.5 2 3.5 ns t oeq oe to output valid [24] 4.0 4.0 4.0 4.0 ns t oelz oe to output in low-z [19, 22, 23] 0 0 0 0 ns t oehz oe to output in high-z [19, 22, 23] 3.5 3.5 3.5 3.5 ns set-up times t s address, controls and data in [25] 1.5 2.0 2.0 2.0 ns hold times t h address, controls and data in [25] 0.5 0.5 0.5 0.5 ns notes: 21. test conditions as specified with the output loading as shown in ac test loads unless otherwise noted. values in table are a ssociated with the operating frequencies listed. 22. measured at 200 mv from steady state. 23. at any given temperature and voltage condition, t kqhz is less than t kqlz and t oehz is less than t oelz . 24. oe is a ? don ? t care ? when a byte write enable is sampled low. 25. this is a synchronous device. all synchronous inputs must meet specified set-up and hold time, except for ? don ? t care ? as defined in the truth table.
cy7c1345a/gvt71128e36 document #: 38-05123 rev. *a page 10 of 16 timing diagrams read timing [26] note: 26. ce active in this timing diagram means that all chip enables ce , ce2 , and ce2 are active. clk adsp# adsc# address bw1#, bw2#, bw3#, bw4#, bwe#, gw# ce# (see note) adv# oe# dq a1 a2 q(a1) q(a2) q(a2+1) q(a2+2) q(a2+3) q(a2) q(a2+1) q(a2+2) t kq t kqlz t oelz t kq t s t s t h t h t s t h t kh t kl kc t oeq single read burst read
cy7c1345a/gvt71128e36 document #: 38-05123 rev. *a page 11 of 16 write timing [26] timing diagrams (continued) clk adsp# adsc# address bw1#, bw2#, bw3#, bw4#, bwe# ce# (see note) adv# oe# dq a1 a2 d(a2) d(a2+2) d(a2+3) d(a3) d(a3+1) d(a3+2) t s t s t h t h t s t h gw# a3 d(a1) d(a2+2) t kqx t oehz q d(a2+2) single write burst write burst write
cy7c1345a/gvt71128e36 document #: 38-05123 rev. *a page 12 of 16 read/write timing [26] timing diagrams (continued) clk adsp# adsc# address bw1#, bw2#, bw3#, bw4#, bwe#, gw# ce# (see note) adv# oe# dq a1 a2 a3 q(a1) q(a2) t s t h t s t h a4 d(a3) q(a4) q(a4+1) q(a4+2) q(a4+3) d(a5) d(a5+1) single write burst read burst write single reads a5
cy7c1345a/gvt71128e36 document #: 38-05123 rev. *a page 13 of 16 ordering information speed (mhz) ordering code package name package type operating range 117 cy7c1345a-117ac a101 100-lead thin quad flat pack commercial gvt71128e36t-7 cy7c1345a-117bgc bg119 119-lead fbga (14 x 22 x 2.4 mm) GVT71128E36B-7 100 cy7c1345a-100ac a101 100-lead thin quad flat pack commercial gvt71128e36t-8 cy7c1345a-100bgc bg119 119-lead fbga (14 x 22 x 2.4 mm) gvt71128e36b-8 100 cy7c1345a-100ac a101 100-lead thin quad flat pack commercial gvt71128e36t-9 cy7c1345a-100bgc bg119 119-lead fbga (14 x 22 x 2.4 mm) gvt71128e36b-9 100 cy7c1345a-100ac a101 100-lead thin quad flat pack commercial gvt71128e36t-10 cy7c1345a-100bgc bg119 119-lead fbga (14 x 22 x 2.4 mm) gvt71128e36b-10
cy7c1345a/gvt71128e36 document #: 38-05123 rev. *a page 14 of 16 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 51-85050-a
cy7c1345a/gvt71128e36 document #: 38-05123 rev. *a page 15 of 16 pentium is a registered trademark of intel corporation. powerpc is a trademark of ibm corporation. all product and company names mentioned in this document may be the trademarks of their respective holders. package diagrams (continued) 51-85115-*b 119-lead pbga (14 x 22 x 2.4 mm) bg119
cy7c1345a/gvt71128e36 document #: 38-05123 rev. *a page 16 of 16 document history page document title: cy7c1345a/gvt71128e36 128k x 36 synchronous flow-through burst sram document number: 38-05123 rev. ecn no. issue date orig. of change description of change ** 108314 09/25/01 bri new cypress spec ? converted from galvantech format *a 121069 11/13 /02 dsg updated package drawing 51-85115 (bg119) to rev. *b *b 123136 01/19/03 rbi added power up requirements to operating conditions information.

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