View 88AP270MA2-BGO2C520_3858204.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

marvell. moving forward faster doc. no. mv-s104690-00 , rev. d april 2009 released cover marvell ? pxa270 processor electrical, mechanical, thermal specification
document conventions note: provides related information or information of special importance. caution: indicates potential damage to hardware or software, or loss of data. warning: indicates a risk of personal injury. document status draft for internal use. this document has not passed a complete technical review cycle and ecn signoff process. preliminary tapeout (advance) this document contains design specifications for a product in its initial stage of design and development. a revision of this document or supplementary information may be published at a later date. marvell may make changes to these specifications at any time without notice. contact marvell field application engineers for more information. preliminary information this document contains preliminary specifications. a revision of this document or supplementary information may be published at a later date. marvell may make changes to these specifications at any time without notice. . contact marvell field application engineers for more information. complete information this document contains specifications for a product in its final qualification stages. marvell may make changes to these specifications at any time without notice. contact marvell field application engineers for more information. doc status: technical publication: 0.xx x . y z milestone indicator: draft = 0.xx advance = 1.xx preliminary = 2.xx various revisions indicator work in progress indicator zero means document is released. for more information, visit our website at: www.marvell.com disclaimer no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including phot ocopying and recording, for any purpose, without the express written permission of marvell. marvell retain s the right to make changes to this document at any time, with out notice. marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the impli ed warranties of merchantability or fitness for any particular purpose. further, marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document. marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situati on if any such products failed. do not use marvell products in these types of equipment or applications. with respect to the products described herein, the user or reci pient, in the absence of appropriate u.s. government authorizati on, agrees: 1) not to re-export or release any such information consisting of technology, software or source code controlled for national s ecurity reasons by the u.s. export control regulations ("ear"), to a national of ear country groups d:1 or e:2; 2) not to export the direct product of such technology or such software, to ear country groups d:1 or e:2, if such technology o r software and direct products thereof are controlled for national security reasons by the ear; and, 3) in the case of technology controlled for national security reasons under the ear where the direct product of the technology is a complete plant or component of a plant, not to export to ear country groups d:1 or e:2 the direct product of the plant or major component thereof, if such direct produ ct is controlled for national security reasons by the ear, or is subject to controls under the u.s. munitions list ("usml"). at all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this doc ument in connection with their receipt of any such information. copyright ? 2009. marvell international ltd. all rights reserved. marvell, the marvell logo, moving forward faster, alaska, fas twriter, datacom systems on silicon, libertas, link street, netgx, phyadvantage, prestera, raising the technology bar, the technology within, virtual cable tester, and yukon are registered trademarks of marvell. ants, anyvoltage, discovery, dsp switcher, feroceon, galnet, galtis, horizon, marvell makes it all possible, radlan, unimac, an d vct are trademarks of marvell. intel xscale? is a trademark or registered trademark of intel corporatio n or its subsidiaries in the united states and other countrie s. all other trademarks are the property of their respective owners. pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 2009 marvell page 2 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 3 1 introduction.................................................................................................................. ................11 1.1 about this document......................................................................................................... .............................11 1.1.1 number representation..................................................................................................... ...............11 1.1.2 typographical conventions ................................................................................................. .............11 1.1.3 applicable documents ...................................................................................................... ................11 2 functional overview ........................................................................................................... ........13 3 package information ........................................................................................................... ........15 3.1 package information ......................................................................................................... ..............................16 3.2 processor materials ......................................................................................................... ...............................24 3.3 junction to case temperature thermal resistance............................................................................. .........25 3.4 processor markings .......................................................................................................... ..............................25 3.5 tray drawing ................................................................................................................ ...................................25 4 pin listing and signal definitions ............................................................................................ .27 4.1 ball map view ............................................................................................................... ..................................27 4.1.1 13x13 mm vf-bga ball map.................................................................................................. ..........27 4.1.2 23x23 mm pbga ball map .................................................................................................... ...........32 4.2 pin use..................................................................................................................... .......................................35 4.3 signal types ................................................................................................................ ...................................58 4.4 memory controller reset and initialization.................................................................................. ....................59 4.5 power-supply pins ........................................................................................................... ...............................60 5 electrical specifications ..................................................................................................... ........63 5.1 absolute maximum ratings .................................................................................................... ........................63 5.2 operating conditions ........................................................................................................ ..............................64 5.2.1 internal power domains .................................................................................................... ...............68 5.3 power-consumption specifications............................................................................................ .....................69 5.4 dc specification............................................................................................................ ..................................74 5.5 oscillator electrical specifications........................................................................................ ...........................75 5.5.1 32.768-khz oscillator specifications ...................................................................................... ..........75 5.5.2 13.000-mhz oscillator specifications ...................................................................................... .........77 5.6 clk_pio and clk_tout specifications ......................................................................................... ..............78 5.7 48 mhz output specifications ................................................................................................ .........................79 6 ac timing specifications ...................................................................................................... .....81 6.1 ac test load specifications ................................................................................................. ..........................81
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 4 april 2009 released 6.2 reset and power manager timing specifications............................................................................... ............82 6.2.1 power-on timing specifications............................................................................................ ...........82 6.2.2 hardware reset timing ..................................................................................................... ...............84 6.2.3 watchdog reset timing ..................................................................................................... ..............84 6.2.4 gpio reset timing......................................................................................................... ..................84 6.2.5 sleep mode timing ......................................................................................................... ..................86 6.2.6 deep-sleep mode timing .................................................................................................... .............87 6.2.7 gpio states in deep-sleep mode ............................................................................................ ........88 6.2.8 standby-mode timing....................................................................................................... ................90 6.2.9 idle-mode timing .......................................................................................................... ....................90 6.2.10 frequency-change timing .................................................................................................. .............90 6.2.11 voltage-change timing .................................................................................................... ................90 6.3 gpio timing specifications .................................................................................................. ..........................91 6.4 memory and expansion-card timing specifications............................................................................. ..........91 6.4.1 internal sram read/write timing specifications............................................................................ .92 6.4.2 sdram parameters and timing diagrams ...................................................................................... 92 6.4.3 rom parameters and timing diagrams........................................................................................ ...98 6.4.4 flash memory parameters and timing diagrams ..........................................................................103 6.4.5 sram parameters and timing diagrams....................................................................................... 113 6.4.6 variable-latency i/o parameters and timing diagrams ................................................................116 6.4.7 expansion-card interface parameters and timing diagrams ........................................................119 6.5 lcd timing specifications ................................................................................................... .........................122 6.6 ssp timing specifications ................................................................................................... .........................123 6.7 jtag boundary scan timing specifications.................................................................................... .............126 6.8 marvell? quick capture technology ac timing................................................................................. ..........127 6.9 multimediacard timing specifications ........................................................................................ ..................129 6.10 secure digital (sd/sdio) timing ............................................................................................ ......................129
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 5 figure 1: marvell? pxa270 processor block diagram, typical system .........................................................14 figure 2: marvell? pxa270m processor part numbers ............................................................................... ...15 figure 3: 13x13mm vf-bga marvell? pxa270 processor package, top view...............................................16 figure 4: 13x13mm vf-bga marvell? pxa270 processor package, bottom view.........................................17 figure 5: 13x13mm vf-bga marvell? pxa270 processor package, side view .............................................18 figure 6: marvell? pxa270m 13mm x 13mm package mark diagram ...........................................................19 figure 7: marvell? pxa270m 23mm x 23mm package mark diagram ...........................................................20 figure 8: 23x23 mm pbga marvell? pxa270 processor package (top view) ..............................................21 figure 9: 23x23 mm pbga marvell? pxa270 processor package (bottom view).........................................22 figure 10: 23x23 mm pbga marvell? pxa270 processor package (side view) .............................................22 figure 11: package compliance criteria .......................................................................................... .................23 figure 12: 13x13mm vf-bga marvell? pxa270 processor package, bottom view.........................................24 figure 13: marvell? pxa270 processor production markings, (laser mark on top side)................................25 figure 14: 13x13 mm vf-bga ball map, top view (upper left quarter) ............................................................28 figure 15: 13x13 mm vf-bga ball map, top view (upper right quarter)..........................................................29 figure 16: 13x13 mm vf-bga ball map, top view (bottom left quarter) ..........................................................30 figure 17: 13x13 mm vf-bga ball map, top view (bottom right quarter) .......................................................31 figure 18: 23x23 mm pbga ball map, top view (upper left quarter).............................................................32 figure 19: 23x23 mm pbga ball map, top view (upper right quarter) ..........................................................33 figure 20: 23x23 mm pbga ball map, top view (lower left quarter).............................................................34 figure 21: 23x23 mm pbga ball map, top view (lower right quarter) ..........................................................35 figure 22: ac test load ......................................................................................................... ...........................81 figure 23: power on reset timing................................................................................................ ....................83 figure 24: hardware reset timing ................................................................................................ ....................84 figure 25: gpio reset timing.................................................................................................... .......................85 figure 26: sleep mode timing .................................................................................................... .......................86 figure 27: deep-sleep-mode timing ............................................................................................... ..................87 figure 28: sdram timing ......................................................................................................... ........................95 figure 29: sdram 4-beat read/4-beat write, different banks timing ............................................................96 figure 30: sdram 4-beat write/4-beat write, same bank-same row timing................................................97 figure 31: sdram fly-by dma timing .............................................................................................. ...............98 figure 32: 32-bit non-burst rom, sram, or flash read timing....................................................................1 00 figure 33: 32-bit burst-of-eight rom or flash read timing....................................................................... ....101 figure 34: eight-beat burst read from 16-bit burst-of-four rom or flash timing ........................................102 figure 35: 16-bit rom/flash/sram read for 4/2/1 bytes timing...................................................................1 03 figure 36: synchronous flash burst-of-eight read timing......................................................................... ....106 figure 37: synchronous flash stacked burst-of-eight read timing...............................................................10 7 figure 38: first-access latency configuration timing ............................................................................ ........108 figure 39: synchronous flash burst read example ................................................................................. ......110 figure 40: 32-bit flash write timing ............................................................................................ ...................111 figure 41: 32-bit stacked flash write timing .................................................................................... .............112 figure 42: 16-bit flash write timing ............................................................................................ ...................113 figure 43: 32-bit sram write timing ............................................................................................. .................115 figure 44: 16-bit sram write for 4/2/1 byte(s) timing........................................................................... .........116
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 6 april 2009 released figure 45: 32-bit vlio read timing.............................................................................................. ..................118 figure 46: 32-bit vlio write timing ............................................................................................. ...................119 figure 47: expansion-card memory or i/o 16-bit access timing ...................................................................1 21 figure 48: expansion-card memory or i/o 16-bit access to 8-bit device timing ...........................................122 figure 49: lcd timing definitions ............................................................................................... ....................122 figure 50: ssp master mode timing definitions ................................................................................... ..........124 figure 51: timing diagram for ssp slave mode transmitting data to an external peripheral .......................125 figure 52: timing diagram for ssp slave mode receiving data from external peripheral ............................125 figure 53: jtag boundary-scan timing ............................................................................................ .............127 figure 54: marvell? quick capture interface timing.............................................................................. .........128 figure 55: multimedia card timing diagrams...................................................................................... .............129 figure 56: sd/sdio timing diagrams.............................................................................................. .................130
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 7
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 8 april 2009 released table 1: supplemental documentation............................................................................................. ..............12 table 2: processor material properties .......................................................................................... ................25 table 3: pin use summary........................................................................................................ .....................36 table 4: pin use and mapping notes .............................................................................................. ...............58 table 5: signal types ........................................................................................................... ..........................59 table 6: memory controller pin reset values..................................................................................... ...........59 table 7: discrete (13x13 vf-bga) power supply pin summary ...................................................................60 table 8: absolute maximum ratings ............................................................................................... ...............63 table 9: voltage, temperature, and frequency electrical specifications ......................................................64 table 10: memory voltage and frequency electrical specifications ................................................................ 66 table 11: core voltage and frequency electrical specifications .................................................................. ...67 table 12: internally generated power domain descriptions ........................................................................ ....68 table 13: core voltage specifications for lower power modes..................................................................... .68 table 14: typical power-consumption specifications.............................................................................. ........69 table 15: maximum idle and low power mode power-consumption specifications .......................................72 table 16: standard input, output, and i/o pin dc operating conditions ........................................................74 table 17: typical 32.768-khz crystal requirements............................................................................... .........75 table 18: typical external 32.768-khz oscillator requirements.................................................................. ...77 table 19: typical 13.000-mhz crystal requirements ............................................................................... .......77 table 20: typical external 13.000-mhz oscillator requirements ................................................................... .78 table 21: clk_pio specifications ................................................................................................ ...................78 table 22: clk_tout specifications ............................................................................................... .................79 table 23: 48 mhz output specifications .......................................................................................... ................79 table 24: standard input, output, and i/o-pin ac operating conditions ........................................................81 table 25: power-on timing specifications(oscc[cri] = 0)......................................................................... ...83 table 26: hardware reset timing specifications (oscc[cri] = 0).................................................................84 table 27: hardware reset timing specifications (oscc[cri] = 1)................................................................84 table 28: gpio reset timing specifications ............................................................... ...................................85 table 29: sleep-mode timing specifications ...................................................................................... .............87 table 30: deep-sleep mode timing specifications ................................................................................. .........87 table 31: gpio pu/pd timing specifications for deep-sleep mode ................................................................89 table 32: standby-mode timing specifications .................................................................................... ...........90 table 33: idle-mode timing specifications....................................................................................... ................90 table 34: frequency-change timing specifications ................................................................................ ........90 table 35: voltage-change timing specification for a 1-byte command..........................................................91 table 36: gpio timing specifications ............................................................................................ ..................91 table 37: sram read/write ac specification ...................................................................................... ...........92 table 38: sdram interface ac specifications..................................................................................... ............92 table 39: rom ac specification .................................................................................................. ....................99 table 40: synchronous flash read ac specifications .............................................................................. ....104 table 41: flash memory ac specification......................................................................................... .............110 table 42: sram write ac specification........................................................................................... ..............114 table 43: vlio timing ........................................................................................................... .........................117 table 44: expansion-card interface ac specifications ............................................................................ ......120
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 9 table 45: lcd timing specifications............................................................................................. .................123 table 46: ssp master mode timing specifications................................................................................. .......124 table 47: timing specification ssp slave mode transmitting data to external peripheral...........................125 table 48: timing specification for ssp slave mode receiving data from external peripheral .....................126 table 49: boundary scan timing specifications ................................................................................... .........126 table 50: marvell? quick capture ac timing specification ........................................................................ ..127 table 51: multimedia card timing specifications ................................................................................. ...........129 table 52: sd/sdio timing specifications ......................................................................................... .............130
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 10 april 2009 released
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev.d april 2009 released page 11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 1 introduction the marvell? pxa270 processor (pxa270 processor) provides industry-leading multimedia performance, low-power capabilities, rich peripheral integration and second generation memory stacking. designed from the ground up for wireless clients, it incorporates the latest marvell advances in mobile technology over its predecessor, the marvell? pxa255 processor. these same attributes and features also make the pxa270 processor ideal for embedded applications. the pxa270 processor redefines scalability by operating from 104 mhz up to 624 mhz, providing enough performance for the most demanding mobile applications. the pxa270 processor is the first marvell processor to include intel? wireless mmx? technology, enabling high-performance, low-power multimedia acceleration with a general-purpose instruction set. the marvell? quick capture interface provides a flexible and powerful camera interface for capturing digital images and video. while performance is key in the pxa270 processor, power consumption is also a critical component. the new capabilities of wireless intel speedstep? technology set the standard for low-power consumption. the pxa270 processor is offered in two packages: 13x13 mm vfbga and 23x23 mm pbga. 1.1 about this document this document constitutes the electrical, mechanical, and thermal specifications for the pxa270 processor. it contains a functional overview, mechanical data, package signal locations, targeted electrical specifications, and functional bus waveforms. for detailed functional descriptions other than parametric performance, refer to the marvell? pxa27x processor family developers manual . 1.1.1 number representation all numbers in this document are base 10 unless designated otherwise. hexadecimal numbers have a prefix of 0x, and binary numbers have a prefix of 0b. for example, 107 is represented as 0x6b in hexadecimal and 0b110_1011 in binary. 1.1.2 typographical conventions all signal and register-bit names appear in uppercase. active low items are prefixed with a lowercase ?n?. bits within a signal name are enclosed in angle brackets: external_address<31:0> ncs<1> bits within a register bit field are enclosed in square brackets: register_bitfield[3:0] register_bit[0] single-bit items have either of two states: ? clear ? the item contains the value 0b0. to clear a bit, write 0b0 to it. ? set ? the item contains the value 0b1. to set a bit, write 0b1 to it. 1.1.3 applicable documents table 1 lists supplemental information sources for the pxa270 processor. contact a marvell representative for the latest document revisions and ordering instructions.
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev.d copyright ? 4/3/09 marvell page 12 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 table 1: supplemental documentation document title marvell? pxa27x processor family developers manual arm ? architecture version 5t specification (document number arm* ddi 0100d-10), and arm ? architecture reference manual (document number arm* ddi 0100b) intel xscale? core developer?s manual intel? wireless mmx? technology developer?s guide marvell? pxa27x processor design guide marvell? pxa27x processor power supply requirements application note
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 2 functional overview the marvell? pxa270 processor is an integrated system-on-a-chip microprocessor for high performance, dynamic, low-power portable handheld and hand-set devices as well as embedded platforms. it incorporates the intel xscale? technology which complies with the arm* version 5te instruction set (excluding floating-point instructions) and follows the arm* programmer?s model. the pxa270 processor also provides intel? wireless mmx? media enhancement technology, which supports integer instructions to accelerate audio and video processing. in addition, it incorporates wireless intel speedstep? technology, which provides sophisticated power management capabilities enabling excellent mips/mw performance. the pxa270 processor provides a scalable, bi-directional data interface to a cellular baseband processor, supporting seven logical channels and other features. the operating-system (os) timer channels and synchronous serial ports (ssps) also accept an external network clock input so that they can be synchronized to the cellular network. the processor also provides a universal subscriber identity module* (usim) card interface. the pxa270 processor memory interface gives designers flexibility as it supports a variety of external memory types. the processor also provides four 64 kilobyte banks of on-chip sram, which can be used for program code or multimedia data. each bank can be configured independently to retain its contents when the processor enters a low-power mode. an integrated lcd panel controller supports displays up to 800 by 600 pixels, permitting 1-, 2-, 4-, and 8-bit gray scale and 1-, 2-, 4-, 8-, 16-, 18-, and 24-bit color pixels. a 256-byte palette ram provides flexible color mapping. a set of serial devices and general-system resources offers computational and connectivity capability for a variety of applications. figure 1 shows the block diagram for a typical pxa270 processor system.
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 14 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 1: marvell? pxa270 processor block diagram, typical system general purpose i/o dma controller and bridge mhz osc xscale? micro- memory controller pcmcia & cf control variable control dynamic control static control memory memory latency i/o asic xcvr rom/ flash/ sram socket 0 socket 1 marvell? wireless mmx? usb host system bus controller internal sram 13 power management clock control primary gpio peripheral bus address and data address and data bus ac97 rtc i 2 s os timers 4 x pwm interrupt usim 3 x ssp irda i 2 c full function uart usb client bb processor interface keypad interface bluetooth uart sdcard/mmc interface memory stick interface lcd lcd khz osc 32.768 controller architecture intel? jtag controller debug usb otg camera interface sdram ge neral p ur pose i /o dma controller and bridge mhz os c xscale? mi cro- memory controller pcmcia & cf control var ia ble control dynamic control static control memory memory latency i /o as ic xcvr sdram/ boot rom/ flash/ sram soc ket 0 soc ket 1 intel? wireless mmx? usb ho st system bus controller in tern al sram 13 power management clock control p rimar y gp io per iphera l bus address and data address and data b us ac 97 rt c i 2 s os timers 4 x pwm i nterrupt usim 3 x ssp irda i 2 c full function ua rt usb client bb processor interface k e ypad interface bluet oot h* uart sdcard/mmc interface memory stick int erface lc d lcd khz osc 32 .76 8 controller architecture in tel? jtag controller debug rom usb otg camer a interface ? note note memory stick is not available on pxa270m (ap270m) skus.
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 3 package information this chapter provides the mechanical specifications for the pxa270 processor. the pxa270 processor is offered in two packages. part numbers are shown in figure 2 . the 13- by 13-mm, 356-ball, 0.50-mm vf-bga molded matrix array package is shown in figure 3 , figure 4 , figure 5 , and figure 6 . the 23- by 23-mm, 360-ball, 1.0-mm pbga molded matrix array package is shown in figure 7 , figure 8 , figure 9 , and figure 10 . figure 2: marvell? pxa270m processor part numbers
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 16 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 3.1 package information note note figure 4 and figure 5 show all dimensions in millimeters (mm). figure 3: 13x13mm vf-bga marvell? pxa270 processor package, top view a b c d e f g h j k l m n p r t u v w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a1
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 4: 13x13mm vf-bga marvell? pxa270 processor package, bottom view 11.50 11.50 0.50 0.50 a b 0.15 m c a b 0.15 m c ?0.300.05 (356) 130.10 130.10
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 18 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 5: 13x13mm vf-bga marvell? pxa270 processor package, side view 0.210.04 0.450.05 0.18 min. ? 0.30 max. 1.0 max. 0.10 c 0.12 c c seating plane 0.91 min. -
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 6: marvell? pxa270m 13mm x 13mm package mark diagram
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 20 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 7: marvell? pxa270m 23mm x 23mm package mark diagram
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 note note figure 8 , figure 9 and figure 10 show all dimensions in millimeters (mm). figure 8: 23x23 mm pbga marvell? pxa270 processor package (top view) a1 corner 14.70 0.25
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 22 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 9: 23x23 mm pbga marvell? pxa270 processor package (bottom view) 1.00 1.00 1.00 17 16 15 14 13 12 1.00 u t r p n m l k j h g f corner pin #1 4 11 10 9 8 7 6 5 e d c b a 3 2 1 v w y aa ab 18 19 20 21 22 ball diameter = 0.60 +/-0.10 mm figure 10: 23x23 mm pbga marvell? pxa270 processor package (side view) 0.20 c c 0.15 // seating plane 3
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 11: package compliance criteria
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 24 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 3.2 processor materials figure 12: 13x13mm vf-bga marvell? pxa270 processor package, bottom view tab le 2 describes the basic material properties of the processor components.
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 3.3 junction to case temperature thermal resistance 3.4 processor markings the diagram in this section details the processor?s top markings, which identify the pxa270 processor in the 356-ball vf-bga and 360-ball pbga package. a pb-free (lead-free) package is indicated by the letter ?e? on the 3rd line of information (marvell legal line). the ?e? appears after the date stamp. 3.5 tray drawing for tray drawing information, refer to the intel developer website for the intel? wireless communications and computing package users guide . table 2: processor material properties component vf-bga material pbga material mold compound shinetsu kmc 2500 vat1 sumitomo g770le solder balls(leaded) 63% sn/37% pb 63% sn/37% pb solder balls(pb-free) 94.5% sn / 5.0% ag / 0.5% cu 94.5% sn / 5.0% ag / 0.5% cu parameter vf-bga value and units pbga value and units theta jc 2 degrees c / watt 1.4 degrees c / watt figure 13: marvell? pxa270 processor production markings, (laser mark on top side) bulverde production mark diagram laser mark on top side of package product lot # intel legal i pxa270c0c416 fpo# m c ?03 taiwan pin 1 indicator coo bulverde production mark diagram laser mark on top side of package product lot # intel legal i pxa270c0c416 fpo# m c ?03 taiwan pin 1 indicator coo
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 26 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 4 pin listing and si gnal definitions this chapter describes the signals and pins for the marvell? pxa270 processor. for descriptions of all pxa270 processor signals, refer to the ?system architecture? chapter in the marvell? pxa27x processor family developer?s manual . table 4 lists the mapping of signals to specific package pins. many of the package pins are multiplexed so that they can be configured for use as a general-purpose i/o signal or as one of two or three alternate functions using the gpio alternate-function select registers. some signals can be configured to appear on one of several different package pins. 4.1 ball map view note note in the following ball map figures the lowercase letter ?n?, which normally indicates negation, appears as uppercase ?n?. 4.1.1 13x13 mm vf-bga ball map figure 14 through figure 17 shows the ball map for the vf-bga pxa270 processor.
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 28 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 14: 13x13 mm vf-bga ball map, top view (upper left quarter) 123456789101112 a vss_core vss_core gpio<15> vcc_mem vcc_sram ma<1> vcc_core vcc_sram vcc_sram gpio<49> gpio<47> vcc_io b vss_core vss_core ncs<0> vcc_sram vss_core gpio<33> gpio<78> vcc_mem gpio<18> gpio<12> gpio<46> vcc_core c ma<18> ma<22> vcc_mem ma<24> vss_mem ma<0> gpio<80> gpio<79> rdnwr gpio<13> gpio<11> gpio<31> d ma<17> ma<21> vcc_core ma<23> vss_mem ma<25> vss_core vss_core vss_mem vss_core vss_io vss_core e ma<13> vcc_mem ma<19> ma<20> f vcc_mem ma<14> ma<16> vss_mem g ma<8> ma<11> ma<12> ma<15> h vcc_mem ma<9> ma<10> vss_mem j ma<3> ma<6> ma<7> vss_mem k md<15> ma<4> ma<5> ma<2> vss_core vss_core vss_core l md<14> md<31> vcc_mem vss_mem vss_core vss_core vss_core m vcc_mem md<30> md<29> md<13> vss_core vss_core vss_core
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 15: 13x13 mm vf-bga ball map, top view (upper right quarter) 13 14 15 16 17 18 19 20 21 22 23 24 gpio<113> gpio<28> gpio<37> vcc_io gpio<24> gpio<16> gpio<92> gpio<32> gpio<34> gpio<118> vcc_usb vcc_usb a gpio<29> gpio<38> gpio<26> gpio<23> gpio<110> gpio<112> gpio<35> gpio<44> vcc_core usbc_p vcc_usb vcc_usb b gpio<30> gpio<36> gpio<27> gpio<17> gpio<111> gpio<41> gpio<45> usbc_n gpio<42> gpio<43> gpio<88> gpio<116> c gpio<22> gpio<40> vss_io gpio<25> gpio<109> vss_io gpio<39> gpio<117> vss_core gpio<89> usbh_n<1> gpio<114> d gpio<115> usbh_p<1> uio vcc_usim e vss_io gpio<90> gpio<91> vcc_core f vss_core gpio<59> gpio<60> gpio<58> g vss_io gpio<62> gpio<63> gpio<61> h vss_core gpio<64> vcc_core vcc_lcd j vss_core vss_core vss_core vss_core gpio<66> gpio<67> gpio<65> k vss_core vss_core vss_core gpio<68> gpio<71> gpio<69> vcc_core l vss_core vss_core vss_core vss_core gpio<73> vcc_core gpio<70> m
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 30 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 16: 13x13 mm vf-bga ball map, top view (bottom left quarter) n md<27> md<28> md<12> vss_mem vss_core vss_core vss_core p vcc_mem md<11> md<26> md<10> vss_core vss_core vss_core r md<24> vss_mem md<25> md<9> vss_core vss_core vss_core t md<23> vcc_core md<8> vss_mem u md<7> vcc_mem vss_core md<5> v md<21> md<22> md<6> vss_mem w md<20> vcc_mem vcc_core vss_core y md<19> md<4> md<3> vss_mem aa md<18> vcc_mem md<2> md<16> vss_mem nsdcas vss_core vss_mem vss_mem gpio<55> gpio<84> vss_core ab md<1> vss_mem md<17> md<0> nwe gpio<20> nsdcs<0> nsdcs<1> dqm<0> dqm<1> gpio<56> gpio<81> ac vcc_mem vcc_mem vss_mem sdclk<0> noe vcc_mem nsdras vcc_mem dqm<2> dqm<3> gpio<57> gpio<85> ad vcc_mem vcc_mem sdclk<2> vcc_core gpio<21> sdcke sdclk<1> vcc_mem gpio<82> gpio<83> vcc_core vcc_bb 123456789101112
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 17: 13x13 mm vf-bga ball map, top view (bottom right quarter) vss_core vss_core vss_core vss_io gpio<86> gpio<87> gpio<72> n vss_core vss_core vss_core vss_core gpio<76> gpio<75> vcc_lcd p vss_core vss_core vss_core gpio<77> gpio<19> gpio<74> vcc_core r tms tck testclk gpio<14> t ntrst gpio<9> tdi vss_io u vss gpio<0> gpio<10> tdo v gpio<3> nvdd_faul t gpio<4> clk_req w nreset_o ut nreset pwr_en gpio<1> y vss_bb gpio<54> vss_core vss_io gpio<97> gpio<95> vss_io pwr_cap< 3> vss txtal_in txtal_out sys_en aa gpio<50> gpio<53> gpio<106> gpio<105> gpio<102> gpio<99> gpio<93> vcc_batt pwr_cap< 0> pwr_out boot_sel nbatt_fau lt ab gpio<48> gpio<52> gpio<107> gpio<103> gpio<101> gpio<100> gpio<96> vcc_pll pxtal_in pwr_cap< 2> vss vss ac gpio<51> gpio<108> gpio<104> vcc_core vcc_io gpio<98> gpio<94> vss_pll pxtal_out pwr_cap< 1> vss vss ad 13 14 15 16 17 18 19 20 21 22 23 24
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 32 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 4.1.2 23x23 mm pbga ball map figure 18: 23x23 mm pbga ball map, top view (upper left quarter) 1234567891011 a vss_mem vss_mem ma[25] gpio[15] gpio[79] gpio[13] gpio[12] gpio[11] gpio[46] gpio[113] gpio[29] b vss_mem vcc_mem vss_mem vcc_ram ma[1] vss_mem vcc_ram vcc_ram vss_mem vcc_io gpio[30] c ma[16] ma[17] vcc_mem ma[24] vcc_ram vcc_mem gpio[33] rdnwr vcc_mem gpio[47] gpio[31] d ma[14] ma[15] ma[19] ma[22] ma[0] ncs_0 gpio[80] gpio[78] gpio[18] gpio[49] vcc_core e ma[11] ma[12] ma[21] ma[23] vss_core vcc_core vss_core vcc_core vss_core f ma[9] vss_mem vcc_mem ma[20] vcc_core g ma[7] ma[8] ma[13] ma[18] vss_core h ma[4] vss_mem vcc_mem ma[10] vcc_core j ma[3] ma[2] ma[6] ma[5] vss_core vss_core vss_core vss_core k md[15] md[30] vcc_mem md[31] vss_core vss_core vss_core l md[14] vss_mem md[29] vcc_core vss_core vss_core vss_core
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 19: 23x23 mm pbga ball map, top view (upper right quarter) 12 13 14 15 16 17 18 19 20 21 22 gpio[22] gpio[38] gpio[26] gpio[25] gpio[23] gpio[111] gpio[92] gpio[41] gpio[44] vcc_usb vcc_usb a vss_io gpio[36] gpio[24] vss_io gpio[112] gpio[39] vss_io gpio[34] gpio[118] gpio[43] vcc_usb b gpio[40] gpio[27] gpio[16] gpio[110] gpio[32] gpio[45] gpio[117] nc nc gpio[89] gpio[88] c gpio[28] gpio[37] vcc_io gpio[17] gpio[109] gpio[35] usbc_p vcc_usb gpio[42] vss_io usbh_n[1] d vss_core vcc_core vss_core vcc_core vss_core usbc_n gpio[116] gpio[115] usbh_p[1] e vcc_core gpio[114] uio vcc_usim gpio[61] f vss_core gpio[91] gpio[58] gpio[60] gpio[62] g vcc_core gpio[90] gpio[59] vss_io gpio[64] h vss_core vss_core vss_core vss_core gpio[66] gpio[63] vcc_lcd gpio[69] j vss_core vss_core vss_core gpio[67] gpio[65] gpio[68] gpio[70] k vss_core vss_core vss_core vcc_core gpio[71] gpio[72] gpio[73] l
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 34 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 20: 23x23 mm pbga ball map, top view (lower left quarter) m md[13] md[11] vcc_mem md[12] vss_core vss_core vss_core n md[28] md[26] md[24] md[25] vss_core vss_core vss_core p md[27] vss_mem vcc_mem md[8] vss_core vss_core vss_core vss_core r md[10] md[23] md[21] md[7] vcc_core t md[9] vss_mem vcc_mem md[5] vss_core u md[22] md[6] md[4] md[2] vcc_core v md[20] vss_mem vcc_mem md[16] vss_core vcc_core vss_core vcc_core vss_core w md[19] md[18] md[1] md[0] gpio[20] nsdras sdcke dqm[0] gpio[55] gpio[81] vcc_core y md[3] md[17] vcc_mem nsdcas vcc_mem gpio[21] vcc_mem nsdcs[1] vcc_mem gpio[84] gpio[48] aa vss_mem vcc_mem nwe noe nsdcs[0] vss_mem dqm[1] gpio[82] vss_mem gpio[85] vcc_bb ab vss_mem vss_mem sdclk[0] sdclk[2] sdclk[1] dqm[2] dqm[3] gpio[56] gpio[57] gpio[83] vss_bb 1234567891011
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 35 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 4.2 pin use the pin-use summary shown in tab l e 3 does not include the 36 center balls identified as k10 through r15 (vf-bga) or j9 through p14 (pbga), all of which function as vss_core (see the recommendations for connecting the 36 center balls in the marvell? pxa27x processor family design guide ). each signal?s alternate function inputs are shown in the upper section of each signal row and the outputs are shown in the lower section of each signal row. for example, gpio<48> has a primary input function of cif_dd<5> and a secondary output function of npoe. figure 21: 23x23 mm pbga ball map, top view (lower right quarter) vss_core vss_core vss_core vcc_lcd gpio[86] vss_io gpio[87] m vss_core vss_core vss_core vss_io gpio[75] gpio[76] gpio[74] n vss_core vss_core vss_core vss_core gpio[19] gpio[14] gpio[77] testclk p vcc_core tck tms tdo tdi r vss_core gpio[4] ntrst clk_req gpio[9] t vcc_core nbatt_fau lt gpio[0] gpio[1] gpio[10] u vss_core vcc_core vss_core vcc_core vss_core boot_sel nvdd_faul t sys_en gpio[3] v gpio[50] gpio[106] gpio[104] vcc_io gpio[96] pwr_cap [3] vss pwr_out nreset nreset_o ut pwr_en w gpio[52] gpio[105] gpio[102] gpio[97] gpio[93] vcc_batt pwr_cap [2] pwr_cap [0] vss txtal_in txtal_out y gpio[53] gpio[108] vss_io gpio[100] gpio[98] gpio[94] vss_io vss_pll pxtal_out pwr_cap [1] vss aa gpio[51] gpio[54] gpio[107] gpio[103] gpio[101] gpio[99] gpio[95] vcc_pll pxtal_in vss vss ab 12 13 14 15 16 17 18 19 20 21 22
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 36 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 table 3: pin use summary (sheet 1 of 22) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state vcc_mem d6 a3 ma<25> ocz ma<25> ma<25> ? ? refer to ta b l e 6 c4 c4 ma<24> ocz ma<24> ma<24> ? ? refer to ta b l e 6 d4 e4 ma<23> ocz ma<23> ma<23> ? ? refer to ta b l e 6 c2 d4 ma<22> ocz ma<22> ma<22> ? ? refer to ta b l e 6 d2 e3 ma<21> ocz ma<21> ma<21> ? ? refer to ta b l e 6 e4 f4 ma<20> ocz ma<20> ma<20> ? ? refer to ta b l e 6 e3 d3 ma<19> ocz ma<19> ma<19> ? ? refer to ta b l e 6 c1 g4 ma<18> ocz ma<18> ma<18> ? ? refer to ta b l e 6 d1 c2 ma<17> ocz ma<17> ma<17> ? ? refer to ta b l e 6 f3 c1 ma<16> ocz ma<16> ma<16> ? ? refer to ta b l e 6 g4 d2 ma<15> ocz ma<15> ma<15> ? ? refer to ta b l e 6 f2 d1 ma<14> ocz ma<14> ma<14> ? ? refer to ta b l e 6 e1 g3 ma<13> ocz ma<13> ma<13> ? ? refer to ta b l e 6 g3 e2 ma<12> ocz ma<12> ma<12> ? ? refer to ta b l e 6 g2 e1 ma<11> ocz ma<11> ma<11> ? ? refer to ta b l e 6 h3 h4 ma<10> ocz ma<10> ma<10> ? ? refer to ta b l e 6 h2 f1 ma<9> ocz ma<9> ma<9> ? ? refer to ta b l e 6 g1 g2 ma<8> ocz ma<8> ma<8> ? ? refer to ta b l e 6 j3 g1 ma<7> ocz ma<7> ma<7> ? ? refer to ta b l e 6 j2 j3 ma<6> ocz ma<6> ma<6> ? ? refer to ta b l e 6 k3 j4 ma<5> ocz ma<5> ma<5> ? ? refer to ta b l e 6 k2 h1 ma<4> ocz ma<4> ma<4> ? ? refer to ta b l e 6 j1 j1 ma<3> ocz ma<3> ma<3> ? ? refer to ta b l e 6 k4 j2 ma<2> ocz ma<2> ma<2> ? ? refer to ta b l e 6 a6 b5 ma<1> ocz ma<1> ma<1> ? ? refer to ta b l e 6 c6 d5 ma<0> ocz ma<0> ma<0> ? ? refer to ta b l e 6 note: refer to table 4 for numbered notes on reset and sleep states.
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 l2 k4 md<31> ico cz md<31> md<31> ? ? refer to ta b l e 6 m2 k2 md<30> ico cz md<30> md<30> ? ? refer to ta b l e 6 m3 l3 md<29> ico cz md<29> md<29> ? ? refer to ta b l e 6 n2 n1 md<28> ico cz md<28> md<28> ? ? refer to ta b l e 6 n1 p1 md<27> ico cz md<27> md<27> ? ? refer to ta b l e 6 p3 n2 md<26> ico cz md<26> md<26> ? ? refer to ta b l e 6 r3 n4 md<25> ico cz md<25> md<25> ? ? refer to ta b l e 6 r1 n3 md<24> ico cz md<24> md<24> ? ? refer to ta b l e 6 t1 r2 md<23> ico cz md<23> md<23> ? ? refer to ta b l e 6 v2 u1 md<22> ico cz md<22> md<22> ? ? refer to ta b l e 6 v1 r3 md<21> ico cz md<21> md<21> ? ? refer to ta b l e 6 w1 v1 md<20> ico cz md<20> md<20> ? ? refer to ta b l e 6 y1 w1 md<19> ico cz md<19> md<19> ? ? refer to ta b l e 6 aa1 w2 md<18> ico cz md<18> md<18> ? ? refer to ta b l e 6 ab3 y2 md<17> ico cz md<17> md<17> ? ? refer to ta b l e 6 aa4 v4 md<16> ico cz md<16> md<16> ? ? refer to ta b l e 6 k1 k1 md<15> ico cz md<15> md<15> ? ? refer to ta b l e 6 table 3: pin use summary (sheet 2 of 22) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4 for numbered notes on reset and sleep states.
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 38 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 l1 l1 md<14> ico cz md<14> md<14> ? ? refer to ta b l e 6 m4 m1 md<13> ico cz md<13> md<13> ? ? refer to ta b l e 6 n3 m4 md<12> ico cz md<12> md<12> ? ? refer to ta b l e 6 p2 m2 md<11> ico cz md<11> md<11> ? ? refer to ta b l e 6 p4 r1 md<10> ico cz md<10> md<10> ? ? refer to ta b l e 6 r4 t1 md<9> ico cz md<9> md<9> ? ? refer to ta b l e 6 t3 p4 md<8> ico cz md<8> md<8> ? ? refer to ta b l e 6 u1 r4 md<7> ico cz md<7> md<7> ? ? refer to ta b l e 6 v3 u2 md<6> ico cz md<6> md<6> ? ? refer to ta b l e 6 u4 t4 md<5> ico cz md<5> md<5> ? ? refer to ta b l e 6 y2 u3 md<4> ico cz md<4> md<4> ? ? refer to ta b l e 6 y3 y1 md<3> ico cz md<3> md<3> ? ? refer to ta b l e 6 aa3 u4 md<2> ico cz md<2> md<2> ? ? refer to ta b l e 6 ab1 w3 md<1> ico cz md<1> md<1> ? ? refer to ta b l e 6 ab4 w4 md<0> ico cz md<0> md<0> ? ? refer to ta b l e 6 ac5 aa4 noe ocz noe noe ? ? refer to ta b l e 6 ab5 aa3 nwe ocz nwe nwe ? ? refer to ta b l e 6 ac7 w6 nsdras ocz nsdras nsdras ? ? refer to ta b l e 6 table 3: pin use summary (sheet 3 of 22) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4 for numbered notes on reset and sleep states.
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 39 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 aa6 y4 nsdcas ocz nsdcas nsdcas ? ? refer to ta b l e 6 ab9 w8 dqm<0> ocz dqm<0> dqm<0> ? ? refer to ta b l e 6 ab10 aa7 dqm<1> ocz dqm<1> dqm<1> ? ? refer to ta b l e 6 ac9 ab6 dqm<2> ocz dqm<2> dqm<2> ? ? refer to ta b l e 6 ac10 ab7 dqm<3> ocz dqm<3> dqm<3> ? ? refer to ta b l e 6 ab7 aa5 nsdcs< 0> ocz nsdcs<0> nsdcs<0> ? ? refer to ta b l e 6 ab8 y8 nsdcs< 1> oc nsdcs<1> nsdcs<1> ? ? refer to ta b l e 6 ad6 w7 sdcke oc sdcke sdcke ? ? refer to ta b l e 6 ac4 ab3 sdclk< 0> oc sdclk<0> sdclk<0> ? ? refer to ta b l e 6 ad7 ab5 sdclk< 1> ocz sdclk<1> sdclk<1> ? ? refer to ta b l e 6 ad3 ab4 sdclk< 2> oc sdclk<2> sdclk<2> ? ? refer to ta b l e 6 c9 c8 rdnwr ocz rdnwr rdnwr ? ? refer to ta b l e 6 b3 d6 ncs<0> ocz ncs<0> ncs<0> ? ? refer to ta b l e 6 a3 a4 gpio<15 > ico cz gpio<15> ? ? ? pu-1 note[1] note[4] npce<1> ncs<1> refer to ta b l e 6 ? b9 d9 gpio<18 > ico cz gpio<18> rdy ? ? pd-0 note[1] note [3] ??? ab6 w5 gpio<20 > ico cz gpio<20> dreq<0> mbreq ? pu-1 note[1] note[3] nsdcs<2> refer to table 6 ?? ad5 y6 gpio<21 > ico cz gpio<21> ? ? ? pu-1 note[1] note[3] nsdcs<3> refer to table 6 dval<0> mbgnt table 3: pin use summary (sheet 4 of 22) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4 for numbered notes on reset and sleep states.
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 40 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 b6 c7 gpio<33 > ico cz gpio<33> ffrxd 19 ffdsr 19 ? pu-1 note[1] note [4] dval<1> ncs<5> refer to ta b l e 6 mbgnt a10 d10 gpio<49 > ico cz gpio<49> ? ? ? pu-1 note[1] note [5] ?npwe refer to ta b l e 6 ? b7 d8 gpio<78 > ico cz gpio<78> ? ? ? pu-1 note[1] note[4] npce<2> ncs<2> refer to ta b l e 6 ? c8 a5 gpio<79 > ico cz gpio<79> ? ? ? pu-1 note[1] note[4] psktsel ncs<3> refer to ta b l e 6 pwm_out <2> c7 d7 gpio<80 > ico cz gpio<80> dreq<1> mbreq ? pu-1 note[1] note[4] ?ncs<4> refer to ta b l e 6 pwm_out <3> vcc_bb ac13 y11 gpio<48 > ico cz gpio<48> cif_dd<5> ? ? pu-1 note[1] note [5] bb_ob_dat< 1> npoe refer to ta b l e 6 ? ab13 w12 gpio<50 > ico cz gpio<50> cif_dd<3> ? sspsclk <2> pu-1 note[1] note [5] bb_ob_dat< 2> npioir refer to ta b l e 6 sspsclk <2> ad13 ab12 gpio<51 > ico cz gpio<51> cif_dd<2> ? ? pu-1 note[1] note [5] bb_ob_dat< 3> npioiw refer to ta b l e 6 ? table 3: pin use summary (sheet 5 of 22) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4 for numbered notes on reset and sleep states.
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 ac14 y12 gpio<52 > ico cz gpio<52> cif_dd<4> sspsclk<3> ? pd-0 note[1] note [3] bb_ob_clk sspsclk<3> ? ab14 aa12 gpio<53 > ico cz gpio<53> ffrxd usb_p2_3 ? pd-0 note[1] note [3] bb_ob_stb cif_mclk sspsysc lk aa14 ab13 gpio<54 > ico cz gpio<54> ? bb_ob_wait cif_pclk pd-0 note[1] note [3] npce<2> ? aa10 w9 gpio<55 > ico cz gpio<55> cif_dd<1> bb_ib_dat<1 > ? pu-1 note[1] note [5] ?npreg ? ab11 ab8 gpio<56 > ico cz gpio<56> npwait bb_ib_dat<2 > ? pu-1 note[1] note [5] usb_p3_4 ? ? ac11 ab9 gpio<57 > ico cz gpio<57> niois16 bb_ib_dat<3 > ? pu-1 note[1] note [5] ? ? ssptxd ab12 w10 gpio<81 > ico cz gpio<81> ? cif_dd<0> ? pu-1 note[1] note [3] ssptxd3 bb_ob_dat< 0> ? ad9 aa8 gpio<82 > ico cz gpio<82> ssprxd3 bb_ib_dat<0 > cif_dd<5 > pu-1 note[1] note [3] ??ffdtr ad10 ab10 gpio<83 > ico cz gpio<83> sspsfrm3 bb_ib_clk cif_dd<4 > pd-0 note[1] note [3] sspsfrm3 fftxd ffrts aa11 y10 gpio<84 > ico cz gpio<84> sspsclk3 bb_ib_stb cif_fv pd-0 note[1] note [3] sspsclk3 ? cif_fv ac12 aa10 gpio<85 > ico cz gpio<85> ffrxd dreq<2> cif_lv pd-0 note[1] note [3] npce<1> bb_ib_wait cif_lv vcc_lcd table 3: pin use summary (sheet 6 of 22) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4 for numbered notes on reset and sleep states.
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 42 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 t24 p20 gpio<14 > ico cz gpio<14> l_vsync sspsfrm2 ? pd-0 note[1] note [3] ? sspsfrm2 uclk r22 p19 gpio<19 > ico cz gpio<19> sspsclk2 ? ffrxd pd-0 note[1] note [3] sspsclk2 l_cs nurst g24 g20 gpio<58 > ico cz gpio<58> ? ldd<0> ? pd-0 note[1] note [3] ? ldd<0> ? g22 h20 gpio<59 > ico cz gpio<59> ? ldd<1> ? pd-0 note[1] note [3] ? ldd<1> ? g23 g21 gpio<60 > ico cz gpio<60> ? ldd<2> ? pd-0 note[1] note [3] ? ldd<2> ? h24 f22 gpio<61 > ico cz gpio<61> ? ldd<3> ? pd-0 note[1] note [3] ? ldd<3> ? h22 g22 gpio<62 > ico cz gpio<62> ? ldd<4> ? pd-0 note[1] note [3] ? ldd<4> ? h23 j20 gpio<63 > ico cz gpio<63> ? ldd<5> ? pd-0 note[1] note [3] ? ldd<5> ? j22 h22 gpio<64 > ico cz gpio<64> ? ldd<6> ? pd-0 note[1] note [3] ? ldd<6> ? k24 k20 gpio<65 > ico cz gpio<65> ? ldd<7> ? pd-0 note[1] note [3] ? ldd<7> ? k22 j19 gpio<66 > ico cz gpio<66> ? ldd<8> ? pd-0 note[1] note [3] ? ldd<8> ? k23 k19 gpio<67 > ico cz gpio<67> ? ldd<9> ? pd-0 note[1] note [3] ? ldd<9> ? l21 k21 gpio<68 > ico cz gpio<68> ? ldd<10> ? pd-0 note[1] note [3] ? ldd<10> ? l23 j22 gpio<69 > ico cz gpio<69> ? ldd<11> ? pd-0 note[1] note [3] ? ldd<11> ? table 3: pin use summary (sheet 7 of 22) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4 for numbered notes on reset and sleep states.
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 43 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 m24 k22 gpio<70 > ico cz gpio<70> ? ldd<12> ? pd-0 note[1] note [3] ? ldd<12> ? l22 l20 gpio<71 > ico cz gpio<71> ? ldd<13> ? pd-0 note[1] note [3] ? ldd<13> ? n24 l21 gpio<72 > ico cz gpio<72> ? ldd<14> ? pd-0 note[1] note [3] ? ldd<14> ? m22 l22 gpio<73 > ico cz gpio<73> ? ldd<15> ? pd-0 note[1] note [3] ? ldd<15> ? r23 n22 gpio<74 > ico cz gpio<74> ? ? ? pd-0 note[1] note [3] ? l_fclk_rd ? p23 n20 gpio<75 > ico cz gpio<75> ? ? ? pd-0 note[1] note [3] ?l_lclk _a0? p22 n21 gpio<76 > ico cz gpio<76> ? ? ? pd-0 note[1] note [3] ?l_pclk_wr? r21 p21 gpio<77 > ico cz gpio<77> ? ? ? pd-0 note[1] note [3] ? l_bias ? n22 m20 gpio<86 > ico cz gpio<86> ssprxd2 ldd<16> usb_p3_5 pd-0 note[1] note [3] npce<1> ldd<16> ? n23 m22 gpio<87 > ico cz gpio<87> npce<2> ldd<17> usb_p3_1 pd-0 note[1] note [3] ssptxd2 ldd<17> sspsfrm 2 vcc_io c11 a8 gpio<11 > ico cz gpio<11> ext_sync<0 > ssprxd2 usb_p3_1 pd-0 note[1] note [3], note[11 chout<0> pwm_out2 48_mhz b10 a7 gpio<12 > ico cz gpio<12> ext_sync<1 > cif_dd<7> ? pd-0 note[1] note [3], note[11 chout<1> pwm_out3 48_mhz table 3: pin use summary (sheet 8 of 22) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4 for numbered notes on reset and sleep states.
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 44 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 c10 a6 gpio<13 > ico cz gpio<13> clk_ext kp_dkin<7> kp_mkin< 7> pd-0 note[1] note [3], note[11 ] ssptxd2 ? ? a18 c14 gpio<16 > ico cz gpio<16> kp_mkin<5> ? ? pd-0 note[1] note [3] ?pwm_out<0 > fftxd c16 d15 gpio<17 > ico cz gpio<17> kp_mkin<6> cif_dd<6> ? pd-0 note[1] note [3] ?pwm_out<1 > ? d13 a12 gpio<22 > ico cz gpio<22> sspextclk2 sspsclken2 sspsclk2 pd-0 note[1] note [3] kp_mkout<7 > sspsysclk2 sspsclk2 b16 a16 gpio<23 > ico cz gpio<23> ? sspsclk ? pd-0 note[1] note [3] cif_mclk sspsclk ? a17 b14 gpio<24 > ico cz gpio<24> cif_fv sspsfrm ? pd-0 note[1] note [3] cif_fv sspsfrm ? d16 a15 gpio<25 > ico cz gpio<25> cif_lv ? ? pd-0 note[1] note [3] cif_lv ssptxd ? b15 a14 gpio<26 > ico cz gpio<26> ssprxd cif_pclk ffcts pd-0 note[1] note [3] ??? c15 c13 gpio<27 > ico cz gpio<27> sspextclk sspsclken cif_dd<0 > pd-0 note[1] note [3] sspsysclk ? ffrts a14 d12 gpio<28 > ico cz gpio<28> ac97_bitclk i2s_bitclk sspsfrm pd-0 note[1] note [3] i2s_bitclk ? sspsfrm b13 a11 gpio<29 > ico cz gpio<29> ac97_sdata _in_0 i2s_sdata_i n sspsclk pd-0 note[1] note [3] ssprxd2 ? sspsclk table 3: pin use summary (sheet 9 of 22) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4 for numbered notes on reset and sleep states.
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 45 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 c13 b11 gpio<30 > ico cz gpio<30> ? ? ? pd-0 note[1] note [3] i2s_sdata_o ut ac97_sdata _out usb_p3_2 c12 c11 gpio<31 > ico cz gpio<31> ? ? ? pd-0 note[1] note [3] i2s_sync ac97_sync usb_p3_6 a20 c16 gpio<32 > ico cz gpio<32> ? ? ? pd-0 note[1] note [3] mssclk mmclk ? a21 b19 gpio<34 > ico cz gpio<34> ffrxd kp_mkin<3> sspsclk3 pd-0 note[1] note [3] usb_p2_2 ? sspsclk3 b19 d17 gpio<35 > ico cz gpio<35> ffcts usb_p2_1 sspsfrm 3 pd-0 note[1] note [3] ?kp_mkout< 6> ssptxd3 c14 b13 gpio<36 > ico cz gpio<36> ffdcd sspsclk2 kp_mkin< 7> pd-0 note[1] note [3] usb_p2_4 sspsclk2 ? a15 d13 gpio<37 > ico cz gpio<37> ffdsr sspsfrm2 kp_mkin< 3> pd-0 note[1] note [3] usb_p2_8 sspsfrm2 fftxd b14 a13 gpio<38 > ico cz gpio<38> ffri kp_mkin<4> usb_p2_3 pd-0 note[1] note [3] ssptxd3 ssptxd2 pwm_out <1> d19 b17 gpio<39 > ico cz gpio<39> kp_mkin<4> ? sspsfrm 3 pd-0 note[1] note [3] usb_p2_6 fftxd sspsfrm 3 d14 c12 gpio<40 > ico cz gpio<40> ssprxd2 ? usb_p2_5 pd-0 note[1] note [3] kp_mkout<6 > ffdtr sspsclk3 c18 a19 gpio<41 > ico cz gpio<41> ffrxd usb_p2_7 ssprxd3 pd-0 note[1] note [3] kp_mkout<7 > ffrts ? table 3: pin use summary (sheet 10 of 22) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4 for numbered notes on reset and sleep states.
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 46 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 c21 d20 gpio<42 > ico cz gpio<42> btrxd icp_rxd ? pd-0 note[1] note [3] ??cif_mclk c22 b21 gpio<43 > ico cz gpio<43> ? ? cif_fv pd-0 note[1] note [3] icp_txd bttxd cif_fv b20 a20 gpio<44 > ico cz gpio<44> btcts ? cif_lv pd-0 note[1] note [3] ??cif_lv c19 c17 gpio<45 > ico cz gpio<45> ? ? cif_pclk pd-0 note[1] note [3] ac97_syscl k btrts sspsysc lk3 b11 a9 gpio<46 > ico cz gpio<46> icp_rxd std_rxd ? pd-0 note[1] note [3] ?pwm_out<2 > ? a11 c10 gpio<47 > ico cz gpio<47> cif_dd<0> ? ? pd-0 note[1] note [3] std_txd icp_txd pwm_out <3> c23 c22 gpio<88 > ico cz gpio<88> usbhpwr<1 > ssprxd2 sspsfrm 2 pd-0 note[1] note [3] ? ? sspsfrm 2 d22 c21 gpio<89 > ico cz gpio<89> ssprxd3 ? ffri pd-0 note[1] note [3] ac97_syscl k usbhpen<1> ssptxd2 a19 a18 gpio<92 > ico cz gpio<92> mmdat<0> ? ? pd-0 note[1] note [3] mmdat<0> msbs ? ab19 y16 gpio<93 > ico cz gpio<93> kp_dkin<0> cif_dd<6> ? pd-0 note[1] note [3] ac97_sdata _out ?? ad19 aa17 gpio<94 > ico cz gpio<94> kp_dkin<1> cif_dd<5> ? pd-0 note[1] note [3] ac97_sync ? ? table 3: pin use summary (sheet 11 of 22) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4 for numbered notes on reset and sleep states.
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 47 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 aa18 ab18 gpio<95 > ico cz gpio<95> kp_dkin<2> cif_dd<4> kp_mkin< 6> pd-0 note[1] note [3] ac97_reset _n ?? ac19 w16 gpio<96 > ico cz gpio<96> kp_dkin<3> mbreq ffrxd pd-0 note[1] note [3] dval<1> kp_mkou t<6> aa17 y15 gpio<97 > ico cz gpio<97> kp_dkin<4> dreq<1> kp_mkin< 3> pd-0 note[1] note [3] ?mbgnt? ad18 aa16 gpio<98 > ico cz gpio<98> kp_dkin<5> cif_dd<0> kp_mkin< 4> pd-0 note [1] note [3] ac97_syscl k ? ffrts ab18 ab17 gpio<99 > ico cz gpio<99> kp_dkin<6> ac97_sdata _in_1 kp_mkin< 5> pd-0 note [1] note [3] ? ? fftxd ac18 aa15 gpio<10 0> ico cz gpio<100 > kp_mkin<0> dreq<2> ffcts pd-0 note[1] note [3] ??? ac17 ab16 gpio<10 1> ico cz gpio<101 > kp_mkin<1> ? ? pd-0 note[1] note [3] ??? ab17 y14 gpio<10 2> ico cz gpio<102 > kp_mkin<2> ? ffrxd pd-0 note[1] note [3] npce<1> ? ? ac16 ab15 gpio<10 3> ico cz gpio<103 > cif_dd<3> ? ? pd-0 note[1] note [3] ?kp_mkout< 0> ? ad15 w14 gpio<10 4> ico cz gpio<104 > cif_dd<2> ? ? pd-0 note[1] note [3] psktsel kp_mkout< 1> ? ab16 y13 gpio<10 5> ico cz gpio<105 > cif_dd<1> ? ? pd-0 note[1] note [3] npce<2> kp_mkout< 2> ? table 3: pin use summary (sheet 12 of 22) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4 for numbered notes on reset and sleep states.
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 48 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 ab15 w13 gpio<10 6> ico cz gpio<106 > cif_dd<9> ? ? pd-0 note[1] note [3] ?kp_mkout< 3> ? ac15 ab14 gpio<10 7> ico cz gpio<107 > cif_dd<8> ? ? pd-0 note[1] note [3] ?kp_mkout< 4> ? ad14 aa13 gpio<10 8> ico cz gpio<108 > cif_dd<7> ? ? pd-0 note[1] note [3] chout<0> kp_mkout< 5> ? d17 d16 gpio<10 9> ico cz gpio<109 > mmdat<1> mssdio ? pd-0 note[1] note [3] mmdat<1> mssdio ? b17 c15 gpio<11 0> ico cz gpio<110 > mmdat<2>/m mccs<0> ??pd-0 note[1] note [3] mmdat<2>/m mccs<0> ?? c17 a17 gpio<11 1> ico cz gpio<111 > mmdat<3>/m mccs<1> ??pd-0 note[1] note [3] mmdat<3>/m mccs<1> ?? b18 b16 gpio<11 2> ico cz gpio<112 > mmcmd nmsins ? pd-0 note[1] note [3] mmcmd ? ? a13 a10 gpio<11 3> ico cz gpio<113 > ? ? usb_p3_3 pd-0 note[1] note [3] i2s_sysclk ac97_reset _n ? d24 f19 gpio<11 4> note [17] ico cz gpio<114 > note [17] cifdd_<1> ? ? pd-0 note[1] note [3] uvs0 ? e21 e21 gpio<11 5> note [17] ico cz gpio<115 > note [17] dreq<0> cif_dd<3> mbreq pu-1 note[1] note [3] uen nuvs1 pwm_out <1> table 3: pin use summary (sheet 13 of 22) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4 for numbered notes on reset and sleep states.
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 c24 e20 gpio<11 6> ico cz gpio<116 > cif_dd<2> ac97_sdata _in_0 udet pu-1 note[1] note [3] dval<0> nuvs2 mbgnt d20 c18 gpio<11 7> ico cz gpio<117 > scl ? ? pu-1 note[1] note [3], note[1 2] scl ? ? a22 b20 gpio<11 8> ico cz gpio<118 > sda ? ? pu-1 note[1] note [3], note[1 2] sda ? ? vcc_usb b22 d18 usbc_p iao az usbc_p usbc_p ? ? hi-z hi-z c20 e19 usbc_n iao az usbc_n usbc_n ? ? hi-z hi-z e22 e22 usbh_p <1> iao az usbh_p< 1> usbh_p<1> ? ? hi-z hi-z d23 d22 usbh_n <1> iao az usbh_n< 1> usbh_n<1> ? ? hi-z hi-z vcc_usim f22 h19 gpio<90 > ico cz gpio<90> kp_mkin<5> usb_p3_5 cif_dd<4 > pd-0 note[1] note [3] ? nurst ? f23 g19 gpio<91 > ico cz gpio<91> kp_mkin<6> usb_p3_1 cif_dd<5 > pd-0 note[1] note [3] ?uclk? e23 f20 uio ico cz uio uio ? ? driven low hi-z vcc_reg v22 u20 gpio<0> ico cz gpio<0> gpio<0> ? ? pd-0 note[1] note [3] y24 u21 gpio<1> ico cz gpio<1> gpio<1> ? ? pu-1 note[1] note [7] table 3: pin use summary (sheet 14 of 22) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4 for numbered notes on reset and sleep states.
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 50 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 w21 v22 gpio<3> ico cz gpio<3> pwr_scl ? ? pu-1 note[1] hi-z w23 t19 gpio<4> ico cz gpio<4> pwr_sda ? ? pu-1 note[1] hi-z u22 t22 gpio<9> note [18] ico cz gpio<9> note [18] ??ffcts pd-0 note[1] note [7] hz_clk ? chout<0 > v23 u22 gpio<10 > note [18] ico cz gpio<10> note [18] ffdcd ? usb_p3_5 pd-0 note[1] note [7] hz_clk ? chout<1 > pd-0 note[1] note [7] w24 t21 clk_re q ico cz clk_req clk_req ? ? pu-1 note [8] y22 w20 nreset ic nreset nreset ? ? input - note [9] input y21 w21 nreset _out oc nreset_ out nreset_out ? ? low note [8] ab23 v19 boot_s el ic boot_se l boot_sel ? ? input input y23 w22 pwr_e n oc pwr_en pwr_en ? ? note[16] note [8] ab24 u19 nbatt_ fault ic nbatt_fa ult nbatt_fault ? ? low input w22 v20 nvdd_f ault ic nvdd_fa ult nvdd_fault ? ? low input aa24 v21 sys_en ico cz sys_en sys_en ? ? ? note [7] ab21 y19 pwr_c ap<0> oa ? pwr_cap<0> ? ? ? note [7] ad22 aa21 pwr_c ap<1> oa ? pwr_cap<1> ? ? ? note [7] ac22 y18 pwr_c ap<2> oa ? pwr_cap<2> ? ? ? note [7] table 3: pin use summary (sheet 15 of 22) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4 for numbered notes on reset and sleep states.
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 aa20 w17 pwr_c ap<3> oa ? pwr_cap<3> ? ? ? note [7] u21 t20 ntrst ic ntrst ntrst ? ? input - note [9] input u23 r22 tdi ic tdi tdi ? ? input - note [9] input v24 r21 tdo ocz tdo tdo ? ? hi-z hi-z t21 r20 tms ic tms tms ? ? input - note [9] input t22 r19 tck ic tck tck ? ? input input t23 p22 testcl k ic testclk testclk ? ? pd-0 input vcc_osc ac21 ab20 pxtal_i n ia pxtal_in pxtal_in ? ? note[2] note [2] ad21 aa20 pxtal_ out oa pxtal_o ut pxtal_out ? ? note[2] note [2] aa22 y21 txtal_i n ia txtal_in txtal_in ? ? note[2] note [2] aa23 y22 txtal_ out oa txtal_ou t txtal_out ? ? note[2] note [2] ab22 w19 pwr_o ut oa pwr_out pwr_out ? ? hi-z hi-z supplies ab20 y17 vcc_ba tt ps vcc_bat t vcc_batt ? ? input input a12 b10 vcc_io ps vcc_io vcc_io ? ? input input ad17 w15 vcc_io ps vcc_io vcc_io ? ? input input a16 d14 vcc_io ps vcc_io vcc_io ? ? input input b24 a21 vcc_us b ps vcc_usb vcc_usb ? ? input input a24 a22 vcc_us b ps vcc_usb vcc_usb ? ? input input table 3: pin use summary (sheet 16 of 22) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4 for numbered notes on reset and sleep states.
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 52 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 a23 b22 vcc_us b ps vcc_usb vcc_usb ? ? input input b23 d19 vcc_us b ps vcc_usb vcc_usb ? ? input input p24 m19 vcc_lc d ps vcc_lcd 0 vcc_lcd ? ? input input j24 j21 vcc_lc d ps vcc_lcd 1 vcc_lcd ? ? input input p1 b2 vcc_me m ps vcc_mem vcc_mem ? ? input input c3 c3 vcc_me m ps vcc_mem vcc_mem ? ? input input e2 c6 vcc_me m ps vcc_mem vcc_mem ? ? input input l3 c9 vcc_me m ps vcc_mem vcc_mem ? ? input input ad2 f3 vcc_me m ps vcc_mem vcc_mem ? ? input input ac2 h3 vcc_me m ps vcc_mem vcc_mem ? ? input input ac1 k3 vcc_me m ps vcc_mem vcc_mem ? ? input input ad1 m3 vcc_me m ps vcc_mem vcc_mem ? ? input input m1 p3 vcc_me m ps vcc_mem vcc_mem ? ? input input h1 t3 vcc_me m ps vcc_mem vcc_mem ? ? input input f1 v3 vcc_me m ps vcc_mem vcc_mem ? ? input input ad8 y3 vcc_me m ps vcc_mem vcc_mem ? ? input input u2 y5 vcc_me m ps vcc_mem vcc_mem ? ? input input table 3: pin use summary (sheet 17 of 22) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4 for numbered notes on reset and sleep states.
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 53 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 aa2 y7 vcc_me m ps vcc_mem vcc_mem ? ? input input ac8 y9 vcc_me m ps vcc_mem vcc_mem ? ? input input b8 aa2 vcc_me m ps vcc_mem vcc_mem ? ? input input a4 n/a vcc_me m ps vcc_mem vcc_mem ? ? input input ac6 n/a vcc_me m ps vcc_mem vcc_mem ? ? input input w2 n/a vcc_me m ps vcc_mem vcc_mem ? ? input input ad12 aa11 vcc_bb ps vcc_bb vcc_bb ? ? input input ac20 ab19 vcc_pl l ps vcc_pll vcc_pll ? ? input input a9 b4 vcc_sr am ps vcc_sra m vcc_sram ? ? input input a8 b7 vcc_sr am ps vcc_sra m vcc_sram ? ? input input a5 b8 vcc_sr am ps vcc_sra m vcc_sram ? ? input input b4 c5 vcc_sr am ps vcc_sra m vcc_sram ? ? input input b12 d11 vcc_co re ps vcc_cor e vcc_core ? ? input input a7 e6 vcc_co re ps vcc_cor e vcc_core ? ? input input d3 e8 vcc_co re ps vcc_cor e vcc_core ? ? input input j23 f5 vcc_co re ps vcc_cor e vcc_core ? ? input input l24 h5 vcc_co re ps vcc_cor e vcc_core ? ? input input table 3: pin use summary (sheet 18 of 22) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4 for numbered notes on reset and sleep states.
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 54 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 f24 l4 vcc_co re ps vcc_cor e vcc_core ? ? input input ad16 e15 vcc_co re ps vcc_cor e vcc_core ? ? input input r24 e17 vcc_co re ps vcc_cor e vcc_core ? ? input input m23 f18 vcc_co re ps vcc_cor e vcc_core ? ? input input b21 h18 vcc_co re ps vcc_cor e vcc_core ? ? input input w3 l19 vcc_co re ps vcc_cor e vcc_core ? ? input input ad4 r5 vcc_co re ps vcc_cor e vcc_core ? ? input input t2 u5 vcc_co re ps vcc_cor e vcc_core ? ? input input ad11 v6 vcc_co re ps vcc_cor e vcc_core ? ? input input n/a v8 vcc_co re ps vcc_cor e vcc_core ? ? input input n/a w11 vcc_co re ps vcc_cor e vcc_core ? ? input input n/a r18 vcc_co re ps vcc_cor e vcc_core ? ? input input n/a u18 vcc_co re ps vcc_cor e vcc_core ? ? input input n/a v15 vcc_co re ps vcc_cor e vcc_core ? ? input input n/a v17 vcc_co re ps vcc_cor e vcc_core ? ? input input e24 f21 vcc_us im ps vcc_usi m vcc_usim ? ? input input aa21 w18 vss ps vss vss ? ? input input ac24 y20 vss ps vss vss ? ? input input table 3: pin use summary (sheet 19 of 22) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4 for numbered notes on reset and sleep states.
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 55 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 ad24 aa22 vss ps vss vss ? ? input input ac23 ab21 vss ps vss vss ? ? input input ad23 ab22 vss ps vss vss ? ? input input v21 n/a vss ps vss vss ? ? input input d11 b12 vss_io ps vss_io vss_io ? ? input input aa19 b15 vss_io ps vss_io vss_io ? ? input input d15 b18 vss_io ps vss_io vss_io ? ? input input n21 d21 vss_io ps vss_io vss_io ? ? input input aa16 h21 vss_io ps vss_io vss_io ? ? input input h21 m21 vss_io ps vss_io vss_io ? ? input input f21 n19 vss_io ps vss_io vss_io ? ? input input d18 aa14 vss_io ps vss_io vss_io ? ? input input u24 aa18 vss_io ps vss_io vss_io ? ? input input d5 a1 vss_me m ps vss_mem vss_mem ? ? input input f4 a2 vss_me m ps vss_mem vss_mem ? ? input input h4 b1 vss_me m ps vss_mem vss_mem ? ? input input j4 b3 vss_me m ps vss_mem vss_mem ? ? input input ac3 b6 vss_me m ps vss_mem vss_mem ? ? input input ab2 b9 vss_me m ps vss_mem vss_mem ? ? input input l4 f2 vss_me m ps vss_mem vss_mem ? ? input input t4 h2 vss_me m ps vss_mem vss_mem ? ? input input v4 l2 vss_me m ps vss_mem vss_mem ? ? input input table 3: pin use summary (sheet 20 of 22) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4 for numbered notes on reset and sleep states.
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 56 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 aa5 p2 vss_me m ps vss_mem vss_mem ? ? input input aa8 t2 vss_me m ps vss_mem vss_mem ? ? input input aa9 v2 vss_me m ps vss_mem vss_mem ? ? input input d9 aa1 vss_me m ps vss_mem vss_mem ? ? input input n4 aa6 vss_me m ps vss_mem vss_mem ? ? input input r2 aa9 vss_me m ps vss_mem vss_mem ? ? input input c5 ab1 vss_me m ps vss_mem vss_mem ? ? input input y4 ab2 vss_me m ps vss_mem vss_mem ? ? input input aa13 ab11 vss_bb ps vss_bb vss_bb ? ? input input ad20 aa19 vss_pl l ps vss_pll vss_pll ? ? input input b2 e5 vss_co re ps vss_cor e vss_core ? ? input input a2 e7 vss_co re ps vss_cor e vss_core ? ? input input b1 e9 vss_co re ps vss_cor e vss_core ? ? input input a1 g5 vss_co re ps vss_cor e vss_core ? ? input input j21 j5 vss_co re ps vss_cor e vss_core ? ? input input d10 e14 vss_co re ps vss_cor e vss_core ? ? input input aa15 e16 vss_co re ps vss_cor e vss_core ? ? input input table 3: pin use summary (sheet 21 of 22) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4 for numbered notes on reset and sleep states.
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 57 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 m21 e18 vss_co re ps vss_cor e vss_core ? ? input input u3 g18 vss_co re ps vss_cor e vss_core ? ? input input aa7 j18 vss_co re ps vss_cor e vss_core ? ? input input p21 p5 vss_co re ps vss_cor e vss_core ? ? input input k21 t5 vss_co re ps vss_cor e vss_core ? ? input input g21 v5 vss_co re ps vss_cor e vss_core ? ? input input d21 v7 vss_co re ps vss_cor e vss_core ? ? input input d12 v9 vss_co re ps vss_cor e vss_core ? ? input input d8 p18 vss_co re ps vss_cor e vss_core ? ? input input w4 t18 vss_co re ps vss_cor e vss_core ? ? input input aa12 v14 vss_co re ps vss_cor e vss_core ? ? input input b5 v16 vss_co re ps vss_cor e vss_core ? ? input input d7 v18 vss_co re ps vss_cor e vss_core ? ? input input table 3: pin use summary (sheet 22 of 22) vf-bga ball# (13x13) pbga ball# (23x23) name type function after reset primary function secondary alternate function third alternate function reset state sleep state note: refer to table 4 for numbered notes on reset and sleep states.
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 58 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 4.3 signal types table 4: pin use and mapping notes (sheet 1 of 2) note description [1] gpio reset/deep sleep operation: after any reset is asserted or if the pxa270 processor is in deep sleep mode, these pins are configured as gpio inputs by default. the input buffers for these pins are disabled to prevent current drain and must be enabled prior to use by clearing the read disable hold bit, pssr[rdh]. until rdh is cleared, each pin is pulled high (pu-1), pulled low (pd-0), or floated (hi-z). [2] crystal oscillator pins: these pins connect the external crystals to the on-chip oscillators and are not affected by either reset or sleep. for more information, see the ?clocks and power? chapter in the marvell? pxa27x processor family developer?s manual . [3] gpio sleep operation: during the transition into sleep mode, the configuration of these pins is determined by the corresponding gpio setting. this pin is not driven during sleep if the direction of the pin is selected to be an input. if the direction of the pin is selected as an output, the value contained in the power manager gpio sleep-state register (pgsr0/1/2/3) is driven out onto the pin and held while the pxa270 processor is in sleep mode. upon exit from sleep mode, gpios that are configured as outputs continue to hold the standby, sleep, or deep-sleep state until software clears the peripheral control hold bit, pssr[ph]. software must clear this bit (by writing 0b1 to it) after the peripherals have been fully configured, as described in note[1], but before the process actually uses them. gpios that are configured as inputs immediately after exiting sleep mode cannot be used until pssr[rdh] is cleared. [4] static memory control pins: during sleep mode, these pins can be programmed either to drive the value in the power manager gpio sleep-state register (pgsr0/1/2/3) or to be placed in a hi-z (undriven) state. to select the hi-z state, software must set pcfr[fs]. if fs is not set, these pins function as described in note[3] during the transition to sleep mode. [5] pcmcia control pins: during sleep mode, these pins can be programmed either to drive the value in the power manager gpio sleep-state register (pgsr0/1/2/3) or to be placed in a hi-z (undriven) state. to select the hi-z state, software must set pcfr[fp]. if fp is not set, these pins function as described in note[3] during the transition to sleep mode. [6] (reserved) [7] when the power manager overrides the gpio alternate function, the power manager gpio sleep-state registers (pgsr0/1/2/3) and the pssr[rdh] bit are ignored. pullup and pulldown are disabled immediately after the power manager overrides the gpio function. [8] output functions during sleep mode [9] pull-up always enabled [10] (reserved) [11] pins do not function during sleep mode if the os timer is active [12] pins must be floated by software during sleep mode (floating does not happen automatically) [13] (reserved) [14] (reserved) [15] the pin is three-stateable (hi-z) based on the value of pcfr[fs]. there is no pgsr0/1/2/3 setting associated with the pin because it is not a gpio. [16] pwr_en goes high during reset, between the assertion of the reset pin and the de-assertion of internal reset within the pxa270 processor, after sys_en is driven high.
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 59 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 4.4 memory controller reset and initialization on reset, the sdram interface is disabled. reset values for the boot rom are determined by boot_sel (see the marvell? pxa27x processor family developers manual , memory controller chapter). boot rom is immediately available for reading upon exit from reset, and all memory interface control registers are available for writing. on hardware reset, the memory pins and controller are in the state shown in tab l e 6 . [17] gpios 114 and115: the alternate function configuration of these pins is ignored when either pucr[usim114] or pucr[usim115] bits are set. setting these bits forces the usim enable signal onto these gpios. [18] when software sets the oscc[pio_en] or oscc[tout_en] bits, then any gpio alternate function setting applied to gpio<9> or gpio <10> is overridden with the clk_pio function on gpio<9> and clk_tout on gpio<10>. [19] refer to table 6 . table 5: signal types type description ic cmos input oc cmos output ocz cmos output, three-stateable icocz cmos bidirectional, three-stateable ia analog input oa analog output iaoa analog bidirectional iaoaz analog bidirectional - three-stateable ps power supply table 4: pin use and mapping notes (sheet 2 of 2) note description table 6: memory controller pin reset values (sheet 1 of 2) pin name reset, sleep, standby, deep-sleep, frequency change, and manual self-refresh mode values sdclk <3 1 :0> 0b000 sdcke 0 dqm <3:0> 0b0000 nsdcs <3:2> gpio (memory controller drives 0b11) ? nsdcs <1:0> 0b11 nwe 1 nsdras 1 nsdcas 1 noe 1
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 60 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 the address signals are driven low and data signals are pulled low during sleep, standby, deep-sleep, frequency-change modes, and manual self-refresh. all other memory control signals are in the same state that they are in after a hardware reset. if the sdrams are in self-refresh mode, they are kept there by driving sdcke low. 4.5 power-supply pins table 7 summarize the power-supply ball count. ma <25:0> 0x0000_0000 1 rdnwr 0 md <31:0> 0x0000_0000 2 ncs <0> 1 ncs <5:1> gpio (memory controller drives 0b11111) npioir gpio (memory controller drives high) npioiw gpio (memory controller drives high) npoe gpio (memory controller drives high) npwe gpio (memory controller drives high) note: ? this indicates that the gpio pin, if configured for the alternate function used by the memory controller during reset, drives the represented value. note: sclk<3> is only available on pxa270 processor family packages 1. ma pins are driven 2. md pins are pulled low table 6: memory controller pin reset values (sheet 2 of 2) pin name reset, sleep, standby, deep-sleep, frequency change, and manual self-refresh mode values table 7: discrete (13x13 vf-bga) powe r supply pin summary (sheet 1 of 2) name number of package balls 13x13 mm vf-bga number of pachage balls 23x23 mm pbga vcc_batt 1 1 vcc_io 3 3 vcc_usb 4 4 vcc_lcd 2 2 vcc_mem 19 16 vcc_bb 1 1 vcc_pll 1 1 vcc_sram 4 4 vcc_core 14 20 vcc_usim 1 1 vss 6 5
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 vss_io 9 9 vss_mem 17 17 vss_bb 1 1 vss_pll 1 1 vss_core 56 56 table 7: discrete (13x13 vf-bga) powe r supply pin summary (sheet 2 of 2) name number of package balls 13x13 mm vf-bga number of pachage balls 23x23 mm pbga
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 62 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 63 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 5 electrical specifications 5.1 absolute maximum ratings the absolute maximum ratings (shown in table 8 ) define limitations for electrical and thermal stresses. these limits prevent permanent damage to the marvell? pxa270 processor. note note absolute maximum ratings are not operating ranges. table 8: absolute maximum ratings symbol description min max units t s storage temperature ?40 125 c v cc_ol1 offset voltage between any of the following pins: vcc_core ?0.3 0.3 v v cc_ol2 offset voltage between any of the following pins: vcc_sram ?0.3 0.3 v v cc_oh1 offset voltage between any of the following pins: vcc_mem ?0.3 0.3 v v cc_oh2 offset voltage between any of the following pins: vcc_io ?0.3 0.3 v v cc_oh3 offset voltage between vcc_lcd<0> and vcc_lcd<1> ?0.3 0.3 v v cc_hv voltage applied to high-voltage supply pins (vcc_bb, vcc_usb, vcc_usim, vcc_mem, vcc_io<, vcc_lcd) vss?0.3 vss+4.0 v v cc_lv voltage applied to low-voltage supply pins (vcc_core, vcc_pll, vcc_sram) vss?0.3 vss+1.45 v v ip voltage applied to non-supply pins except pxtal_in, pxtal_out, txtal_in, and txtal_out pins vss?0.3 vss+4.0 v v ip_x voltage applied to xtal pins (pxtal_in, pxtal_out, txtal_in, txtal_out) vss?0.3 vss+1.45 v v esd maximum esd stress voltage, three stresses maximum: any pin to any supply pin, either polarity, or any pin to all non-supply pins together, either polarity ? 2000 v i eos maximum dc input current (electrical overstress) for any non-supply pin ? 5 ma
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 64 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 5.2 operating conditions this section shows operating voltage, frequency, and temperature specifications for the pxa270 processor. table 9 shows each power domains supported voltages (except for vcc_mem and vcc_core). table 10 shows all of the supported memory voltages and frequency operating ranges (vcc_mem). table shows all of the supported core voltage and frequency ranges (vcc_core). the operating temperature specification is a function of voltage and frequency. table 9: voltage, temperature, and frequency electrical specifications (sheet 1 of 3) symbol description min typical max units operating temperature tc a s e package operating temperature ? (standard temp) -25 ? +85 c package operating temperature ? (extended temp - pbga only) -40 ? +85 theta jc junction-to-case temperature gradient (vf-bga) ? 2 ? c / watt junction-to-case temperature gradient (pbga) ? 1.4 ? vcc_batt voltage vvcc0 voltage applied on vcc_batt @3.0v 2.40 3.00 3.75 v vvdf1 voltage difference between vcc_batt and vcc_io during power-on reset or deep-sleep wake-up (from the assertion of sys_en to the de-assertion of nreset_out) 0 ? 0.30 v vvdf2 voltage difference between vcc_batt and vcc_io when vcc_io is enabled 0 ? 0.20 v tbramp ramp rate ? 10 12 mv/ s vcc_pll voltage vvcc1 voltage applied on vcc_pll @1.3v (+10 / -10%) 1.17 1.30 1.43 v tpwrramp ramp rate ? 10 12 mv/ s vcc_bb voltages vvcc2a voltage applied on vcc_bb @1.8v (+20 / -5%) 1.71 1.80 2.16 v vvcc2b voltage applied on vcc_bb @2.5v (+10 / -10%) 2.25 2.50 2.75 v vvcc2c voltage applied on vcc_bb @3.0v (+10 / -10%) 2.70 3.0 3.30 v vvcc2d voltage applied on vcc_bb @3.3v (+10 / -10%) 2.97 3.3 3.63 v tsysramp ramp rate ? 10 12 mv/ s
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 65 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 vcc_bb may optionally be tied to the same pmic regulator as vcc_io if the system design allows both vcc_io and vcc_bb to use the same voltage level. this allows the gpio?s on vcc_bb to be used at the same voltage level. vcc_lcd voltages vvcc3a voltage applied on vcc_lcd @1.8v (+20 / -5%) 1.71 1.80 2.16 v vvcc3b voltage applied on vcc_lcd @2.5v (+10 / -10%) 2.25 2.50 2.75 v vvcc3c voltage applied on vcc_lcd @3.0v (+10 / -10%) 2.70 3.0 3.30 v vvcc3d voltage applied on vcc_lcd @3.3v (+10 / -10%) 2.97 3.3 3.63 v tsysramp ramp rate ? 10 12 mv/ s vcc_io voltages vvcc4a voltage applied on vcc_io @3.0v (+10 / -10.3%) 2.69175 3.0 3.30 v vvcc4b voltage applied on vcc_io @3.3v (+10 / -10%) 2.97 3.3 3.63 v tsysramp ramp rate ? 10 12 mv/ s vcc_io must be maintained at a voltage as high as or higher than, all other supplies except for vcc_batt and vcc_usb vcc_usim voltages vvcc5a voltage applied on vcc_usim @1.8v (+20 / -5%) 1.71 1.80 2.16 v vvcc5b voltage applied on vcc_usim @3.0v (+10 / -10%) 2.70 3.0 3.30 v tsysramp ramp rate ? 10 12 mv/ s if the system does not use the usim module, vcc_usim can be tied to vcc_io (at any supported vcc_io voltage level). this allows the gpio?s on vcc_usim to be used at the same voltage level as vcc_io gpio?s. note: software must not configure usim signals to be used if this is done. vcc_sram voltage vvcc6 voltage applied on vcc_sram @1.1v (+10 / -10%) 0.99 1.10 1.21 v tpwrramp ramp rate ? 10 12 mv/ s vcc_usb voltage vvcc7a voltage applied on vcc_usb @3.0v (+10 / -10%) 2.70 3.00 3.30 v table 9: voltage, temperature, and frequency electrical specifications (sheet 2 of 3) symbol description min typical max units
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 66 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 table 10 shows the supported memory frequency and memory supply voltage operating ranges for the pxa270 processor. table 10: memory voltage and frequency electrical specifications table 11 shows the supported core frequency and core supply voltage operating ranges for the pxa270 processor. each frequency range is specified in the following format: vvcc7b voltage applied on vcc_usb @3.3v (+10 / -10%) 2.97 3.30 3.63 v tsysramp ramp rate ? 10 12 mv/ s ? system design must ensure that the device case temperature is maintained within the specified limits. in some system applications it may be necessary to use external thermal management (for example, a package-mounted heat spreader) or configure the device to limit power consumption and maintain acceptable case temperatures. table 9: voltage, temperature, and frequency electrical specifications (sheet 3 of 3) symbol description min typical max units symbol description min typical max units memory voltage and frequency range 1 vmem1 voltage applied on vcc_mem 1.71 1.80 2.16 v fsm1a external synchronous memory frequency, sdclk1, sdclk2 13 ? 104 mhz fsm1b external synchronous memory frequency, sdclk0 13 ? 104 mhz ts y s r a m p ramp rate ? 10 12 mv/ s memory voltage and frequency range 2 vmem2 voltage applied on vcc_mem 2.25 2.50 2.75 v fsm2a external synchronous memory frequency, sdclk1, sdclk2 13 ? 104 mhz fsm2b external synchronous memory frequency, sdclk0 13 ? 104 mhz ts y s r a m p ramp rate ? 10 12 mv/ s memory voltage and frequency range 3 vmem3 voltage applied on vcc_mem 2.70 3.0 3.3 v fsm3a external synchronous memory frequency, sdclk1, sdclk2 13 ? 104 mhz fsm3b external synchronous memory frequency, sdclk0 13 ? 104 mhz ts y s r a m p ramp rate ? 10 12 mv/ s memory voltage and frequency range 4 vmem4 voltage applied on vcc_mem 2.97 3.30 3.63 v fsm4a external synchronous memory frequency, sdclk1, sdclk2 13 ? 104 mhz fsm4b external synchronous memory frequency, sdclk0 13 ? 104 mhz tsysramp ramp rate ? 10 12 mv/ s
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 67 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 (core frequency/internal system bus frequency/ memory controller frequency/sdram frequency) note note refer to the ?clocks and power? section of the marvell? pxa27x processor family developers manual for supported frequencies, clock register settings as listed in table 11 . table 11: core voltage and frequency electrical specifications (sheet 1 of 2) symbol description min typical max units core voltage and frequency range 1 (13/ 13/13/13 cccr[cpdis]=1, cccr[ppdis]=1) vvccc1 voltage applied on vcc_core 0.95 1.0 1.705 v fcore1 core operating frequency 13 ? 13 mhz tpwrramp ramp rate ? 10 12 mv/ s core voltage and frequency range 2 (13/13/13/13 cccr[cpdis]=1, cccr[ppdis]=0), (91/45.5/91/45.5), and (104/104/104/104) vvccc2 voltage applied on vcc_core 0.95 1.0 1.705 v fcore2 core operating frequency 91 ? 104 mhz tpwrramp ramp rate ? 10 12 mv/ s core voltage and frequency range 3 (156/104/104/104) vvccc3 voltage applied on vcc_core 0.95 1.00 1.705 v fcore3 core operating frequency ? 156 ? mhz tpwrramp ramp rate ? 10 12 mv/ s core voltage and frequency range 4 (208/208/208/104) and (208/208/104/104) vvccc4 voltage applied on vcc_core 1.12 1.18 1.705 v fcore4 core operating frequency ? 208 ? mhz tpwrramp ramp rate ? 10 12 mv/ s core voltage and frequency range 4a (208/104/104/104) vvccc4a voltage applied on vcc_core 0.9975 1.05 1.705 v fcore4a core operating frequency ? 208 ? mhz tpwrramp ramp rate ? 10 12 mv/ s core voltage and frequency range 5 (312/208/208/104) and (312/208/104/104) vvccc5 voltage applied on vcc_core 1.1875 1.25 1.705 v fcore5 core operating frequency ? 312 ? mhz tpwrramp ramp rate ? 10 12 mv/ s core voltage and frequency range 5a (312/104/104/104) vvccc5a voltage applied on vcc_core 0.99 1.1 1.705 v fcore5a core operating frequency ? 312 ? mhz tpwrramp ramp rate ? 10 12 mv/ s
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 68 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 5.2.1 internal power domains the external power supplies are used to generate several internal power domains, which are shown in table 12 . refer to the power manager / internal power domain block diagram in the ?clocks and power? section of the marvell? pxa27x processor family developers manual for more information on internal power domains. table 12: internally generated power domain descriptions table 13 shows the recommended core voltage specification for each of the lower power modes. table 13: core voltage specifications for lower power modes core voltage and frequency range 6 (416/208/208/104) amd (416/208/104/104) vvccc6 voltage applied on vcc_core 1.2825 1.35 1.705 v fcore6 core operating frequency ? 416 ? mhz tpwrramp ramp rate ? 10 12 mv/ s core voltage and frequency range 7 (520/208/208/104) and (520/208/104/104) vvccc7 voltage applied on vcc_core 1.3775 1.45 1.705 v fcore7 core operating frequency ? 520 ? mhz tpwrramp ramp rate ? 10 12 mv/ s core voltage and frequency range 8 (624/208/208/104) and (624/208/104/104) vvccc8 voltage applied on vcc_core 1.4725 1.55 1.705 v fcore8 core operating frequency ? 624 ? mhz tpwrramp ramp rate ? 10 12 mv/ s ?core operating frequency not offered in pbga package. table 11: core voltage and frequency electrical specifications (sheet 2 of 2) name units generation tolerance vcc_reg io associated with deep-sleep-active units switched between vcc_batt and vcc_io - vcc_osc oscillator power supplie s generated from vcc_reg +/- 30% vcc_rtc rtc and power manager supply switched between vcc_osc and vcc_core - vcc_pi power manager i 2 c supply switched between vcc_osc and vcc_core - vcc_cpu cpu core independent power-down from vcc_core - vcc_per peripheral units independent power-down from vcc_core - vcc_rx particular internal sram unit switched between vcc_osc and vcc_sram - mode description min typical max units standby voltage applied on vcc_core 1.045 1.1 1.21 v deep-idle voltage applied on vcc_core 0.95 1.0 1.705 v
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 69 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 5.3 power-consumption specifications power consumption depends on the operating voltage and frequency, peripherals enabled, external switching activity, and external loading and other factors. use these specifications as a guideline for power consumption capacity. these typical guidelines vary across different platforms and software applications. table 14 contains three sets of power consumption information: active power consumption , idle power consumption , and low-power modes power consumption . the data set are projected numbers based off of measured data at room temperature. for active power consumption data, no peripherals are enabled except for uart. table 15 contains idle and low power mode maximum power consumption information based on experimental and manufacturing test limits. table 14: typical power-consumption specifications (sheet 1 of 4) parameter description typical units conditions active power consumption 624 mhz active power (208 mhz system bus) 925 mw vcc_core = 1.55v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v 520 mhz active power (208 mhz system bus) 747 mw vcc_core = 1.45v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v 416 mhz active power (208 mhz system bus) 570 mw vcc_core = 1.35v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v 312 mhz active power (208 mhz system bus) 390 mw vcc_core = 1.25v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v 312 mhz active power (104 mhz system bus) 375 mw vcc_core = 1.1v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 70 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 208 mhz active power (208 mhz system bus) 279 mw vcc_core = 1.15v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v 104 mhz active power (104 mhz system bus) 116 mw vcc_core = 0.9v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v 13 mhz active power (cccr[cpdis=1) 44.2 mw vcc_core = 0.85v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v idle power consumption 624 mhz idle power (208 mhz system bus) 260 mw vcc_core = 1.55v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v 520 mhz idle power (208 mhz system bus) 222 mw vcc_core = 1.45v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v 416 mhz idle power (208 mhz system bus) 186 mw vcc_core = 1.35v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v 312 mhz idle power (208 mhz system bus) 154 mw vcc_core = 1.25v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v table 14: typical power-consumption specifications (sheet 2 of 4) parameter description typical units conditions
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 71 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 312 mhz idle power (104 mhz system bus) 109 mw vcc_core = 1.1v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v 208 mhz idle power (208 mhz system bus) 129 mw vcc_core = 1.15v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v 104 mhz idle power (104 mhz system bus) 64 mw vcc_core = 0.9v vcc_sram = 1.1v vcc_pll = 1.3v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v low power modes power consumption 13 mhz idle mode 1 power (lcd on) 15.4 mw vcc_core, vcc_sram, vcc_pll = 0.85v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v 13 mhz idle mode 1 power (lcd off) 8.5 mw vcc_core, vcc_sram, vcc_pll = 0.85v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v deep-sleep mode 0.1014 mw vcc_core, vcc_sram, vcc_pll = 0v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v table 14: typical power-consumption specifications (sheet 3 of 4) parameter description typical units conditions
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 72 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 table 15: maximum idle and low power mode power-consumption specifications sleep mode 0.1630 mw vcc_core, vcc_sram, vcc_pll = 0v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v standby mode 1.7224 mw vcc_core, vcc_sram, vcc_pll = 1.1v vcc_mem, vcc_bb, vcc_usim, vcc_lcd = 1.8v vcc_io, vcc_batt, vcc_usb= 3.0v note: 1) 13 mhz idle mode (cccr[cpdis] =1 (cccr[ppdis] = 1) table 14: typical power-consumption specifications (sheet 4 of 4) parameter description typical units conditions parameter description maximum units conditions idle mode power consumption 624mhz idle current on vcc_core (px=208mhz) 770 ma te m p = 8 5 c tc a s e , vcc_core=vcc_sram=vc c_pll=1.705v, vcc_peri 1 =3.63v, vcc_io=3.63v, vcc_batt=3.75v 520mhz idle current on vcc_core (px=208mhz) 630 ma te m p = 8 5 c tc a s e , vcc_core=vcc_sram=vc c_pll=1.595v, vcc_peri=3.63v, vcc_io=3.63v, vcc_batt=3.75v 416mhz idle current on vcc_core (px=208mhz) 500 ma te m p = 8 5 c tc a s e , vcc_core=vcc_sram=vc c_pll=1.485v, vcc_peri=3.63v, vcc_io=3.63v, vcc_batt=3.75v 312mhz idle current on vcc_core (px=208mhz) 380 ma te m p = 8 5 c tc a s e , vcc_core=vcc_sram=vc c_pll=1.375v, vcc_peri=3.63v, vcc_io=3.63v, vcc_batt=3.75v 208mhz idle current on vcc_core (px=208mhz) 260 ma te m p = 8 5 c tc a s e , vcc_core=vcc_sram=vc c_pll=1.265v, vcc_peri=3.63v, vcc_io=3.63v, vcc_batt=3.75v
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 73 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 104mhz idle current on vcc_core, (px=104mhz) 150 ma te m p = 8 5 c tc a s e , vcc_core=vcc_sram=vc c_pll=0.99v, vcc_peri=3.63v, vcc_io=3.63v, vcc_batt=3.75v idle current on vcc_peri 1 , all core speeds 200 ma te m p = 8 5 c tc a s e , vcc_core=vcc_sram=vc c_pll=any, vcc_peri=3.63v, vcc_io=3.63v, vcc_batt=3.75v idle current on vcc_io, all core speeds 50 ma te m p = 8 5 c tc a s e , vcc_core=vcc_sram=vc c_pll=any, vcc_peri=3.63v, vcc_io=3.63v, vcc_batt=3.75v idle current on vcc_pll, all core speeds 100 ma te m p = 8 5 c tc a s e , vcc_core=vcc_sram=vc c_pll=any, vcc_peri=3.63v, vcc_io=3.63v, vcc_batt=3.75v deep-idle mode power consumption 13mhz deep idle current on vcc_core (lcd off) 105 ma te m p = 8 5 c tc a s e , vcc_core=vcc_sram=vc c_pll=0.935v, vcc_peri=3.63v, vcc_io=3.63v, vcc_batt=3.75v standby mode power consumption standby current on vcc_core 5 ma temp=room, vcc_core=vcc_sram=vc c_pll=1.1v, vcc_peri=1.8v, vcc_io=vcc_batt=3.0v standby current on vcc_peri 1.6 ma temp=room, vcc_core=vcc_sram=vc c_pll=1.1v, vcc_peri=1.8v, vcc_io=vcc_batt=3.0v standby current on vcc_io 1 ma temp=room, vcc_core=vcc_sram=vc c_pll=1.1v, vcc_peri=1.8v, vcc_io=vcc_batt=3.0v sleep mode power consumption sleep current on vcc_core 0.15 ma temp=room, vcc_core=vcc_pll=0v, vcc_sram=0.95v, vcc_peri=1.8v, vcc_io=vcc_batt=3.0v parameter description maximum units conditions
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 74 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 5.4 dc specification the dc characteristics for each pin include input sense levels, output drive levels, and currents. these parameters can be used to determine maximum dc loading and to determine maximum transition times for a given load. table 16 shows the dc operating conditions for the high- and low-strength input, output, and i/o pins. note note vcc_io must be maintained at a voltage as high as or higher than all other supplies except vcc_batt and vcc_usb. sleep current on vcc_peri 0.47 ma temp=room, vcc_core=vcc_pll=0v, vcc_sram=0.95v, vcc_peri=1.8v, vcc_io=vcc_batt=3.0v sleep current on vcc_io 0.70 ma temp=room, vcc_core=vcc_pll=0v, vcc_sram=0.95v, vcc_peri=1.8v, vcc_io=vcc_batt=3.0v sleep current on vcc_pll 0.043 ma temp=room, vcc_core=vcc_pll=0v, vcc_sram=0.95v, vcc_peri=1.8v, vcc_io=vcc_batt=3.0v note: 1) vcc_peri = vcc_mem + vcc_bb + vcc_usim + vcc_lcd parameter description maximum units conditions table 16: standard input, output, and i/o pin dc operating conditions (sheet 1 of 2) symbol description min max units testing conditions / notes input dc operating conditions (vcc = 1.8v, 2.5, 3.0, 3.3 typical) vih 1 input high voltage, all standard input and i/o pins, relative to applicable vcc (vcc_io, vcc_mem, vcc_bb, vcc_lcd, or vcc_usim) 0.8 * vcc vcc + 0.1 v ? vih_usb input high voltage for the usb bus voltage domain (vcc_usb) 0.8 * vcc 3.6 v ? vil 1 input low voltage, all standard input and i/o pins, relative to applicable vss (vss_io, vss_mem, or vss_bb) and vcc (vcc_io, vcc_mem, vcc_bb, vcc_lcd, vcc_usb, or vcc_usim) vss - 0.1 0.2 * vcc v ? os dc overshoot voltage / duration ? +1 v max duration of 4ns
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 75 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 5.5 oscillator electrical specifications the pxa270 processor contains two oscillators: a 32.768-khz oscillator and a 13.000-mhz oscillator. each oscillator requires a specific crystal. 5.5.1 32.768-khz oscillator specifications the 32.768 - khz oscillator is connected between the txtal_in (amplifier input) and txtal_out (amplified output). table 17 and ta b l e 1 8 list the appropriate 32.768 - khz specifications. to drive the 32.768 - khz crystal pins from an external source: 1. drive the txtal_in pin with a digital signal that has low and high levels as listed in ta b l e 1 8 . do not exceed vcc_pll or go below vss_pll by more than 100 mv. the minimum slew rate is 1 volt per 1 s. the maximum current drawn from the external clock source when the clock is at its maximum positive voltage is typically 1 ma. 2. float the txtal_out pin or drive it in complement to the txtal_in pin, with the same voltage level and slew rate. warning warning the txtal_in and txtal_out pins must not be driven from an external source if the pxa270 processor sleep / deep sleep dc-dc converter is enabled. us dc undershoot voltage / duration ? -1 v max duration of 4ns output dc operating conditions (vcc = 1.8, 2.5, 3.0, 3.3 typical) voh 1 output high voltage, all standard output and i/o pins, relative to applicable vcc (vcc_io, vcc_mem, vcc_bb, vcc_lcd, vcc_usb, or vcc_usim) vcc - 0.3 vcc v ioh = -4 ma 2 , -3 ma 3 vol 1 output low voltage, all standard output and i/o pins, relative to applicable vss (vss_io, vss_mem, or vss_bb) vss vss + 0.3 v ioh = 4 ma 2 , 3 ma 3 notes: 1. programmable drive strengths set to 0x 5 for memory and lcd programmable signals. 2. the current for the high-strength pins are ma<25:0>, md< 31:0>, noe, nwe, nsdras, nsdcas, dqm<3:0>, nsdcs<3:0>, sdcke<1>, sdclk<3:0>, rdnwr, ncs<5:0>, and npwe. 3. the current for all other output and i/o pins are low strength. table 16: standard input, output, and i/o pin dc operating conditions (sheet 2 of 2) symbol description min max units testing conditions / notes table 17: typical 32.768-khz crystal requirements (sheet 1 of 2) parameter minimum typical maximum units frequency range ? 32.768 ? khz frequency tolerance ?30 ? +30 ppm frequency stability, parabolic coefficient ? ? ?0.04 ppm/( c ) 2
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 76 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 drive level ? ? 1.0 uw load capacitance (c l )67.512.5pf shunt capacitance (c o )?0.9?pf motional capacitance (c i )?2.1?ff equivalent series resistance (r s ) ? 18 65 k ? insulation resistance at 100 v dc 100 ? ? m ? aging, at operating temperature per year ? ? 3.0 ppm table 17: typical 32.768-khz crystal requirements (sheet 2 of 2) parameter minimum typical maximum units
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 77 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 5.5.2 13.000-mhz oscillator specifications the 13.000-mhz oscillator is connected between the pxtal_in (amplifier input) and pxtal_out (amplified output). table 19 and ta b l e 2 0 list the 13.000-mhz specifications. to drive the 13.000-mhz crystal pins from an external source: 1. drive the pxtal_in pin with a digital signal with low and high levels as listed in ta bl e 2 0 . do not exceed vcc_pll or go below vss_pll by more than 100 mv. the minimum slew rate is 1 volt / 1 ns. the maximum current drawn from the external clock source when the clock is at its maximum positive voltage typically is 1 ma. 2. float the pxtal_out pin or drive it in complement to the pxtal_in pin, with the same voltage level, slew rate, and input current restrictions. warning warning the pxtal_in and pxtal_out pins must not be driven from an external source if the pxa270 processor sleep / deep sleep dc-dc converter is enabled. table 18: typical external 32.768-khz oscillator requirements symbol description min typical max units amplifier specifications vih_x input high voltage, txtal_in 0.99 1.10 1.21 v vil_x input low voltage, txtal_in ?0.10 0.00 0.10 v iin_xt input leakage, txtal_in ? ? 1 a cin_xt input capacitance, txtal_in/txtal_out ? 18 25 pf ts_xt stabilization time ? ? 10 s board specifications rp_xt parasitic resistance, txtal_in/txtal_out to any node 20 ? ? m cp_xt parasitic capacitance, txtal_in/txtal_out, total ? ? 5 pf cop_xt parasitic shunt capacitance, txtal_in to txtal_out ? ? 0.4 pf table 19: typical 13.000-mhz crystal requirements parameter minimum typical maximum units frequency range 12.997 13.000 13.002 mhz frequency tolerance at 25 c ?50 ? +50 ppm oscillation mode ? fnd ? ? maximum change over temperature range ?50 ? +50 ppm drive level ? 10 100 uw
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 78 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 5.6 clk_pio and clk_tout specifications clk_pio can be used to drive a buffered version of the pxtal_in oscillator input or can be used as a clock input alternative to pxtal_in. refer to ta b l e 2 1 for clk_pio specifications. a buffered and inverted version of the txtal_in oscillator output is driven out on clk_tout. refer to tab le 2 2 for clk_tout specifications. note note clk_tout and clk_pio are only available when software sets the oscc[pio_en] and oscc[tout_en] bits. load capacitance (c l )?10?pf maximum series resistance (r s )?50? aging per year, at operating temperature ? ? 5.0 ppm table 20: typical external 13.000-mhz oscillator requirements symbol description min typical max units amplifier specifications vih_x input high voltage, pxtal_in 0.99 1.10 1.21 v vil_x input low voltage, pxtal_in ?0.10 0.00 0.10 v iin_xp input leakage, pxtal_in ? ? 10 a cin_xp input capacitance, pxtal_in/pxtal_out ? 40 50 pf ts_xp stabilization time ? ? 67.8 ms board specifications rp_xp parasitic resistance, pxtal_in/pxtal_out to any node 20 ? ? m cp_xp parasitic capacitance, pxtal_in/pxtal_out, total ? ? 5 pf cop_xp parasitic shunt capacitance, pxtal_in to pxtal_out ? ? 0.4 pf table 19: typical 13.000-mhz crystal requirements (continued) parameter minimum typical maximum units table 21: clk_pio specifications parameter specifications frequency 13 mhz frequency accuracy (derived from 13 mhz crystal) +/-200ppm symmetry/duty cycle variation 30/70 to 70/30% at vcc
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 79 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 5.7 48 mhz output specifications software may configure gpio<11> or gpio<12> alternate functions to enable the 48-mhz clock output. the 48-mhz output clock is a divided-down output generated from the 312-mhz peripheral pll. refer to ta b l e 2 3 for the 48-mhz output specifications. refer to section 3 of this document for gpio alternate functions in the pin usage table. jitter +/-20ps max load capacitance (c l ) 50pf max rise and fall time (tr & tf) 15ns max with 50pf load table 22: clk_tout specifications parameter specifications frequency 32khz frequency accuracy (derived from 32 khz crystal) +/-200ppm symmetry/duty cycle variation 30/70 to 70/30% at vcc jitter +/-20ps max load capacitance (c l ) 50pf max rise and fall time (tr & tf) 15ns max with 50pf load table 21: clk_pio specifications (continued) parameter specifications table 23: 48 mhz output specifications parameter specifications frequency (derived from 13 mhz crystal) 48 mhz frequency accuracy (derived from 13 mhz crystal) +/-200ppm (maximum) symmetry/duty cycle variation 30/70 to 70/30% at vcc jitter +/-20ps max load capacitance (c l ) 50pf max rise and fall time (tr & tf) 15ns max with 50pf load
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 80 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 6 ac timing specifications a pin?s alternating-current (ac) characteristics include input and output capacitance. these factors determine the loading for external drivers and other load analyses. the ac characteristics also include a derating factor, which indicates how much the ac timings might vary with different loads. note note the timing diagrams in this chapter show bursts that start at 0 and proceed to 3 or 7. however, the least significant address (0) is not always received first during a burst transfer, because the marvell? pxa270 processor requests the critical word first during burst accesses. table 24 shows the ac operating conditions for the high- and low-strength input, output, and i/o pins. all ac specification values are valid for the device?s entire temperature range. 6.1 ac test load specifications figure 22 represents the timing reference load used in defining the relevant timing parameters of the part. it is not intended to be a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. system designers use ibis or other simulation tools to correlate the timing reference load to system environment. manufacturers correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). table 24: standard input, output, and i/o-pin ac operating conditions symbol description min typical max units c in input capacitance, all standard input and i/o pins ? ? 10 pf c out_h output capacitance, all standard high-strength output and i/o pins 20 ? 50 pf c out_l output capacitance, all standard low-strength output and i/o pins 20 ? 50 pf figure 22: ac test load i /o 50 pf ? = 50
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 82 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 6.2 reset and power manager timing specifications the processor asserts the nreset_out pin in one of several different modes: ? power-on reset ? hardware reset ? watchdog reset ? gpio reset ? sleep mode ? deep-sleep mode the following sections give the timing and specifications for entry into and exit from these modes. 6.2.1 power-on timing specifications power-on reset begins when a power supply is detected on the backup battery pin, vcc_batt, after the processor has been powered off. a power-on reset is equivalent to a hardware reset, in that all units are reset to the same known state as with a hardware reset. a power-on reset is a complete and total reset that occurs only at initial power on. the external power-supply system must enable the power supplies for the processor in a specific sequence to ensure proper operation. figure 23 shows the timing diagram for a power-on reset sequence. tab l e 2 5 details the timing. the sequence for power-on reset is as follows: 1. vcc_batt is established, then nreset should be de-asserted to initiate power-on reset. 2. pwr_out is asserted. the processor asserts nreset_out. 3. the external power-control subsystem de-asserts nbatt_fault to signal that the main battery is connected and not discharged. 4. the processor asserts the sys_en signal to enable the power supplies vcc_io, vcc_mem, vcc_bb, vcc_usb, and vcc_lcd. vcc_usim can be established at this time also but can be independently controlled through its own control signals. vcc_io must be established first. the other supplies can turn on in any order, but they must all be established within 125 milliseconds of the assertion of sys_en. 5. the processor asserts the pwr_en signal to enable the power supplies vcc_core, vcc_sram, and vcc_pll. these supplies can turn on in any order but must all be established within 125 milliseconds of the assertion of pwr_en. 6. the external power-control subsystem de-asserts nvdd_fault to signal that all system power supplies have been properly established. 7. the processor de-asserts nreset_out and enters run mode, executing code from the reset vector. note note nvdd_fault is sampled only when the sys_del and pwr_del timers have expired. refer to the marvell? pxa27x processor family developer?s manual , ?initial power on? and ?deep-sleep exit states? for a state diagram.
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 83 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 23: power on reset timing table 25: power-on timing specifications(oscc[cri] = 0) symbol description min typical max units t 1 delay from vcc_batt assertion to nreset de-assertion 10 ? ? ms t 2 delay from nreset de-assertion to sys_en assertion ? 10 1 ? ms t 3 delay from sys_en assertion to pwr_en assertion ? 125 ? ms t 4 power supply stabilization time (time to the de-assertion of nvdd_fault after the assertion of pwr_en) ? ? 120 ms t 5 delay from the assertion of pwr_en to the de-assertion of nreset_out ? 125 ? ms t bramp vcc_batt power-on ramp rate ? 10 12 mv/ s t sysramp power-on ramp rate for all external high -voltage power domains ? 10 12 mv/ s t pwrramp power-on ramp rate for all external low -voltage power domains (including dynamic voltage changes on vcc_core) ? 10 12 mv/ s notes: 1. if the oscc[cri] =1 then the delay from nreset de-assertion to sys_en assertion is 3000ms note: this long delay is attributed to the fact that when the cri bit is read as 1, (which indicates that the clk_req pin was floated during a hardware or power- on reset) the processor oscillator is supplied externally, which then forces the system to wait for the 32 khz oscillator and the 13 mhz oscillator to stabilize. vcc_usb, vcc_io, vcc_mem, vcc_bb, vcc_lcd, vcc_usim vcc_core, vcc_sram, vcc_pll nbatt_fault nreset sys_en pwr_en nvdd_fault vcc_batt nreset_out t 1 t 3 t 5 t 2 t 4 t sysramp t bramp t pwrramp
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 84 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 6.2.2 hardware reset timing the timing sequences shown in figure 24 for hardware reset and the specifications in table 26 and table 27 assume stable power supplies at the assertion of nreset. follow the timings indicated in section 6.2.1 if the power supplies are unstable. 6.2.3 watchdog reset timing watchdog reset is generated internally and therefore has no external pin dependencies. the sys_en and pwr_en power signals de-assert and the nreset_out pin asserts during watchdog reset. the timing is similar to that for power-on reset ? see figure 23 for details. 6.2.4 gpio reset timing gpio reset is generated externally, and the reset gpio source is reconfigured as a standard gpio as soon as the reset propagates internally. the clocks module is not reset by gpio reset, so the reset timing varies based on the selected clock frequency. since gpio assertions are ignored during a frequency change sequence, if gpio<1> is asserted during a frequency change sequence, it must remain asserted low for 240 ns after the frequency change completes for the gpio reset to be figure 24: hardware reset timing table 26: hardware reset timing specifications (oscc[cri] = 0) symbol description min typical max units t 6 delay between nreset asserted and nreset_out asserted ? < 100 ns 10 ms t 7 assertion time of nreset 6 ? ? ms t 8 delay between nreset de-asserted and nreset_out de-asserted 256 ? 265 ms nreset n reset_out t7 note: nbatt_fault and nvdd_fault must be deasserted during the reset sequence. t6 t8 table 27: hardware reset timing specifications (oscc[cri] = 1) symbol description min typical max units t 6 delay between nreset asserted and nreset_out asserted ? < 100 ns 10 ms t 7 assertion time of nreset 6 ? ? ms t 8 delay between nreset de-asserted and nreset_out de-asserted 2256 ? 3265 ms
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 85 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 recognized. figure 25 shows the timing of gpio reset, and table 28 shows the gpio reset timing specifications. note note when bit gprod is set in the power manager general configuration register, nreset_out is not asserted during gpio reset. for register details, see the ?clocks and power manager? chapter in the marvell? pxa27x processor family developer?s manual . table 28: gpio reset timing specifications figure 25: gpio reset timing gp[1] nreset_out ncs0 ta_gpio<1> tdhw_out_a tdhw_out tcs0 symbol description min typical max units notes ta_gpio<1> minimum assert time of gpio<1> in 13.000-mhz input clock cycles 4 ? ? cycles 1, 2, 4 tdhw_out_a delay between gpio<1> asserted and nreset_out asserted in 13.000-mhz input clock cycles 6 ? 8 cycles 4 tdhw_out delay between nreset_out asserted and nreset_out de-asserted, run or turbo mode 230 ? ? nsec
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 86 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 6.2.5 sleep mode timing sleep mode is internally asserted, and it asserts the nreset_out and pwr_en signals. figure 26 and ta b l e 2 9 show the required timing parameters for sleep mode. note note when bit sl_rod is set in the power manager sleep configuration register, nreset_out, is not asserted during sleep mode. see the ?clocks and power manager? chapter in the marvell? pxa27x processor family developer?s manual for register details. figure 26: sleep mode timing tdhw_out_f delay between nreset_out asserted and nreset_out de-asserted, during frequency change sequence 5 ? 380 s 3 tcs0 delay between nreset_out de-assertion and ncs0 assertion 1000 ? ? ns 5 notes: 1. gpio<1> is not recognized as a reset source again until configured to do so in software. software must check the state of gpio<1> before configuring as a reset to ensure that no spurious reset is generated. for details, see the ?clocks and power manager? chapter in the marvell? pxa27x processor family developer?s manual . 2. if gpio<1> reset is asserted during a frequency change sequence, the minimum assert time of gpio<1> needs to be 512*n processor clock cycles plus up to 4 cycles of the 13.000-mhz input clock cycles for the reset to be recognized. 3. time during the frequency-change sequence depends on the state of the pll lock detector at the assertion of gpio reset. the lock detector has a maximum time of 350 s plus synchronization. 4. in standby, sleep, and deep-sleep modes, this time is in addition to the wake-up time from the low-power mode. 5. the tcs0 specification is also applicable to power-on reset, hardware reset, watchdog reset and deep-sleep/sleep mode exit. symbol description min typical max units notes sys_en vcc_usb, vcc_io, vcc_bb,vcc_mem, vcc_lcd, vcc_usim pwr_en nvdd_fault vcc_core, vcc_sram, vcc_pll nreset_out (high) (enabled) wakeup event sleep (entry) sleep sleep (exit) normal i pxa27x state: tentry texit tpwrdelay
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 87 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 6.2.6 deep-sleep mode timing deep-sleep mode is internally asserted, and it asserts the nreset_out and pwr_en signals. figure 27 and ta b l e 3 0 show the required timing parameters for sleep mode. the timing specifications listed are for software-invoked (not battery or vdd fault) deep-sleep entry, unless specified. figure 27: deep-sleep-mode timing table 29: sleep-mode timing specifications symbol description min typical max 3 units t entry 5 delay between mcr sleep command issue to de-assertion of pwr_en 0.56 ? 2.5 1 msec t exit delay between wakeup event and run mode 0.50 ? 136.65 2,4 msec t pwrdelay delay between assertion of pwr_en to pll enable 2 0 ? 125 msec notes: 1. -1ms if not using dc2dc and -0.94ms if any internal sram banks are not powered 2. 0.15ms less time if exiting from sleep mode to 13m mode 3. add 0.1ms if the wake up event is external 4. oscillator start/crystal stable times are programmable (300us-11ms) note: 5ms is user programmable using t he oscc[osd] bit. the remaining 6ms is an internal timer which counts until the oscillator is stable. (typical stabilization is 500 s. maximum can be upto 5ms) 5. nreset_out and nvdd_fault are programmable during sleep mode vcc_usb, vcc_io, vcc_bb, vcc_mem, vcc_lcd, vcc_usim vcc_core, vcc_sram, vcc_pll normal sys_en pwr_en nvdd_fault nreset_out wakeup event deep sleep (entry) deep sleep deep sleep (exit) i pxa27x state: tdentry tdexit tdpwr_delay deep-sleep command tdsys_delay tenable table 30: deep-sleep mode timing specifications (sheet 1 of 2) symbol description min typical max 3 units t dentry 5 delay between deep-sleep command issue to de-assertion of sys_en 0.66 ? 1.66 1 msec t enable delay between de-assertion of pwr_en and sys_en ? 30 ? usec t dexit delay between wakeup event and run mode 0.60 ? 261.75 2,4 msec
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 88 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 6.2.7 gpio states in deep-sleep mode if the external high voltage power domains (vcc_io, vcc_mem, vcc_bb, vcc_lcd, vcc_usb, vcc_usim) remain powered on during deep-sleep, the pgsr values are driven onto all the gpio pins (that are configured as outputs) for a finite time period, then the pins default to the reset state (pu/pd) as described in chapter 2 of this manual. this sequence occurs for either software-initiated or fault-initiated deep-sleep entry. note note gpios<0,1,3,4,9,10> never float. they are powered from vcc_batt so when the system and the core power domains are removed (controlled by sys_en and pwr_en), the pu/pd resistors remain enabled due to vcc_batt remaining on. the delay between the initiation of deep-sleep mode and enabling the gpio pu/pd states is system dependant because the processor is performing an unpredictable workload and requires an unknown amount of time to complete current processes. refer to the deep-sleep mode, ?clocks and power? section of the marvell? pxa27x processor family developers manual for a description on deep-sleep mode entry sequence. table 31 shows the time period that the gpio pullup/pulldowns are enabled. listed below are the regulators and converter naming conventions: l1 = sleep/deep-sleep linear regulator l2 = high-current linear regulator t dsysdelay delay between assertion of sys_en to pwr_en 2 0 ? 125 msec t dpwrdelay delay between assertion of pwr_en to pll enable 2 0 ? 125 msec note: timing specifications for nbatt_fault and/or nvdd_fault asserted deep-sleep mode entry are below: fault assert delay between nbatt_fault or nvdd_fault assertion (during all modes of operation including sleep mode) and deep-sleep mode entry 6 (the de-assertion of sys_en defines when the processor is in deep-sleep mode) 0.33 ? 1.56 msec notes: 1. -1ms if not using dc2dc 2. 0.15ms less time if exiting from deep-sleep mode to 13m mode 3. add 0.1ms if the wake up event is external 4. oscillator start/crystal stable times are programmable (300us-11ms) note: 6ms is user programmable using t he oscc[osd] bit. the remaining 5ms is an internal timer which counts until the oscillator is stable. (typical stabilization is 500 s. maximum can be upto 5ms) 5. nreset_out and nvdd_fault are programmable during sleep mode 6. assumes pmcr[bidae or vidae] bits are set to zero (default state) - the pmcr[bidae or vidae] bits are only read by the processor if nbatt_fa ult or nvdd_fault signals are asserted table 30: deep-sleep mode timing specifications (sheet 2 of 2) symbol description min typical max 3 units
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 89 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 dc2dc = sleep/deep-sleep dc-dc converter note note if the external high voltage power domains (vcc_io, vcc_mem, vcc_bb, vcc_lcd, vcc_usb, vcc_usim) are powered off during deep-sleep mode, the gpios behave the same as described above; however, they float after the supplies are removed. table 31: gpio pu/pd timing specifications for deep-sleep mode description l2 l1 dc2dc units duration of the gpio pu/pd states being enabled and the de-assertion of pwr_en 0.1 0.13 1.13 msec
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 90 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 6.2.8 standby-mode timing 6.2.9 idle-mode timing 6.2.10 frequency-change timing 6.2.11 voltage-change timing the pwr i 2 c uses the regular i 2 c protocol. the pwr i 2 c is clocked at 40 khz (160 khz fast-mode operation is supported). software controls the time required for initiating the voltage change sequence through completion. the voltage-change timing is a product of the number of commands table 32: standby-mode timing specifications symbol description min typical max units ? 13m mode to standby mode entry ? 0.34 ? msec ? standby mode exit to 13m mode 1 0.28 ? 11.28 2 msec ? run mode to standby mode entry ? 0.34 ? msec ? standby mode exit to run mode 1 0.43 ? 11.43 2 msec notes: 1. the 13m oscillator is programmable 2. add 0.1ms if the wake up event is external table 33: idle-mode timing specifications symbol description min typical max units ? 13m mode to deep idle mode entry ? 1 ? s ? deep idle mode exit to 13m mode ? 1 ? s ? run mode to idle run mode entry ? 1 ? s ? idle run mode exit to run mode ? 1 ? s table 34: frequency-change timing specifications symbol description min typical max units ? delay between mcr command to frequency change sequence completion ? 150 1 ? s ? delay to change between turbo, half-turbo and run modes ? 1 2 ? s ? delay to enter 13m mode from any run mode 3 ? 1 ? s ? delay to exit 13m mode to any run mode ? 2 4 ? s notes: 1. any change to the cccr[2n or l] bits followed by a write to clfcfg[f] to initiate a frequency change sequence, results in a pll restart 2. changing between turbo, half-turbo and run modes does not require a pll restart 3. software can only change into 13m mode from any run mode 4. assuming software uses the pll early enable feat ure (cccr[pll_early_en] prior to a frequency change sequence
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 91 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 issued plus the number of software-programmed delays. ta b l e 3 5 shows the timing of a 1 byte command issued to the power manager ic. set the i 2 c programmable output ramp rate with a default/reset ramp rate of 10mv/ s (refer to vcc_core ramp rate specification in the electrical section ) to support vcc_core dynamic voltage management. table 35: voltage-change timing specification for a 1-byte command 6.3 gpio timing specifications table 36 shows the general-purpose i/o (gpio) ac timing specifications. 6.4 memory and expansion-card timing specifications interfaces with the following memories must observe the ac timing requirements given in the following subsections: ? section 6.4.1, ?internal sram read/write timing specifications? ? section 6.4.2, ?sdram parameters and timing diagrams? ? section 6.4.3, ?rom parameters and timing diagrams? symbol description min typical max units ? delay between voltage change sequence start 1 to command received by pmic ? 18 ? cycles 2 notes: 1. write 1 to pwrmode[vc] 2. 40 khz cycles table 36: gpio timing specifications symbol parameter min max units notes tagpio 1 assertion time required to detect gpio edge 154 ? ns run, idle, or sense power modes tagpiolp 2 assertion time required to detect gpio low-power edge 62.5 ? s standby, sleep, or deep-sleep power modes tdgpio 1 de-assertion time required to detect gpio edge 154 ? ns run, idle, or sense power modes tdgpiolp 2 de-assertion time required to detect gpio low-power edge 62.5 ? s standby, sleep, or deep-sleep power modes tdigpio 3 time required for a gpio edge to be detected internally 231 ? ns run, idle, or sense power modes tdigpiolp 4 time required for a gpio low- power edge to be detected internally 93.75 ? s standby, sleep, or deep-sleep power modes notes: 1. period equal to two 13-mhz cycles 2. period equal to two 32-khz cycles 3. period equal to three 13-mhz cycles 4. period equal to three 32-khz cycles note 4 describes the complete timing for a standby, sleep, or deep-sleep wake up source to be asserted and detected internally (2 cycles for assertion (note 2) and 1 additional cycle for detection).
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 92 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 ? section 6.4.4, ?flash memory parameters and timing diagrams? ? section 6.4.5, ?sram parameters and timing diagrams? ? section 6.4.6, ?variable-latency i/o parameters and timing diagrams? ? section 6.4.7, ?expansion-card interface parameters and timing diagrams? note note the diagrams in this section use the following conventions: ? input signals to the processor are represented using dashed waveforms. ? outputs and bidirectional signals are represented using solid waveforms. ? fixed parameters are shown using double arrows in grey (black and white print) or green (color print). ? programmable parameters are shown using bold single arrows. ? the processor register that is used to change a specific timing is given in the corresponding timing table. 6.4.1 internal sram read/write timing specifications 6.4.2 sdram parameters and timing diagrams table 38 shows the timing parameters used in figure 28 . also see section 6.4.3 and figure 32 for additional sdram bus tenure information. see figure 31 for sdram fly-by bus tenures. table 37: sram read/write ac specification symbols parameters min typ max units tsramrd 4-beat read transfer ? 9 ? system bus clocks tsramwr 4-beat write transfer ? 7 ? system bus clocks table 38: sdram interface ac specifications (sheet 1 of 3) symbols parameters vcc_mem = 1.8v +20% / ?5% 3 vcc_mem = 2.5v +/- 10% 4 vcc_mem = 3.3v +/- 10% 5 units notes min typ max min typ max min typ max tsdclk sdclk1, sdclk2 period 9.6 ? 76.9 9.6 ?76.9 9.6 ? 76.9 ns 1, 2 tsdcmd nsdcas, nsdras, nwe, nsdcs assert time 1 ?1 1 ?1 1 ?1 sdcl k ? tsdcas nsdcas to nsdcas assert time 2 ?? 2 ?? 2 ?? sdcl k ? tsdrcd nsdras to nsdcas assert time 1 mdcnf g[dtcx] 3 1 mdcnf g[dtcx] 3 1 mdcnf g[dtcx] 3 sdcl k 6
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 93 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 tsdrp nsdras pre charge 2 mdcnf g[dtcx] 3 2 mdcnf g[dtcx] 3 2 mdcnf g[dtcx] 3 sdcl k 6 tsdcl cas latency 2 mdcnf g[dtcx] 3 2 mdcnf g[dtcx] 3 2 mdcnf g[dtcx] 3 sdcl k 6 tsdras nsdras active time 3 mdcnf g[dtcx] 7 3 mdcnf g[dtcx] 7 3 mdcnf g[dtcx] 7 sdcl k 6 tsdrc nsdras cycle time 4 mdcnf g[dtcx] 11 4 mdcnf g[dtcx] 11 4 mdcnf g[dtcx] 11 sdcl k 6 tsdwr write recovery time (time from last data in the precharge) 2 ?2 2 ?2 2 ?2 sdcl k ? tsdsdos ma<24:10>, md<31:0>, dqm<3:0>, nsdcs<3:0>, nsdras, nsdcas, nwe, noe, sdcke1, rdnwr output setup time to sdclk<2:1> rise 2.5 ?? 2.5 ? 2.5 ?? ns ? tsdsdoh ma<24:10>, md<31:0>, dqm<3:0>, nsdcs<3:0>, nsdras, nsdcas, nwe, noe, sdcke1, rdnwr output hold time from sdclk<2:1> rise 1.5 ?? 1.5 ? 1.5 ?? ns ? vcc_core = 0.85 v +/? 10%, with 1.71 v<= vcc_mem <= 3.63 v vcc_core = 1.1 v +/? 10%, with 1.71 v <= vcc_mem <= 3.63 v vcc_core = 1.3 v +/? 10%, with 1.71 v <= vcc_mem <= 3.63 v table 38: sdram interface ac specifications (sheet 2 of 3) symbols parameters vcc_mem = 1.8v +20% / ?5% 3 vcc_mem = 2.5v +/- 10% 4 vcc_mem = 3.3v +/- 10% 5 units notes min typ max min typ max min typ max
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 94 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 tsdsdis md<31:0> read data input setup time from sdclk<2:1> rise 3.0 ?? 3.0 ?? 0.5 ?? ns ? tsdsdih md<31:0> read data input hold time from sdclk<2:1> rise 2.0 ?? 2.0 ?? 1.8 ?? ns ? notes: 1. sdclk for sdram slowest period is acco mplished by divide-by-2 of the 26-mhz cl k_mem. the fastest possible sdclk is accomplished by configuring clk_mem at 104 mhz and not setting mdrefr[kxdb2]. 2. sdclk1 and sdclk2 frequencies are configured to be clk_mem frequency divided by 1 or 2, depending on the bit fields mdrefr[k1db2] and mdrefr[k2db2] settings. 3. these numbers are for vcc_mem = 1.8 v +20% / ?5%, vol = 0.4 v, and voh = 1.4 v, with each applicable 4-bit field of the system memory buffer strength registers (bscntrp and bscntrn) set to tbd (msb:lsb) and each applicable sdclk<2:1> divide-by-2 and divide-by-4 regist er bits mdrefr[kxdb2] clear. 4. these numbers are for vcc_mem = 2.5 v +/? 10%, vol = 0.4 v , and voh = 2.1 v, with each applicable 4-bit field of the system memory buffer strength registers (bscntrp and bscntrn ) set to 0b1010 (msb:lsb) and each applicable sdclk<2:1> divide-by-2 and divide-by-4 regi ster bit mdrefr[kxdb2] clear. 5. these numbers are for vcc_mem = 3.3 v +/? 10%, vol = 0.4 v , and voh = 2.4 v, with each applicable 4-bit field of the system memory buffer strength registers (bscntrp and bscntrn ) set to 0b1010 (msb:lsb) and each applicable sdclk<2:1> divide-by-2 and divide-by-4 regi ster bit mdrefr[kxdb2] clear. 6. refer to the ?memory controller? chapter in the marvell? pxa27x processor family developer?s manual for register configuration. table 38: sdram interface ac specifications (sheet 3 of 3) symbols parameters vcc_mem = 1.8v +20% / ?5% 3 vcc_mem = 2.5v +/- 10% 4 vcc_mem = 3.3v +/- 10% 5 units notes min typ max min typ max min typ max
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 95 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 28: sdram timing nop act nop read nop pre nop act nop write nop pre nop 0b0000 0 1 2 3 tsdrcd tsdras tsdcmd tsdrp tsdrc tsdcmd tsdcl twr tsdsdoh tsdsdos tsdih tsdsdis tsdclk mask data values sdclk<1> sdcke<1> command nsdcs<0> nsdras nsdcas nwe md<31:0> read md<31:0> write dqm<3:0> rdnwr
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 96 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 29: sdram 4-beat read/4-beat write, different banks timing read(0) pre(1) nop act(1) nop write(1) nop col bank row col rd0_0 rd0_1 rd0_2 rd0_3 wd1_0 wd1_1 wd1_2 wd1_3 0b0000 0 1 2 3 1. mdcnfg[dtc] = 0b00 (cl = 2, trp = 2 clk, trcd = 1 clk), mdcnfg[stack] = 0b00 mask data bytes sdclk<1> sdcke<1> command nsdcs<0> nsdcs<1> nsdras nsdcas ma<24:10> nwe md<31:0> (read) md<31:0> (write) dqm<3:0> rdnwr 2. see the sdram timing diagram. notes:
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 97 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 30: sdram 4-beat write/4-beat write, same bank-same row timing nop write(0) nop write(0) nop col col wd0_0 wd0_1 wd0_2 wd0_3 wd0_4 wd0_5 wd0_6 wd0_7 mask0 mask1 mask2 mask3 mask4 mask5 mask6 mask7 mask data bytes 1. mdcnfg[dtc] = 0b01 (cl = 2, trp = 2 clks) sdclk<1> sdcke<1> command nsdcs<0> nsdras nsdcas ma<24:10> nwe md<31:0> dqm<3:0> rdnwr 2. see the sdram timing diagram. notes:
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 98 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 6.4.3 rom parameters and timing diagrams table 39 lists the timings for rom reads. see figure 32 , figure 33 , figure 34 , and figure 35 for timings diagrams representing burst and non-burst rom reads. note note table 39 lists programmable register items. see the ?memory controller? chapter in the marvell? pxa27x processor family developer?s manual for register configurations for more information on these items. figure 31: sdram fly-by dma timing read pre nop act nop write nop col bank row col rd0 rd1 rd2 rd3 wd0 wd1 wd2 wd3 0b0000 mask0 mask1 mask2 mask3 drive data wd3 drive data wd2 drive data wd1 drive data wd0 latch dval[1] asserted latch data rd3 latch data rd2 latch data rd1 latch data rd0 1. mdcnfg[dtc] = 0b00 (cl = 2, trp = 2 clk, trcd = 1 clk) mask data bytes latch data on rising edge of sdclk<1> when dval<0> is asserted. using dval<1> driven two clocks early, drive data on rising edge of sdclk<2>. sdclk<1> sdclk<2> sdcke<1> command nsdcs<0> nsdcs<2> nsdras nsdcas ma<24:10> nwe md<31:0> dqm<3:0> rdnwr dval<0> dval<1> 2. see the sdram timing diagram. notes:
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 99 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 table 39: rom ac specification symbols parameters min typ max units ? notes tromas address setup to ncs assert 1 ? 1 clk_mem ? tromces ncs setup to noe asserted ? ? 0 clk_mem ? tromceh ncs hold from noe de-asserted ? ? 0 clk_mem ? tromdsoh md setup to address valid 1.5 ? ? clk_mem ? tromdoh md hold from address valid 0 ? ? clk_mem ? tromavdvf address valid to data latched for the first read access 2 mscx[rdf]+2 32 clk_mem ? tromavdvs address valid to data latched for subsequent reads of non-burst devices 1 mscx[rdf]+1 31 clk_mem ? tflashavdvs address valid to data valid for subsequent reads of burst devices 1 mscx[rdn]+1 31 clk_mem ? tromcd ncs de-asserted after a read of next ncs or nsdcs asserted (minimum) 1 mscx[rrr]*2+ 1 15 clk_mem ? ? numbers shown as integer multiples of the clk_mem period ar e ideal. actual numbers vary with pin-to-pin differences in loading and transition direction (rise or fall). for more information, refer to the ?memory control? chapter in the marvell? pxa27x processor family developer?s manual .
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 100 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 32: 32-bit non-burst rom, sram, or flash read timing 0 1 2 3 0b00 0b00 / 0b01 / 0b10 / 0b11 0b00 corresponding mask value tromcd tromavdls tromavdls tromavdls tromavdlf tromas tromdoh tromdsoh tromdoh tromdsoh tromdoh tromdsoh tromdoh tromdsoh tromceh tromces note: msc0[rdf0] = 4, msc0[rrr0] = 1 clk_mem ncs<0> ma<25:2> ma<1:0>(sa1110x='0') ma<1:0>(sa1110x='1') nadv(nsdcas) noe nwe rdnwr md<31:0> dqm<3:0>(sa1110x='0') dqm<3:0>(sa1110x='1') ncsx or nsdcsx
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 101 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 33: 32-bit burst-of-eight rom or flash read timing 0 1 2 3 4 5 6 7 0b00 0b00 / 0b01 / 0b10 / 0b11 0b0000 corresponding mask value tromcd tromavdls tromavdlf tdoh tdsoh tceh tces tas note: msc0[rdf0] = 4, msc0[rdn0] = 1, msc0[rrr0] = 1 clk_mem ncs<0> ma<25:5> ma<4:2> ma<1:0>(sa1110x='0') ma<1:0>(sa1110x='1') nadv(nsdcas) noe nwe rdnwr md<31:0> dqm<3:0>(sa1110x='0') dqm<3:0>(sa1110x='1') ncsx or nsdcsx
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 102 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 34: eight-beat burst read from 16-bit burst-of-four rom or flash timing address 0 1 2 3 0 1 2 3 0b0 0b0 / 0b1 0b00 0b00 or 0b10/0b01 tromcd tromavdls tromavdlf tromavdls tromavdlf tromdoh tromdsoh tromdoh tromdsoh tromceh tromces tromas note: msc0[rdf0] = 4, msc0[rdn0] = 1, msc0[rrr0] = 0 clk_mem ncs<0> ma<25:4> ma<3> ma<2:1> ma<0>(sa1110x='0') ma<0>(sa1110x='1') nadv(nsdcas) noe nwe rdnwr md<15:0> dqm<1:0>(sa1110x='0') dqm<1:0>(sa1110x='1') ncsx or nsdcsx
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 103 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 6.4.4 flash memory parameters and timing diagrams the following sections describe the read/write parameters and timing diagrams for asynchronous and synchronous flash-memory interfaces with the memory controller. 6.4.4.1 flash memory read parameters and timing diagrams section 6.4.4.2 describes asynchronous flash reads. section 6.4.4.3 describes synchronous flash reads. 6.4.4.2 asynchronous flash read parameters and timing diagrams the timings listed in ta b l e 3 9 for rom reads also apply to asynchronous flash reads. see figure 32 , figure 33 , figure 34 , and figure 35 for timings diagrams representative of an asynchronous flash read. 6.4.4.3 synchronous flash read parameters and timing diagrams table 40 lists the timing parameters used in figure 36 , and, for stacked flash packages, figure 37 . figure 35: 16-bit rom/flash/sram read for 4/2/1 bytes timing addr addr + 1 addr addr addr addr + 1 0 0 0 0 0/1 0/1 0/1 0/1 0b00 0b00 0b00 0b00 mask mask mask mask tflashavdvs tromavdlf tromavdlf tromavdlf tromavdls tromavdlf tromcd tromcd tromcd tromdoh tromdsoh tromdoh tromdsoh tromdoh tromdsoh tromdoh tromdsoh tromdoh tromdsoh tromdoh tromdsoh tromces tromces tromces tromceh tromces tromas tromas tromas tromas 32-bit read note: msc0[rdf0] = 2, msc0[rdn0] = 1, msc0[rrr0] = 1 16-bit read 8-bit read applies to: 16-bit rom or non-burst flash 16-bit sram applies to: 16-bit rom or non-burst flash 16-bit sram 16-bit burst flash applies to: 16-bit rom or non-burst flash 16-bit sram 16-bit burst flash 32-bit read applies to: 16-bit burst flash clk_mem ncs<0> ma<25:1> ma<0>(sa1110x='0') ma<0>(sa1110x='1') nadv(nsdcas) noe nwe rdnwr md<15:0> dqm<1:0>(sa1110x='0') dqm<1:0>(sa1110x='1')
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 104 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 table 40: synchronous flash read ac specifications (sheet 1 of 2) symbols parameters min typ max min typ max min typ max units notes divide by 1 2 divide by 2 3 divide by 4 4 tffclk sdclk0 period 9.6 ? 38.5 19. 2 ? 76.9 38.5 ? 154 ns 1 tffas ma<25:0> setup to nsdcas (as nadv) asserted 1 ? 1 1 ? 2 1 ? 4 clk_mem ? tffces ncs setup to nsdcas (as nadv) asserted 1 ? 1 1 ? 2 1 ? 4 clk_mem ? tffadv nsdcas (as nadv) pulse width 1 ? 1 3 ? 3 7 ? 7 clk_mem ? tffos nsdcas (as nadv) de-assertion to noe assertion 1 fcc ? 1 (for fcc<5) fcc ? 2 (for fcc>=5) 13 2 (fcc ? 1) * 2 (for fcc<5) (fcc ? 2) * 2 (for fcc>=5) 26 7 (fcc * 4) ? 7 (for fcc<5) (fcc ? 2) * 4 (for fcc>=5) 52 clk_mem 5 tffceh noe de-assertion to ncs de-assertion 4 ? 4 8 ? 8 16 ? 16 clk_mem ? tffds clk to data valid 2 fcc 15 2 fcc 15 2 fcc 15 clk_mem 5 vcc_mem = 1.8v +20% / -5% 6 vcc_mem = 2.5v +/- 10% 7 vcc_mem = 3.3v +/- 10% 8 tffsdos ma<25:0>, md<31:0>, dqm<3:0>, ncs<3:0>, nsdcas (nadv), nwe, noe, rdnwr output setup time to sdclk0 rise 8 ? ? 8 ? ? 8 ? ? ns ? tffsdoh md<31:0>, dqm<3:0>, ncs<3:0>, nsdcas (nadv), nwe, noe, rdnwr output hold time from sdclk0 rise 4.5 ? ? 4.5 ? ? 4.5 ? ? ns ?
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 105 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 vcc_core = 0.85 v +/? 10%, with 1.71 v<= vcc_mem <= 3.63 v vcc_core = 1.1 v +/? 10%, with 1.71 v <= vcc_mem <= 3.63 v vcc_core = 1.3 v +/? 10%, with 1.71 v <= vcc_mem <= 3.63 v tffsdis md<31:0> read data input setup time from sdclk0 rise 2.2 ? ? 2.2 ? ? 2.2 ? ? ns ? tffsdih md<31:0> read data input hold time from sdclk0 rise 2.9 ? ? 2.9 ? ? 2.9 ? ? ns ? notes: 1. sdclk0 may be configured to be clk_mem divided by 1, 2 or 4. sdclk0 for synchronous flash memory can be at the slowest, divide-by-4 of the 26-mhz clk_mem. the fastest pos sible sdclk0 is accomplished by configuring clk_mem at 104 mhz and clearing the mdrefr[k0db2] or mdrefr[k0db4] bit fields. 2. sdclk0 frequency equals clk_mem frequency (mdrefr[k0db4] and mdrefr[k0db2] bit fields are clear) 3. sdclk0 frequency equals clk_mem/2 frequency (mdrefr[k0db2] is set and mdrefr[k0db4] is clear). 4. sdclk0 frequency equals clk_mem/4 frequency (mdrefr[k0db4] is set). 5. use sxcnfg[sxclx] to configure the val ue for the frequency configuration code (fcc). 6. these numbers are for vcc_mem = 1.8 v +20% / -5%, vol = 0.4 v, and voh = 1.4 v, with each applicable 4-bit field of the system memory buffer strength registers (bscn trp and bscntrn) set to tbd (msb:lsb) and each applicable sdclk0 divide-by-2 and divide-by-4 register bits (mdrefr[k0db2] and mdrefr[k0db4]) clear. if mdrefr[k0db2 is set, the corresponding output setup and hold times are increased and decr eased, respectively, by 0.25 times the sdclk0 period. 7. these numbers are for vcc_mem = 2.5 v +/? 10%, vol = 0.4 v, and voh = 2.1 v, with each applicable 4-bit field of the system memory buffer strength registers (bscntrp and bscntrn) set to 0b1010 (msb:lsb) and each applicable sdclk0 divide-by-2 and divide-by-4 register bit (mdrefr[k0db2] and mdrefr[k0db4]) clear. if mdrefr[k0db2 is set, the corresponding output setup and hold times are increased and decr eased, respectively, by 0.25 times the sdclk0 period. 8. these numbers are for vcc_mem = 3.3 v +/? 10%, vol = 0.4 v, and voh = 2.4 v, with each applicable 4-bit field of the system memory buffer strength registers (bscntrp and bscntrn) set to 0b1010 (msb:lsb) and each applicable sdclk0 divide-by-2 and divide-by-4 register bit (mdrefr[k0db2] and mdrefr[k0db4]) clear. if mdrefr[k0db2 is set, the corresponding output setup and hold times are increased and decr eased, respectively, by 0.25 times the sdclk0 period. table 40: synchronous flash read ac specifications (sheet 2 of 2) symbols parameters min typ max min typ max min typ max units notes
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 106 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 36: synchronous flash burst-of-eight read timing 0b00 0b00/0b01/0b10/0b11 0b0000 corresponding mask value code+1 code notes: 1) sxcnfg[cl] = 0b100 (cl = 5, frequency code configuration = 4) 2) code = frequency configuration code clk_mem sdclk<0> ma<19:2> ma<1:0>(sa1110x=0) ma<1:0>(sa1110x=1) ncs<0> nadv(nsdcas) noe nwe md<31:0> dqm<3:0>(sa1110x=0) dqm<3:0>(sa1110x=1)
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 107 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 38 indicates which clock data would be latched following the assertion of nsdcas(adv), depending on the configuration of the sxcnfg[sxclx] bit field. the period in the diagram indicated by different frequency configuration codes (fcodes or fccs) is equal to the number of sdclk0 cycles between the read command and the clock edge on which data is driven onto the bus. figure 37: synchronous flash stacked burst-of-eight read timing 0b00 0b00/0b01/0b10/0b11 0b0000 corresponding mask value code+1 code note: sxcnfg[cl] = 0b100 (cl = 5, frequency code configuration = 4) sa1110cr[sxstack] = 0b01 clk_mem sdclk<3> ma<19:2> ma<1:0>(sa1110x=0) ma<1:0>(sa1110x=1) ncs<0> nadv(nsdcas) noe nwe md<31:0> dqm<3:0>(sa1110x=0) dqm<3:0>(sa1110x=1)
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 108 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 the burst read example shown in figure 39 represents waveforms that result when sxcnfg[sxclx] is configured as 0b0100, representing a frequency configuration code equal to 3. the following example can help determine the appropriate setting for sxcnfg[sxclx]. parameters defined by the processor: ? tffsdoh (max) = sdclk<0> to ce# (nce), adv# (nadv), or address valid, whichever occurs last ? tffsdis (min) = data setup to sdclk<0> parameters defined by flash memory: ? tvlqv (min) = adv# low to output delay ? tvlch (min) = adv# low to clock ? tchqv (max) = sdclk<0> to output valid use the following equations when calculating the frequency configuration code: (1) sdclk period = (1 / frequency) (2) n (sdclk period) tvlqv - tvlch - tchqv figure 38: first-access latency configuration timing valid address 0b0000 beat 0 beat 1 beat 2 beat 3 beat 4 beat 5 beat 0 beat 1 beat 2 beat 3 beat 4 beat 0 beat 1 beat 2 beat 3 beat 0 beat 1 beat 2 beat 0 beat 1 beat 0 code 7 code 6 code 5 code 4 code 3 code 2 note: code = frequency configuration code sdclk<0> ncs<0> ma<19:0> nsdcas dqm<3:0> md (code = 2) md (code = 3) md (code = 4) md (code = 5) md (code = 6) md (code = 7)
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 109 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 (3) n = (tvlqv - tvlch - tchqv) / sdclk period, where n = frequency configuration code rounded up to integer value (4) sdclk period tchqv + tffsdis example the timing information below is only an example. see table 40 for actual synchronous ac timings. sdclk<0> frequency = 50 mhz tvlqv = 70 ns (typical timing from synchronous flash memory) tvlch = 10 ns (min) tchqv = 14 ns (min) from eq.(1):1 / 50 (mhz) = 20 ns from eq.(2):n(20 ns) 70 ns - 10 ns - 14 ns n(20 ns) 46 ns n = (46 / 20) ns = 2.3 ns n = 3 use equation 4 to help verify the maximum possible frequency at which the synchronous flash memory can run with the memory controller. the following example uses equation 4: sdclk<0> frequency = 66 mhz tchqv = 11 ns (max) tffsdis = 3 ns (min) from eq. (1):1 / 66 (mhz) = 15.15 ns from eq. (4):15.15 ns 11 ns + 3 ns 15.15 ns 14 ns the results from this example indicate that the 66-mhz memory works without problems with the memory controller. note note all ac timings must be considered to avoid timing violations in the memory-to-memory-controller interface.
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 110 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 6.4.4.4 flash memory write parameters and timing diagrams table 41 lists the ac specification for both burst and non-burst flash writes shown in figure 40 and, for stacked flash packages , figure 41 . figure 39: synchronous flash burst read example valid address beat 0 beat1 tchqv tffsdoh tffsdoh tffsdoh tffsdis tvlqv tavch sdclk<0> ncs<0> nsdcas (adv#) ma md table 41: flash memory ac specification (sheet 1 of 2) symbols parameters min typ max units 1 notes tflashas address setup to ncs assert 1 ? 1 clk_mem ? tflashah address hold from nwe de-asserted 1 ? 1 clk_mem ? tflashasw address setup to nwe asserted 1 ? 3 clk_mem 2 tflashces ncs setup to nwe asserted 2 ? 2 clk_mem ? tflashceh ncs hold from nwe de-asserted 1 ? 1 clk_mem ? tflashwl nwe asserted time 1 mscx[rdf]+1 31 clk_mem ? tflashdswh md/dqm setup to nwe de-asserted 2 mscx[rdf]+2 32 clk_mem ? tflashdh md/dqm hold from nwe de-asserted 1 ? 1 clk_mem ? tflashdsoh md setup to address valid 1.5 ? ? clk_mem ?
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 111 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 tflashdoh md hold from address valid 0 ? ? clk_mem ? tflashcd ncs de-asserted after a read/write to next ncs or nsdcs asserted (minimum) 1 mscx[rrr]*2 + 1 15 clk_mem ? notes: 1. numbers shown as integer multiples of the clk_mem period ar e ideal. actual numbers vary with pin-to-pin differences in loading and transition direction (rise or fall). 2. on the first data beat of burst transfer, the tflashasw is 3 clk_mem periods. on subsequent data beats, the tflashasw is 1 clk_mem period. figure 40: 32-bit flash write timing table 41: flash memory ac specification (sheet 2 of 2) symbols parameters min typ max units 1 notes command address data address 0b00 0b00 cmd data 0b0000 0b0000 tflashcd tflashdswh tflashdswh tflashwl tflashwl tflashcd tflashdh tflashdh tflashah tflashceh tflashces tflashasw tflashah tflashceh tflashces tflashasw tflashas tflashas note: msc0[rdf0] = 2, msc0[rrr0] = 2 first bus cycle second bus cycle clk_mem ncs<0> ma<25:2> ma<1:0> nwe noe rdnwr md<31:0> dqm<3:0> nadv(nsdcas) n csx or nsdcsx
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 112 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 41: 32-bit stacked flash write timing command address data address 0b00 0b00 cmd data 0b0000 0b0000 tflashcd tflashdswh tflashdswh tflashwl tflashwl tflashcd tflashdh tflashdh tflashah tflashceh tflashces tflashasw tflashah tflashceh tflashces tflashasw tflashas tflashas * msc0[rdf0] = 2, msc0[rrr0] = 2, sa1110{sxstack] = 00 first bus cycle second bus cycle clk_mem nwe ma<25:2> ma<1:0> n cs<0> or ncs<1> noe rdnwr md<31:0> dqm<3:0> nadv(nsdcas) ncsx
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 113 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 6.4.5 sram parameters and timing diagrams the following sections describe the read/write parameters and timing diagrams for sram interfaces with the memory controller. 6.4.5.1 sram read parameters and timing diagrams the timing for a read access is identical to that for a non-burst rom read (see figure 32 ). the timings listed in ta b l e 3 9 for rom reads are also used for sram reads. see figure 32 and figure 35 for timings diagrams representing 16-bit sram transferring four, two, and one byte(s) during read-bus tenures. 6.4.5.2 sram write parameters and timing diagrams figure 43 and figure 44 show the timing for 32-bit and 16-bit sram writes. table 42 lists the timings used in figure 43 and figure 44 . figure 42: 16-bit flash write timing addr 0b0 bytes 1:0 0b00 tflashcd tflashdswh tflashwl tflashdh tflashceh tflashces tflashas applies to: 16-bit non-burst flash 16-bit burst flash note: msc1[rdn2] = 2, msc1[rdf2] = 1, msc1[rrr2] = 2 clk_mem ncs<2> ma<25:1> ma<0> nwe noe rdnwr md<15:0> dqm<1:0> nadv(nsdcas) ncsx or nsdcsx
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 114 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 during writes, data pins are actively driven by the processor and are not three-stated, regardless of the states of the individual dqm signals. for sram writes, the dqm signals are used as byte enables. note note table 42 lists programmable register items. see the ?memory controller?chapter in the marvell? pxa27x processor family developer?s manual for register configurations for more information on these items. table 42: sram write ac specification symbols parameters min typ max units 1 notes tsramas address setup to ncs assert 1 ? 1 clk_mem ? tsramah address hold from nwe de-asserted 1 ? 1 clk_mem ? tsramasw address setup to nwe asserted 1 ? 3 clk_mem 2 tsramces ncs setup to nwe asserted 2 ? 2 clk_mem ? tsramceh ncs hold from nwe de-asserted 1 ? 1 clk_mem ? tsramwl nwe asserted time 1 mscx[rdn]+1 31 clk_mem ? tsramdswh md/dqm setup to nwe de-asserted 2 mscx[rdn]+2 32 clk_mem ? tsramdh md/dqm hold from nwe de-asserted 1 ? 1 clk_mem ? tramcd ncs de-asserted after a read to next ncs or nsdcs asserted (minimum) 1 mscx[rrr]*2+1 15 clk_mem ? notes: 1. numbers shown as integer multiples of the clk_mem period ar e ideal. actual numbers vary with pin-to-pin differences in loading and transition direction (rise or fall). 2. on the first data beat of burst transfer, the tsramasw is 3 clk_mem periods. on subsequent data beats, the tsramasw is 1 clk_mem period.
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 115 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 43: 32-bit sram write timing 0 1 2 3 byte addr byte addr byte addr byte addr d0 d1 d2 d3 mask0 mask1 mask2 mask3 tsramcd tsramwl tsramwl tsramwl tsramwl tsramdoh tsramdh tsramdswh tsramcehw tsramah tsramasw tsramah tsramasw tsramcesw tsramas note: 4-beat burst, msc0[rdn0] = 2, msc0[rrr0] = 1 clk_mem ncs<0> ma<25:2> ma<1:0> nwe noe rdnwr md<31:0> dqm<3:0> ncsx or nsdcsx nadv(nsdcas)
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 116 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 6.4.6 variable-latency i/o parameters and timing diagrams the following sections describe the read/write parameters and timing diagrams for vlio memory interfaces with the memory controller. table 43 lists the timing-information references for both the read and the write timing diagrams. note note table 43 lists programmable register items. for more information on these items, see the ?memory controller? chapter in the marvell? pxa27x processor family developer?s manual for register configurations. figure 44: 16-bit sram write for 4/2/1 byte(s) timing addr addr+1 addr addr '0' '0' '0' '0' or '1' bytes 1:0 bytes 3:2 bytes 1:0 byte 0 or 1 0b00 0b00 0b01 / 0b10 tsramc d tsramdswh tsramdswh tsramdswh tsramwl tsramwl tsramwl tsramwl tsramcd tsramcd tsramdh tsramdh tsramdswh tsramdh tsramdh tsramceh tsramces tsramceh tsramces tsramceh tsramwl tsramasw tsramah tsramces tramas tramas tramas 32-bit write 16-bit write 8-bit write note: msc1[rdf2]=1, msc1[rdn]=2, msc1[rrr2]=2 clk_mem ncs<2> ma<25:1> ma<0> nwe noe rdnwr md<15:0> dqm<1:0> nadv(nsdcas) n csx or nsdcsx
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 117 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 6.4.6.1 variable latency i/o read timing figure 45 shows the timing for 32-bit variable-latency i/o (vlio) memory reads. table 43 lists the timing parameters used in these diagrams. table 43: vlio timing symbols parameters min typ max 2 units 1 notes tvlioas address setup to ncs asserted 1 ? 1 clk_mem ? tvlioah address hold from npwe/noe de-asserted 2 mscx[rdn] 30 clk_mem ? tvlioasrw0 address setup to npwe/noe asserted (1st access) 3 ? 3 clk_mem ? tvlioasrwn address setup to npwe/noe asserted (next access(es)) 2 mscx[rdn] 30 clk_mem ? tvlioces ncs setup to npwe/noe asserted 2 ? 2 clk_mem ? tvlioceh ncs hold from npwe/noe de-asserted 1 ? 1 clk_mem ? tvliodswh md/dqm setup (minimum) to npwe de-asserted 5 mscx[rdf]+2 32 clk_mem ? tvliodh md/dqm hold from npwe de-asserted 2 mscx[rdn] 30 clk_mem ? tvliodsoh md setup to address changing 1.5 ? clk_mem ? tvliodoh md hold from address changing 0 ? ns ? tvliordyh rdy hold from npwe/noe de-asserted 0 ? ? ns ? tvliorwa npwe/noe assert period between writes 4 msc[rdf]+1 + waits 31 + waits clk_mem ? tvliorwd npwe/noe de-asserted period between writes 4 mscx[rdn*2] 60 clk_mem 3 tvliocd ncs de-asserted after a read/write to next ncs or nsdcs asserted (minimum) 1 mscx[rrr]*2 + 1 15 clk_mem ? notes: 1. numbers shown as integer multiples of the clk_mem period ar e ideal. actual numbers vary with pin-to-pin differences in loading and transition direction (rise or fall). 2. maximum values reflect the register dynamic ranges. 3. depending on the programmed value of msc[rdn] and the clk_ mem speed, this can be a significant amount of time. processor does not drive the data bus during this time between transfers. if the vlio does not drive the data bus during this time between transfers, the data bus is not driven for this period of time. if ms c[rdn] is programmed to 60 (which equals 60 clk_mem cycles), then the data bus could potentia lly not be driven for 30*2 = 60 clk_mem cycles.
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 118 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 6.4.6.2 variable-latency i/o write timing figure 46 shows the timing for 32-bit vlio memory writes. table 43 list the timing parameters used in figure 46 . figure 45: 32-bit vlio read timing addr addr + 1 addr + 2 addr + 3 0b00 0b00/0b01/0b10/0b11 0b0000 corresponding mask value tvlioc d tvliorwa tvliorwd tvliorwa tvliorwd tvliorwa tvliorwd tvliodoh tvliodsoh tvliodoh tvliodsoh tvliodoh tvliodsoh tvliodoh tvliodsoh tvliordyh tvliordyh tvliordyh tvliordyh tvlioceh tvlioah tvlioasrwn tvlioah tvlioasrwn tvlioah tvlioasrwn tvlioah tvlioasrw0 tvlioces tvlioas 0 waits 1 wait 2 waits 3 waits note: msc0[rdf0] = 3, msc0[rdn0 = 2, msc0[rrr0] = 1 clk_mem ncs<0> ma<25:2> ma<1:0>(sa1110x='0') ma<1:0>(sa1110x='1') noe npwe rdnwr rdy rdy_sync md<31:0> dqm<3:0>(sa1110x='0') dqm<3:0>(sa1110x='1') ncsx or nsdcsx
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 119 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 6.4.7 expansion-card interface parameters and timing diagrams the following sections describe the read/write parameters and timing diagrams for compactflash* and pc card* (expansion card) memory interfaces with the memory controller. table 44 shows the timing parameters used in the timing diagrams, figure 47 and figure 48 . note note table 44 lists programmable register items. see the ?memory controller? chapter in the marvell? pxa27x processor family developer?s manual for register configurations for more information on these items. figure 46: 32-bit vlio write timing addr addr + 1 addr + 2 addr + 3 0b00 d0 d1 d2 d3 mask0 mask1 mask2 mask3 tvliocd tvliorwa tvliorwd tvliorwa tvliorwd tvliorwa tvliorwd tvliorwa tvliodh tvliodh tvliodswh tvliodh tvliodswh tvliodh tvliodswh tvliodswh tvliordyh tvliordyh tvliordyh tvliordyh tvlioceh tvlioah tvlioasrwn tvlioah tvlioasrwn tvlioah tvlioasrwn tvlioah tvlioasrw0 tvlioces tvlioas 0 waits note: msc0[rdf0] = 3, msc0[rdn0] = 2, msc0[rrr0] = 1 1 wait 2 waits 3 waits clk_mem ncs<0> ma<25:2> ma<1:0> npwe noe rdnwr rdy rdy_sync md<31:0> dqm<3:0> ncsx or nsdcsx
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 120 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 table 44: expansion-card interface ac specifications symbols parameters min typ max units notes tcdavcl address valid to cmd low 2 mcx[set] 127 clk_mem 1,2,3,4 tcdchai cmd high to address invalid 0 mcx[hold] 63 clk_mem 1,2,3,5 tcddvcl write data valid to cmd low ? 1 ? clk_mem 1,3 tcdchwdi cmd high to write data invalid ? 4 ? clk_mem 1,3 tcddvch read data valid to cmd high 2 ? ? clk_mem 1,3 tcdchrdi cmd high to read data invalid 0 ? ? ns 3 tcdcmd cmd assert during transfers ? tcdclps + tcdphch + npwait assertion ? clk_mem 1,3 tcdilcl niois16 low to cmd low 4 ? ? clk_mem 1,3 tcdchih cmd high to niois16 high 2 ? ? clk_mem 1,3 tcdclps cmd low to npwait sample ? x_asst_wait ? clk_mem 1,3,6,7 tcdphch npwait high to cmd high ? x_asst_hold ? clk_mem 1,3,6,8 notes: 1. all numbers shown are ideal, integer multiples of the clk_mem per iod. actual numbers vary with pin-to-pin differences in loading and transition direction (rise or fall). 2. includes signals ma[25:0], npreg, and npsktsel. 3. cmd refers to signals npwe, npoe, npiow, and npior 4. refer to the marvell? pxa27x processor family developer?s manual , expansion memory timing configuration registers to change the assertion of cmd using the mcx[set] bit fields. 5. refer to the marvell? pxa27x processor family developer?s manual , expansion memory timing configuration registers to increase the assertion of cmd using the mcx[hold] bit fields. 6. refer to the marvell? pxa27x processor family developer?s manual , expansion memory timing configuration registers to increase timings. the timings are changed by programming the mcx[asst] respective bit fields. refer to the pc card interface command assertion code table to see the effect of mcx[asst]. 7. tcdclps equals clk_mem * x_asst_wait. refer to the pc card interface command assertion code table in the marvell? pxa27x processor family developer?s manual for the correlation between x_asst_wait and the mcx[asst] bit field. 8. tcdphch equals clk_mem * x_asst_hold. refer to the pc card interface command assertion code table in the marvell? pxa27x processor family developer?s manual for the correlation between x_asst_hold and the mcx[asst] bit field.
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 121 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 47: expansion-card memory or i/o 16-bit access timing read data latch tcdcmd tcdphch tcdclps tcdavcl tcdchai tcdchrdi tcddvch tcdchwdi tcddvcl tcdchih tcdilcl clk_mem npce[2],npce[1] ma[25:0],npreg,psktsel npwe,npoe,npiow,npior niois16 md[15:0] (write) rdnwr npwait md[15:0] (read)
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 122 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 6.5 lcd timing specifications figure 49 describes the lcd timing parameters. the lcd pin timing specifications are referenced to the pixel clock (l_pclk_wr). table 45 gives the values for the parameters. figure 49: lcd timing definitions figure 48: expansion-card memory or i/o 16-bit access to 8-bit device timing low byte high byte read data latch read data latch tcdphch tcdclps tcdphch tcdclps tcdcmd tcdchai tcdavcl tcdcmd tcdchai tcdavcl tcdchwdi tcdchwdi tcddvcl tcdchrdi tcddvch tcdchrdi tcddvch tcdchih tcdilcl clk_mem ma<25:1>,npreg,psktsel ma<0> npce<2> npce<1> npiow (or) npior rdnwr niois16 npwait md<7:0> (read) md<7:0> (write)
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 123 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 6.6 ssp timing specifications figure 50 describes the ssp timing parameters. the ssp pin timing specifications are referenced to sspclk. table 46 gives the values for the parameters. table 45: lcd timing specifications symbol description min max units notes tpclkdv l_pclk_wr rise/fall to l_ldd<17:0> driven valid ? 7 ns 1 tpclklv l_pclk_wr fall to l_lclk_a0 driven valid ? 7 ns 2 tpclkfv l_pclk_wr fall to l_fclk_rd driven valid ? 7 ns 2 tpclkbv l_pclk_wr rise to l_bias driven valid ? 14 ns 2 notes: 1. the lcd data pins can be programmed to be driven on ei ther the rising or falling edge of the pixel clock (l_pclk_wr). 2. these lcd signals can toggle when l_pclk_wr is not clocking (between frames). at this time, they are clocked with the internal version of the pixel cl ock before it is driven out onto the l_pclk_wr pin. l _pclk_wr l_ldd l_lclk_a0 l_bias l_fclk_rd tpclklv tpclkfv tpclkbv tpclkdv lccr3[pcp] = 1 l_ldd l_lclk_a0 l_bias l _fclk_rd tpclklv tpclkfv tpclkbv tpclkdv l _pclk_wr lccr3[pcp] = 0
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 124 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 note note in figure 50 , read the term ?tsfmv? as ?tstxv.? figure 50: ssp master mode timing definitions table 46: ssp master mode timing specifications symbol description min max units notes ts f m v sspsclk rise to sspsfrm driven valid 21 ns trxds ssprxd valid to sspsclk fall (input setup) 11 ns trxdh sspsclk fall to ssprxd invalid (input hold) 0 ns ts f m v sspsclk rise to ssptxd valid 22 ns sspsclk sspsfrm ssptxd ssprxd t sfmv t sfmv t rxds t rxdh
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 125 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 51: timing diagram for ssp slave mode transmitting data to an external peripheral figure 52: timing diagram for ssp slave mode receiving data from external peripheral pxa27x processor transmitting data sspsclk (from peripheral) ssptxd (from ssp) pxa27x ssp (slave mode) transmitting data to external peripheral sspsfrm (from peripheral) tsclk2txd_output_delay tsfrm2txd_output_delay pxa27x processor transmitting data sspsclk (from peripheral) ssptxd (from ssp) pxa27x ssp (slave mode) transmitting data to external peripheral sspsfrm (from peripheral) tsclk2txd_output_delay tsfrm2txd_output_delay table 47: timing specification ssp slave mode transmitting data to external peripheral parameter description min typ max units tsfrm2txd_output_delay frame to tx data out 10.58 ns tsclk2txd_output_delay clock to tx data out 10.52 ns pxa27 processor receiving data sspsclk (from peripheral) ssprxd (from peripheral) sspsfrm (from peripheral) pxa27x ssp (slave mode receiving data from external peripheral data capture tsclk_input_delay tsfrm_input_delay trxd_input_delay data capture pxa27 processor receiving data sspsclk (from peripheral) ssprxd (from peripheral) sspsfrm (from peripheral) pxa27x ssp (slave mode receiving data from external peripheral data capture tsclk_input_delay tsfrm_input_delay trxd_input_delay data capture
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 126 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 6.7 jtag boundary scan timing specifications table 49 shows the ac specifications for the jtag boundary-scan test signals. figure 53 shows the timing diagram. table 48: timing specification for ssp slave mode receiving data from external peripheral parameter description min typical max units tsfrm_input_delay frame to rx data capture 5.21 ns tsclk_input_delay clock to rx data capture 5.04 ns trxd_input_delay rx data setup to capture 4.81 ns table 49: boundary scan timing specifications symbol parameter min max units notes tbsf tck frequency 0.0 33.33 mhz ? tbsch tck high time 15.0 ? ns measured at 1.5 v tbscl tck low time 15.0 ? ns measured at 1.5 v tbscr tck rise time ? 5.0 ns 0.8 v to 2.0 v tbscf tck fall time ? 5.0 ns 2.0 v to 0.8 v tbsis1 input setup to tck tdi, tms 4.0 ? ns ? tbsih1 input hold from tck tdi, tms 6.0 ? ns ? tbsis2 input setup to tck ntrst 25.0 ? ns ? tbsih2 input hold from tck ntrst 3.0 ? ns ? tntrst assertion time of ntrst 6 ? ms ? tbsov1 tdo valid delay 1.5 6.9 ns relative to falling edge of tck tof1 tdo float delay 1.1 5.4 ns relative to falling edge of tck
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 127 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 6.8 marvell? quick capture technology ac timing table 50 lists the timing parameters used in figure 54 . figure 53: jtag boundary-scan timing ca p ture- i r shift-ir run-test/idle tof1 tbsov1 tbsov1 tbsov1 tbsov1 tbsov1 tbsov1 tbsov1 tbsih1 tbsis1 tbsih1 tbsis1 tbsih2 tbsis2 tbscl tbsch tbsf tck ntrst tms tdi tdo controller state tes t - lo gi c - r es et run-test/idle selec t- dr-s c an se l ect- ir- scan e x i t1-ir up dat e- ir t e s t-log i c - re s et tntrst table 50: marvell? quick capture ac timing specification symbol description min typical max units tciis camera interface setup time 5 ? ? ns tciih camera interface hold time 5 ? ? ns
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 128 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 54: marvell? quick capture interface timing tciis tciih cif_pclk* cif_dd * cif_pclk data sampling edge determined by the cicr 4[pcp] setting
copyright ? 4/3/09 marvell doc. no. mv-s104690-00 rev. d april 2009 released page 129 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 6.9 multimediacard timing specifications 6.10 secure digital (sd/sdio) timing figure 56 and ta b l e 5 2 define the secure digital (sd/sdio) controller ac timing specifications. figure 55: multimedia card timing diagrams table 51: multimedia card timing specifications symbol parameter min max unit notes t freq mmclk frequency data transfer mode 019.5mhz t freq mmclk frequency identification mode 0400khz t wh clock high time 10 ? ns t wl clock low time 10 ? ns t rise clock rise time ? 10 ns 1 t fall clock fall time ? 10 ns 1 t isu data input setup time 3 ? ns t ih data input hold time 3 ? ns t osu output data setup time 13.1 ? ns t oh output data hold time 9.7 ? ns note: 52.rise and fall times measured from 10% - 90% of voltage level. t wh clock high time 10 ? ns t wl clock low time 10 ? ns t rise clock rise time ? 10 ns 1 t fall clock fall time ? 10 ns 1 data in invalid data in data out invalid data out toh tosu tih tisu twl tfreq twh twl twh tfreq mmclk m mdat0/1 m mdat2/3
pxa270 processor electrical, mechanical, and thermal specification doc. no. mv-s104690-00 rev. d copyright ? 4/3/09 marvell page 130 april 2009 released 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 figure 56: sd/sdio timing diagrams data in invalid invalid data out td(q) td(id) tih tisu tfreq twh twl twh tfreq twl mmclk m mdat0/1 m mdat2/3 table 52: sd/sdio timing specifications symbol parameter min max unit notes t freq mmclk frequency data transfer mode 019.5mhz t freq mmclk frequency identification mode 0 1 /100 400 khz t wh clock high time 50 ? ns t wl clock low time 50 ? ns t rise clock rise time ? 10 ns 2 t fall clock fall time ? 10 ns 2 t isu data input setup time 5 ? ns t ih data input hold time 5 ? ns t d(q) output delay time during data transfer mode 014ns t d(id) output delay time during identification mode 050ns notes: 1. 0 khz is when the clock is stopped. the minimum 100 khz frequency range is where continuous clock is required. 2. rise and fall times measured from 10% - 90% of voltage level.
marvell. moving forward faster marvell semiconductor, inc. 5488 marvell lane santa clara, ca 95054, usa tel: 1.408.222.2500 fax: 1.408.752.9028 www.marvell.com back cover

▲Up To Search▲

Price & Availability of 88AP270MA2-BGO2C520

	To Download 88AP270MA2-BGO2C520 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .