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ds04-21336-2e fujitsu semiconductor data sheet assp single serial input pll frequency synthesizer on-chip 2.5 ghz prescaler mb15e06 n description the fujitsu mb15e06 is serial input phase locked loop (pll) frequency synthesizers with a 2.5 ghz prescaler. a 64/65 or a 128/129 can be selected for the prescaler that enables pulse swallow operation. the latest bicmos process technology is used, resuitantly a supply current is limited as low as 8 ma typ. this op- erates with a supply voltage of 3.0 v (typ.) . furthermore, a super charger circuit is included to get a fast tuning as well as low noise performance. as a result of this, mb15e06 is ideally suitable for digital mobile communications, such as gps (global positioning system) , wireless lan, catv (cable television) etc. n features ? high frequency operation : 2.5 ghz max ? low power supply voltage : v cc = 2.7 to 3.6 v ? very low power supply current : i cc = 8.0 ma typ. (v cc = 3 v) ? power saving function : i ps = 10 m a max. ? pulse swallow function : 64/65 or 128/129 ? serial input 14-bit programmable reference divider : r = 5 to 16, 383 ? serial input 18-bit programmable divider consisting of: - binary 7-bit swallow counter : 0 to 127 - binary 11-bit programmable counter : 5 to 2, 047 ? wide operating temperature : ta = - 40 to 85 c ? plastic 16-pin ssop package (fpt-16p-m05) n pac k ag e 16-pin plastic ssop 16-pad plastic bcc (fpt-16p-m05) (lcc-16p-m06)
mb15e06 2 n pin assignment top view osc in osc out v p v cc d o gnd xfin fin f r f p ld/fout zc ps le data clock 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 osc out v p v cc d o gnd xfin f p ld / fout zc ps le data osc in f r fin clock 1 2 3 4 5 678 9 10 11 12 13 14 15 16 (top view) (fpt-16p-m05) (top view) (lcc-16p-m06)
mb15e06 3 n pin descriptions ( ) : for bcc package. pin no. pin name i/o descriptions 1 (16) osc in i programmable reference divider input. oscillator input connection to a tcxo. 2 (1) osc out o oscillator output. 3 (2) v p ? power supply voltage input for the charge pump. 4 (3) v cc ? power supply voltage input. 5 (4) d o o charge pump output. phase of the charge pump can be reversed by fc input. 6 (5) gnd ? ground. 7 (6) xfin i prescaler complementary input, and should be grounded via a capacitor. 8 (7) fin i prescaler input. connection with an external vco should be done with ac coupling. 9 (8) clock i clock input for the 19-bit shift register. data is shifted into the shift register on the rising edge of the clock. (open is prohibited.) 10 (9) data i serial data input using binary code. the last bit of the data is a control bit. (open is prohibited.) control bit = h ; data is transmitted to the programmable reference counter. control bit = l ; data is transmitted to the programmable counter. 11 (10) le i load enable signal input (open is prohibited.) when le is high, the data in the shift register is transferred to a latch, according to the control bit in the serial data. 12 (11) ps i power saving mode control. this pin must be set at l at power-on. (open is prohibited.) ps = h ; normal mode ps = l ; power saving mode 13 (12) zc i forced high-impedance control for the charge pump (with internal pull up resistor.) zc = h ; normal do output. zc = l ; do becomes high impedance. 14 (13) ld/fout o lock detect signal output (ld) /phase comparator monitoring output (fout) . the output signal is selected by lds bit in the serial data. lds = h ; outputs fout (fr/fp monitoring output) lds = l ; outputs ld (h at locking, l at unlocking.) 15 (14) f p o phase comparator output for an external charge pump. 16 (15) f r o phase comparator output for an external charge pump.
mb15e06 4 n block diagram clock data fin le osc out osc in ps d o v p f r ld/ fout f p x fin gnd v cc md zc c n t sw fc lds fr fp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (16) (1) (2) (3) (4) (5) (6) (7) (15) (14) (13) (12) (11) (10) (9) (8) for ssop package for bcc package ( ) crystal oscillator circuit super charger prescaler 64 / 65 , 128 / 129 intermittent mode control (power save) ld / fr / fp selector lock detector phase comparator 19-bit shift register 14-bit latch 3-bit latch binary 14-bit reference counter 7-bit latch 11-bit latch binary 7-bit swallow counter binary 11-bit programmable counter control 1-bit
mb15e06 5 n absolute maximum ragings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit remark min. max. power supply voltage v cc - 0.5 + 4.0 v v p v cc + 6.0 v output voltage v o - 0.5 v cc + 0.5 v input voltage v i - 0.5 v cc + 0.5 v output current i o - 10 + 10 ma open drain withstand voltage v oop - 0.5 + 7.0 v storage temperature t stg - 55 + 125 c parameter symbol value unit remark min. typ. max. power supply voltage v cc 2.7 3.0 3.6 v v p v cc ? 6.0 v input voltage v i gnd ? v cc v operating temperature ta - 40 ?+ 85 c
mb15e06 6 n electrical characteristics *1 : conditions ; v cc = 3.0 v, ta = 25 c, in locking state. *2 : conditions ; ta = 25 c parameter symbol condition value unit min. typ. max. power supply current* 1 i cc fin if = 2500 mhz, fosc = 12 mhz ? 8.0 ? ma power saving current* 2 ips vcc current at ps = l and zc = h ?? 10 m a operating frequency fin ? 100 ? 2500 mhz crystal oscillator operating frequency f osc min. 500 mvp - p3 ? 40 mhz input sensitivity fin vfin if 50 w termination (refer to the test circuit.) C10 ? +2 dbm oscin v osc ? 500 ? v cc mvp - p input voltage data, clock, le, ps, zc v ih ? v cc 0.7 ?? v v il ??? v cc 0.3 input current data, clock, le, ps i ih ?- 1.0 ?+ 1.0 m a i il ?- 1.0 ?+ 1.0 zc i ih ?- 1.0 ?+ 1.0 m a i il pull up input - 100 ? 0 oscin i ih ? 0 ?+ 100 m a i il ?- 100 ? 0 output voltage f pv ol open drain output ?? 0.4 v f r, ld/fout v oh ? v cc - 0.4 ? C v v ol ??? 0.4 do v doh ? v p - 0.4 ? C v v dol ??? 0.4 high impedance cutoff current do i off ??? 1.1 m a output current f pi ol open drain output 1.0 ?? ma f r, ld/fou i oh ???- 1.0 ma i ol ? 1.0 ?? do i doh v cc = 3.0 v, vp = 5 v, v doh = 4.0 v ?- 10.0* 2 ? ma i dol v cc = 3.0 v, vp = 5 v, v dol = 1.0 v ? 10.0* 2 ?
mb15e06 7 n function descriptions pulse swallow function the divide ratio can be calculated using the following equation : f vco = [ (m n) + a] f osc ? r (a < n) serial data input serial data is processed using the data, clock, and le pins. serial data controls the programmable reference divider and the programmable divider separately. binary serial data is entered through the data pin. one bit of data is shifted into the shift register on the rising edge of the clock. when the load enable pin is high, stored data is latched according to the control bit data as follows: table.1 control bit shift register configuration f vco : output frequency of external voltage controlled oscillator (vco) n : preset divide ratio of binary 11-bit programmable counter (5 to 2,047) a : preset divide ratio of binary 7-bit swallow counter (0 a 127) f osc : output frequency of the reference frequency oscillator r : preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383) m : preset divide ratio of modules prescaler (64 or 128) control bit (cnt) destination of serial data h 17 bit latch (for the programmable reference divider) l 18 bit latch (for the programmable divider) lsb data flow msb 123456789101112131415161718 crrrrrrrrrrrrrr n1234567891011121314swfclds t programmable reference counter cnt : control bit [table. 1] r1 to r14 : divide ratio setting bit for the programmable reference counter (5 to 16,383) [table. 2] sw : divide ratio setting bit for the prescaler (64/65 or 128/129) [table. 5] fc : phase control bit for the phase comparator [table. 7] lds : ld/fout signal select bit [table. 6] note : start data input with msb first
mb15e06 8 table2. binary 14-bit programmable reference counter data setting note : divide ratio less than 5 is prohibited. table.3 binary 11-bit programmable counter data setting note : divide ratio less than 5 is prohibited. divide ratio (n) range = 5 to 2,047 divide ratio (r) r 14 r 13 r 12 r 11 r 10 r 9 r 8 r 7 r 6 r 5 r 4 r 3 r 2 r 1 5 00000000000101 6 00000000000110 16383 1 1 1 1 1 1 1 1 1 1 1 1 1 1 divide ratio (n) n 11 n 10 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 n 1 5 00000000101 6 00000000110 2047 11111111111 lsb data flow msb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 caaaaaaannnnnnnnnnn n12345671234567891011 t programmable reference counter cnt : control bit [table. 1] n1 to n11 : divide ratio setting bits for the programmable counter ( 5 to 2,047 ) [table. 3] a1 to a7 : divide ratio setting bits for the swallow counter ( 0 to 127 ) [table. 4] note : start data input with msb first
mb15e06 9 table.4 binary 7-bit swallow counter data setting note : divide ratio (a) range = 0 to 127 table. 5 prescaler data setting table. 6 ld/fout output select data setting relation between the fc input and phase characteristics the fc bit changes the phase characteristics of the phase comparator. both the internal charge pump output level (d o ) and the phase comparator output ( f r, f p) are reversed according to the fc bit. also, the monitor pin (f out ) output is controlled by the fc bit. the relationship between the fc bit and each of d o , f r, and f p is shown below. table. 7 fc bit data setting (lds = h) * : high impedance divide ratio (a) a 7 a 6 a 5 a 4 a 3 a 2 a 1 0 0000000 1 0000001 127 1111111 sw prescaler divide ratio h 64/65 l 128/129 lds ld/fout output signal h fout signal l ld signal fc = high fc = low do f r f p ld/fout do f r f p ld/fout f r > f p h l l (fr) l h z* (fp) f r < f p l h z* (fr) h l l (fp) f r = f p z* l z* (fr) z* l z* (fp)
mb15e06 10 when designing a synthesizer, the fc pin setting depends on the vco and lpf characteristics. 3. power saving mode (intermittent mode control circuit) setting a ps pin to low, the ic enters into power saving mode resultatly current sonsumption can be limited to 10 m a (max.) . setting ps pin to high, power saving mode is released so that the ic works normally. in addition, the intermittent operation control circuit is included which helps smooth start up from the power saving mode. in general, the power consumption can be saved by the intermittent operation that powering down or waking up the synthesizer. such case, if the pll is powered up uncontrolled, the resulting phase comparator output signal is unpredictable due to an undefined phase relation between reference frequency (f r ) and compar- ison frequency (f p ) and may in the worst case take longer time for lock up of the loop. to prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector during power up, thus keeping the loop locked. during the power saving mode, the corresponding section except for indispensable circuit for the power saving function stops working, then current consumption is reduced to 10 m a (max.) . note : while the power saving mode is executed, zc pin should be set at h or open. if zc is set at l during power saving mode, approximately 10 m a current flows. ps pin must be set l at power-on. the power saving mode can be released (ps : l ? h) 1 m s later after power supply remains stable. during the power saving mode, it is possible to input the serial data. (1) (2) lpf output voltage vco output frequency large high * : when the lpf and vco characteristics are similar to (1) , set fc bit high. * : when the vco characteristics are similar to (2) , set fc bit low. on off v cc clock data le ps (1) (2) (3) t v 3 1 m s t ps 3 100 ns (1) ps = l (power saving mode) at power on (2) set serial data 1 m s later after power supply remains stable (v cc 3 2.2 v) . (3) release power saving mode (ps : l ? h) 100 ns later after setting serial data.
mb15e06 11 table.8 ps pin setting table.9 zc pin setting ps pin status h normal mode l power saving mode zc pin do output h normal output l high impedance
mb15e06 12 n serial data input timing (msb) clock le t 1 t 2 t 5 t 3 t 6 t 0 3 100 ns, t 1 , t 2 , t 4 3 20 ns, t 3 , t 5 3 30 ns, t 6 3 100 ns (lsb) c:control bit t 0 t 4 on rising edge of the clock, one bit of the data is transferred into the shift register.
mb15e06 13 n phase comparator output waveform fr fp ld f p d o h z l f r z f p d o f r t wu t wl l h [fc = "h"] [fc = "l"] note : 1. phase error detection range : - 2 p to + 2 p 2. pulses on do output signal during locked state are output to prevent dead zone. 3. ld output becomes low when phase is t wu or more. ld output becomes high when phase error is t wl or less and continues to be so for three cysles or more. 4. t wu and t wl depend on oscin input frequency. t wu 3 8/fosc (e. g. t wu 3 625ns, foscin = 12.8 mhz) t wl 16/fosc (e. g. t wl 1250ns, foscin = 12.8 mhz) 5. ld becomes high during the power saving mode (ps = l.)
mb15e06 14 n test circuit (for measuring input sensitivity fin/oscin) ? s ?g 50 w 1000 pf s ?g 50 w 1000 pf 0.1 m f 0.1 m f v cc = v p = 3 v 86 43 1 9101112 14 75 2 13 15 16 1000 pf v cc controller (setting divide ratio) oscilloscope note : ssop
mb15e06 15 n typical characteristics 1. fin input sensitivity 2. oscin input sensitivity + 10 0 - 10 - 20 - 30 - 40 fin (mhz) 0 1000 2000 v fin (dbm) 4000 spec v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v ta = + 25 c 3000 vfin vs. fin + 10 - 10 - 20 - 30 - 40 0 vfosc vs. fosc fosc (mhz) 0 50 100 vfosc (dbm) ta = + 25 c v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v spec
mb15e06 16 3. do output current 0 5 10 15 20 0 - 5 - 10 - 15 - 20 5.0 4.0 3.0 2.0 1.0 0 5.0 4.0 3.0 2.0 1.0 0 v cc = 3 v ta = + 25 c v p = 5 v v p = 3 v v oh (v) i oh (ma) v oh vs. i oh v cc = 3 v ta = + 25 c v p = 5 v v p = 3 v v ol (v) i ol (ma) v ol vs. i ol
mb15e06 17 4. fin input impedance 5. oscin input impedance 10.188 w - 36.666 w 1 ghz 10.731 w 1.4438 w 1.5 ghz 16.474 w 31.454 w 2 ghz 1; 2; 3; 4; 29.314 w 50.516 w 2.5 ghz 1 4 3 2 3.516 k w - 43.99 k w 1 mhz 150.5 w - 4.8388 k w 10 mhz 30.13 w - 2.389 k w 20 mhz 1; 2; 3; 4; 12.844 w - 948.37 w 50 mhz 3 1 2 4
mb15e06 18 n reference information s.g spectrum analyzer oscin fin do lpf vco test circuit 15 k w 910 w 0.03 m f 400 pf 3000 pf 10.1339 m s 1.9903829 ms d mkr x : 500.01844 m s 38.00500 mhz 29.99500 mhz 2.000 khz / div y : - 74.8009 mhz 10.1339 m s 1.9903829 ms d mkr x : 500.01844 m s 250.0000 mhz 0 hz 50.00000 mhz / div y : - 74.8009 mhz ref 10 db / 0.0 dbm att 10 db rbw 300 hz vbw 300 hz span 50.0 khz 1.8350000 ghz center ref 10 db / 0.0 dbm att 10 db rbw 10 khz vbw 10 khz span 1.00 mhz 1.83500 ghz center typical plots measured with the test circuit are shown below. each plot shows lock up time, phase noise and reference leakage. fvco = 1835 mhz kv = 87 mhz/v fr = 200 khz fosc = 13 mhz lpf : pll lock up time = 500 m s (1797.6 mhz ? 1872.4 mhz, within 1khz) pll phase noise @ within loop band = 69.4 dbc/h pll reference leakage @ 200 khz offset = 74.6 dbc
mb15e06 19 n application example 10 k w 0.1 m f 1000 pf output v p 12 k w 12 k w 10 k w lpf vco 16 15 13 12 11 10 9 123 4 56 78 0.1 m f 1000 pf lock detect. mb15e06 from a controller f r f p ld/fout zc clock ps le data osc in osc out v p v cc d o gnd xfin fin tcxo 1000 pf vp : 5.5 v max note : 1. 2. ssop-16 in case of using a crystal resonator, it is necessary to optimize matching between the crystal and this lsi, and perform detailed system evaluation. it is recommended to consult with a supplier of the crystal resonator. (reference oscillator circuit provides its own bias, feedback resistor is 100 k w (typ) .)
mb15e06 20 n ordering information part number package remarks MB15E06PFV1 16-pin plastic ssop (fpt-16p-m05) mb15e06pv1 16-pad plastic bcc (lcc-16p-m06)
mb15e06 21 n package dimension 16-pin plastic ssop (fpt-16p-m05) * : these dimensions do not include resin protrusion. dimensions in : mm (inches) c 1994 fujitsu limited f16013s-2c-4 0.50?.20 (.020?008) 0.10?.10(.004?004) (stand off) 0 10 details of "a" part 4.55(.179)ref 5.00?.10(.197?004) * 0.65?.12 5.40(.213) 4.40?.10 6.40?.20 nom (.252?008) (.173?004) * (.0256?0047) .006 ?001 +.002 ?.02 +0.05 0.15 .009 ?002 +.004 ?.05 +0.10 0.22 .049 ?004 +.008 ?.10 +0.20 1.25 0.10(.004) "a" index (mounting height)
mb15e06 22 16-pad plastic bcc (lcc-16p-m06) dimensions in : mm (inches) c 1999 fujitsu limited c16017s-1c-1 0.325?.10 (.013?004) 3.40(.134)typ "a" 0.40?.10 (.016?004) 2.45(.096) 0.80(.031) ref typ 4.55?.10 (.179?004) 0.80(.031)max mounting height 0.075?.025 (.003?001) (stand off) 0.05(.002) 6 9 1 14 9 14 1 6 0.40?.10 (.016?004) 0.75?.10 (.030?004) details of "a" part 1.725(.068) ref 1.15(.045) ref "b" details of "b" part (.024?004) 0.60?.10 (.024?004) 0.60?.10 0.65(.026) typ index area (.134?004) 3.40?.10
mb15e06 all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: 81(44) 754-3763 fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9907 ? fujitsu limited printed in japan

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