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3.3 v dual-loop 50 mbps to 3.3 gbps laser diode driver adn2847 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features 50 mbps to 3.3 gbps operation single 3.3 v operation typical rise/fall time: 80 ps bias current range: 2 ma to 100 ma modulation current range: 5 ma to 80 ma monitor photodiode current: 50 a to 1200 a dual mpd functionality for dwdm 50 ma supply current at 3.3 v closed-loop control of power and extinction ratio full current parameter monitoring laser fail and laser degrade alarms automatic laser shutdown (als) optional clocked data supports fec rates 48-lead (7 mm 7 mm) lfcsp package 32-lead (5 mm 5 mm) lfcsp package applications sonet oc-1/3/12/48 sdh stm-0/1/4/16 fibre channel gigabit ethernet dwdm dual mpd wavelength control general description the adn2847 uses a unique control algorithm to control both average power and extinction ratio of the laser diode (ld) after initial factory setup. external component count and pcb area are low, as both power and extinction ratio control are fully integrated. programmable alarms are provided for laser fail (end of life) and laser de grade (impending fail). optional dual mpd current monitoring is designed into the adn2847 specifically for dwdm wavelength control. the adn2847 is specified for the ?40c to +85c temperature range and is available in a 48-lead lfcsp package and a 32-lead lfcsp package. functional block diagram control datap datan clkp clkn imodp ld v cc v cc gnd aset i mod i bias gnd gnd gnd gnd gnd lbwset idtone pavcap ercap erset pset impd2 impd v cc mpd ibmon immon impdmon impdmon2 als fa i l degrade clksel v cc gnd v cc adn2847 imodn i bias r z 02745-001 figure 1.
adn2847 rev. a | page 2 of 16 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing diagrams.......................................................................... 4 absolute maximum ratings............................................................ 5 thermal resistance ...................................................................... 5 esd caution.................................................................................. 5 die pad coordinates ........................................................................ 6 pin configurations and function descriptions ........................... 7 theory of operation ........................................................................ 9 control........................................................................................... 9 loop bandwidth selection .......................................................... 9 alarms.............................................................................................9 monitor currents ....................................................................... 10 dual mpd dwdm function (48-lead lfcsp only) ......... 10 idtone (48-lead lfcsp only)............................................. 10 data and clock inputs............................................................... 10 ccbias........................................................................................ 10 i bias ................................................................................................ 10 automatic laser shutdown....................................................... 10 alarm interfaces ......................................................................... 11 power consumption .................................................................. 11 laser diode interfacing............................................................. 11 optical supervisor...................................................................... 11 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 15 revision history 10/06rev. 0 to rev. a updated format..................................................................universal change to data sheet title.............................................................. 1 changes to figure 1.......................................................................... 1 changes to specifications ................................................................ 3 added i bias section ......................................................................... 10 changes to laser diode interfacing section............................... 11 changes to figure 14...................................................................... 12 changes to figure 15...................................................................... 13 changes to ordering guide .......................................................... 15 1/03revision 0: initial version
adn2847 rev. a | page 3 of 16 specifications v cc = 3.0 v to 3.6 v. temperature range: ?40c to +85c. all specifications t min to t max , unless otherwise noted. typical values specified at t a = 25c. table 1. parameter min typ max unit conditions/comments laser bias current (i bias , als) output current i bias 2 100 ma i bias when als is asserted 0.1 ma als assertion time 5 s i bias < 10% of nominal i bias compliance voltage 1.2 v cc v ccbias compliance voltage 1.2 v cc v modulation current (imodp, imodn) 1 output current i mod 5 80 ma compliance voltage 1.5 v cc v i mod when als is asserted 0.1 ma rise time 2 80 120 ps see figure 3 for device rise time histogram fall time 2 80 120 ps see figure 4 for device fall time histogram random jitter 2 1 1.5 ps rms pulse width distortion 2 15 ps i mod = 40 ma monitor pd (mpd, mpd2) current 50 1200 a average current compliance voltage 1.65 v power set input (pset) capacitance 80 pf monitor photodiode current into rpset resistor 50 1200 a average current voltage 1.1 1.2 1.3 v extinction ratio set input (erset) allowable resistance range 1.2 25 k voltage 1.1 1.2 1.3 v alarm set (aset) allowable resistance range 1.2 25 k voltage 1.1 1.2 1.3 v hysteresis 5 % control loop low loop bandwidth selection time constant 0.22 sec lbwset = gnd 2.25 sec lbwset = v cc data inputs (datap, datan, clkp, clkn) 3 v p-p (single-ended, peak-to-peak) 100 500 mv data and clock inputs are ac-coupled input impedance (single-ended) 50 t setup 4 50 ps see figure 2 t hold 4 100 ps see figure 2 logic inputs (als, lbwset, clksel) v ih 2.4 v v il 0.8 v alarm outputs (fail, degrade) internal 30 k pull-up v oh 2.4 v v ol 0.8 v idtone user to supply current sink in the range of 50 a to 4 ma compliance voltage v cc ? 1.5 v i out /i in ratio 2 f in 5 0.01 1 mhz
adn2847 rev. a | page 4 of 16 parameter min typ max unit conditions/comments ibmon, immon, impdmon, impdmon2 ibmon, immon division ratio 100 a/a impdmon, impdmon2 1 a/a impdmon to impdmon2 matching 2 % i mpd = 1200 a compliance voltage 0 v cc ?1.2 v supply i cc 6 50 ma i bias = i mod = 0 v cc 7 3.0 3.3 3.6 v 1 the high speed performance for the die ve rsion of adn2847 can be achiev ed when using the bonding diagram shown in figure 6. 2 measured into a 25 load us ing a 11110000 pattern at 2.5 gbps. 3 when the voltage on datap is greater than the voltage on datan, the modulation current flows in the imodp pin. 4 guaranteed by design and characterization. not production tested. 5 idtone can cause eye distortion. 6 i ccmin for power calculation in the power consumption section is the typical i cc given. 7 all v cc pins should be shorted together. timing diagrams datap/ datan setup hold t h t s clkp 02745-002 figure 2. setup and hold time rise time (ps) 0 76 count (%) 10 20 30 40 78 82 84 86 88 90 92 94 96 98 100 80 0 2745-007 figure 3. rise time distribution under worst-case operating conditions 82 86 88 90 92 94 96 98 100 102 104 84 fal l t i m e ( p s) 0 80 count (%) 10 20 30 40 02745-008 figure 4. fall time distribution under worst-case operating conditions
adn2847 rev. a | page 5 of 16 absolute maximum ratings t a = 25c, unless otherwise noted. table 2. parameter rating v cc to gnd 4.2 v digital inputs (als, lbwset, clksel) ?0.3 v to v cc + 0.3 v imodn, imodp v cc + 1.2 v operating temperature range industrial ?40c to +85c storage temperature range ?65c to +150c junction temperature (t j max) 150c power dissipation 1 (w) (t j max ? t a )/ ja lead temperature (soldering 10 sec) 300c 1 power consumption formul ae are provided in the power consumption section. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja unit 48-lead lfcsp 25 c/w 32-lead lfcsp 32 c/w esd caution
adn2847 rev. a | page 6 of 16 die pad coordinates gnd2 v cc 2 imodn imodn gnd2 imodp imodp gnd2 gnd2 i bias i bias ccbias gnd clkn clkp gnd1 datap datan gnd1 v cc 1 gnd pavcap ercap 2280 m 2620 m gnd gnd4 gnd impd v cc 4 impd2 impdmon impdmon2 lbwset aset erset pset gnd2 gnd gnd3 v cc 3g n d clksel als fail degrade idtone gnd2 ibmon immon 02745-003 figure 5. metallization photograph die rotated 90 in package 2280m 1 2620m top bottom left right 02745-004 figure 6. bonding diagram table 4. die pad coordinates 1 pad number pad name x[m] y[m] 1 tp1 (gnd) ?996 1026 2 lbwset ?996 853 3 aset ?996 679 4 erset ?996 506 5 pset ?996 332 6 tp2 (gnd) ?996 159 7 impd ?996 ?15 8 impdmon ?996 506 9 impdmon2 ?996 ?361 10 impd2 ?996 ?534 11 gnd4 ?996 ?724 12 v cc 4 ?995 ?964 13 ercap ?925 ?1191 14 pavcap ?777 ?1191 15 tp3 (gnd) ?606 ?1191 16 v cc 1 ?389 ?1191 17 gnd1 ?200 ?1191 18 datan ?70 ?1191 19 datap 83 ?1191 20 gnd1 263 ?1191 21 clkp 442 ?1191 22 clkn 596 ?1191 23 tp4 (gnd) 762 ?1191 24 tp5 (gnd) 996 ?1109 pad number pad name x[m] y[m] 25 tp6 (gnd) 996 ?935 26 clksel 996 ?762 27 degrade 996 ?589 28 fail 996 ?415 29 als 996 ?242 30 v cc 3 996 ?19 31 gnd3 996 251 32 immon 996 441 33 ibmon 996 614 34 gnd2 996 804 35 idtone 995 993 36 gnd2 995 1133 37 gnd2 867 1191 38 v cc 2 713 1191 39 imodn 500 1191 40 imodn 396 1191 41 gnd2 242 1191 42 imodp 88 1191 43 imodp ?16 1191 44 gnd2 ?239 1191 45 gnd2 ?443 1191 46 i bias ?633 1191 47 i bias ?772 1191 48 ccbias ?912 1191 1 with the origin in the center of the die (see figure 5 ).
adn2847 rev. a | page 7 of 16 pin configurations and function descriptions pin 1 indicator adn2847 top view tp1 1 lbwset 2 aset 3 erset 4 pset 5 tp2 6 impd 7 impdmon 8 impdmon2 9 impd2 10 gnd4 11 v cc 4 12 36 gnd2 35 idtone 34 gnd2 33 ibmon 32 immon 31 gnd3 30 v cc 3 29 als 28 fail 27 degrade 26 clksel 25 tp6 48 ccbias 47 i bias 46 i bias 45 gnd2 44 gnd2 43 imodp 42 imodp 41 gnd2 40 imodn 39 imodn 38 v cc 2 37 gnd2 ercap 13 pavcap 14 tp3 15 v cc 1 16 gnd1 17 datan 18 datap 19 gnd1 20 clkp 21 clkn 22 tp4 23 tp5 24 02745-005 figure 7. 48-lead lfcsp pin 1 indicator adn2847 top view lbwset 1 aset 2 erset 3 pset 4 impd 5 impdmon 6 gnd4 7 v cc 4 8 24 ibmon 23 immon 22 gnd3 21 v cc 3 20 als 19 fail 18 degrade 17 clksel ercap 9 pavcap 10 v cc 1 11 datan 12 datap 13 gnd1 14 clkp 15 clkn 16 32 ccbias 31 i bias 30 gnd2 29 gnd2 28 imodp 27 gnd2 26 imodn 25 v cc 2 02745-006 figure 8. 32-lead lfcsp table 5. pin function descriptions pin umber 4ead 32ead nemonic description 1 n/a tp1 test pin. in normal operation, tp1 = gnd. 2 1 lbwset select low loop bandwidth. 3 2 aset alarm current threshold setting pin. 4 3 erset extinction ratio set pin. 5 4 pset average optical power set pin. 6 n/a tp2 test pin. in normal operation, tp2 = gnd. 7 5 impd monitor photodiode input. 8 6 impdmon mirrored current from monitor photodiode. 9 n/a impdmon2 mirrored current from monito r photodiode 2. (for use with two mpds). 10 n/a impd2 monitor photodiode in put 2. (for use with two mpds). 11 7 gnd4 supply ground. 12 8 v cc 4 supply voltage. 13 9 ercap extinction ratio loop capacitor. 14 10 pavcap average power loop capacitor. 15 n/a tp3 test pin. in normal operation, tp3 = gnd. 16 11 v cc 1 supply voltage. 17 n/a gnd1 supply ground. 18 12 datan data, negative differential terminal. 19 13 datap data, positive differential terminal. 20 14 gnd1 supply ground. 21 15 clkp data clock positive differential terminal. used if clksel = v cc . 22 16 clkn data clock negative differential terminal. used if clksel = v cc . 23 n/a tp4 test pin. in normal operation, tp4 = gnd. 24 n/a tp5 test pin. in normal operation, tp5 = gnd. 25 n/a tp6 test pin. in normal operation, tp6 = gnd. 26 17 clksel clock select. active = v cc . used if data is clocked into chip. 27 18 degrade degrade alarm output. 28 19 fail fail alarm output. 29 20 als automatic laser shutdown. 30 21 v cc 3 supply voltage.
adn2847 rev. a | page 8 of 16 pin number 48-lead 32-lead mnemonic description 31 22 gnd3 supply ground. 32 23 immon modulation current mirror output. 33 24 ibmon bias current mirror output. 34 n/a gnd2 supply ground. 35 n/a idtone idtone. requires external current sink to ground. 36 n/a gnd2 supply ground. 37 n/a gnd2 supply ground. 38 25 v cc 2 supply voltage. 39 26 imodn modulation current negative output. connect via a matching resistor to v cc . 40 n/a imodn modulation current negative output. connect via a matching resistor to v cc . 41 27 gnd2 supply ground. 42 28 imodp modulation current positive output. connect to laser diode. 43 n/a imodp modulation current positive output. connect to laser diode. 44 29 gnd2 supply ground. 45 30 gnd2 supply ground. 46 31 i bias laser diode bias current. 47 n/a i bias laser diode bias current. 48 32 ccbias extra laser diode bias. (connected to vcc when dc-coupled to laser diode. connected to i bias when ac-coupled to laser diode).
adn2847 rev. a | page 9 of 16 theory of operation laser diodes have current-in to light-out transfer functions, as shown in figure 9 . two key characteristics of this transfer function are the threshold current, i th , and the slope in the linear region beyond the threshold current, referred to as slope efficiency (li). er = p av = p1 p0 p1 + p0 2 p li = i th current p1 p av p0 optical power p i i 02745-009 figure 9. laser transfer function control a monitor photodiode (mpd) is required to control the ld. the mpd current is fed into the adn2847 to control the power and extinction ratio, continuously adjusting the bias current and modulation current in response to the changing threshold current and light-to-current slope efficiency of the laser. the adn2847 uses automatic power control (apc) to maintain a constant average power over time and temperature. the adn2847 uses closed-loop extinction ratio control to allow optimum setting of the extinction ratio for every device. thus, sonet/sdh interface standards can be met over device variation, temperature, and laser aging. closed-loop modulation control eliminates the need to either overmodulate the ld or include external components for temperature compensation. this reduces research and development time and second sourcing issues caused by characterizing lds. average power and extinction ratio are set using the pset pin and the erset pin, respectively. potentiometers are connected between these pins and ground. the potentiometer r pset is used to change the average power. the potentiometer r erset is used to adjust the extinction ratio. both pset and erset are kept 1.2 v above gnd. the r pset and r erset potentiometers can be calculated using the following formulas: () v2.1 av pset i r = () 1 1 v2.1 _ av cw cwmpd erset p er er p i r + ? = where: i av is the average mpd current. p cw is the dc optical power specified on the laser data sheet. i mpd_cw is the mpd current at that specified p cw . p av is the average power required. er is the desired extinction ratio (er = p1/p0). note that i erset and i pset changes from device to device; however, the control loops determines actual values. it is not required to know exact values for li or mpd optical coupling. loop bandwidth selection for continuous operation, the user should hardwire the lbwset pin high and use 1 f capacitors to set the actual loop bandwidth. these capacitors are placed between the pavcap pin and the ercap pin and ground. it is important that these capacitors are low leakage multilayer ceramics with an insulation resistance greater than 100 g or a time constant of 1000 seconds, whichever is less. table 6. operation mode lbwset recommended pavcap recommended ercap continuous 50 mbps to 3.3 gbps high 1 f 1 f optimized for 2.5 gbps to 3.3 gbps low 22 nf 22 nf setting lbset low and using 22 nf capacitors results in a shorter loop time constant (a 10 reduction over using 1 f capacitors and keeping lbwset high.) alarms the adn2847 is designed to allow interface compliance to itut-g958 (11/94) section 10.3.1.1.2 (transmitter fail) and section 10.3.1.1.3 (transmitter degrade). the adn2847 has two active high alarms, degrade and fail. a resistor between ground and the aset pin is used to set the current at which these alarms are raised. the current through the aset resistor is a ratio of 100:1 to the fail alarm threshold. the degrade alarm is raised at 90% of this level. example: ma45 soma50 = = degrade fail i i a500 100 ma50 100 === fail aset i i k 4.2 a500 2.1 v2.1 === aset aset i r where the smallest valid value for r aset is 1.2 k, because this corresponds to the i bias maximum of 100 ma.
adn2847 rev. a | page 10 of 16 the laser degrade alarm, degrade, is provided to give a warning of imminent laser failure if the laser diode degrades further or environmental conditions continue to stress the ld, such as increasing temperature. the laser fail alarm, fail, is activated when the transmitter can no longer be guaranteed to be sonet/sdh compliant. this occurs when one of the following conditions arises: ? the aset threshold is reached. ? the als pin is set high. this shuts off the modulation and bias currents to the ld, resulting in the mpd current dropping to zero. this gives closed-loop feedback to the system that als has been enabled. degrade is raised only when the bias current exceeds 90% of aset current. monitor currents ibmon, immon, impdmon, and impdmon2 are current controlled current sources from v cc . they mirror the bias, modulation, and mpd current for increased monitoring functionality. an external resistor to gnd gives a voltage proportional to the current monitored. if the monitoring functions impdmon and impdmon2 are not required, the impd pin and the impd2 pin must be grounded and the monitor photodiode output must be connected directly to the pset pin. dual mpd dwdm function (48-lead lfcsp only) the adn2847 has circuitry for a second monitor photodiode, mpd2. the second photodiode current is mirrored to impdmon2 for wavelength control purposes and is summed internally with the first monitor photodiode current for the power control loop. for single mpd circuits, the mpd2 pin is tied to gnd. this enables the system designer to use the two currents to control the wavelength of the laser diode using various optical filtering techniques inside the laser module. if the monitor current functions impdmon and impdmon2 are not required, then the impd pin and impd2 pin can be grounded and the monitor photodiode output can be connected directly to pset. idtone (48-lead lfcsp only) the idtone pin is supplied for fiber identification/supervisory channels or control purposes in wdm. this pin modulates the optical one level over a possible range of 2% of minimum i mod to 10% of maximum i mod . the level of modulation is set by con- necting an external current sink between the idtone pin and ground. there is a gain of two from this pin to the i mod current. figure 12 shows how the ad9850/ad9851 or the ad9834 can be used with the adn2847 to allow fiber identification. if the id_tone function is not used, the idtone pin should be tied to v cc . note that using idtone during transmission can cause optical eye degradation. data and clock inputs data and clock inputs are ac-coupled (10 nf capacitors are recommended) and terminated via a 100 internal resistor between datap and datan, and also between the clkp pin and the clkn pin. there is a high impedance circuit to set the common-mode voltage that is designed to allow for maximum input voltage headroom over temperature. it is necessary that ac coupling is used to eliminate the need for matching between common-mode voltages. adn2847 r = 2.5k ? , data r = 3k ? , clk (to flip-flops) 400a typ datap datan v reg r 50 ? 50? 02745-010 figure 10. ac coupling of data inputs for input signals that exceed 500 mv p-p single-ended, it is necessary to insert an attenuation circuit as shown in figure 11 . r1 r2 r3 datap/clkp datan/clkn r in adn2847 notes 1. r in = 100 ? = the differential input impedance of the adn2847. 02745-011 figure 11. attenuation circuit ccbias when the laser is used in ac-coupled mode, the ccbias pin and the i bias pin should be tied together ( figure 15 ). in dc- coupled mode, ccbias should be tied to v cc . i bias to achieve optimum eye quality, one pull-up resistor (r z ) is necessary, as shown in both circuits in figure 14 and figure 15 . the recommended resistor r z value is approximately 200 ~ 500 . automatic laser shutdown the adn2847 als allows compliance to itu-t-g958 (11/94), section 9.7. when als is logic high, both bias and modulation currents are turned off. correct operation of als can be confirmed if the fail alarm is raised when als is asserted. note that this is the only time degrade is low while fail is high.
adn2847 rev. a | page 11 of 16 ad9850/ad9851 ad9834 dds 50 ? i out 1.25ma to 20ma i out 50 ? r set controller 37.5a to 600a lp filter (dc-coupled) 500 ? bc550 0.125ma to 2ma 10khz to 1mhz idtone adn2847 35 32 immon 50a to 800a 1k ? 1/2 ad8602 bc550 1.3k ? 1/2 ad8602 clkin ref clock 20mhz to 180mhz 9 21 20 12 02745-012 figure 12. application circuit to allow fiber identification using the ad9850/ad9851 alarm interfaces the fail and degrade outputs have an internal pull-up resistor of 30 k, used to pull the digital high value to v cc . however, the alarm can be overdriven with an external resistor allowing alarm interfacing to non-v cc levels. non-v cc alarm output levels must be below the v cc used for the adn2847. power consumption the adn2847 die temperature must be kept below 125c. both lfcsp packages have an exposed paddle that should be connected in such a manner that is at the same potential as the adn2847 ground pins. the ja for both packages is specified in the absolute maximum ratings section. power consumption can be calculated using i cc = i ccmin + 0.3 i mod p = v cc i cc + ( i bias v bias_pin ) + i mod ( v modp_pin + v modn _ pin )/2 t die = t ambient + ja p thus, the maximum combination of i bias + i mod must be calculated, where: i ccmin = 50 ma (typical value of i cc provided in the specifications section) i bias = i mod = 0 t die = die temperature t ambient = ambient temperature v bias_pin = voltage at i bias pin v modp_pin = average voltage at imodp pin v modn_pin = average voltage at imodn pin laser diode interfacing many laser diodes designed for 2.5 gbps operation are packaged with an internal resistor to bring the effective impedance up to 25 to minimize transmission line effects. in high current applications, the voltage drop across this resistor combined with the laser diode forward voltage makes direct connection between the laser and the driver impractical in a 3 v system. ac coupling the driver to the laser diode removes this headroom constraint. caution must be taken when choosing component values for ac coupling (see figure 15 ) to ensure that the time constants (l/r and rc) are sufficiently long for the data rate and expected number of consecutive identical digits (cids). failure to do this can lead to pattern dependent jitter and vertical eye closure. for designs with low series resistance, or where external components become impractical, the adn2847 supports direct connection to the laser diode (see figure 14 ). in this case, care must be taken to ensure that the voltage drop across the laser diode does not violate the minimum compliance voltage on the imodp pin. optical supervisor the pset and erset potentiometers can be replaced with a dual-digital potentiometer, the adn2850 (see figure 13 ). the adn2850 provides an accurate digital control for the average optical power and extinction ratio and ensures excellent stability over temperature. adn2847 pset erset datap datan idtone datap datan idtone imodp i bias impd adn2850 dac1 dac2 sdi sdo clk tx rx clk cs v cc v cc v cc v cc r z 02745-013 cs figure 13. application using the adn2850 a dual 10-bit digital potentiometer with an extremely low temperature coefficient as an optical supervisor
adn2847 rev. a | page 12 of 16 gnd2 idtone gnd2 ibmon immon gnd3 v cc 3 als fa i l degrade clksel gnd v cc 2 gnd imodn clkn imodn clkp gnd2 gnd1 imodp datap imodp datan gnd2 gnd1 gnd2 v cc 1 gnd i bias i bias pav c a p ercap impd2 impdmon2 impdmon impd gnd pset erset aset lbwset gnd gnd2 ccbias gnd gnd4 v cc 4 adn2847 13 24 36 25 fa i l degrade datap datan clkn clkp gnd v cc 100nf 100nf 100nf 100nf 10f gnd v cc s should have bypass capacitors as close as possible to the actual supply pins on the adn2847 and the laser diode used. conservative decoupling would include 100pf capacitors in parallel with 10nf capacitors. 1 12 1.5k ? 37 48 v cc mpd ld v cc v cc v cc ld = laser diode mpd = monitor photodiode als 1k? 1.5k ? 1.5k ? 10nf 10nf 10nf 10nf 22nf 22nf 10h notes * designates components that need to be optimized for the type of laser used. ** for digital programming, the adn2850 or the adn2860 optical supervisor can be used. * * * * ** ** v cc r z 02745-014 figure 14. dc-coupled 3.3 gbps test circuit, data not clocked
adn2847 rev. a | page 13 of 16 gnd2 idtone gnd2 ibmon immon gnd3 v cc 3 als fa i l degrade clksel gnd v cc 2 gnd imodn clkn imodn clkp gnd2 gnd1 imodp datap imodp datan gnd2 gnd1 gnd2 v cc 1 gnd i bias i bias pavcap ercap impd2 impdmon2 impdmon impd gnd pset erset aset lbwset gnd gnd2 ccbias gnd gnd4 v cc 4 adn2847 13 24 36 25 fai l degrade datap datan clkn clkp gnd v cc 100nf 100nf 100nf 100nf 10f gnd v cc s should have bypass capacitors as close as possible to the actual supply pins on the adn2847 and the laser diode used. conservative decoupling would include 100pf capacitors in parallel with 10nf capacitors. 1 12 1.5k ? 37 48 v cc v cc v cc mpd ld ld = laser diode mpd = monitor photodiode als 1k ? 1.5k ? 1.5k ? 10nf 10nf 10nf 10nf 1f 1f 1h notes * designates components that need to be optimized for the type of laser used. ** for digital programming, the adn2850 or the adn2860 optical supervisor can be used. * * * * * * * * ** ** * * v cc r z 02745-015 figure 15. ac-coupled 50 mbps to 3.3 gbps test circuit, data not clocked 02745-016 figure 16. 2.5 gbps optical eye at 25c. average power = 0 dbm, extinction ratio = 10 db, prbs 31 pattern. eye obtained using a dfb laser. 02745-017 figure 17. 2.5 gbps optical eye at 85c. average power = 0 dbm, extinction ratio = 10 db, prbs 31 pattern. eye obtained using a dfb laser.
adn2847 rev. a | page 14 of 16 outline dimensions compliant to jedec standards mo-220-vhhd-2 0.30 0.23 0.18 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 12 max 1.00 0.85 0.80 seating plane coplanarity 0.08 1 32 8 9 25 24 16 17 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indicator top view 5.00 bsc sq 4.75 bsc sq 3.25 3.10 sq 2.95 pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bottom view) figure 18. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-2) dimensions shown in millimeters pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vkkd-2 figure 19. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp-48-1) dimensions shown in millimeters
adn2847 rev. a | page 15 of 16 ordering guide model temperature range package description package option adn2847acp-32 ?40c to +85c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-2 adn2847acp-32-rl ?40c to +85c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-2 adn2847acp-32-rl7 ?40c to +85c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-2 adn2847acpz-32 1 ?40c to +85c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-2 ADN2847ACPZ-32-RL 1 ?40c to +85c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-2 ADN2847ACPZ-32-RL7 1 ?40c to +85c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-2 adn2847acp-48 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-1 adn2847acp-48-rl ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-1 adn2847acpz-48 1 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-1 eval-adn2847-32-op optical evaluation board eb-adn2847/8-32-ac optical evaluation board 1 z = pb-free part.
adn2847 rev. a | page 16 of 16 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c02745-0-10/06(a)

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