13-bit to 26-bit registered buffer pc2700-/pc3200-compliant cy2sstv16859 rev 1.0, november 21, 2006 page 1 of 7 2200 laurelwood road, santa clara, ca 95054 tel:(4 08) 855-0555 fax:(408) 855-05 50 www.spectralinear.com features ? differential clock inputs up to 280 mhz ? supports lvttl switching levels on the reset# pin ? output drivers have controlled edge rates, so no external resistors are required. ? two kv esd protection ? latch-up performance exceeds 100 ma per jesd78, class ii ? 64-pin tssop/jedec and 56-pin qfn package avail- ability ? jedec specification supported description this 13-bit to 26-bit registered buffer is designed for 2.3v to 2.7 vdd operations. all inputs are compatible with the jedec standard for sstl-2, except the lvcmos reset (rese t#) input. all outputs are sstl_2, class ii compatible. the cy2sstv16859 operates from a differential clock (clk and clk#) of frequency up to 280 mhz. data are registered at crossing of clk going high and clk# going low. when reset# is low, the diff erential input receivers are disabled, and undriven (floating) data and clock inputs are allowed. the lvcmos reset# input must al ways be held at a valid logic high or low level. to ensure defined outputs from the register before a stable clock has been supplied, reset# must be held in the low state during power up. in the ddr dimm application, reset# is completely asynchronous with respect to clk# and clk. therefore, no timing relationship can be guaranteed between the two. when entering reset, the register is cleared and the outputs are driven low quickly, relative to the time to disable the differential input receivers, thus ensuri ng no glitches on the output. however, when coming out of reset, the register becomes active quickly, relative to the time to enable the differential input receivers. block diagram pin configuration d1 vref clk # q1a q1b to 12 other channels clk reset # d c r 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 q13a q12a q11a q10a q9a vddq gnd q8a q7a q6a q5a q4a q3a q2a gnd q1a q13b vddq q12b q11b q10b q9b q8b q7b q6b gnd vddq q5b q4b q3b q2b q1b 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 cy2sstv16859 vddq gnd d13 d12 vdd vddq gnd d11 d10 d9 gnd d8 d7 reset # gnd clk # clk vddq vdd vref d6 gnd d5 d4 d3 gnd vddq vdd d2 d1 gnd vddq
cy2sstv16859 rev 1.0, november 21, 2006 page 2 of 7 pin configuration (continued) 56 qfn package 1 2 3 4 5 6 7 8 9 10 11 12 13 q7a q5a q6a q4a q3a q2a q1a q13b vddq q12b q11b q10b q9b 14 q8b 27 26 25 24 23 22 21 20 19 18 17 16 15 q7b vddq q6b q5b q4b q3b q2b q1b vddq d1 d2 vdd vddq 28 d3 42 41 40 39 38 37 36 35 34 33 32 31 30 d10 d8 d9 d7 reset# gnd clk# clk vddq vdd vref d6 d5 29 d4 44 45 46 47 48 49 50 51 52 53 54 55 56 q8a q9a vddq q10a q11a q12a q13a vddq gnd d13 d12 vdd vddq 43 d11 pin description pin name description tssop qfn 51 38 reset# disable clocking and reset latch 7,15,34,39,43,50, 54,58,63 37,48 gnd ground 37,46,60 26,33,45 vdd supply voltage 6,18,27,33,38,47,59,64 9, 17,23,27,34,44,49,55 vddq supply voltage, quiet 45 32 vref reference voltage for data inputs d(1:13) 16,14,13,12,11,10,9,8,5, 4,3,2,1 7,6,5,4,3,2,1,5 6,54,53,52,51,50 qa(1:13) data outputs 32,31,30,29,28,25 ,24,23,22,21,20, 19,17 22,21,20,19,18,16,15,14,13,12 11,10,8 qb(1:13) data outputs 35,36,40,41,42,44 ,52,53,55,56,57, 61,62 24,25,28,29,30,31,39,40,41,42 43,46,47 d(1:13) data inputs 48,49 35,36 clk, clk# differential clock signals table 1. function table [1,2,3] inputs output reset# clk clk# d q h ll h hh h l or h l or h x q 0 l x or floating x or floating x or floating l notes: 1. h = high voltage level. 2. l = low voltage level. 3. x = don?t care.
cy2sstv16859 rev 1.0, november 21, 2006 page 3 of 7 absolute maximum conditions [4,5] parameter description condition min. max. unit v term [6] terminal voltage with respect to v ss ?0.5 3.6 v v term [7] terminal voltage with respect to v ss ?0.5 v dd + 0.5 v t stg storage temperature ?65 150c c i out dc output current ?50 50 ma i ik continuous clamp current v i <0 or v i >v ss ?50 50 ma i ok continuous clamp current v o <0 or v o >v dd ?50 50 ma i dd i ss continuous current through each v dd, v ddq or v ss ?100 100 ma recommended operating conditions [8] parameter description min. typ. max. unit v dd supply voltage 2.3 2.5 2.7 v v ddq output supply voltage pc1600,pc2100,pc2700 2.3 2.5 2.7 v pc3200 2.5 2.6 2.7 v v ref reference voltage (v ref = v ddq /2) pc1600,pc2100,pc2700 1.15 1.25 1.35 v pc3200 1.25 1.3 1.35 v v tt termination voltage v ref ? 40 mv v ref v ref + 40 mv v v i input voltage 0 ? v dd v v ih ac data input high-level voltage v ref + 310 mv ? ? v v il ac data input low-level voltage ? ? v ref ? 310 mv v v ih dc data input high-level voltage v ref + 150 mv ? ? v v il dc data input low-level voltage ? ? v ref ? 150 mv v v ih reset# input high-level voltage 1.7 ? ? v v il reset# input low-level voltage ? ? 0.7 v v icr clk, clk# common-mode input voltage range 0.97 ? 1.53 v v i(pp) clk, clk# peak-to-peak input voltage 360 ? ? mv i oh high-level output current ? ? ?20 ma i ol low-level output current ? ? 20 ma t a operating free-air temperature 0 ? 85 c dc electrical specifications parameter description condition vdd min. typ. [9] max. unit v ik clamp voltage i i = ?18 ma 2.3v ? ? ?1.2 v v oh high level output voltage i oh = ?100 a 2.3 to 2.7v v dd ? 0.2 ? ? v i oh = ?16 ma 2.3v 1.95 ? ? v v ol low level output voltage i ol = 100 a 2.3 to 2.7v ? ? 0.2 v i ol = 16 ma 2.3 ? ? 0.35 v i i all inputs v i = v dd or v ss 2.7v ? ? 5 a i dd static standby reset# = v ss i o = 0 2.7v ? ? 10 a static operating reset# = v dd , v i = v ih(ac) or v il(ac) 2.7 ? ? 40.0 ma notes: 4. the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required. 5. stresses greater than those listed under absolute maximum condit ions may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specificatio n is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. 6. v dd /v ddq terminals. 7. all terminals except v dd . 8. the reset# input of the device must be held at v dd or v ss to ensure proper device operation. 9. all typical values are measured at t amb = 25c
cy2sstv16859 rev 1.0, november 21, 2006 page 4 of 7 i ddd dynamic operating ? clock only reset# = v dd , v i = v ih(ac) or v il(ac), clk and clk# switching 50% duty cycle i o = 0 2.7v ? 30.0 ? a/ clock mhz dynamic operating ? per each data input reset# = v dd , v i = v ih(ac) or v il(ac), clk and clk# switching 50% duty cycle. one data input switching at half clock frequency, 50% duty cycles. 2.7 ? 15.0 ? a/ clock mhz /data input r oh output high i oh = ?20 ma 2.3 to 2.7v 7 ? 20 r ol output low i ol = 20 ma 2.3 to 2.7v 7 ? 20 r o( ) |r oh ? r ol | each separate bit i o = 20 ma, t a = 25c 2.5v ? ? 4 c i data inputs v i = v ref + 310 mv 2.5 2.5 ? 3.5 pf clk and clk# v icr = 1.25v, v i(pp) = 360 mv 2.5 2.5 ? 3.5 pf reset# v i = v dd or v ss 2.5 2.5 ? 3.5 pf ac electrical specifications parameter description v dd = 2.5v 0.2v unit min. max. f clock clock frequency ? 280 mhz t w pulse duration, clk, cl k# high or low 2.0 ? ns t act differential inputs active time (data inputs must be held low after reset# is taken high). ? 22 ns t inact differential inputs inactive time (data and clock inputs must be held at valid levels (not floating) after reset# is taken low). ?22ns t su set-up time, fast slew rate [10, 12] data before clk , clk# 0.75 ? ns set-up time, slow slew rate [11, 12] 0.9 ? ns t h hold time, fast slew rate [10, 12] data after clk , clk# 0.75 ? ns hold time, slow slew rate [11, 12] 0.9 ? ns table 2. switching characteristics over recommended operating conditions [13] parameter from (input) to (output) v dd = 2.5v 0.2v unit min. max. f max 280 ? mhz t phl reset# q 5 ns t pd clk and clk# q 1.1 2.8 ns notes: 10. for data signal input slew rate 1 v/ns. 11. for data signal input slew rate v/ns and < 1 v/ns. 12. clk and clk# signals input slew rates are 1 v/ns. 13. see test circuits and waveforms. ta = 0c to +85c. dc electrical specifications (continued) parameter description condition vdd min. typ. [9] max. unit
cy2sstv16859 rev 1.0, november 21, 2006 page 5 of 7 output buffer characteristics table 3. output buffer voltage vs. current (v/i) characteristics voltage (v) pull-down pull-up min. i(ma) max. i(ma) min. i(ma) max. i(ma) 0 0 0 ?55 ?162 0.1 6 13 ?55 ?161 0.2 10 25 ?54 ?160 0.3 15 38 ?54 ?159 0.4 19 49 ?54 ?157 0.5 23 60 ?54 ?156 0.6 27 71 ?53 ?154 0.7 30 81 ?53 ?152 0.8 34 91 ?53 ?149 0.9 36 100 ?52 ?146 1.0 38 108 ?52 ?143 1.1 40 115 ?52 ?140 1.2 42 123 ?51 ?137 1.3 43 130 ?50 ?134 1.4 44 137 ?48 ?130 1.5 44 144 ?46 ?125 1.6 45 150 ?44 ?120 1.7 45 158 ?40 ?112 1.8 45 165 ?38 ?104 1.9 45 172 ?35 ?96 2.0 45 179 ?31 ?83 2.1 46 185 ?28 ?72 2.2 46 191 ?23 ?60 2.3 46 196 ?19 ?49 2.4 46 201 ?15 ?38 2.5 46 206 ?10 ?27 2.6 46 211 ?5 ?15 2.7 46 216 0 0 table 4. output buffer slew-rate characteristics dv/dt min. max. rise 0.85 v/ns 15.9 v/ns fall 1.00 v/ns 18.9 v/ns
cy2sstv16859 rev 1.0, november 21, 2006 page 6 of 7 parameter measurement information [14] v dd = 2.5v 0.2v timing diagrams from output under test c l = 30 pf r l = 50 ohm v tt * test point figure 1. load circuit [15] t su t h v icr v i(pp) timing input data input v ref * v ref * v il *** v ih ** figure 2. voltage waveforms set-up and hold times v tt t plh t phl v i(pp) v oh v ol input output v icr v tt v icr figure 3. voltage waveforms propagation dela y times [16, 17] t phl v oh lvcmos reset# input output v dd /2 v tt v ih v il v ol figure 4. voltage waveforms propagation delay times v ref *v ref * v ih ** v il *** input t w figure 5. voltage waveforms pulse duration [18,19] lvcmos reset# input i dd v dd t inact v dd /2 0 v v dd /2 10% 90% t act i ddh i ddl figure 6. voltage waveforms enable and disable times low- and high-level enabling ordering information part number package type product flow cy2sstv16859zc 64-pin tssop commercial, 0 to 70c cy2sstv16859zct 64-pin tssop? tape and reel commercial, 0 to 70c cy2sstv16859zi 64-pin tssop industrial, ?40 to 85c CY2SSTV16859ZIT 64-pin tssop ? tape and reel industrial, ?40 to 85c cy2sstv16859lfc 56-pin qfn commercial, 0 to 70c cy2sstv16859lfct 56-pin qfn ? tape and reel commercial, 0 to 70c cy2sstv16859lfi 56-pin qfn industrial, ?40 to 85c cy2sstv16859lfit 56-pin qfn? tape and reel industrial, ?40 to 85c notes: 14. all input pulses are supplied by generators having the following characteristics: prr < 10 mhz, zo = 50-ohm output slew rate = 1 v/ns 20% (unless otherwise specified). 15. c l includes probe and jig capacitance. 16. the outputs are measured one at a time with one transition per measurement. 17. *v tt = v ref = v ddq /2. 18. **v ih = v ref + 350 mv (ac voltage levels). 19. ***v il = v ref - 350 mv (ac voltage levels).
rev 1.0, november 21, 2006 page 7 of 7 cy2sstv16859 while sli has reviewed all information herein for accuracy and re liability, spectra linear inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. this product i s intended for use in normal commercial applications and is not warranted nor is it inte nded for use in life support, critical medical instruments, o r any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursu ant to additional processing by spectra linear in c., and expressed written agreement by spectra linear inc. spectra linear inc. reserves the righ t to change any circuitry or specification without notice. package drawing and dimension 64-lead thin shrunk small outline package (6 mm x 17 mm) z64 56-lead qfn 8 x 8 mm lf56a
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