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triple , 200 ma, low noise, high psrr voltage regulator adp322/adp323 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 analog devices, inc. all ri ghts reserved. features fixed (adp322) and adjustable output (adp323) options bias v oltage range (vbias) : 2.5 v to 5.5 v ldo input voltage range ( vin1/vin 2, vin3): 1.8 v to 5. 5 v three 200 ma low drop out voltage regulators (ldos) 16- lead , 3 mm 3 mm lfcsp initial accura cy: 1% stable with 1 f ceramic output capacitors no noise bypass capacitor required 3 independ e nt l ogic controlled enable s over c urrent and t hermal protection key specifications high psrr 76 db psrr up to 1 k hz 70 db psrr at 10 k hz 60 db psrr at 100 k hz 40 db psrr at 1 mhz low output noise 29 v rms typical output noise at v out = 1.2 v 55 v rms typical output noise at v out = 2.8 v excellent transient response low dropout voltage: 110 mv at 200 ma load 85 a typical ground current at no load , all ldos ena bled 100 s fast turn - on circuit guaranteed 200 ma output current per regulator ? 40 c to + 125 c junction temperature applications mobile phones digital camera s and audio devices portable and battery - powered equipment portable medical devices post dc - to - dc regulation typical application circuits adp322 vbias vout1 gnd vbias 1f off on en1 off on en2 off on en3 + 1f + ldo 1 en ld1 vbias vbias vout2 1f + ldo 2 en ld2 vout3 1f + ldo 3 en ld3 2.5v to 5.5v vin1/vin2 vin3 1f + 1.8v to 5.5v 1.8v to 5.5v 1f + 09288-001 figure 1 . ty pical application circuit for adp322 adp323 vbias vout1 gnd vbias 1f off on en1 off on en2 off on en3 + 1f + ldo 1 en ld1 vbias vbias vout2 1f + ldo 2 en ld2 vout3 fb1 fb2 fb3 1f + ldo 3 en ld3 2.5v to 5.5v vin1/vin2 vin3 1f + 1.8v to 5.5v 1.8v to 5.5v 1f + 09288-053 figure 2 . typical application circuit for adp323 general description t he adp322/adp323 200 ma triple output ldo s combine high psrr , low noise, low quiescent current , and low d ropout voltage to extend the battery life of portable devices and are ideally suited for wireless applications with demanding performance and board space requirements. the adp322/adp323 psrr is greater than 60 d b for frequencies as high as 100 khz while operating with a low headroom voltage . the adp322/adp323 offer much lower n oise performance than competing ldos without the need for a noise bypass capacitor. the adp322/adp323 are available in a miniature 16-lead, 3 mm 3 mm lfcsp package and are stable with tiny 1 f 30% ceramic output capacitors providing the smallest possible board area for a wide variety of portable power needs. the adp322 is available in output voltage combinations rangin g from 0.8 v to 3.3 v and offer s over current and thermal protection to prevent damage in adverse conditions . the apdp323 adjustable triple ldo can be configured for any output voltage between 0.5 v and 5 v with two resistors for each output.
adp322/adp323 rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical application circuits ............................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 input and output capacitor, recommended specifications .. 4 absolute maximum ratings ............................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 15 applications information .............................................................. 16 capacitor selection .................................................................... 16 undervoltage lockout ............................................................... 17 enable feature ............................................................................ 17 current - limit and thermal o verload protection ................. 18 thermal considerations ............................................................ 18 printed circuit board layout considerations ........................ 20 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 21 revision history 9 /10 revision 0: initial version
adp322/adp323 rev. 0 | page 3 of 24 specifications v in 1 /v in2 = v in3 = (v out + 0.5 v) or 1.8 v (whichever is greater), v bias = 2.5 v , en 1 , en2, en3 = v bias , i out 1 = i out2 = i out3 = 1 0 m a, c in = c out 1 = c out2 = c out3 = 1 f, and t a = 25c , unless otherwise noted. table 1 . parameter symbol condition s min typ max unit voltage range input bias voltage range v bias t j = ?40c to +125c 2.5 5.5 v i nput ldo v oltage r ange v in1 /v in2 /v in3 t j = ?40c to +125c 1.8 5.5 v current ground c urrent with all r egulators on i gnd i out = 0 a 85 a i out = 0 a, t j = ?40c to +125c 160 a i out = 10 ma 120 a i out = 10 ma, t j = ?40c to +125c 220 a i out = 200 ma 250 a i out = 200 ma, t j = ?40c to +125c 380 a bias voltage input current i bias 66 a t j = ?40c to +125 c 140 a shutdown current i gnd - sd en1 = en2 = en3 = gnd 0.1 a en1 = en 2 = en3 = gnd, t j = ?40c to +125c 2.5 a feedback input current fb in 0.01 a voltage accuracy o utput voltage accuracy (adp322) v out ?1 +1 % 1 00 a < i out < 200 ma, v in = (v out + 0.5 v) to 5.5 v, t j = ?40c to +125c ?2 +2 % feedback voltage accuracy (adp 323 ) 1 v fb 0.495 0.5 0.505 v 1 00 a < i out < 200 ma, v in = (v out + 0.5 v) to 5.5 v, t j = ?40c to +125c 0.490 0.510 v line regulation ?v out / ?v in v in = (v out + 0.5 v) to 5.5 v 0.01 %/ v v in = (v out + 0.5 v) to 5.5 v, t j = ?40c to +125c ?0.03 +0.03 %/ v load regulation 2 ?v out / ?i out i out = 1 ma to 200 ma 0.001 %/ma i out = 1 ma to 200 ma, t j = ?40c to +125c 0.005 %/ma dropout voltage 3 v dr opout v out = 3.3 v mv i out = 10 ma 6 mv i out = 10 ma, t j = ?40c to +125c 9 mv i out = 200 ma 110 mv i out = 200 ma, t j = ?40c to +125c 17 0 mv start - up time 4 t start - up v out = 3.3 v , all v out initially off, enable any ldo 240 s v out = 0.8 v 100 s v out = 3.3 v, one v out initially on, enable second or third ldo 160 s v out = 0.8 v 20 s current limit threshold 5 i limit 250 360 600 ma thermal shutdown thermal shutdown threshold ts sd t j rising 155 c therma l shutdown hysteresis ts sd - hys 15 c
adp322/adp323 rev. 0 | page 4 of 24 parameter symbol condition s min typ max unit en input en input logic high v ih 2.5 v v bias 5.5 v 1.2 v en input logic low v il 2.5 v v bias 5.5 v 0.4 v en input leakage current v i- leakage en1 = en2 = en3 = v in or gnd 0.1 a en1 = en2 = en3 = v in or gnd, t j = ?40c to +125c 1 a undervoltage lockout uvlo in put bias voltage (vbias) rising uvlo rise 2.45 v input bias voltage (vbias) falling uvlo fal l 2.0 v hysteresis uvlo hys 180 mv output noise out noise 10 hz to 100 khz, v in = 5 v, v out = 3.3 v 63 v rms 10 hz to 100 khz, v in = 5 v, v out = 2.8 v 55 v rms 10 hz to 100 khz, v in = 3.6 v, v out = 2.5 v 50 v rms 10 hz to 100 khz, v in = 3.6 v, v out = 1.2 v 29 v rms power supply rejection ratio psrr v in = 1.8 v, v out = 0.8 v, i out = 100 ma 100 hz 70 db 1 khz 70 db 10 khz 70 db 100 khz 60 db 1 mhz 40 db v in = 3.8 v, v out = 2.8 v, i out = 100 ma 100 hz 68 db 1 khz 62 db 10 khz 68 db 100 khz 60 db 1 mhz 40 db 1 accuracy when v outx is connected directly to fbx . when the vout x v oltage is set by external feedback resistors, the absolute accuracy in adjust mode depends on the tolerances of the resistors used. 2 based on an end - point calculation using 1 ma and 200 ma loads . 3 the dropout voltage specification applies only to output voltages greater than 1.8 v. dropout voltage is defined as the input - to - output voltage differential when the input voltage is set to the nominal output voltage. 4 start - up time is defined as the time between the rising edge o f enx to v outx being at 90% of its nominal value. 5 current - limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. for exampl e, the current limit for a 3 . 0 v output voltage is defined as the current that causes the output volt age to drop to 90% of 3.0 v, that is, 2.7 v. input and output cap acitor, recommended specifications table 2 . parameter symbol conditions min typ max unit minimum input and output capacitance 1 c min t a = ?40c to +125c 0.70 f capacitor esr r esr t a = ?40c to +125c 0 .001 1 1 the minimum input and output capacitance should be greater than 0. 70 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. x7r and x5r type capacitors are recommended; y5v and z5u capacitors are not recommended for us e with ldos.
adp322/adp323 rev. 0 | page 5 of 24 absolute maximum rat ings table 3 . parameter rating v in 1 /vin 2, vin3 , vbias to gnd C 0. 3 v to +6 .5 v v out 1, v out2 , fb1, fb2 to gnd C 0. 3 v to vin1/v in2 vout3 , fb3 to gnd C 0.3 v t o vin 3 en1 , en 2, en3 to gnd C 0.3 v to +6 .5 v storage temperature range C 65c to +150c operating junction temperature range C 40c to +125c soldering conditions jedec j - std -020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure t o absolute maximum rating conditions for extended periods may affect device reliability. thermal data absolute maximum ratings apply individually only, not in combination. the adp322/adp323 triple ldo can be damaged when the junction temperature limits a re exceeded. monitoring ambient temper ature does not guarantee that the junction temperature (t j ) is within the specified temperature limits. in applications with high power dissipation and poor thermal resistance , the max i mum ambient temperature may have to be derated. in applications with moderate power dissipation and low pcb thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. the junction temperature (t j ) of the device is dependent on the ambient temperature (t a ), the po wer dissipation of the device (p d ), and the junction - to - ambien t thermal resistance of the package ( ja ). maximum junction temperature (t j ) is calculated from the ambient temperature (t a ) and power dissipation (p d ) using the following formula : t j = t a + ( p d ja ) junction - to - ambient thermal resistance ( ja ) of the package is based on modeling and ca lculation using a 4 - layer board. the junction - to - ambient thermal resistance is highly dependent on the application and board layout. in applications where high maximum power dissipation exists, close attention to thermal board design is required. the valu e of ja may vary, depending on pcb material, layout, and environmental conditions. the specified values of ja are based on a 4- layer, 4 inch 3 inch circuit board. see jedec jesd 51 - 9 for detailed information on the board construction. for additional i nformation, see the an - 617 application note , microcsp? wafer level chip scale package . jb is the junction to board thermal characterization parameter with units of c / w. jb of the package is based on modeling and calculation using a 4 - layer board. the je sd51 - 12, guidelines for reporting and using package thermal information , states that thermal characterization parameters are not the same as thermal resistances. jb measures the component power flowing through multiple thermal paths rather than a single p ath as in thermal resistance, jb . therefore, jb thermal paths include convection from the top of the package as wel l as radiation from the package , factors that make jb more useful in real - world applications. maximum junction temperature (t j ) is calcula ted from the board temperature (t b ) and power dissipation (p d ) using the following formula: t j = t b + ( p d jb ) see jedec jesd51 - 8 and jesd51 - 12 for more detailed inform - ation about jb . thermal resistance ja and jb are specified for the worst - case cond itions, that is, a device soldered in a circuit board for surface - mount packages. table 4 . package type ja jb unit 16-l ead , 3 mm 3 mm lfcsp 4 9.5 25.2 c/w esd caution
adp322/adp323 rev. 0 | page 6 of 24 pin configuration s and function descrip tions 12 11 10 1 3 4 gnd nc vin3 9 nc en1 vin1/vin2 2 vbias nc 6 vout2 5 vout1 7 nc 8 vout3 16 en2 15 en3 14 nc 13 nc top view (not to scale) adp322 notes 1. nc = no connec t. 2. connect exposed p ad t o ground plane. 09288-002 figure 3. adp322 pin configuration table 5 . adp322 pin function descriptions pin no. mnemonic description 1 en1 enable input for regulator 1. drive en1 high to turn on regulator 1; drive it low to turn off regulator 1. for autom atic startup, connect en1 to vbias . 2 vbias input voltage bias supply. bypass vbias to gnd with a 1 f or greater capacitor. 3 vin1/vin2 regulator input supply for output voltage 1 and output voltage 2 . bypass vin 1/vin2 to gnd with a 1 f or greater capacitor. 4 nc not connected internally . 5 vout1 regulated output voltage 1 . connect a 1 f or greater output capacitor between vout1 and gnd. 6 vout2 regulated output voltage 2 . connect a 1 f or greater output capacitor between vout2 a nd gnd. 7 nc not connected internally . 8 vout3 regulated output voltage 3 . connect a 1 f or greater output capacitor between vout3 and gnd. 9 nc not connected internally . 10 vin3 regulator input supply for output voltage 3 . bypass vin 3 to gnd with a 1 f or greater capacitor. 11 nc not connected internally . 12 gnd ground pin. 13 nc not connected internally . 14 nc not connected internally . 15 en3 enable input for regulator 3. drive en3 high to turn on regulator 3 ; drive it low to turn off regulator 3 . for autom atic startup, connect en3 to vbias . 16 en2 enable input for regulator 2. drive en3 high to turn on regulator 2; drive it low to turn off regulator 2 . for autom atic startup, connect en2 to vbias . ep exposed pad for enhanced thermal per forman ce. connect to copper ground plane .
adp322/adp323 rev. 0 | page 7 of 24 12 11 10 1 3 4 gnd nc vin3 9 fb3 en1 vin1/vin2 2 vbias fb1 6 vout2 5 vout1 7 fb2 8 vout3 16 en2 15 en3 14 nc 13 nc top view (not to scale) adp323 notes 1. nc = no connec t. 2. connect exposed p ad t o ground plane. 09288-054 figure 4. adp323 pin configuration table 6 . adp323 pin function descriptions pin no. mnemonic description 1 en1 enable input for regulator 1. drive en1 high to turn on regulator 1; drive it low to turn off regulator 1. for autom atic startup, connect en1 to vbias . 2 vbias input voltage bias supply. bypass vbias to gnd with a 1 f or greater capacitor. 3 vin1/vin2 regulator input supply for output voltage 1 and output v oltage 2 . bypass vin 1/vin2 to gnd with a 1 f or greater capacitor. 4 fb1 connect the mid point of the voltage divider from vout1 to gnd to set vout1. 5 vout1 regulated output voltage 1 . connect a 1 f or greater output capacitor between vout1 and gnd. 6 vout2 regulated output voltage 2 . connect a 1 f or greater output capacitor between vout2 and gnd. 7 fb2 connect the mid point of the voltage divider from vout2 to gnd to set vout2. 8 vout3 regulated output voltage 3 . connect a 1 f or greate r output ca pacitor between vout3 and gnd. 9 fb3 connect the mid point of the voltage divider from vout3 to gnd to set vout3. 10 vin3 regulator input supply for output voltage 3 . bypass vin 3 to gnd with a 1 f or greater capacitor. 11 nc not connected internally . 12 gnd ground pin. 13 nc not connected internally . 14 nc not connected internally . 15 en3 enable input for regulator 3. drive en3 high to turn on regulator 3 ; drive it low to turn off regulator 3. for autom atic startup, connect en3 to vbias . 16 en2 enab le input for regulator 2. drive en3 high to turn on regulator 2; drive it low to turn off regulator 2. for autom atic startup, connect en2 to vbias . ep exposed pad for enhanced thermal performance. connect to copper ground plane.
adp322/adp323 rev. 0 | page 8 of 24 typical performance characteristics v in1 /v in2 = v in3 =v bias = 4 v, v out1 = 3.3 v, v out 2 = 1. 8 v, v out 3 = 1. 5 v, i out = 10 ma, c in = c out 1 = c out2 = c out3 = 1 f, v enx is the enable voltage, t a = 25c, unless otherwise noted. 3.27 3.28 3.29 3.30 3.31 3.32 3.33 ?40 ?5 25 85 125 t j (c) v out (v) load = 1ma load = 5ma load = 10ma load = 50ma load = 100ma load = 200ma 09288-003 figure 5 . output voltage vs. junction temperature 3.300 3.305 3.310 3.315 3.320 1 10 100 1000 i load (ma) v out (v) 09288-004 figure 6 . output voltage vs. load current 3.300 3.305 3.310 3.315 3.320 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 v in (v) v out (v) load = 1ma load = 5ma load = 10ma load = 50ma load = 100ma load = 200ma 09288-005 figure 7 . output voltage vs. input voltage 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 1.820 ?40 ?5 25 85 125 t j (c) v out (v) load = 1ma load = 5ma load = 10ma load = 50ma load = 100ma load = 200ma 09288-006 figure 8 . output voltage vs. junction temperature 1.800 1.805 1.810 1.815 1.820 1 10 100 1000 i load (ma) v out (v) 09288-007 figur e 9 . output voltage vs. load current 1.800 1.805 1.810 1.815 1.820 2.1 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 v in (v) v out (v) load = 1ma load = 5ma load = 10ma load = 50ma load = 100ma load = 200ma 09288-008 figure 10 . output voltage vs. input voltage
adp322/adp323 rev. 0 | page 9 of 24 1.480 1.485 1.490 1.495 1.500 1.505 1.510 1.515 1.520 ?40 ?5 25 85 125 t j (c) v out (v) load = 1ma load = 5ma load = 10ma load = 50ma load = 100ma load = 200ma 09288-009 figure 11 . output voltage vs. junction temperature 1.500 1.502 1.504 1.506 1.508 1.510 1 10 100 1000 i load (ma) v out (v) 09288-010 figure 12 . o utput voltage vs. load current 1.500 1.502 1.504 1.506 1.508 1.510 1.80 2.20 2.60 3.00 3.40 3.80 4.20 4.60 5.00 5.40 v in (v) v out (v) load = 1ma load = 5ma load = 10ma load = 50ma load = 100ma load = 200ma 09288-0 11 figure 13 . output voltage vs. input voltage 0 20 40 60 80 100 120 140 ?40 ?5 25 85 125 t j (c) ground current (a) load = 1ma load = 5ma load = 10ma load = 50ma load = 100ma load = 200ma 09288-012 figure 14 . ground current vs. junction temperature, single output loaded 0 20 40 60 80 100 120 1 10 100 1000 i load (ma) ground current (a) 09288-013 figure 15 . ground cur rent vs. load current, single output loaded 0 20 40 60 80 100 120 1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 5.4 v in (v) ground current (a) load = 1ma load = 5ma load = 10ma load = 50ma load = 100ma load = 200ma 09288-014 figure 16 . ground current vs. input voltage, single output loaded
adp322/adp323 rev. 0 | page 10 of 24 0 50 100 150 200 250 300 350 ?40 ?5 25 85 125 t j (c) ground current (a) load = 1ma load = 5ma load = 10ma load = 50ma load = 100ma load = 200ma 09288-015 figure 17 . ground current vs. junction temperature, all outputs loaded equally 0 50 100 150 200 250 300 1 10 100 1000 to tal l oad current (ma) ground current (a) 09288-016 figu re 18 . ground current vs. load current, all outputs loaded equally 0 50 100 150 200 250 300 1.7 2.1 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 v in (v) ground current (a) load = 1ma load = 5ma load = 10ma load = 50ma load = 100ma load = 200ma 09288-017 figure 19 . ground current vs. input voltage, all outputs loaded equally ?40 ?5 25 85 125 t j (c) bias current (a) 0 20 40 60 80 100 120 load = 1ma load = 5ma load = 10ma load = 50ma load = 100ma load = 200ma 09288-018 figure 20 . bias current vs. junction temperature, single output loaded 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 i load (ma) bias current (a) 09288-019 figure 21 . bias current vs. load current, single output load ed 64 66 68 70 72 74 76 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 v in (v) bias current (a) load = 1ma load = 5ma load = 10ma load = 50ma load = 100ma load = 200ma 09288-020 figure 22 . bias current vs. input voltage, single output load ed
adp322/adp323 rev. 0 | page 11 of 24 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 ?50 ?25 0 25 50 75 100 125 t emper a ture (c) shutdown current (a) 3.6 3.8 4.2 4.4 4.8 5.5 09288-021 figure 23 . shutdown current vs. temperature at various input voltages 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 load (ma) dropout (mv) 09288-022 figure 24 . dropout voltage vs. load current and output voltage, v out1 = 3.3 v 2.95 3.00 3.05 3.10 3.15 3.20 3.25 3.30 3.35 3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 v in (v) v out (v) load = 1ma load = 5ma load = 10ma load = 50ma load = 100ma load = 200ma 09288-023 figure 25 . output voltage vs. input voltage (i n dropou t), v out1 = 3.3 v 0 50 100 150 200 250 300 350 3.10 3. 15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 v in (v) ground current (a) load = 1ma load = 5ma load = 10ma load = 50ma load = 100ma load = 200ma 09288-024 figure 26 . ground current vs. input voltage ( i n dropout), v out1 = 3.3 v 0 50 100 150 200 250 300 1 10 100 1000 load (ma) dropout (mv) 09288-025 figure 27 . dropout voltage vs. load current and output voltage, v out2 = 1.8 v 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.70 1.80 1.90 2.00 2.10 v in (v) v out (v) load = 1ma load = 5ma load = 10ma load = 50ma load = 100ma load = 200ma 09288-026 figure 28 . output voltage vs. input voltage ( i n dropout), v out2 = 1.8 v
adp322/adp323 rev. 0 | page 12 of 24 load = 1ma load = 5ma load = 10ma load = 50ma load = 100ma load = 200ma 0 20 40 60 80 100 120 140 160 1.70 1.80 1.90 2.00 2.10 v in (v) ground current (a) 09288-027 figure 29 . gr ound current vs. input voltage (i n dropout), v out2 = 1.8 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 psrr (db) 200ma 100ma 10ma 1ma v ripple = 50mv v in = 2.8v v out = 1.8v c out = 1f frequenc y (hz) 10 100 1k 10k 100k 1m 10m 09288-028 figure 30 . power supply rejection ratio vs. frequenc y, 1.8 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 psrr (db) frequenc y (hz) 10 100 1k 10k 100k 1m 10m 200ma 100ma 10ma 1ma v ripple = 50mv v in = 4.3v v out = 3.3v c out = 1f 09288-029 figure 31 . power supply rejection ratio vs. frequency, 3.3 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 psrr (db) frequenc y (hz) 10 100 1k 10k 100k 1m 10m 200ma 100ma 10ma 1ma v ripple = 50mv v in = 2.5v v out = 1.5v c out = 1f 09288-030 figure 32 . power supply rejection ratio vs. frequency, 1.5 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 frequenc y (hz) psrr (db) 1.8v/200ma 1.8v/100ma 1.8v/10ma 1.2v/200ma 1.2v/100ma 1.2v/10ma v ripple = 50mv 1v headroom 1.8v psrr 1.2 xtalk 10 100 1k 10k 100k 1m 10m 09288-031 figure 33 . power supply rejection ratio vs. frequency, channel -to- channel crosstalk 0.01 0.1 1 10 10 100 1k 10k 100k noise spectra l densit y (nv/ hz) 3.3v 1.8v 1.5v frequenc y (hz) 09288-032 figure 34 . output noise spectral density vs. frequency , v in = 5 v, i load = 10 ma
adp322/adp323 rev. 0 | page 13 of 24 0 10 20 30 40 50 60 70 0.001 0.01 0.1 1 10 100 1000 load current (ma) noise (v rms) 3.3v 1.8v 1.5v 09288-033 figure 35 . output noise vs. load current and output voltage, v in = 5 v ch1 100m a ch2 50mv ch3 10mv ch4 10mv m40 s a ch1 44m a 1 2 3 4 t 9.8% b w b w b w b w ? i load1 v out1 v out2 v out3 09288-034 figure 36 . load transient response, i load1 = 1 ma to 200 ma, i load2 = i load3 = 1 ma , ch1 = i load1 , ch2 = v out1 , ch3 = v out2 , ch4 = v out3 1 2 t 10.2% ch1 200m a m40 s a ch1 124m a b w b w ? ch2 50mv i load1 v out1 09288-035 figure 37 . load transient response, i load1 = 1 ma to 200 ma , c out1 = 1 f , ch1 = i load1 , ch2 = v out1 ch2 1 2 t 10.4% ch1 200m a 50mv m40 s a ch1 84m a b w b w ? i load2 v out2 09288-036 figure 38 . load transient response, i load2 = 1 ma to 200 ma, c out2 = 1 f , ch1 = i load2 , ch2 = v out2 ch1 200m a ch2 50mv m40 s a ch1 124m a 1 2 t 10.2% b w b w ? i load3 v out3 09288-037 figure 39 . load transient response, i load3 = 1 ma to 20 0 ma, c out3 = 1 f , ch1 = i load3 , ch2 = v out3 ch3 10mv b w 1 4 3 2 t 15% ch1 1v ch2 10mv m1s a ch1 4.62v b w ch4 10mv b w b w v in v out1 v out2 v out3 09288-038 figure 40 . line transient response, v in = 4 v to 5 v, i load1 = i load2 = i load3 =100 ma , ch1 = v in , ch2 = v out1 , ch3 = v out2 , ch4 = v out3
adp322/adp323 rev. 0 | page 14 of 24 ch2 1 4 3 2 t 12% ch1 1v 10mv m2s a ch1 4.58v b w ch4 10mv b w ch3 10mv b w b w v in v out1 v out2 v out3 09288-039 figure 41 . line transient response , v in = 4 v to 5 v, i load1 = i load2 = i load3 =1 ma , ch1 = v in , ch2 = v out1 , ch3 = v out2 , ch4 = v out3 ch3 ch2 500mv b w 1 2 t 10.2% ch1 1v 500mv m100 s a ch1 540mv b w ch4 500mv b w b w v enx v out1 v out2 v out3 09288-040 figure 42 . turn - on response , i load1 = i load2 = i load3 =100 ma , ch1 = v en x (the enable voltage) , ch2 = v out1 , ch3 = v out2 , ch4 = v out3
adp322/adp323 rev. 0 | page 15 of 24 theory of operation the adp322/adp323 triple ldo are low quiescent current, low dro p out linear regulator s that operate from 1.8 v to 5.5 v on vin1/vin2 and vin3 and provide up to 20 0 ma of current from each o utput . drawing a l ow 250 a quiescent current (typical) at full load makes the adp322/adp323 ideal for battery - operated portable equipment. shutdown current consumption is typically 1 00 na. optimized for use with small 1 f ceramic capacitors, the adp322/adp323 provide ex cellent transient performance. 0.5v ref overcurrent vout1 vout2 vout3 vin1/vin2 gnd en1 vbias vin3 en3 en2 0.5v ref overcurrent 0.5v ref overcurrent internal bias voltages/currents, uvlo and thermal protect shutdown vout1 shutdown vout2 shutdown vout3 09288-041 + ? + ? + ? figure 43 . adp322 internal block diagram 0.5v ref overcurrent vout1 vout2 vout3 fb1 fb2 fb3 vin1/vin2 gnd en1 vbias vin3 en3 en2 0.5v ref overcurrent 0.5v ref overcurrent internal bias voltages/currents, uvlo and thermal protect shutdown vout1 shutdown vout2 shutdown vout3 09288-055 + ? + ? + ? figure 44 . adp323 internal block diagram internally, the adp322 consists of a reference, three error amplifier s, three feedback voltage divider s , and three pmos pass transistor s . output current is delivered via the pmos pass device, which is controlled by the error amplifier. the error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. if the feedback voltage is lower than the reference voltage, the gate of the pmos device is pulled lower, allowing more current to flow and increasing the output voltage. if the feedback voltage is higher than the reference voltage, the gate of the pmos device is pulled higher, allowing less current to flow and decreasing the output voltage. the adp323 is exactly the same as the adp322 except that the output voltage dividers are internally disconnected and the feedback input of the error am plifiers is brought out for each output. the output voltage can be set using the following formula: v out = 0.5 v(1 + r1 / r2 ) + ( fb in )(r1 ) the value of r1 should be less than 200 k to minimize errors in the output voltage caused by the fb x pin input current . for example, when r1 and r2 each equal 200 k , the output voltage is 1.0 v. the output voltage error introduced by the fb x pin input current is 2 mv or 0.20%, assuming a typical fb x pin input current of 10 na at 25c. the adp322 is available in multiple outpu t voltage options ranging from 0.8 v t o 3 . 3 v. the adp322/adp323 use the en 1/ en 2 and en3 pin s to enable and disable the vout1/vout2/vout3 pin s under normal operating conditions. when the en 1/ en2 and en3 pins are high, vout 1/vout2 /vout3 turn on; when t he en 1/ en 2 and en3 pins are low, vout 1/vout2/vout3 turn off. for automatic startup, the en 1/ en2 and en3 pins can be tied to vbias .
adp322/adp323 rev. 0 | page 16 of 24 applications informa tion capacitor selection output capacitor the adp322/adp323 are designed for operation with small, space - saving ceramic capacitors, but the part s function with most commonly used capacitors as long as care is taken with the effective series resistance (esr) value. the esr of the output capacitor affects the stability of the ldo control loop. a minimum of 0.70 f cap acitance with an esr of 1 ? or less is recommended to ensure the stability of the a dp322/adp323 . transient response to changes in load current is also affected by output capacitance. using a larger value of output capacitance i mproves the transient respon se of the adp322/adp323 to la rge changes in the load current. figure 45 show s the transient response for an output capacitance value of 1 f. ch1 100m a ? ch2 50mv ch4 10mv ch3 10mv m40 s a ch1 44m a 1 2 3 4 t 9.8% i load1 v out1 v out2 v out3 09288-042 b w b w b w b w figure 45 . output transient respons e, i load1 = 1 ma to 200 ma, i load2 = 1 ma, i load 3 = 1 ma , ch1 = i load1 , ch2 = v out1 , ch3 = v out 2 , ch 4 = v out 3 input bypass capacitor c onnecting a 1 f capacitor from vin 1 /vin2 , vin3 , and vbias to gnd reduces the circuit sensitivity to the pcb layout, especially wh en long input traces or high source impedance is encountered. if an output capacitance greater than 1 f is required, the input capacitor should be increased to match it. input and output capacitor properties any good quality ceramic capacitor can be used with the adp322/ adp323 , as long as the capacitor meet s the minimum capacit - ance and maximum esr requirements. ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. capacitor s must have an adequate dielectric to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recommended. y5v and z5u dielectrics are not recommended due to their poor temperature and dc bias characteristics. figure 46 depicts the capacitance vs. voltage bias characteristic of a 0402 1 f, 10 v, x5r capacitor. the voltage stability of a capacitor is strongly influ enced by the capacitor size and voltage rating. in general, a capacitor in a larger package or with a higher voltage rating exhibits better stability. the temperature variation of the x5r dielectric is about 15% over the ?40c to +85c tempera ture range and is not a function of the package or voltage rating. 1.2 1.0 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 vo l tage (v) capacitance (f) 09288-043 figure 46 . capacitance vs. voltage bias characteristic
adp322/adp323 rev. 0 | page 17 of 24 use equation 1 to determine the worst - case capacitance , accounting for capacitor va riation over temperature, compo - nen t tolerance, and voltage. c eff = c bias (1 ? tempco ) (1 ? tol ) (1) where: c bias is the effective capacitance at the operating voltage. tempco is the worst - case capacitor temperature coefficient. tol is the worst - case component tolerance. in this example , tempco over ?40 c to +85 c is assumed to be 15% for an x5r dielectric. tol is assumed to be 10%, and c bias is 0.94 f at 1.8 v ( from the graph in figure 46 ). substituting these values in to equation 1 yields c ef f = 0.94 f (1 ? 0.15) (1 ? 0.1) = 0.719 f therefore, the capacitor chosen in this example meets the mini - mum capacitance requirement of the ldo over temperature and tolerance at the chosen output voltage. to guarantee the performance of the adp322/adp323 triple ldo , it is imperative that the effects of dc bias, temperature, and toler ances on the behavior of the capacitors be evaluated for each application. undervoltage lockout the adp322/adp323 ha ve an internal undervoltage lockout circuit that disab les all inputs and the output when the input voltage bias, vbias, is less than approximately 2.2 v. this ensures that the inputs of the adp322/adp323 and the output behave in a predictable manner during power - up. enable feature the adp322/adp323 use the en x pin s to enable and disable the vout x pin s under normal operating conditions. figure 47 shows that, when a rising voltage on en x cross es the active threshold, vout x turns on. when a falling voltage on en x crosses the inactive thr eshold, vout x turns off. enable vo lt age (v) v out (v) 1.4 1.2 1.0 0.8 0.6 0. 4 0. 2 0 0.4 0.6 0.5 0.7 0.9 0.8 1.0 1.1 1.2 v out @ 4.5v in 09288-044 figure 47 . typical enx pin operation as shown in figure 47, the enx pin has built - in hysteresis. this prevents on/off oscillations that can occur due to noise on the en x pin as it passes through the threshold points. the active/inactive thresholds of the en x pin are derived from the v bias voltage. therefore, these thresholds vary with changing input voltage. figure 48 shows typical en x active/ inactive thre sho lds when t he input voltage varies from 2.5 v to 5.5 v (note that v enx is the enable voltage) . input vo lt age (v) enable thresholds 1.00 0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v enx rise v enx f al l 09288-045 figure 48 . typical en x pin s th resholds vs. input voltage the adp322/adp323 us e an internal soft start to limit the inrush current when the output is enabled. the start - up time for the 2.8 v option is approximately 22 0 s from the time the en x active threshold is crossed to when the output reaches 90% of its final value. the s tart - up time is somewhat depende nt on t he output voltage setting and increases slightly as the output voltage increases. ch3 ch2 500mv b w 1 2 t 10.2% ch1 1v 500mv m100 s a ch1 540mv b w ch4 500mv b w b w v enx v out1 v out2 v out3 09288-046 figure 49 . typical start - up time ,i load1 = i load2 = i load 3 = 1 00 ma , ch1 = v en x (the enable voltage) , ch2 = v out1 , ch3 = v out2 , ch 4 = v out 3
adp322/adp323 rev. 0 | page 18 of 24 current - limit and thermal ov erload protection the adp322/adp323 are protected against damage due to excessive power dissipation by current and thermal overload protection circuits. the adp322/adp323 are designed to current limit when the output load reaches 300 ma (typical). when the output load exceeds 300 ma, the output voltage is reduced to maintain a constant current limit. therm al overload protection is built in, which limits the junction temperature to a maximum of 155 c (typical). under extreme conditions (t hat is, high ambient temperature and power dissipation) when the junction temperature starts to rise above 155 c, the output is turned off, reducing the output current to zero. when the junc tion temperature drops below 140 c, the output is turned on again and the output current is restored to its nominal value. consider the case where a hard short from vout x to gnd occurs. at first, the adp322/adp323 limits current so that only 30 0 ma is conducted into the short. if self - heating of the junc tion is great e nough to cause i ts temperature to rise above 155 c, thermal shutdown activates , turning off the output and reducing the output current to zero. as the junction tempera - ture cools and drops below 140 c, the output turns on and conducts 300 ma into the short, again causing the juncti on temperature to rise above 155 c. this thermal osc illation between 140c and 15 5 c causes a current oscillation between 0 ma and 300 ma that continues as long as the short remains at the output. current and thermal limit protections are intended to protect the device against accidental overload conditions. for reliable operation, device power dissipation must be externally limited so that junction temperatures do not exceed 125c. thermal consideratio ns in most applications, the adp322/adp323 do not dissipate a lot of heat due to high efficiency. however, in applications with a high ambient temperature and high supply voltage to output voltage differential, the heat dissipated in the package is large enough that it can cause the junction temperature of the die to exceed the maximum junction temperature of 125c. when the junction temperature exceeds 155 c, the converter enters thermal shutdown. it recovers only after the junction temper ature decrease s below 140 c to prevent any p ermanent damage. therefore, thermal analysis for the chosen application is very important to guarantee reliable performance over all conditions. the junction temperature of the die is the sum of the ambient temperature of the environment and the tempera - tu re rise of the package due to the power dissipation, as shown in equation 2. to guarantee reliable operation, the junction temperature of the adp322/adp323 must not exceed 125c. to ensure that the junction temperature stays below this maximum value, th e u ser must be aware of the parameters that contribute to junction temperature changes. these parameters include ambient tem - perature, power dissipation in the power device, and thermal resistances between the junction and ambi ent air ( ja ). the ja number is dependent on the package assembly compounds used and the amount of copper to which the gnd pins of the package are soldered on the pcb. table 7 shows typical ja values for the adp3 22/adp323 for various pcb copper sizes. table 7 . typical ja values copper size (mm 2 ) adp322/adp323 triple ldo (c/w) jedec 1 4 9.5 100 83.7 500 68.5 1000 64.7 1 device soldered to jedec standard board . the junction temperature of the adp322/adp323 can be calculated from the following equation: t j = t a + ( p d ja ) (2) where: t a is the ambient temperature. p d is the power dissipation in the die, given by p d = [( v in ? v out ) i load ] + ( v in i gnd ) (3) where: i load is the load c urrent. i gnd is the ground current. v in and v out are input and output voltages, respectively. power dissipation due to ground current is quite small and can be ignored. therefore, the junction temperature equation simplifies to t j = t a + { [( v in ? v out ) i load ] ja } (4) as shown in equation 4, for a given ambient temperature, input - to - output voltage differential, and continuous load current, there exists a minimum copper size requirement for the pcb to ensure that the junction temperature does not rise above 125c. figure 50 to figure 53 show junction temperature calculations for different ambient temperatures, total power dissipation , and areas of pcb copper. in cases w here the board temperature is known, the thermal characterization parameter, jb , can be used to estimate the junction temperature rise. t j is calculated from t b and p d using the formula t j = t b + ( p d jb ) (5) the typical jb va lue for the 16 -lead, 3 mm 3 mm lfcsp is 25.2 c / w.
adp322/adp323 rev. 0 | page 19 of 24 0 20 40 60 80 100 120 140 0 0.2 0.4 0.6 0.8 1.0 1.2 total power dissi pa tion (w) junction temper a ture, t j (c) 1000mm 2 500mm 2 100mm 2 50mm 2 jedec t j max 09288-047 figure 50 . junction temperature vs . total power dissipation, t a = 25c 0 20 40 60 80 100 120 140 0 0.2 0.4 0.6 0.8 1.0 1.2 total po wer dissi pa tion (w) junction temper a ture, t j (c) 1000mm 2 500mm 2 100mm 2 50mm 2 jedec t j max 09288-048 figure 51 . junction temperature vs . total power dissipation, t a = 50c 0 20 40 60 80 100 120 140 0 0.2 0.4 0.6 0.8 1.0 1.2 total power dissi pa tion (w) junction temper a ture, t j (c) 1000mm 2 500mm 2 100mm 2 50mm 2 jedec t j max 09288-049 figure 52 . junction temperature vs . total power dissipation, t a = 85c 0 20 40 60 80 100 120 140 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 total power dissi pa tion (w) junction temper a ture, t j (c) t b = 2 5 c t b = 50c t b = 85c t j max 09288-050 figure 53 . junction temperature vs . total power dissipation and board temperature
adp322/adp323 rev. 0 | page 20 of 24 printed circuit boar d layout considerations heat dissipation from the pa ckage can be improved by increasing the amount of copper attached to the pins of the adp322/adp323 . however, as can be seen from table 7 , a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. place the input capacitor as close as possible to the vin x and gnd pins. place the output capacitor s as close as possible to the vout x and gnd pins. use 0402 or 0603 size capacito rs and resistors to achieve the smallest possible footprint solution on boards where area is limited. 09288-051 figure 54 . example of pcb layout, top side 09288-052 figure 55 . example of pcb layout, bottom side
adp322/adp323 rev. 0 | page 21 of 24 outline dimensions 3.10 3.00 sq 2.90 0.30 0.25 0.20 1.65 1.50 sq 1.45 091609-a 1 0.50 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 0.50 0.40 0.30 seating plane 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indicator 0.80 0.75 0.70 compliant to jedec standards mo-229. for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 56. 16-lead lead frame chip scale package [lfcsp_wq] 3 mm 3 mm body, very, very thin quad (cp-16-27) dimensions shown in millimeters ordering guide model 1 temperature range output voltage (v) 2 package description package option branding vout1 vout2 vout3 adp322acpz-115-r7 ?40c to +125c 3.3 v 2.8 v 1.8 v 16-lead lfcsp_wq cp-16-27 lgu adp322acpz-135-r7 ?40c to +125c 3.3 v 2.5 v 1.8 v 16-lead lfcsp_wq cp-16-27 lgt adp322acpz-145-r7 ?40c to +125c 3.3 v 2.5 v 1.2 v 16-lead lfcsp_wq cp-16-27 ljc adp322acpz-155-r7 ?40c to +125c 3.3 v 1.8 v 1.5 v 16-lead lfcsp_wq cp-16-27 lgs ADP322ACPZ-175-R7 ?40c to +125c 2.8 v 1.8 v 1.2 v 16-lead lfcsp_wq cp-16-27 lgr adp322acpz-189-r7 ?40c to +125c 2.5 v 1.8 v 1.2 v 16-lead lfcsp_wq cp-16-27 ljd adp323acpz-r7 ?40c to +125c adjustable adjust able adjustable 16-lead lfcsp_wq cp-16-27 lgq 1 z = rohs compliant part. 2 for additional voltage options, contact a local sales or distribution representative .
adp322/adp323 rev. 0 | page 22 of 24 notes
adp322/adp323 rev. 0 | page 23 of 24 notes
adp322/adp323 rev. 0 | page 24 of 24 notes ? 2010 analog devices, inc. all rights reserv ed. trademarks and registered trademarks are the property of their respective owners. d09288 -0- 9/10(0)

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