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for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. general description the MAX1246/max1247 12-bit data-acquisition systems combine a 4-channel multiplexer, high-bandwidth track/hold, and serial interface with high conversion speed and low power consumption. the MAX1246 oper- ates from a single +2.7v to +3.6v supply; the max1247 operates from a single +2.7v to +5.25v supply. both devices?analog inputs are software configurable for unipolar/bipolar and single-ended/differential operation. the 4-wire serial interface connects directly to spi/ qspi and microwire devices without external logic. a serial strobe output allows direct connection to tms320-family digital signal processors. the MAX1246/ max1247 use either the internal clock or an external seri- al-interface clock to perform successive-approximation analog-to-digital conversions. the MAX1246 has an internal 2.5v reference, while the max1247 requires an external reference. both parts have a reference-buffer amplifier with a ?.5% voltage- adjustment range. these devices provide a hard-wired shdn pin and a software-selectable power-down, and can be programmed to automatically shut down at the end of a conversion. accessing the serial interface auto- matically powers up the MAX1246/max1247, and the quick turn-on time allows them to be shut down between all conversions. this technique can cut supply current to under 60? at reduced sampling rates. the MAX1246/ max1247 are available in a 16-pin dip and a small qsop that occupies the same board area as an 8-pin so. for 8-channel versions of these devices, see the max146/max147 data sheet. ________________________applications portable data logging medical instruments pen digitizers data acquisition battery-powered instruments process control features 4-channel single-ended or 2-channel differential inputs single-supply operation: +2.7v to +3.6v (MAX1246) +2.7v to +5.25v (max1247) internal 2.5v reference (MAX1246) low power: 1.2ma (133ksps, 3v supply) 54a (1ksps, 3v supply) 1a (power-down mode) spi/qspi/microwire/tms320-compatible 4-wire serial interface software-configurable unipolar or bipolar inputs 16-pin qsop package (same area as 8-pin so) MAX1246/max1247 +2.7v, low-power, 4-channel, serial 12-bit adcs in qsop-16 ________________________________________________________________ maxim integrated products 1 v dd i/o sck (sk) mosi (so) miso (si) v ss shdn sstrb dout din sclk cs com agnd dgnd v dd ch3 4.7 f 0.1 f ch0 0v to +2.5v analog inputs MAX1246 cpu +3v vref 0.047 f refadj __________typical operating circuit 19-1071; rev 2; 10/01 part MAX1246 acpe MAX1246bcpe MAX1246acee 0? to +70? 0? to +70? 0? to +70? temp range pin-package 16 plastic dip 16 plastic dip 16 qsop evaluation kit available ordering information ordering information continued at end of data sheet. MAX1246bcee 0? to +70? 16 qsop inl (lsb) ?/2 ? ?/2 ? spi and qspi are registered trademarks of motorola, inc. microwire is a registered trademark of national semiconductor corp. pin configuration appears at end of data sheet.
MAX1246/max1247 +2.7v, low-power, 4-channel, serial 12-bit adcs in qsop-16 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +2.7v to +3.6v (MAX1246); v dd = +2.7v to +5.25v (max1247); com = 0v; f sclk = 2.0mhz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1246?.7? capacitor at vref pin; max1247?xternal reference, vref = 2.5v applied to vref pin; t a = t min to t max ; unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to agnd, dgnd................................................. -0.3v to 6v agnd to dgnd ...................................................... -0.3v to 0.3v ch0?h3, com to agnd, dgnd ............ -0.3v to (v dd + 0.3v) vref to agnd........................................... -0.3v to (v dd + 0.3v) digital inputs to dgnd .............................................. -0.3v to 6v digital outputs to dgnd ........................... -0.3v to (v dd + 0.3v) digital output sink current .................................................25ma continuous power dissipation (t a = +70?) plastic dip (derate 10.53mw/? above +70?) ......... 842mw qsop (derate 8.36mw/? above +70?) ................... 667mw cerdip (derate 10.00mw/? above +70?) .............. 800mw operating temperature ranges MAX1246_c_e/max1247_c_e .......................... 0? to +70? MAX1246_e_e/max1247_e_e........................ -40? to +85? MAX1246_mje/max1247_mje .................... -55? to +125? storage temperature range ............................ -60? to +150? lead temperature (soldering, 10s) ................................ +300? parameter symbol conditions min typ max units dc accuracy (note 1) resolution 12 bits max124_a 0.5 max124_b 1.0 relative accuracy (note 2) inl max1247c 2.0 lsb no missing codes nmc 12 bits max124_a/max124_b 1 differential nonlinearity dnl max124_c 0.8 lsb max124_a 0.5 3 offset error max124_b 0.5 4 lsb gain error (note 3) 0.5 4 lsb gain temperature coefficient 0.25 ppm/ c channel-to-channel offset matching 0.25 lsb dynamic specifications (10khz sine-wave input, 0v to 2.500vp-p, 133ksps, 2.0mhz external clock, bipolar input mode) max124_a/max124_b 70 73 signal-to-noise + distortion ratio sinad max1247c 73 db max124_a/max124_b -88 -80 total harmonic distortion thd up to the 5th harmonic max1247c -88 db max124_a/max124_b 80 90 spurious-free dynamic range sfdr max1247c 90 db channel-to-channel crosstalk 65khz, 2.500v p-p (note 4) -85 db small-signal bandwidth -3db rolloff 2.25 mhz full-power bandwidth 1.0 mhz
MAX1246/max1247 +2.7v, low-power, 4-channel, serial 12-bit adcs in qsop-16 _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +2.7v to +3.6v (MAX1246); v dd = +2.7v to +5.25v (max1247); com = 0v; f sclk = 2.0mhz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1246 4.7f capacitor at vref pin; max1247 external reference, vref = 2.5v applied to vref pin; t a = t min to t max ; unless otherwise noted.) parameter symbol conditions min typ max units conversion rate internal clock, shdn = float 5.5 7.5 internal clock, shdn = v dd 35 65 conversion time (note 5) t conv external clock = 2mhz, 12 clocks/ conversion 6 s track/hold acquisition time t acq 1.5 s aperture delay 30 ns aperture jitter <50 ps shdn = float 1.8 internal clock frequency shdn = v dd 0.225 mhz 0.1 2.0 external clock frequency data transfer only 0 2.0 mhz analog/com inputs unipolar, com = 0v 0 to vref input voltage range, single- ended and differential (note 6) bi p ol ar , c om = v re f / 2 vref / 2 v multiplexer leakage current on/off leakage current, v ch _ = 0v or v dd 0.01 1 a input capacitance 16 pf internal reference (MAX1246 only, reference buffer enabled) vref output voltage t a = +25 c 2.480 2.500 2.520 v vref short-circuit current 30 ma MAX1246_c 30 50 MAX1246_e 30 60 vref temperature coefficient MAX1246_m 30 80 ppm/ c load regulation (note 8) 0ma to 0.2ma output load 0.35 mv internal compensation mode 0 capacitive bypass at vref external compensation mode 4.7 f capacitive bypass at refadj 0.047 f refadj adjustment range v bst = v lx = v in = 28v, v fb = 1.5v 1.5 % external reference at vref (buffer disabled) vref input voltage range (note 9) 1.0 vdd + 50mv v vref input current vref = 2.5v 100 150 v vref input resistance 18 25 k ? shutdown vref input current 0.01 100 a refadj buffer disable threshold vdd - 0.5 v
MAX1246/max1247 +2.7v, low-power, 4-channel, serial 12-bit adcs in qsop-16 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = +2.7v to +3.6v (MAX1246); v dd = +2.7v to +5.25v (max1247); com = 0v; f sclk = 2.0mhz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1246 4.7f capacitor at vref pin; max1247 external reference, vref = 2.5v applied to vref pin; t a = t min to t max ; unless otherwise noted.) parameter symbol conditions min typ max units external reference at refadj internal compensation mode 0 capacitive bypass at vref external compensation mode 4.7 f MAX1246 2.06 reference buffer gain max1247 2.00 v/v MAX1246 50 refadj input current max1247 10 a
MAX1246/max1247 +2.7v, low-power, 4-channel, serial 12-bit adcs in qsop-16 _______________________________________________________________________________________ 5 electrical characteristics (continued) (v dd = +2.7v to +3.6v (MAX1246); v dd = +2.7v to +5.25v (max1247); com = 0v; f sclk = 2.0mhz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1246 4.7f capacitor at vref pin; max1247 external reference, vref = 2.5v applied to vref pin; t a = t min to t max ; unless otherwise noted.) v 3.0 v ih v dd = 3.6v din, sclk, cs input high voltage v dd > 3.6v, max1247 only mv 0.3 psr supply rejection (note 10) v dd = 2.7v to v dd(max) , full-scale input, external reference = 2.500v pf 15 c in din, sclk, cs input capacitance a 0.01 1 i in din, sclk, cs input leakage v 0.2 v hyst din, sclk, cs input hysteresis v 0.8 v il din, sclk, cs input low voltage 2.0 a 4.0 i s shdn input current v 0.4 v sl shdn input low voltage v v dd - 0.4 v sh shdn input high voltage shdn = 0v or v dd na 100 shdn maximum allowed leakage, mid input v v dd / 2 v flt shdn voltage, floating shdn = float shdn = float units min typ max symbol parameter (note 7) v in = 0v or v dd v dd 3.6v i dd conditions positive supply current, MAX1246 a 1.2 2.0 a 0.01 10 i l three-state leakage current v v dd - 0.5 v oh output voltage high v 0.8 v ol output voltage low 0.4 2.70 3.60 pf 15 c out three-state output capacitance MAX1246 cs = v dd (note 7) cs = v dd i source = 0.5ma i sink = 16ma i sink = 5ma v 2.70 5.25 v dd positive supply voltage max1247 0.9 1.5 operating mode, full-scale input 30 70 v dd = 5.25v v dd = 3.6v 3.5 15 v dd = 5.25v v dd = 3.6v 1.2 10 full power-down ma 1.8 2.5 30 70 1.2 10 operating mode, full-scale input fast power-down full power-down ma v 1.1 v dd - 1.1 v sm shdn input mid voltage fast power-down i dd a positive supply current, max1247 digital inputs (din, sclk, cs, shdn) digital outputs (dout, sstrb) power requirements
MAX1246/max1247 +2.7v, low-power, 4-channel, serial 12-bit adcs in qsop-16 6 _______________________________________________________________________________________ __________________________________________typical operating characteristics (v dd = 3v, vref = 2.5v, f sclk = 2mhz, c load = 20pf, t a = +25 c, unless otherwise noted.) 0.5 0 1024 2048 3072 4096 integral nonlinearity vs. code 0.3 -0.3 -0.5 -0.1 0.1 0.4 0.2 -0.4 -0.2 0 max1247-01 code inl (lsb) 0.50 0.00 2.25 2.75 4.25 integral nonlinearity vs. supply voltage 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 v dd (v) inl (lsb) 3.75 5.25 3.25 4.75 max1247-02 MAX1246 max1247 0.00 0.10 0.20 0.30 0.40 0.50 0.05 0.15 0.25 0.35 0.45 -60 -20 20 60 100 140 integral nonlinearity vs. temperature temperature (?) inl (lsb) max1247-03 max1247 MAX1246 v dd = 2.7v timing characteristics (v dd = +2.7v to +3.6v (MAX1246); v dd = +2.7v to +5.25v (max1247); t a = t min to t max ; unless otherwise noted.) note 1: tested at v dd = 2.7v; com = 0v; unipolar single-ended input mode. note 2: relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. note 3: MAX1246 internal reference, offset nulled; max1247 external reference (v ref = +2.500v), offset nulled. note 4: ground on channel; sine wave applied to all off channels. note 5: conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. note 6: the common-mode range for the analog inputs is from agnd to v dd . note 7: guaranteed by design. not subject to production testing. note 8: external load should not change during conversion for specified accuracy. note 9: adc performance is limited by the converter s noise floor, typically 300vp-p. note 10: measured as | v fs (2.7v) - v fs (v dd.max ) | . internal clock mode only (note 7) external clock mode only, figure 2 external clock mode only, figure 1 din to sclk setup figure 1 figure 2 figure 1 max124_ _c/e conditions max124_ _m ns 20 240 figure 1 ns t csh ns 240 t str cs rise to sstrb output disable ns 240 t sdv cs fall to sstrb output enable 240 t sstrb sclk fall to sstrb ns 200 t cl sclk pulse width low ns 200 sclk pulse width high ns 0 cs to sclk rise hold ns 100 t css cs to sclk rise setup ns 240 t tr cs rise to output disable ns 240 t dv cs fall to output enable t ch 20 200 t do sclk fall to output data valid ns 0 t dh din to sclk hold ns s 1.5 t acq acquisition time 0 t sck sstrb rise to sclk rise ns 100 t ds units min typ max symbol parameter
MAX1246/max1247 +2.7v, low-power, 4-channel, serial 12-bit adcs in qsop-16 _______________________________________________________________________________________ 7 ____________________________typical operating characteristics (continued) (v dd = 3v, vref = 2.5v, f sclk = 2mhz, c load = 20pf, t a = +25 c, unless otherwise noted.) 2.00 0.50 2.25 2.75 supply current vs. supply voltage 1.75 1.25 1.50 1.00 0.75 supply voltage (v) supply current (ma) 3.75 5.25 3.25 4.25 4.75 max1247-04 r l = code = 101010100000 c load = 50pf max1247 MAX1246 c load = 20pf 4.0 3.5 0 2.25 2.75 shutdown supply current vs. supply voltage 3.0 2.5 1.5 2.0 1.0 0.5 v dd (v) shutdown supply current ( a) 3.75 5.25 3.25 4.25 4.75 max1247-05 full power-down 2.5020 2.4990 2.25 2.75 internal reference voltage vs. supply voltage 2.5015 2.5005 2.5010 2.5000 2.4995 v dd (v) vref (v) 3.75 5.25 3.25 4.25 4.75 max1247-06 0.8 0.9 1.0 1.1 1.2 1.3 -60 -20 20 60 100 140 supply current vs. temperature temperature ( c) supply current (ma) max1247-07 max1247 MAX1246 r load = code = 101010100000 0 10203040506070 fft plot frequency (khz) amplitude (db) -120 -100 -80 -60 -40 -20 0 20 max1247-10 v dd = 2.7v f in = 10k f sample = 133k 0 0.4 0.8 1.2 1.6 2.0 -60 -20 20 60 100 140 shutdown current vs. temperature temperature ( c) shutdown current ( a) max1247-08 2.494 2.495 2.496 2.497 2.498 2.499 2.500 2.501 -60 -20 20 60 100 140 MAX1246 internal reference voltage vs. temperature temperature ( c) vref (v) max1247-09 v dd = 2.7v v dd = 3.6v 11.0 11.2 11.4 11.6 11.8 12.0 1 10 100 effective number of bits vs. frequency max1247-11 frequency (khz) effective number of bits v dd = 2.7v
MAX1246/max1247 +2.7v, low-power, 4-channel, serial 12-bit adcs in qsop-16 8 _______________________________________________________________________________________ ____________________________typical operating characteristics (continued) (v dd = 3v, vref = 2.5v, f sclk = 2mhz, c load = 20pf, t a = +25 c, unless otherwise noted.) 0.50 0 2.25 2.75 4.25 offset vs. supply voltage 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 v dd (v) offset (lsb) 3.75 3.25 4.75 5.25 max1247-12 0.50 0 2.25 2.75 3.75 gain error vs. supply voltage 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 v dd (v) gain error (lsb) 3.25 4.25 5.25 4.75 max1247-13 0.50 0 2.25 2.75 3.75 channel-to-channel gain matching vs. supply voltage 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 v dd (v) gain matching (lsb) 3.25 4.25 5.25 4.75 max1247-14 0.50 0 -55 -30 45 offset vs. temperature 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 temperature ( ? c) offset (lsb) 20 -5 70 145 120 95 max1247-15 0.50 0 2.25 2.75 4.25 channel-to-channel offset matching vs. supply voltage 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 v dd (v) offset matching (lsb) 3.75 3.25 5.25 4.75 max1247-18 0.50 0 -55 -30 20 gain error vs. temperature 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 temperature ( ? c) gain error (lsb) -5 45 120 145 95 70 max1247-16 0.50 0 -55 -30 20 channel-to-channel gain matching vs. temperature 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 temperature ( ? c) gain matching (lsb) -5 45 145 120 95 70 max1247-17 0.50 0 -55 -30 45 channel-to-channel offset matching vs. temperature 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 temperature ( ? c) offset matching (lsb) 20 -5 70 145 120 95 max1247-19
MAX1246/max1247 +2.7v, low-power, 4-channel, serial 12-bit adcs in qsop-16 _______________________________________________________________________________________ 9 name function 1 v dd positive supply voltage 2 5 ch0 ch3 sampling analog inputs pin 6 com ground reference for analog inputs. com sets zero-code voltage in single-ended mode. must be stable to 0.5lsb. 7 shdn three-level shutdown input. pulling shdn low shuts the MAX1246/max1247 down; otherwise, they are fully operational. pulling shdn high puts the reference-buffer amplifier in internal compensation mode. letting shdn float puts the reference-buffer amplifier in external compensation mode. 12 dout serial data output. data is clocked out at sclk s falling edge. high impedance when cs is high. 11 dgnd digital ground 10 agnd analog ground 8 vref reference-buffer output/adc reference input. reference voltage for analog-to-digital conversion. in internal reference mode (MAX1246 only), the reference buffer provides a 2.500v nominal output, externally adjustable at refadj. in external reference mode, disable the internal buffer by pulling refadj to v dd . 16 sclk serial clock input. clocks data in and out of serial interface. in external clock mode, sclk also sets the conversion speed. (duty cycle must be 40% to 60%.) 15 cs active-low chip select. data will not be clocked into din unless cs is low. when cs is high, dout is high impedance. 14 din serial data input. data is clocked in at sclk s rising edge. 13 sstrb serial strobe output. in internal clock mode, sstrb goes low when the MAX1246/max1247 begin the a/d conversion, and goes high when the conversion is finished. in external clock mode, sstrb pulses high for one clock period before the msb decision. high impedance when cs is high (external clock mode). ______________________________________________________________pin description v dd 6k ? dgnd dout c load 50pf c load 50pf dgnd 6k ? dout a) high-z to v oh and v ol to v oh b) high-z to v ol and v oh to v ol v dd 6k ? dgnd dout c load 50pf c load 50pf dgnd 6k ? dout a) v oh to high-z b) v ol to high-z figure 1. load circuits for enable time figure 2. load circuits for disable time 9 refadj input to the reference-buffer amplifier. to disable the reference-buffer amplifier, tie refadj to v dd .
MAX1246/max1247 +2.7v, low-power, 4-channel, serial 12-bit adcs in qsop-16 10 ______________________________________________________________________________________ _______________detailed description the MAX1246/max1247 analog-to-digital converters (adcs) use a successive-approximation conversion technique and input track/hold (t/h) circuitry to convert an analog signal to a 12-bit digital output. a flexible seri- al interface provides easy interface to microprocessors (ps). figure 3 is a block diagram of the MAX1246/ max1247. pseudo-differential input the sampling architecture of the adc s analog com- parator is illustrated in the equivalent input circuit (figure 4). in single-ended mode, in+ is internally switched to ch0 ch3, and in- is switched to com. in differential mode, in+ and in- are selected from two pairs: ch0/ch1 and ch2/ch3. configure the channels with tables 2 and 3. please note that the codes for ch0 ch3 in the MAX1246/max1247 correspond to the codes for ch2 ch5 in the eight-channel (max146/ max147) versions. in differential mode, in- and in+ are internally switched to either of the analog inputs. this configuration is pseudo-differential to the effect that only the signal at in+ is sampled. the return side (in-) must remain stable within 0.5lsb (0.1lsb for best results) with respect to agnd during a conversion. to accomplish this, connect a 0.1f capacitor from in- (the selected analog input) to agnd. during the acquisition interval, the channel selected as the positive input (in+) charges capacitor c hold . the acquisition interval spans three sclk cycles and ends on the falling sclk edge after the last bit of the input control word has been entered. at the end of the acquisition interval, the t/h switch opens, retaining charge on c hold as a sample of the signal at in+. the conversion interval begins with the input multiplexer switching c hold from the positive input (in+) to the negative input (in-). in single-ended mode, in- is simply com. this unbalances node zero at the comparator s input. the capacitive dac adjusts during the remainder of the conversion cycle to restore node zero to 0v within the limits of 12-bit resolution. this action is equiv- alent to transferring a 16pf x [(v in + ) - (v in -)] charge from c hold to the binary-weighted capacitive dac, which in turn forms a digital representation of the analog input signal. track/hold the t/h enters its tracking mode on the falling clock edge after the fifth bit of the 8-bit control word has been shifted in. it enters its hold mode on the falling clock edge after the eighth bit of the control word has been shifted in. if the converter is set up for single-ended inputs, in- is connected to com, and the converter samples the + input. if the converter is set up for dif- ferential inputs, in- connects to the - input, and the difference of | in+ - in- | is sampled. at the end of the conversion, the positive input connects back to in+, and c hold charges to the input signal. the time required for the t/h to acquire an input signal is a function of how quickly its input capacitance is charged. if the input signal s source impedance is high, the acquisition time lengthens, and more time must be input shift register control logic int clock output shift register +1.21v reference (MAX1246) t/h analog input mux 12-bit sar adc in dout sstrb v dd dgnd agnd sclk din com refadj vref out ref clock +2.500v 20k ? *a 2.00 (max1247) 7 8 9 6 12 13 14 15 16 ch3 5 ch2 4 ch1 3 ch0 2 MAX1246 max1247 cs shdn 1 11 10 2.06* a figure 3. block diagram ch0 ch1 ch2 ch3 com c switch track t/h switch r in 9k ? c hold hold 12-bit capacitive dac vref zero comparator + 16pf single-ended mode: in+ = ch0 ch3, in- = com. differential mode: in+ and in- selected from pairs of ch0/ch1 and ch2/ch3. at the sampling instant, the mux input switches from the selected in+ channel to the selected in- channel. input mux figure 4. equivalent input circuit
MAX1246/max1247 +2.7v, low-power, 4-channel, serial 12-bit adcs in qsop-16 ______________________________________________________________________________________ 11 bit name description 7(msb) start the first logic 1 bit after cs goes low defines the beginning of the control byte. 6 sel2 these three bits select which of the four channels are used for the conversion (tables 2 and 3). 5 sel1 4 sel0 3 uni/bip 1 = unipolar, 0 = bipolar. selects unipolar or bipolar conversion mode. in unipolar mode, an analog input signal from 0v to vref can be converted; in bipolar mode, the signal can range from -vref / 2 to +vref / 2. 2 sgl/dif 1 = single ended, 0 = differential. selects single-ended or differential conversions. in single- ended mode, input signal voltages are referred to com. in differential mode, the voltage difference between two channels is measured (tables 2 and 3). 1 pd1 selects clock and power-down modes. 0(lsb) pd0 pd1 pd0 mode 0 0 full power-down 0 1 fast power-down 1 0 internal clock mode 1 1 external clock mode table 1. control-byte format allowed between conversions. the acquisition time, t acq , is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired. it is calculated by the following equation: t acq = 9 x (r s + r in ) x 16pf where r in = 9k ? , r s = the source impedance of the input signal, and t acq is never less than 1.5s. note that source impedances below 1k ? do not significantly affect the adc s ac performance. higher source impedances can be used if a 0.01f capacitor is connected to the individual analog inputs. note that the input capacitor forms an rc filter with the input source impedance, limiting the adc s signal bandwidth. input bandwidth the adc s input tracking circuitry has a 2.25mhz small-signal bandwidth, so it is possible to digitize high-speed transient events and measure periodic sig- nals with bandwidths exceeding the adc s sampling rate by using undersampling techniques. to avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. analog input protection internal protection diodes, which clamp the analog input to v dd and agnd, allow the channel input pins to swing from agnd - 0.3v to v dd + 0.3v without damage. however, for accurate conversions near full scale, the inputs must not exceed v dd by more than 50mv or be lower than agnd by 50mv. if the analog input exceeds 50mv beyond the sup- plies, do not forward bias the protection diodes of off channels over 4ma. how to start a conversion start a conversion by clocking a control byte into din. with cs low, each rising edge on sclk clocks a bit from din into the MAX1246/max1247 s internal shift register. after cs falls, the first arriving logic 1 bit defines the control byte s msb. until this first start bit arrives, any number of logic 0 bits can be clocked into din with no effect. table 1 shows the control-byte format. the MAX1246/max1247 are compatible with spi / qspi and microwire devices. for spi, select the correct clock polarity and sampling edge in the spi control registers: set cpol = 0 and cpha = 0. micro- wire, spi, and qspi all transmit a byte and receive a byte at the same time. using the typical operating bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (msb) (lsb) start sel2 sel1 sel0 uni/bip sgl/dif pd1 pd0
MAX1246/max1247 +2.7v, low-power, 4-channel, serial 12-bit adcs in qsop-16 12 ______________________________________________________________________________________ circuit, the simplest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the adc, and two more 8-bit trans- fers to clock out the 12-bit conversion result). see figure 19 for MAX1246/max1247 qspi connections. simple software interface make sure the cpu s serial interface runs in master mode so the cpu generates the serial clock. choose a clock frequency from 100khz to 2mhz. 1) set up the control byte for external clock mode and call it tb1. tb1 should be of the format: 1xxxxx11 binary, where the xs denote the particular channel and conversion mode selected. 2) use a general-purpose i/o line on the cpu to pull cs low. 3) transmit tb1 and, simultaneously, receive a byte and call it rb1. ignore rb1. 4) transmit a byte of all zeros ($00 hex) and, simulta- neously, receive byte rb2. 5) transmit a byte of all zeros ($00 hex) and, simulta- neously, receive byte rb3. 6) pull cs high. figure 5 shows the timing for this sequence. bytes rb2 and rb3 contain the result of the conversion, padded with one leading zero and three trailing zeros. the total conversion time is a function of the serial-clock fre- quency and the amount of idle time between 8-bit transfers. to avoid excessive t/h droop, make sure the total conversion time does not exceed 120s. digital output in unipolar input mode, the output is straight binary (figure 16). for bipolar inputs, the output is two s com- plement (figure 17). data is clocked out at the falling edge of sclk in msb-first format. clock modes the MAX1246/max1247 may use either an external serial clock or the internal clock to perform the succes- sive-approximation conversion. in both clock modes, the external clock shifts data in and out of the MAX1246/max1247. the t/h acquires the input signal as the last three bits of the control byte are clocked into din. bits pd1 and pd0 of the control byte program the clock mode. figures 6 9 show the timing characteristics common to both modes. external clock in external clock mode, the external clock not only shifts data in and out, but it also drives the analog-to-digital conversion steps. sstrb pulses high for one clock period after the last bit of the control byte. succes- sive-approximation bit decisions are made and appear at dout on each of the next 12 sclk falling edges (figure 5). sstrb and dout go into a high-impedance state when cs goes high; after the next cs falling edge, sstrb outputs a logic low. figure 7 shows the sstrb timing in external clock mode. the conversion must complete in some minimum time, or droop on the sample-and-hold capacitors may degrade conversion results. use internal clock mode if the serial clock frequency is less than 100khz, or if serial clock interruptions could cause the conversion interval to exceed 120s. sel2 sel1 sel0 ch0 ch1 ch2 ch3 com 00 1 + 10 1 + 01 0 + 11 0 + table 2. channel selection in single-ended mode (sgl/ d d i i f f = 1) sel2 sel1 sel0 ch0 ch1 ch2 ch3 00 1 + 01 0 + 10 1 + 11 0 + table 3. channel selection in differential mode (sgl/ d d i i f f = 0)
MAX1246/max1247 +2.7v, low-power, 4-channel, serial 12-bit adcs in qsop-16 ______________________________________________________________________________________ 13 internal clock in internal clock mode, the MAX1246/max1247 generate their own conversion clocks internally. this frees the p from the burden of running the sar conversion clock and allows the conversion results to be read back at the processor s convenience, at any clock rate from 0mhz to 2mhz. sstrb goes low at the start of the conversion and then goes high when the conversion is complete. sstrb is low for a maximum of 7.5s ( shdn = float), during which time sclk should remain low for best noise performance. an internal register stores data when the conversion is in progress. sclk clocks the data out of this register at any time after the conversion is complete. after sstrb goes high, the next falling clock edge produces the msb of the conversion at dout, followed by the remaining bits in msb-first format (figure 8). cs does not need to be held low once a conversion is started. pulling cs high prevents data from being clocked into the MAX1246/max1247 and three-states dout, but it does not adversely affect an internal clock mode ? ? ? ? ? ? ? ? ? ? ? ? cs sclk din dout t csh t css t cl t ds t dh t dv t ch t do t tr t csh figure 6. detailed serial-interface timing sstrb cs sclk din dout 14 8 12 16 20 24 start sel2 sel1 sel0 uni/ bip sgl/ dif pd1 pd0 b11 msb b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 lsb acquisition (f sclk = 2mhz) idle filled with zeros idle conversion t acq a/d state rb1 rb2 rb3 1.5 s figure 5. 24-clock external clock mode conversion timing (microwire and spi compatible, qspi compatible with f sclk 2mhz)
MAX1246/max1247 +2.7v, low-power, 4-channel, serial 12-bit adcs in qsop-16 14 ______________________________________________________________________________________ conversion already in progress. when internal clock mode is selected, sstrb does not go into a high- impedance state when cs goes high. figure 9 shows the sstrb timing in internal clock mode. in this mode, data can be shifted in and out of the MAX1246/max1247 at clock rates exceeding 2.0mhz if the minimum acquisition time (t acq ) is kept above 1.5s. data framing the falling edge of cs does not start a conversion. the first logic high clocked into din is interpreted as a start bit and defines the first bit of the control byte. a conversion starts on sclk s falling edge, after the eighth bit of the control byte (the pd0 bit) is clocked into din. the start bit is defined as follows: the first high bit clocked into din with cs low any time the converter is idle; e.g., after v dd is applied. or the first high bit clocked into din after bit 5 of a con- version in progress is clocked onto the dout pin. if cs is toggled before the current conversion is com- plete, the next high bit clocked into din is recognized as a start bit; the current conversion is terminated, and a new one is started. sstrb cs sclk din dout 14 8 12 18 20 24 start sel2 sel1 sel0 uni/ bip sgl/ dif pd1 pd0 b11 msb b10 b9 b2 b1 b0 lsb filled with zeros idle conversion 7.5 s max (shdn = float) 2 3 5 6 7 9 10 11 19 21 22 23 t conv acquisition (f sclk = 2mhz) idle a/d state 1.5 s figure 8. internal clock mode timing ? ? ? ? ? ? ? ? ? ? ? ? t sdv t sstrb pd0 clocked in t str sstrb sclk cs t sstrb ? ? ? ? ? ? ? ? figure 7. external clock mode sstrb detailed timing
MAX1246/max1247 +2.7v, low-power, 4-channel, serial 12-bit adcs in qsop-16 ______________________________________________________________________________________ 15 sclk din dout cs s control byte 0 control byte 1 s conversion result 0 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 conversion result 1 sstrb b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 control byte 2 s 1 81 15 15 81 cs sclk din dout s 18 16 18 16 control byte 0 control byte 1 s conversion result 0 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b11 b10 b9 b8 conversion result 1 ? ? ? ? ? ? ? ? ? ? ? ? figure 10a. external clock mode, 15 clocks/conversion timing figure 10b. external clock mode, 16 clocks/conversion timing the fastest the MAX1246/max1247 can run with cs held low between conversions is 15 clocks per conversion. figure 10a shows the serial-interface timing necessary to perform a conversion every 15 sclk cycles in external clock mode. if cs is tied low and sclk is continuous, guarantee a start bit by first clocking in 16 zeros. most microcontrollers (cs) require that conversions occur in multiples of 8 sclk clocks; 16 clocks per con- version is typically the fastest that a c can drive the MAX1246/max1247. figure 10b shows the serial- interface timing necessary to perform a conversion every 16 sclk cycles in external clock mode. pd0 clock in t sstrb t csh t conv t sck sstrb sclk dout t css t do note: for best noise performance, keep sclk low during conversion. cs figure 9. internal clock mode sstrb detailed timing
MAX1246/max1247 +2.7v, low-power, 4-channel, serial 12-bit adcs in qsop-16 16 ______________________________________________________________________________________ __________ applications information power-on reset when power is first applied, and if shdn is not pulled low, internal power-on reset circuitry activates the MAX1246/max1247 in internal clock mode, ready to convert with sstrb = high. after the power supplies stabilize, the internal reset time is 10s, and no conver- sions should be performed during this phase. sstrb is high on power-up and, if cs is low, the first logical 1 on din is interpreted as a start bit. until a conversion takes place, dout shifts out zeros. (also see table 4.) reference-buffer compensation in addition to its shutdown function, shdn selects inter- nal or external compensation. the compensation affects both power-up time and maximum conversion speed. the100khz minimum clock rate is limited by droop on the sample-and-hold and is independent of the compensation used. float shdn to select external compensation. the typical operating circuit uses a 4.7f capacitor at vref. a 4.7f value ensures reference-buffer stability and allows converter operation at the 2mhz full clock speed. external compensation increases power-up time (see the choosing power-down mode section and table 4). pull shdn high to select internal compensation. internal compensation requires no external capacitor at vref and allows for the shortest power-up times. the maximum clock rate is 2mhz in internal clock mode and 400khz in external clock mode. choosing power-down mode you can save power by placing the converter in a low- current shutdown state between conversions. select full power-down mode or fast power-down mode via bits 1 and 0 of the din control byte with shdn high or floating (tables 1 and 5). in both software power-down modes, the serial interface remains operational, but the adc does not convert. pull shdn low at any time to shut down the converter completely. shdn overrides bits 1 and 0 of the control byte. full power-down mode turns off all chip functions that draw quiescent current, reducing supply current to 2a (typ). fast power-down mode turns off all circuitry except the bandgap reference. with fast power-down mode, the supply current is 30a. power-up time can be shortened to 5s in internal compensation mode. table 4 shows how the choice of reference-buffer com- pensation and power-down mode affects both power-up delay and maximum sample rate. in external compensa- tion mode, power-up time is 20ms with a 4.7f compen- sation capacitor when the capacitor is initially fully discharged. from fast power-down, start-up time can be eliminated by using low-leakage capacitors that do not discharge more than 1/2lsb while shut down. in power- down, leakage currents at vref cause droop on the ref- erence bypass capacitor. figures 11a and 11b show the various power-down sequences in both external and internal clock modes. software power-down software power-down is activated using bits pd1 and pd0 of the control byte. as shown in table 5, pd1 and pd0 also specify the clock mode. when software shutdown is asserted, the adc operates in the last specified clock mode until the conversion is complete. then the adc powers down into a low quiescent-current state. in internal clock mode, the interface remains active and conversion results may be clocked out after the MAX1246/max1247 enter a software power-down. the first logical 1 on din is interpreted as a start bit and powers up the MAX1246/ max1247. following the start bit, the data input word or control byte also reference buffer reference- buffer compensation mode vref capacitor (f) power-down mode power-up delay (s) maximum sampling rate (ksps) enabled internal fast 5 26 enabled internal full 300 26 enabled external 4.7 fast see figure 13c 133 enabled external 4.7 full see figure 13c 133 disabled fast 2 133 disabled full 2 133 table 4. typical power-up delay times
MAX1246/max1247 +2.7v, low-power, 4-channel, serial 12-bit adcs in qsop-16 ______________________________________________________________________________________ 17 determines clock mode and power-down states. for example, if the din word contains pd1 = 1, then the chip remains powered up. if pd0 = pd1 = 0, a power-down resumes after one conversion. hardware power-down pulling shdn low places the converter in hardware power-down (table 6). unlike software power-down mode, the conversion is not completed; it stops coin- cidentally with shdn being brought low. shdn also controls the clock frequency in internal clock mode. letting shdn float sets the internal clock frequency to 1.8mhz. when returning to normal operation with shdn floating, there is a t rc delay of approximately 2m ? x c l , where c l is the capacitive loading on the shdn pin. pulling shdn high sets internal clock frequency to 225khz. this feature eases the settling-time requirement for the reference voltage. with an external reference, the MAX1246/ max1247 can be considered fully powered up within 2s of actively pulling shdn high. powered up hardware power- down powered up powered up 12 data bits 12 data bits invalid data valid data external external sx xxxx 11 s 00 xx x x x xx xxx s11 software power-down mode dout din clock mode shdn sets external clock mode sets external clock mode sets software power-down power-down powered up powered up data valid data valid internal sx xxxx 10 s 00 xx x x x s mode dout din clock mode sets internal clock mode sets power-down conversion conversion sstrb figure 11a. timing diagram power-down modes, external clock figure 11b. timing diagram power-down modes, internal clock
MAX1246/max1247 +2.7v, low-power, 4-channel, serial 12-bit adcs in qsop-16 18 ______________________________________________________________________________________ figure 12. average supply current vs. conversion rate with external reference 1000 10,000 0.1 0.1 average supply current vs. conversion rate with external reference 100 10 1 conversion rate (hz) i dd (a) 1 100 10 1k 10k 1m 100k max1247-12 v ref = v dd = 3.0v r load = code = 101010100000 1 channel 4 channels figure 13b. MAX1246 supply current vs. conversion rate, fastpd 10,000 1 0.1 1 average supply current vs. conversion rate (using fastpd) 1000 100 10 conversion rate (hz) i dd ( a) 100 1m 10 1k 10k 100k max1247-f13b r load = code = 101010100000 4 channels 1 channel figure 13a. MAX1246 supply current vs. conversion rate, fullpd 100 1 0.01 0.1 1 average supply current vs. conversion rate (using fullpd) 10 conversion rate (hz) average supply current ( a) 100 10 1k max1247-f13a r load = code = 101010100000 4 channels 1 channel figure 13c. typical reference-buffer power-up delay vs. time in shutdown 2.0 0.0 0.001 0.01 0.1 1 10 typical reference-buffer power-up delay vs. time in shutdown 1.5 1.0 0.5 time in shutdown (sec) power-up delay (msec) max1247-f13c power-down sequencing the MAX1246/max1247 auto power-down modes can save considerable power when operating at less than maximum sample rates. figures 12, 13a, and 13b show the average supply current as a function of the sam- pling rate. the following discussion illustrates the vari- ous power-down sequences. lowest power at up to 500 conversions/channel/second the following examples show two different power-down sequences. other combinations of clock rates, compen- sation modes, and power-down modes may give lowest power consumption in other applications. figure 13a depicts the MAX1246 power consumption for one or four channel conversions utilizing full power- down mode and internal-reference compensation. a 0.047f bypass capacitor at refadj forms an rc filter with the internal 20k ? reference resistor with a 0.9ms time constant. to achieve full 12-bit accuracy, 10 time constants or 9ms are required after power-up. waiting this 9ms in fastpd mode instead of in full power-up can reduce power consumption by a factor of 10 or more. this is achieved by using the sequence shown in figure 14.
MAX1246/max1247 +2.7v, low-power, 4-channel, serial 12-bit adcs in qsop-16 ______________________________________________________________________________________ 19 lowest power at higher throughputs figure 13b shows the power consumption with external-reference compensation in fast power-down, with one and four channels converted. the external 4.7f compensation requires a 200s wait after power-up with one dummy conversion. this circuit combines fast multi-channel conversion with the lowest power consumption possible. full power-down mode may provide increased power savings in applications where the MAX1246/max1247 are inactive for long periods of time, but where intermittent bursts of high-speed conversions are required. internal and external references the MAX1246 can be used with an internal or external reference voltage, whereas an external reference is required for the max1247. an external reference can be connected directly at vref or at the refadj pin. an internal buffer is designed to provide 2.5v at vref for both the MAX1246 and the max1247. the MAX1246 s internally trimmed 1.21v reference is buf- fered with a 2.06 gain. the max1247 s refadj pin is also buffered with a 2.00 gain to scale an external 1.25v reference at refadj to 2.5v at vref. internal reference (MAX1246) the MAX1246 s full-scale range with the internal refer- ence is 2.5v with unipolar inputs and 1.25v with bipo- lar inputs. the internal reference voltage is adjustable to 1.5% with the circuit in figure 15. external reference with both the MAX1246 and max1247, an external ref- erence can be placed at either the input (refadj) or the output (vref) of the internal reference-buffer ampli- fier. the refadj input impedance is typically 20k ? for the MAX1246, and higher than 100k ? for the max1247. 100 din refadj vref 1.21v 0v 2.50v 0v 101 1 1 1100 101 fullpd fastpd nopd fullpd fastpd 9ms wait complete conversion sequence t buffen 200 s = rc = 20k ? x c refadj (zeros) ch1 ch7 (zeros) figure 14. MAX1246 fullpd/fastpd power-up sequence +3.3v 510k 24k 100k 0.047? 9 refadj MAX1246 figure 15. MAX1246 reference-adjust circuit pd1 pd0 device mode 0 0 full power-down 0 1 fast power-down 1 0 internal clock 1 1 external clock table 5. software power-down and clock mode table 6. hard-wired power-down and internal clock frequency shdn state device mode reference buffer compensation internal clock frequency 1 enabled internal 225khz floating enabled external 1.8mhz 0 power-down n/a n/a
MAX1246/max1247 +2.7v, low-power, 4-channel, serial 12-bit adcs in qsop-16 20 ______________________________________________________________________________________ at vref, the dc input resistance is a minimum of 18k ? . during conversion, an external reference at vref must deliver up to 350a dc load current and have 10 ? or less output impedance. if the reference has a higher output impedance or is noisy, bypass it close to the vref pin with a 4.7f capacitor. using the refadj input makes buffering the external reference unnecessary. to use the direct vref input, disable the internal buffer by tying refadj to v dd . in power-down, the input bias current to refadj can be as much as 25a with refadj tied to v dd . pull refadj to agnd to minimize the input bias current in power-down. transfer function table 7 shows the full-scale voltage ranges for unipolar and bipolar modes. the external reference must have a temperature coeffi- cient of 4ppm/ c or less to achieve accuracy to within 1lsb over the 0 c to +70 c commercial temperature range. figure 16 depicts the nominal, unipolar input/output (i/o) transfer function, and figure 17 shows the bipolar input/output transfer function. code transitions occur halfway between successive-integer lsb values. output coding is binary, with 1lsb = 610v (2.5v / 4096) for unipolar operation, and 1lsb = 610v [(2.5v / 2 - -2.5v / 2) / 4096] for bipolar operation. layout, grounding, and bypassing for best performance, use printed circuit boards. wire-wrap boards are not recommended. board layout should ensure that digital and analog signal lines are separated from each other. do not run analog and digi- tal (especially clock) lines parallel to one another, or digital lines underneath the adc package. figure 18 shows the recommended system ground connections. establish a single-point analog ground (star ground point) at agnd, separate from the logic ground. connect all other analog grounds and dgnd to the star ground. no other digital system ground should be connected to this ground. for lowest-noise operation, the ground return to the star ground s power supply should be low impedance and as short as possible. high-frequency noise in the v dd power supply may affect the high-speed comparator in the adc. bypass the supply to the star ground with 0.1f and 1f capacitors close to pin 1 of the MAX1246/max1247. minimize capacitor lead lengths for best supply-noise rejection. if the power supply is very noisy, a 10 ? resis- tor can be connected as a lowpass filter (figure 18). high-speed digital interfacing with qspi the MAX1246/max1247 can interface with qspi using the circuit in figure 19 (f sclk = 2.0mhz, cpol = 0, cpha = 0). this qspi circuit can be programmed to do a conversion on each of the four channels. the result is stored in memory without taxing the cpu, since qspi incorporates its own microsequencer. the MAX1246/max1247 are qspi compatible up to its maximum external clock frequency of 2mhz. output code full-scale transition 11 . . . 111 11 . . . 110 11 . . . 101 00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 123 0 (com) fs fs - 3/2lsb fs = vref + com zs = com input voltage (lsb) 1lsb = vref 4096 figure 16. unipolar transfer function, full scale (fs) = vref + com, zero scale (zs) = com unipolar mode bipolar mode full scale zero scale positive zero negative full scale scale full scale vref + com com vref / 2 com -vref / 2 + com + com table 7. full scale and zero scale
MAX1246/max1247 +2.7v, low-power, 4-channel, serial 12-bit adcs in qsop-16 ______________________________________________________________________________________ 21 tms320lc3x interface figure 20 shows an application circuit to interface the MAX1246/max1247 to the tms320 in external clock mode. the timing diagram for this interface circuit is shown in figure 21. use the following steps to initiate a conversion in the MAX1246/ max1247 and to read the results: 1) the tms320 should be configured with clkx (transmit clock) as an active-high output clock and clkr (tms320 receive clock) as an active-high input clock. clkx and clkr on the tms320 are tied together with the MAX1246/max1247 s sclk input. 2) the MAX1246/ max1247 s cs pin is driven low by the tms320 s xf_ i/o port to enable data to be clocked into the MAX1246/max1247 s din. 3) an 8-bit word (1xxxxx11) should be written to the MAX1246/max1247 to initiate a conversion and place the device into external clock mode. refer to table 1 to select the proper xxxxx bit values for your specific application. 4) the MAX1246/ max1247 s sstrb output is moni- tored via the tms320 s fsr input. a falling edge on the sstrb output indicates that the conversion is in progress and data is ready to be received from the MAX1246/ max1247. 5) the tms320 reads in one data bit on each of the next 16 rising edges of sclk. these data bits rep- resent the 12-bit conversion result followed by four trailing bits, which should be ignored. 6) pull cs high to disable the MAX1246/ max1247 until the next conversion is initiated. 011 . . . 111 011 . . . 110 000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 100 . . . 001 100 . . . 000 - fs com* input voltage (lsb) output code zs = com +fs - 1lsb *com vref / 2 + com fs = vref 2 -fs = + com -vref 2 1lsb = vref 4096 figure 17. bipolar transfer function, full scale (fs) = vref / 2 + com, zero scale (zs) = com +3v +3v gnd supplies dgnd +3v dgnd com agnd v dd digital circuitry MAX1246 max1247 r* = 10 ? *optional figure 18. power-supply grounding connection
MAX1246/max1247 +2.7v, low-power, 4-channel, serial 12-bit adcs in qsop-16 22 ______________________________________________________________________________________ xf clkx clkr dx dr fsr cs sclk din dout sstrb tms320lc3x MAX1246 max1247 figure 20. MAX1246/max1247-to-tms320 serial interface 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 MAX1246 max1247 mc683xx (power supplies) sck pcs0 mosi miso 1 f 0.1 f 0.1 f (gnd) analog inputs +3v +3v v dd ch0 ch1 ch2 ch3 com shdn vref sclk cs din sstrb dout dgnd agnd refadj +2.5v figure 19. MAX1246/max1247 qspi connections, external reference
MAX1246/max1247 +2.7v, low-power, 4-channel, serial 12-bit adcs in qsop-16 ______________________________________________________________________________________ 23 _ordering information (continued) * contact factory for availability of cerdip package, and for processing to mil-std-883b. part ? MAX1246aepe MAX1246bepe MAX1246aeee -40 c to +85 c -40 c to +85 c -40 c to +85 c temp range pin-package 16 plastic dip 16 plastic dip 16 qsop MAX1246beee inl (lsb) 1/2 1 -40 c to +85 c 16 qsop 1/2 1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 sclk cs din sstrb dout dgnd agnd refadj v dd ch0 ch1 ch2 ch3 com shdn vref top view MAX1246 max1247 dip/qsop __________________pin configuration ___________________chip information transistor count: 2554 MAX1246amje -55 c to +125 c 16 cerdip* MAX1246bmje -55 c to +125 c 16 cerdip* 1/2 1 max1247 acpe max1247bcpe max1247acee 0 c to +70 c 0 c to +70 c 0 c to +70 c 16 plastic dip 16 plastic dip 16 qsop max1247bcee max1247ccee 1/2 1 0 c to +70 c 16 qsop 1/2 -0 c to +70 c 16 qsop 1 max1247bepe -40 c to +85 c 16 plastic dip 2 1 max1247aeee -40 c to +85 c 16 qsop max1247beee max1247amje -40 c to +85 c 16 qsop 1/2 -55 c to +125 c 16 cerdip* 1 max1247bmje -55 c to +125 c 16 cerdip* 1/2 1 cs sclk din sstrb dout start sel2 sel1 sel0 uni/bip sgl/dif pd1 pd0 msb b10 b1 lsb high impedance high impedance figure 21. tms320 serial-interface timing diagram max1247aepe -40 c to +85 c 16 plastic dip 1/2 max1247ceee -40 c to +85 c 16 qsop 2
MAX1246/max1247 +2.7v, low-power, 4-channel, serial 12-bit adcs in qsop-16 24 ______________________________________________________________________________________ ________________________________________________________package information qsop.eps
+2.7v, low-power, 4-channel, serial 12-bit adcs in qsop-16 MAX1246/max1247 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 25 ? 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products. ___________________________________________package information (continued) pdipn.eps

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