may 2009 ?2009 fairchild semiconductor corporation FDMA1024NZ rev.b 3 www.fairchildsemi.com 1 FDMA1024NZ dual n-channel power trench ? mosfet g2 s1 g1 d2 d1 s2 s1 g1 d2 s2 microfet 2x2 d1 g2 pin 1 d1 d2 6 5 4 1 2 3 FDMA1024NZ dual n-channel powertrench ? mosfet 20 v, 5.0 a, 54 m ? features ? max r ds(on) = 54 m ? at v gs = 4.5 v, i d = 5.0 a ? max r ds(on) = 66 m ? at v gs = 2.5 v, i d = 4.2 a ? max r ds(on) = 82 m ? at v gs = 1.8 v, i d = 2.3 a ? max r ds(on) = 114 m ? at v gs = 1.5 v, i d = 2.0 a ? hbm esd protection level = 1.6 kv (note 3) ? low profile - 0.8 mm maximum - in the new package microfet 2x2 mm ? rohs compliant general description this device is designed specifical ly as a single package solution for dual switching requirements in cellular handset and other ultra-portable applications. it features two independent n-channel mosfets with low on -state resistance for minimum conduction losses. the microfet 2x2 package offers exceptional thermal performance for its physical size and is well suited to linear mode applications. applications ? baseband switch ? loadswitch ? dc-dc conversion mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage 20 v v gs gate to source voltage 8 v i d drain current -continuous (note 1a) 5.0 a -pulsed 6.0 p d power dissipation (note 1a) 1.4 w power dissipation (note 1b) 0.7 t j , t stg operating and storage junction temperature range ?55 to +150 c r ja thermal resistance, junction to ambient (note 1a) 86 (single operation) c/w r ja thermal resistance, junction to ambient (note 1b) 173 (single operation) r ja thermal resistance, junction to ambient (note 1c) 69 (dual operation) r ja thermal resistance, junction to ambient (note 1d) 151 (dual operation) device marking device package reel size tape width quantity 024 FDMA1024NZ microfet 2x2 7 ? 8 mm 3000 units ? free from halogenated compounds and antimony oxides
FDMA1024NZ dual n-channel power trench ? mosfet www.fairchildsemi.com 2 ?2009 fairchild semiconductor corporation FDMA1024NZ rev.b 3 electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diod e characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v 20 v ? bv dss ? t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c 19 mv / c i dss zero gate voltage drain current v ds = 16 v, v gs = 0 v 1 a i gss gate to source leakage current v gs = 8 v, v ds = 0 v 10 a v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a 0.4 0.7 1.0 v ? v gs(th) ? t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c -3 mv/c r ds(on) static drain to source on-resistance v gs = 4.5 v, i d = 5.0 a 37 54 m ? v gs = 2.5 v, i d = 4.2 a 43 66 v gs = 1.8 v, i d = 2.3 a 52 82 v gs = 1.5 v, i d = 2.0 a 67 114 v gs = 4.5 v, i d = 5.0 a, t j = 125 c 51 75 g fs forward transconductance v dd = 5 v, i d = 5.0 a 16 s c iss input capacitance v ds = 10 v, v gs = 0 v, f = 1 mhz 375 500 pf c oss output capacitance 70 95 pf c rss reverse transfer capacitance 40 65 pf r g gate resistance f = 1 mhz 4.3 ? t d(on) turn-on delay time v dd = 10 v, i d = 5.0 a v gs = 4.5 v, r gen = 6 ? 5.3 11 ns t r rise time 2.2 10 ns t d(off) turn-off delay time 18 33 ns t f fall time 2.3 10 ns q g total gate charge v gs = 4.5 v, v dd = 10 v, i d = 5.0 a 5.2 7.3 nc q gs gate to source gate charge 0.6 nc q gd gate to drain ?miller? charge 0.9 nc i s maximum continuous source -drain diode forward current v sd source to drain diode forward voltage v gs = 0 v, i s = 1.1 a (note 2) 0.7 1.2 v t rr reverse recovery time i f = 5.0 a, di/dt = 100 a/ s 19 35 ns q rr reverse recovery charge 5 10 nc a 1.1
FDMA1024NZ dual n-channel power trench ? mosfet www.fairchildsemi.com 3 ?2009 fairchild semiconductor corporation FDMA1024NZ rev.b 3 notes : 1. r ja is determined with the device mounted on a 1 in 2 oz. copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ja is determined by the user's board design. (a) r ja = 86 c/w when mounted on a 1 in 2 pad of 2 oz copper, 1.5 " x 1.5 " x 0.062 " thick pcb. for single operation. (b) r ja = 173 c/w when mounted on a minimum pad of 2 oz copper. for single operation. (c) r ja = 69 o c/w when mounted on a 1 in 2 pad of 2 oz copper, 1.5 ? x 1.5 ? x 0.062 ? thick pcb. for dual operation. (d) r ja = 151 o c/w when mounted on a minimum pad of 2 oz copper. for dual operation. 2. pulse test : pulse width < 300 us, duty cycle < 2.0 % 3: the diode connected between the gate and source serves only as protection against esd. no gate overvoltage rating is implied . a)86 o c/w when mounted on a 1 in 2 pad of 2 oz copper. b)173 o c/w when mounted on a minimum pad of 2 oz copper. c)69 o c/w when mounted on a 1 in 2 pad of 2 oz copper. d)151 o c/w when mounted on a minimum pad of 2 oz copper.
FDMA1024NZ dual n-channel power trench ? mosfet www.fairchildsemi.com 4 ?2009 fairchild semiconductor corporation FDMA1024NZ rev.b 3 typical characteristics t j = 25 c unless otherwise noted figure 1. 0.0 0.2 0.4 0.6 0.8 1.0 0 1 2 3 4 5 6 v gs = 4.5 v v gs = 2.5 v pulse duration = 80 s duty cycle = 0.5% max v gs = 1.8 v v gs = 1.5 v v gs = 3.5 v i d , drain current (a) v ds , drain to source voltage (v) on-region characteristics figure 2. 123456 0.5 1.0 1.5 2.0 2.5 3.0 v gs = 3.5 v pulse duration = 80 s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 2.5 v v gs = 1.8 v v gs = 1.5 v v gs = 4.5 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n - r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 i d = 5 a v gs = 4.5 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 40 80 120 160 200 i d = 2.5 a t j = 25 o c t j = 125 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m ? ) pulse duration = 80 s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 0.0 0.5 1.0 1.5 2.0 0 1 2 3 4 5 6 v ds = 5 v pulse duration = 80 s duty cycle = 0.5% max t j = -55 o c t j = 25 o c t j = 125 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1e-3 0.01 0.1 1 10 t j = -55 o c t j = 25 o c t j = 125 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
FDMA1024NZ dual n-channel power trench ? mosfet www.fairchildsemi.com 5 ?2009 fairchild semiconductor corporation FDMA1024NZ rev.b 3 figure 7. 0123456 0 1 2 3 4 5 q g , gate charge (nc) v gs , gate to source voltage (v) i d = 5 a v dd = 10 v v dd = 8 v v dd = 12 v gate charge characteristics figure 8. 0.1 1 10 20 10 100 1000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 03691215 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 v gs = 0 v t j = 25 o c t j = 125 o c v gs , gate to source voltage (v) i g , gate leakage current (a) gate leakage current vs gate to source voltage figure 10. forward bias safe operating area 0.1 1 10 0.01 0.1 1 10 60 dc 10 s 1 s 100 ms 10 ms 1 ms 100 us i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r ja = 173 o c/w t a = 25 o c figure 11. 10 -3 10 -2 10 -1 10 0 10 1 100 1000 1 10 100 p (pk) , peak transient power (w) v gs = 4.5 v single pulse r ja = 173 o c/w t a = 25 o c t, pulse width (sec) 0.3 single pulse maximum power dissipation typical characteristics t j = 25 c unless otherwise noted
FDMA1024NZ dual n-channel power trench ? mosfet www.fairchildsemi.com 6 ?2009 fairchild semiconductor corporation FDMA1024NZ rev.b 3 figure 12. junction to ambient transient thermal response curve 10 -3 10 -2 10 -1 110 100 1000 0.01 0.1 1 single pulse r ja = 173 o c/w duty cycle-descending order normalized thermal impedance, z ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 2 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z ja x r ja + t a typical characteristics t j = 25 c unless otherwise noted
FDMA1024NZ dual n-channel power trench ? mosfet www.fairchildsemi.com 7 ?2009 fairchild semiconductor corporation FDMA1024NZ rev.b 3 dimensional outlin e and pad layout
www.fairchildsemi.com FDMA1024NZ dual n-channel power trench ? mosfet ?2009 fairchild semiconductor corporation FDMA1024NZ rev.b 3 trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes wi thout further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s wo rldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fai rchild semiconductor corporation. as used herein: 1. life support devices or systems ar e devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform c an be reasonably expected to cause the failure of the life su pport device or system, or to affect its safety or effectiveness. product status definitions definition of terms auto-spm? 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