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| $ i b o o f m 7 p m u b h f % f u f d u p s t 4 f s j f t 169 2 ( f o f s b m % f t d s j q u j p o ' f b u v s f t " q q m j d b u j p o t 7 * / 7 * / 7 % & 5 7 4 4 7 * / 7 % & 5 3 3 l 7 % & 5 $ . 0 4 7 % & 5 / d i 0 q f o e s b j o 5 z q j d b m " q q m j d b u j p o $ j s d v j u 5 z q j d b m 1 f s g p s n b o d f $ i b s b d u f s j t u j d supply current vs. input voltage memory battery back-up circuitry microprocessor reset circuits power failure detection system power-on reset circuits system battery life monitors and re-charge voltage monitors delay circuitry cmos low power consumption 2 voltage detectors built-in detect voltage accuracy : 2% detect voltage range : 1.5v ~ 5.0v sot-25 package the xc612 series consist of 2 voltage detectors, in 1 mini-molded, sot- 25 package. the series provides accuracy and low power consumption through cmos processing and laser trimming and consists of a highly accurate voltage reference source, 2 comparators, hysteresis and output driver circuits. the input (v in1 ) for voltage detector 1 (v d1 ) dually functions as the power supply pin for both detector 1 (v d1 ) and detector 2 (v d2 ). highly accurate : set-up voltage accuracy ?% low-power consumption : typ.2.0 a (v in1 =v in2 =2.0v, quiescent state) detect voltage : 1.5v ~ 5.0v programmable in 0.1v steps. detector? voltages can be set-up independently conditionaly, xc612n : v det1 >v det2 xc612d, xc612e : v det1 v det2 , v det1 < v det2 operating voltage range : 1.0v ~ 10.0v temperature characteristics : ?00ppm/? output configuration : n-channel open drain small package : sot-25 (150mw) mini-mold * cmos output is under development ? 5 b ? ? - # supply current: iss ( a) input voltage: v in1 (v) 7 * / 1 7 * / 4 @ 9 $ ?? 9 $ 4 f s j f t 1 j o $ p o g j h v s b u j p o 1 j o " t t j h o n f o u 1 s p e v d u $ m b t t j g j d b u j p o selection guide ordering information 4 0 5 5 0 1 7 * & 8 7 % & 5 7 % & 5 + * / 7 * / 7 4 4 pin number 1 pin name function 2 4 5 detector 1 input, power supply. voltage detector 1 output voltage detector 2 input voltage detector 2 output 3 ground v det1 v in2 v det2 v in1 v ss 5 z q f 7 % & 5 7 % & 5 9 $ / / d i 0 q f o e s b j o / d i 0 q f o e s b j o 9 $ % / d i 0 q f o e s b j o $ . 0 4 9 $ & $ . 0 4 / d i 0 q f o e s b j o a a a a a b c d e f xc612 x x x x x x x e.g.33 = 3.3v 50 = 5.0v designator a d e b c description designator description output configuration: n=n-channel open drain d=v det1 n-ch open drain, v det2 cmos e=v det1 cmos, v det2 n-ch open drain detect voltage (v det1 ) e.g.25 = 2.5v 38 = 3.8v detect voltage (v det2 ) package type: m=sot-25 device orientation r=embossed tape (orientation of device: right) l=embossed tape (orientation of device: left) 4 @ 9 $ ?? 9 $ 4 f s j f t . b s l j o h 1 b d l b h j o h * o g p s n b u j p o sot-25 ? ? ? ? n j o ? 4 0 5 5 0 1 7 * & 8 ? ? ? ? % & 4 * ( / " 5 0 3 / % & $ 0 / ' * ( 6 3 " 5 * 0 / 7 % & 5 / d i 0 q f o e s b j o / d i 0 q f o e s b j o $ . 0 4 7 % & 5 / d i 0 q f o e s b j o $ . 0 4 / d i 0 q f o e s b j o 1 3 0 % 6 $ 5 / " . & 9 $ / . 9 $ % . 9 $ & . q we r wqw 9 $ 4 f s j f t # m p d l % j b h s b n 7 * / 7 * / 7 % & 5 7 % & 5 7 s f g 7 4 4 xc612n series 7 * / 7 * / 7 % & 5 7 % & 5 7 s f g 7 4 4 xc612d series 7 * / 7 * / 7 % & 5 7 % & 5 7 s f g 7 4 4 xc612e series 4 @ 9 $ ?? 9 $ 4 f s j f t " c t p m v u f . b y j n v n 3 b u j o h t 1 " 3 " . & 5 & 3 * o q v u 7 p m u b h f 7 * / * o q v u 7 p m u b h f 7 * / 0 v u q v u 7 p m u b h f 7 % & 5 / d i 0 q f o e s b j o 0 v u q v u 7 p m u b h f 7 % & 5 $ . 0 4 0 v u q v u $ v s s f o u 7 % & 5 0 v u q v u 7 p m u b h f 7 % & 5 / d i 0 q f o e s b j o 0 v u q v u 7 p m u b h f 7 % & 5 $ . 0 4 0 v u q v u $ v s s f o u 7 % & 5 1 p x f s % j t t j q b u j p o 0 q f s b u j o h " n c j f o u 5 f n q f s b u v s f 4 u p s b h f 5 f n q f s b u v s f 4 : . # 0 - 7 * / 7 * / 7 7 % & 5 7 7 % & 5 * 7 % & 5 7 7 % & 5 7 7 % & 5 * 7 % & 5 1 e 5 p q s 5 t u h 6 / * 5 4 7 7 7 7 n " 7 7 n " n 8 ? ? $ 0 / % * 5 * 0 / 4 7 4 4 ? 7 4 4 ? 7 * / 7 4 4 ? 7 4 4 ? 7 * / ? ? 5 b1 ? 4 @ 9 $ ?? 9 $ 4 f s j f t parameter symbol conditions min typ max units detect voltage v det1 v df1 voltage when v det1 changes from h to l following a reduction of v in1 v df1 x 0.98 v df1 v df1 x 1.02 v detect voltage v det2 v df2 voltage when v det2 changes from h to l following a reduction of v in2 v df2 x 0.98 v df1 x 1.02 v df2 v hysteresis range 1 v hys1 voltage (v dr1 ) - v df1 when v det1 changes from l to h following an increase of v in1 v df1 (t) x 0.08 v df1 (t) x 0.05 v df1 (t) x 0.02 v df2 (t) x 0.08 v df 2(t) x 0.05 v df2 (t) x 0.02 hysteresis range 2 v hys2 voltage (v dr2 ) - v df2 when v det2 changes from l to h following an increase of v in2 supply current (input current v in1 ) i ss 3.90 4.50 5.10 5.70 6.30 1.35 1.50 1.95 2.40 3.00 v in1 =1.5v 2.0v 3.0v 4.0v 5.0v 1.30 1.50 1.70 1.90 2.10 0.45 0.50 0.65 0.80 1.00 v in1 =1.5v 2.0v 3.0v 4.0v 5.0v a input current v in2 i in2 a operating voltage v in1 v df (t) = 1.5v to 6.0v 101.5 v output current * i vdet n-ch p-ch v ds = 0.5v 2.2 7.7 10.1 11.5 13.0 -10.0 -2.0 0.3 3.0 5.0 6.0 7.0 v in1 =1.0v v in1 =2.0v v in1 =3.0v v in1 =4.0v v in1 =5.0v v ds = -2.1v v in1 =8.0v (cmos) ma temperature characteristics * e 30 : : : : : : : 0 q f s b u j o h & y q m b o b u j p o timing chart (pull up voltage =input voltage v in1 ) operational notes (n-ch open drain) 5 j n j o h $ i b s u " 7 * / w p m u b h f t b c p w f s f m f b t f w p m u b h f 7 * / t x f f q w p m u b h f # f d b v t f b w p m u b h f i j h i f s u i b o u i f n j o j n v n p q f s b u j o h w p m u b h f j t b q q m j f e u p u i f w p m u b h f j o q v u q j o 7 * / h s p v o e w p m u b h f x j m m c f p v u q v u b u u i f p v u q v u q j o 7 % & 5 e v s j o h t u b h f 4 u b h f t b s f u i f t b n f b t j o # c f m p x 5 j n j o h $ i b s u # 7 * / 7 * / q w e r t y y y q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q qt r wqw 9 $ 4 f s j f t 9 $ / 4 f s j f t 9 $ / 4 f s j f t * / j o d m v e f t u i s p v h i d v s s f o u w p m u b h f e s p q 7 p m u b h f e f u f d u p s t j o q v u w p m u b h f 7 * / " o j o q v u q s p u f d u e j p e f j t d p o o f d u f e g s p n j o q v u e f u f d u p s t j o q v u 7 * / u p j o q v u e f u f d u p s t j o q v u 5 i f s f g p s f t i p v m e u i f w p m u b h f b q q m j f e u p 7 * / f y d f f e 7 * / d v s s f o u x j m m g m p x u i s p v h i 7 * / w j b u i f e j p e f s f g f s u p e j b h s b n 0 t d j m m b u j p o b t b s f t v m u p g u i s p v h i d v s s f o u 4 j o d f u i f 9 $ t f s j f t b s f $ . 0 4 * $ t u i s p v h i d v s s f o u x j m m g m p x x i f o u i f * $ t j o u f s o b m d j s d v j u t x j u d i j o h p q f s b u f t e v s j o h s f m f b t f b o e e f u f d u p q f s b u j p o t $ p o t f r v f o u m z p t d j m m b u j p o j t m j b c m f u p p d d v s b t b s f t v m u p g e s p q t j o w p m u b h f b u u i f u i s p v h i d v s s f o u t s f t j t u p s 3 * / e v s j o h s f m f b t f w p m u b h f p q f s b u j p o t s f g f s u p e j b h s b n 4 j o d f i z t u f s f t j t f y j t u t e v s j o h e f u f d u p q f s b u j p o t p t d j m m b u j p o j t v o m j l f m z u p p d d v s 1 m f b t f v t f u i j t * $ x j u i j o u i f t q f d j g j f e n b y j n v n b c t p m v u f s b u j o h t 1 m f b t f f o t v s f u i b u j o q v u w p m u b h f 7 * / j t m f t t u i b o 7 * / 7 s f g f s u p / # c f m p x 8 j u i b s f t j t u p s d p o o f d u f e c f u x f f o u i f 7 * / q j o b o e u i f j o q v u p t d j m m b u j p o j t m j b c m f u p p d d v s b t b s f t v m u p g u i s p v h i d v s s f o u b u u i f u j n f p g s f m f b t f s f g f s u p / # c f m p x 8 j u i b s f t j t u p s d p o o f d u f e c f u x f f o u i f 7 * / q j o b o e u i f j o q v u e f u f d u b o e s f m f b t f w p m u b h f x j m m s j t f b t b s f t v m u p g u i f * $ t t v q q m z d v s s f o u g m p x j o h u i s p v h i u i f 7 * / q j o * o p s e f s u p t u b c j m j t f u i f * $ t p q f s b u j p o t q m f b t f f o t v s f u i b u u i f 7 * / q j o t j o q v u g s f r v f o d z t s j t f b o e g b m m u j n f t b s f n p s f u i b o t f d 7 4 i p v m e u i f q p x f s t v q q m z w p m u b h f 7 * / f y d f f e 7 w p m u b h f e f u f d u p s t e f u f d u w p m u b h f 7 % ' b o e u i f s f m f b t f w p m u b h f 7 % 3 x j m m t i j g u t p n f x i b u ' p s $ . 0 4 p v u q v u q s p e v d u t i j h i m f w f m p v u q v u w p m u b h f x i j d i j t h f o f s b u f e x i f o u i f u s b o t j f o u s f t q p o t f j t s f m f b t f e c f d p n f t j o q v u w p m u b h f p g 7 * / / # % j b h s b n 7 p m u b h f e f u f d u p s t j o q v u w p m u b h f 7 * / % j b h s b n 5 i s p v h i d v s s f o u p t d j m m b u j p o 7 % & 5 7 % & 5 7 * / 7 * / 3 * / * 4 4 7 * / 7 * / 3 * / 7 4 4 * 4 4 n.b. % j s f d u j p o t g p s v t f notes on use 4 @ 9 $ ?? 9 $ 4 f s j f t 5 f t u $ j s d v j u t circuit 1. 7 * / 7 % & 5 7 % & 5 7 * / 7 4 4 7 * / 7 7 3 l ? 7 % ' 7 % ' 7 ) : 4 7 ) : 4 7 % ' 7 % ' 7 ) : 4 7 ) : 4 circuit 2. 7 * / 7 % & 5 7 % & 5 7 * / * 4 4 7 4 4 7 * / * * / " " circuit 3. 7 * / 7 * / 7 % & 5 7 4 4 7 * / 7 % & 5 7 % 4 * 7 % & 5 * a resistor is not needed if the product is cmos output type. 9 $ / 4 f s j f t 7 * / 7 * / 7 % & 5 7 4 4 7 * / 7 % & 5 7 % 4 7 % 4 * 7 % & 5 * 7 % & 5 9 $ % 4 f s j f t 4 @ 9 $ ?? 9 $ 4 f s j f t circuit 4. 7 * / 7 % 3 7 % & 5 5 j n f 5 j n f u % - : 7 % & 5 7 % & 5 7 * / 7 4 4 7 * / l ? 3 x b w f g p s n n f b t v s f n f o u x b w f g p s n n f b t v s f n f o u 7 * / 7 * / 7 % & 5 7 4 4 7 * / 7 % & 5 7 % 4 7 % 4 * 7 % & 5 * 7 % & 5 9 $ & 4 f s j f t 4 @ 9 $ ?? 5 z q j d b m 1 f s g p s n b o d f $ i b s b d u f s j t u j d t ? 5 b ? ? ? 5 b ? ? note : unless otherwise stated, pull up resistance = 100k with n-ch open drain output types. ( 1 ) supply current vs. input voltage ( 2 ) detect & release voltage vs. ambient temperature - # - # - # - # input voltage: v in2 (v) input current: i in2 ( a) supply current: iss ( a) input voltage: v in1 (v) 7 % 3 7 % ' ambient temp.: topr ( : : : : : : : : : : : : : : : : : 9 $ 4 f s j f t 7 7 7 7 * / 7 7 7 % 4 7 7 7 7 7 * / 7 7 - # - # ( 4 ) n-ch driver output current vs. v ds - # - # 7 % ' 1 7 7 % ' 1 7 7 % ' 1 7 7 % 4 7 output current: i vdet1 (ma) output current: i vet2 (ma) output current: i vet2 ( a) 7 % 4 7 7 % 4 7 output current: i vet1 ( a) 7 * / 7 7 * / 7 7 % ' 1 7 5 p q s ? ? ? 5 p q s ? ? ? ( 5 ) n-ch driver output current vs. input voltage - # - # 7 % ' 1 7 7 % ' 1 7 output current: i vet1 (ma) input voltage: v in1 (v) output current: i vdet2 (ma) input voltage: v in2 (v) 7 % 4 7 7 % 4 7 4 @ 9 $ ?? 9 $ 4 f s j f t 5 z q j d b m " q q m j d b u j p o $ j s d v j u t window comparator circuit (example covers n-channel open drain product's circuits.) 7 * / 7 0 6 5 7 % ' 7 % ' 7 4 4 5 j n f 5 j n f 7 4 4 7 * / 7 0 6 5 7 * / 3 3 7 4 4 7 4 4 7 4 4 7 % & 5 7 * / 7 % & 5 7 * / 7 % % 7 * / 3 3 3 7 4 4 7 0 6 5 7 4 4 7 4 4 7 % & 5 7 * / 7 % & 5 / p u f t p o s f t j t u p s t 3 b o e 3 t g v o d u j p o t % f u f d u w p m u b h f \ 3 3 3 ^ 7 % ' / # 7 % ' e f u f d u w p m u b h f 7 % 1 m f b t f t f u v q t p u i b u ) z t u f s f t j t 7 ) : 4 \ 3 3 ^ 7 ) : 4 / p u f 1 m f b t f f o t v s f u i b u j o q v u w p m u b h f 7 * / j t m f t t u i b o 7 * / 7 7 * / 7 % % 3 3 % % $ % 7 4 4 7 4 4 7 4 4 7 % & 5 7 * / 7 % & 5 / p u f % f m b z p q f s b u f t b u c p u i u j n f t p g s f m f b t f b o e e f u f d u p q f s b u j p o t detect voltages above respective established voltages circuit (example covers n-channel open drain product's circuits.) voltage detect circuit with delay built-in (example covers n-channel open drain product's circuits.) 4 @ 9 $ ?? |
Price & Availability of XC612D3833MR
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