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ltc4302-1/ltc4302-2 1 sn430212 430212fs applicatio s u features typical applicatio u descriptio u the ltc ? 4302-1/ltc4302-2 addressable i 2 c bus and smbus compatible bus buffers allow a peripheral board to be inserted and removed from a live backplane without corruption of the bus. the ltc4302-1/ltc4302-2 main- tain electrical isolation between the backplane and periph- eral board until their v cc supply is valid and a master device on the backplane side addresses the ltc4302-1/ ltc4302-2 and commands them to connect. the ltc4302-1/ltc4302-2s address pin provides 32 pos- sible addresses set by an external resistive divider be- tween v cc and gnd. the ltc4302-1/ltc4302-2 work with supply voltages ranging from 2.7v to 5.5v. the sda and scl inputs and outputs do not load the bus lines when v cc is low. rise time accelerator circuitry* allows for heavier capaci- tive bus loading while still meeting system timing require- ments. during insertion, the sda and scl lines are precharged to 1v to minimize bus disturbances. two general purpose input/output pins (gpios) on the ltc4302-1 can be configured as inputs, open-drain out- puts or push-pull outputs. the ltc4302-2 option replaces one gpio pin with a second supply voltage pin v cc2 , providing level shifting between systems with different supply voltages. the ltc4302-1/ltc4302-2 are available in a 10-pin msop package. n live board insertion n 5v/3.3v level translator n servers n capacitance buffer/bus extender n nested addressing , ltc and lt are registered trademarks of linear technology corporation. n bidirectional buffer for sda and scl lines increases fanout n connect sda and scl lines with 2-wire bus commands n prevents sda and scl corruption during live board insertion and removal from backplane n compatible with i 2 c tm standard mode, i 2 c fast mode and smbus standards n rise time accelerators on sda, scl lines n 1v precharge on sda and scl lines n 32 unique addresses from a single address pin n two general purpose inputs-outputs (ltc4302-1) n translates between 5v and 3.3v systems (ltc4302-2) n small 10-pin msop package addressable 2-wire bus buffers v cc ltc4302-1 sdain c1 0.01 f card sda card scl r7 10k r6 10k r8 1k r9 1k 2.7v to 5.5v r3 10k r4 10k r5 10k r1 1870 r2 2000 sda scl sclin conn address gnd led led 4203 ta01a sdaout sclout gpio1 gpio2 i 2 c is a trademark of philips electronics n.v. *u.s. patent no. 6,650,174 4032 f10 output side 50pf input side 150pf input-output connection t plh 0.1 m s/div
ltc4302-1/ltc4302-2 2 sn430212 430212fs symbol parameter conditions min typ max units power supply/start-up v cc positive supply voltage ltc4302-1 l 2.7 5.5 v v cc2 card side supply voltage ltc4302-2 l 2.7 5.5 v i cc supply current v sdain = 0v, v cc = 5.5v (note 2) ltc4302-1 l 5.9 8 ma i vcc v cc supply current v sdain = 0v, v cc = v cc2 = 5.5v l 3.4 5 ma (note 2) ltc4302-2 i vcc2 v cc2 supply current v sdain = 0v, v cc = v cc2 = 5.5v l 2.3 4 ma (note 2) ltc4302-2 v uvlou uvlo upper threshold v cc rising l 2.5 2.7 v v uvlol uvlo lower threshold v cc falling 2.35 v v uvlo2u v cc2 uvlo upper threshold ltc4302-2 l 2.5 2.7 v v uvlo2l v cc2 uvlo lower threshold ltc4302-2 2.35 v v pre precharge voltage sda, scl floating l 0.8 1 1.2 v v thconn conn threshold voltage l 0.8 1.5 2.2 v t phl conn delay, on-off 60 ns t plh conn delay, off-on 20 ns v cc to gnd ................................................. C0.3v to 7v sdain, sclin, sdaout, sclout, gpio1, conn, gpio2 (ltc4302-1), v cc2 (ltc4302-2) ........................................ C0.3v to 7v address ....................................... C0.3v to v cc + 0.3v order part number consult ltc marketing for parts specified with wider operating temperature ranges. ltc4302cms-1 ltc4302ims-1 (note 1) t jmax = 125 c, q ja = 130 c/w ms part marking ltyf ltyg absolute axi u rati gs w ww u package/order i for atio uu w operating temperature range ltc4302c-1/ltc4302c-2 ...................... 0 c to 70 c ltc4302i-1/ltc4302i-2 .................... C 40 c to 85 c storage temperature range ................. C 65 c to 125 c lead temperature (soldering, 10 sec).................. 300 c order part number ms part marking 1 2 3 4 5 sdain sclin conn address gnd 10 9 8 7 6 sdaout sclout v cc gpio2 gpio1 top view ms package 10-lead plastic msop ltc4302cms-2 LTC4302IMS-2 ltaby ltabz electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 2.7v to 5.5v (ltc4302-1), v cc = v cc2 = 2.7v to 5.5v (ltc4302-2) unless otherwise noted. t jmax = 125 c, q ja = 130 c/w 1 2 3 4 5 sdain sclin conn address gnd 10 9 8 7 6 sdaout sclout v cc v cc2 gpio1 top view ms package 10-lead plastic msop
ltc4302-1/ltc4302-2 3 sn430212 430212fs electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 2.7v to 5.5v (ltc4302-1), v cc = v cc2 = 2.7v to 5.5v (ltc4302-2) unless otherwise noted. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the i cc tests are performed with the backplane-to-card connection circuitry activated. note 3: when the gpios are in open-drain output or input mode, the logic high voltage can be provided by a pull-up supply voltage ranging from 2.2v to 5.5v, independent of the v cc voltage. note 4: i pullup,ac varies with temperature and v cc voltage as shown in the typical performance characteristics section. note 5: the connection circuitry always regulates its output to a higher voltage than its input. the magnitude of this offset voltage as a function of the pull-up resistor and v cc voltage is shown in the typical performance characteristics section. note 6: the specifications in this section illustrate the ltc4302-1/ ltc4302-2s compatibility with the i 2 c fast mode, the i 2 c standard mode and smbus specifications. see the timing diagram on page 5 for illustrations of the timing parameters. note 7: c b = total capacitance of one bus line in pf. note 8: the digital interface circuit controls the data fall time only when acknowledging or transmitting zeros during a read operation. the input- output connection data and clock outputs meet the fall time specification provided that the corresponding inputs meet the fall time specification. note 9: guaranteed by design. not subject to test. symbol parameter conditions min typ max units general purpose i/os v low i/o logic low voltage i sink = 10ma, v cc = 2.7v l 0.36 0.8 v v high i/o logic high voltage i source = 200 m a, v cc = 2.7v l 2.4 v i leak i/o leakage current v i/o = 0v to 5.5v (note 3) l 5 m a v thresh input threshold voltage input mode l 0.8 1.5 2.2 v rise time accelerators i pullup,ac transient boosted pull-up current positive transition on sda, scl, l 12 ma slew rate = 0.8v/ m s, v cc = 2.7v (note 4) input-output connection v os output-input offset voltage 10k to v cc on sda, scl pins (note 5), l 0 100 175 mv c in digital input capacitance (note 9) 10 pf v ol output low voltage sda, scl pins, i sink = 3ma l 0 0.4 v i leak input leakage current sda, scl pins, v cc = 0v to 5.5v l 5 m a connection circuits inactive 2-wire digital interface voltage characteristics v lth logic threshold voltage l 0.3v cc 0.5v cc 0.7v cc v i leak digital input leakage v cc = 0v to 5.5v l 5 m a v ol digital output low voltage i pullup = 3ma into sdain pin l 0.4 v 2-wire digital interface timing characteristics (note 6) f i2c,max i 2 c operating frequency (note 9) 400 600 khz t buf bus free time between stop and start (note 9) 0.75 1.3 m s condition t hd,sta hold time after (repeated) start condition (note 9) 45 100 ns t su,sta repeated start condition setup time (note 9) C30 0 ns t su,sto stop condition setup time (note 9) C30 0 ns t hd,dati data hold time input (note 9) C25 0 ns t hd,dato data hold time output 300 600 900 ns t su,dat data setup time (note 9) 50 100 ns t sp pulse width of spikes suppressed by (note 9) 50 150 250 ns the input filter t f data fall time (notes 7, 8, 9) 20 + 300 ns 0.1c b
ltc4302-1/ltc4302-2 4 sn430212 430212fs typical perfor a ce characteristics uw C40 25 85 temperature ( c) i cc (ma) 4302 g01 6.1 5.9 5.7 5.5 5.3 5.1 4.9 4.7 4.5 4.3 v cc = 5.5v v cc = 2.7v 50 25 0 25 50 75 100 temperature ( c) t phl (ns) 4302 g02 100 80 60 40 20 0 v cc = 2.7v v cc = 3.3v v cc = 5.5v c in = c out = 100pf r pullupin = r pullupout = 10k i cc vs temperature input C output t phl vs temperature i pullupac vs temperature sda, scl v os 50 25 0 25 50 75 100 temperature ( c) i pullupac (ma) 4302 g03 12 10 8 6 4 2 0 v cc = 2.7v v cc = 5v v cc = 3v r pullup (k ) 0 10 20 30 40 v out C v in (mv) 4302 g04 300 250 200 150 100 50 0 v cc = 3.3v v cc = 5v v in = 0v (specifications are at t a = 25 c unless otherwise noted.)
ltc4302-1/ltc4302-2 5 sn430212 430212fs uu u pi fu ctio s sdain (pin 1): serial data input. connect this pin to the sda bus on the backplane. do not float. sclin (pin 2): serial clock input. connect this pin to the scl bus on the backplane. do not float. conn (pin 3): register reset and connection sense input. driving this pin low resets the registers to their default state: gpios in output open-drain high impedance mode, rise time accelerators disabled and the input-to- output connection disabled. communication with the ltc4302-1/ltc4302-2 is disabled when conn is low. when conn is brought back high, the registers remain in the default state and communication is enabled. address (pin 4): 2-wire address programming input. the 2-wire address is programmed by connecting address to a resistive divider between v cc and ground. the voltage on address is converted by an internal analog-to-digital (a/d) converter into a 5-bit digital word. this resulting digital code represents the least significant five bits of the 2-wire address. 1% resistors must be used to ensure accurate address programming. 32 unique addresses are possible. see table 1 for 1% resistor values and corresponding addresses. care must also be taken to minimize capacitance on address. resistors must be placed close to the ltc4302-1/ltc4302-2s v cc , gnd and address pins. gnd (pin 5): ground. connect this pin to a ground plane for best results. gpio1 (pin 6): general purpose input/output (gpio1). gpio1 can be used as an input, an open-drain output or a push-pull output. the n-channel mosfet pulldown de- vice is capable of driving leds. when used in input or open-drain output mode, the i/o pin can be pulled up to a supply voltage ranging from 2.2v to 5.5v independent of the v cc voltage. gpio2 (pin 7, ltc4302-1): general purpose input/out- put. gpio2 can be used as an input, an open-drain output, or a push-pull output. the n-channel mosfet pulldown device is capable of driving leds. when used in input or open-drain output mode, the i/o pin can be pulled up to a supply voltage ranging from 2.2v to 5.5v independent of the v cc voltage. v cc2 (pin 7, ltc4302-2): card side supply voltage. this pin is a power supply pin for the card side busses. connect v cc2 to the cards v cc and connect a bypass capacitor of at least 0.01 m f directly between v cc2 and gnd for best results. v cc (pin 8): main input power supply from backplane. connect a bypass capacitor of at least 0.01 m f directly between v cc and gnd for best results. sclout (pin 9): serial clock output. connect this pin to the scl bus on the i/o card. do not float. sdaout (pin 10): serial data output. connect this pin to the sda bus on the i/o card. do not float. t su, dat t su, sto t su, sta t buf t hd, sta t sp t sp t hd, dato, t hd, dati t hd, sta t f start condition stop condition repeated start condition start condition 4302 td01 sda scl ti i g diagra u ww
ltc4302-1/ltc4302-2 6 sn430212 430212fs block diagra s w ltc4302-1 addressable 2-wire bus buffer C + 1 s filter 5-bit a/d address decoder 100ns glitch filter uvlo address fixed bits 11 inacc outacc connect 2-wire digital interface C + 100ns glitch filter slew rate detector 2ma 2ma 2.5v/ 2.35v v cc conn 8 3 address 4 sclin inacc r lim 50k 2pf v cc sdain 0.55v cc 0.45v cc gnd 4302 bd1 5 sclout 9 backplane-to-card connection slew rate detector 1v precharge uvlo sdain sdaout sclin sclout 100k 100k 2ma outacc slew rate detector sdain inacc sdaout 10 backplane-to-card connection slew rate detector 2ma outacc 100k 100k 1 2 C + v cc data in2 dir2 out cfg2 gpio2 7 v cc data in1 dir1 out cfg1 gpio1 6
ltc4302-1/ltc4302-2 7 sn430212 430212fs block diagra s w v cc2 v cc v cc2 v cc C + 1 s filter 5-bit a/d address decoder 100ns glitch filter uvlo1 uvlo2 address fixed bits 11 inacc outacc connect 2-wire digital interface C + 1 s filter C + 100ns glitch filter slew rate detector connect connect 2ma 2.5v/ 2.35v v cc conn 8 v cc2 7 3 address 4 sclin inacc 50k 2pf v cc sdain 0.55v cc 0.45v cc gnd 4302 bd2 5 sclout 9 connect connect backplane-to-card connection slew rate detector 1v precharge uvlo2 sdaout sclout sdain sclin 100k 100k 2ma 2ma v cc2 v cc1 outacc slew rate detector sdain inacc sdaout 10 backplane-to-card connection slew rate detector 2ma outacc 100k 100k uvlo1 1 2 C + v cc data in1 dir1 out cfg1 gpio1 6 ltc4302-2 addressable 2-wire bus buffer
ltc4302-1/ltc4302-2 8 sn430212 430212fs operatio u live insertion and start-up the ltc4302 allows i/o card insertion into a live back- plane without corruption of the data and clock busses (sda and scl). in its main application, the ltc4302 resides on the edge of a peripheral card with the sclout pin connected to the cards scl bus and the sdaout connected to the cards sda bus. if a card is plugged into a live backplane via a staggered connector, ground and v cc make connection first. the ltc4302 starts in an undervoltage lockout (uvlo) state, ignoring any activity on the sda and scl pins until v cc rises above 2.5v (typical). this ensures that the ltc4302 does not try to function until it has sufficient bias voltage. during this time, the 1v precharge circuitry is also active and forces 1v through 100k nominal resistors to the sda and scl pins. the concept of initializing the sda and scl pins before they make contact with a live backplane is described in the compactpci tm specification. because the i/o card is being plugged into a live backplane, the voltage on the sda and scl busses may be anywhere between 0v and v cc . precharging the scl and sda pins to 1v mini- mizes the worst-case voltage differential these pins will see at the moment of connection, therefore minimizing the amount of disturbance caused by the i/o card. the ltc4302-1 precharges all four sda and scl pins when- ever the v cc voltage is below its uvlo threshold voltage. the ltc4302-2 precharges sdain and sclin whenever v cc is below its uvlo threshold and precharges sdaout and sclout whenever v cc2 is below its uvlo threshold. after ground and v cc connect, sdain and sclin make connection with the backplane sda and scl lines. once the part comes out of uvlo, the precharge circuitry is shut off. finally, the conn pin connects to the short conn pin on the backplane, the 2-wire bus digital interface circuitry is activated and a master on the bus can write to or read from the ltc4302. general i 2 c bus/smbus description the ltc4302 is designed to be compatible with the i 2 c and smbus two wire bus systems. i 2 c bus and smbus are reasonably similar examples of two wire, bidirectional, serial communication busses; however, calling them two wire is not strictly accurate, as there is an implied third wire which is the ground line. large ground drops or spikes between the grounds of different parts on the bus can interrupt or disrupt communications, as the signals on the two wires are both inherently referenced to a ground which is expected to be common to all parts on the bus. both bus types have one data line and one clock line which are externally pulled to a high voltage when they are not being controlled by a device on the bus. the devices on the bus can only pull the data and clock lines low, which makes it simple to detect if more than one device is trying to control the bus; eventually, a device will release a line and it will not pull high because another device is still holding it low. pullups for the data and clock lines are usually provided by external discrete resistors, but external cur- rent sources can also be used. since there are no dedi- cated lines to use to tell a given device if another device is trying to communicate with it, each device must have a unique address to which it will respond. the first part of any communication is to send out an address on the bus and wait to see if another device responds to it. after a response is detected, meaningful data can be exchanged between the parts. typically, one device controls the clock line at least most of the time and normally sends data to the other parts and polls them to send data back. this device is called the master. there can be more than one master, since there is an effective protocol to resolve bus contentions, and non- master (slave) devices can also control the clock to delay rising edges to give themselves more time to complete calculations or communications (clock stretching). slave devices need to control the data line to acknowledge communications from the master. some devices need to send data back to the master; they will be in control of the data line while they are doing so. many slave devices have no need to stretch the clock signal, which is the case with the ltc4302. data is exchanged in the form of bytes, which are 8-bit packets. any byte needs to be acknowledged by the slave or master (data line pulled low) or not acknowledged by the master (data line left high), so communications are compactpci is a trademark of the pci industrial computer manufacturers group.
ltc4302-1/ltc4302-2 9 sn430212 430212fs operatio u broken up into 9-bit segments, one byte followed by one bit for acknowledging. for example, sending out an ad- dress consists of 7-bits of device address, 1-bit that signals whether a read or write operation will be per- formed and then 1 more bit to allow the slave to acknowl- edge. there is no theoretical limit to how many total bytes can be exchanged in a given transmission. i 2 c and smbus are very similar specifications, smbus having been derived from i 2 c. in general, smbus is targeted to low power devices (particularly battery pow- ered ones) and emphasizes low power consumption while i 2 c is targeted to higher speed systems where the power consumption of the bus is not as critical. i 2 c has three different specifications for three different maximum speeds, these being standard mode (100khz max), fast mode (400khz max), and hs mode (3.4mhz max). standard and fast mode are not radically different, but hs mode is very different from a hardware and software perspective and requires an initiating command at standard or fast speed before data can start transferring at hs speed. smbus simply specifies a 100khz maximum speed. the start and stop conditions when the bus is not in use, both scl and sda must be high. a bus master signals the beginning of a transmission with a start condition by transitioning sda from high to low while scl is high. when the master has finished communicating with the slave, it issues a stop condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission. acknowledge the acknowledge signal is used for handshaking between the master and the slave. an acknowledge (low active) generated by the slave lets the master know that the latest byte of information was received. the acknowledge re- lated clock pulse is generated by the master. the transmit- ter master releases the sda line (high) during the ac- knowledge clock pulse. the slave-receiver must pull down the sda line during the acknowledge clock pulse so that it remains stable low during the high period of this clock pulse. when a slave-receiver doesnt acknowledge the slave address (for example, its unable to receive because its performing a real-time function), the data line must be left high by the slave. the master can then generate a stop condition to abort the transfer. if a slave receiver does acknowledge the slave address but some time later in the transfer cannot receive any more data bytes, the master must again abort the transfer. this is indicated by the slave not generating the acknowledge on the first byte to follow. the slave leaves the data line high and the master generates the stop condition. when the master is reading data from the slave, the master acknowledges each byte read except for the last byte read. the master signals a not acknowledge when no other data is to be read and carries out the stop condition. address byte and setting the ltc4302s address the ltc4302s address is set by connecting address to a resistive divider between v cc and ground. the voltage on address is converted into a 5-bit digital word by an a/d converter, as shown in figure 1. this 5-bit word sets the 5 lsbs of the ltc4302s address; its two msbs are always 11. using 1% resistors, the voltage at address is set 0.5lsb away from each code transition. for ex- ample, with v cc =5v, 1lsb=5v/32 codes = 156.25mv/ code. to set an address of 00, set address to 0v + 0.5lsb = 78.125mv. 5-bit a/d 4302 f01 address 4 5 wire r1 r2 v cc figure 1. address compare circuitry
ltc4302-1/ltc4302-2 10 sn430212 430212fs table 1. suggested address 1% resistor values (refer to figure 1 for r1 and r2) address r 1(top) r 2(bottom) 5v ideal allowed address 3.3v ideal allowed address code resistor resistor voltage voltage range voltage voltage range 00 8660 137 0.078125 0.076 to 0.079 0.051563 0.050 to 0.052 01 2800 137 0.234375 0.229 to 0.238 0.154688 0.151 to 0.157 02 1180 100 0.390625 0.383 to 0.398 0.257813 0.253 to 0.263 03 1370 169 0.546875 0.539 to 0.559 0.360938 0.356 to 0.369 04 1070 174 0.703125 0.687 to 0.711 0.464063 0.454 to 0.470 05 1070 221 0.859375 0.842 to 0.870 0.567188 0.556 to 0.574 06 4120 1050 1.015625 0.999 to 1.032 0.670313 0.660 to 0.681 07 3320 1020 1.171875 1.157 to 1.193 0.773438 0.764 to 0.788 08 3160 1150 1.328125 1.315 to 1.354 0.876563 0.868 to 0.893 09 6490 2740 1.484375 1.464 to 1.505 0.979688 0.966 to 0.993 10 2150 1050 1.640625 1.619 to 1.663 1.082813 1.068 to 1.097 11 2050 1150 1.796875 1.774 to 1.820 1.185938 1.171 to 1.201 12 2150 1370 1.953125 1.922 to 1.970 1.289063 1.269 to 1.300 13 1960 1430 2.109375 2.085 to 2.134 1.392188 1.376 to 1.408 14 2100 1740 2.265625 2.241 to 2.290 1.495313 1.479 to 1.512 15 2000 1870 2.421875 2.391 to 2.441 1.598438 1.578 to 1.611 16 1870 2000 2.578125 2.559 to 2.609 1.701563 1.689 to 1.722 17 1740 2100 2.734375 2.710 to 2.759 1.804688 1.788 to 1.821 18 1430 1960 2.890625 2.866 to 2.915 1.907813 1.892 to 1.924 19 1370 2150 3.046875 3.030 to 3.078 2.010938 2.000 to 2.031 20 1150 2050 3.203125 3.180 to 3.226 2.114063 2.099 to 2.129 21 1050 2150 3.359375 3.337 to 3.381 2.217188 2.203 to 2.232 22 2740 6490 3.515625 3.495 to 3.537 2.320313 2.307 to 2.334 23 1150 3160 3.671875 3.646 to 3.685 2.423438 2.407 to 2.432 24 1020 3320 3.838125 3.807 to 3.843 2.526563 2.512 to 2.536 25 1050 4120 3.984375 3.968 to 4.001 2.629688 2.619 to 2.640 26 221 1070 4.140625 4.130 to 4.158 2.732813 2.726 to 2.744 27 174 1070 4.296875 4.289 to 4.313 2.835938 2.830 to 2.846 28 169 1370 4.453125 4.441 to 4.461 2.939063 2.931 to 2.944 29 100 1180 4.609375 4.602 to 4.617 3.042188 3.037 to 3.047 30 137 2800 4.765625 4.762 to 4.771 3.145313 3.143 to 3.149 31 137 8660 4.921875 4.921 to 4.924 3.248438 3.248 to 3.250 operatio u select standard 1% tolerance resistor values that most closely match the ideal resistor values. table 1 shows recommended values for each of the code segments. for code 00, rtop=8660 w , rbottom=137 w . this yields a voltage of 77.87mv. resistors must be placed close to the ltc4302s v cc , gnd and address pins. care must also be taken to minimize capacitance on address. in two-wire bus systems, the master issues the address byte immediately following a start bit. the first seven bits contain the address of the slave device being targeted by the master. if the first two msbs are 1s, and the next 5 bits match the output of the ltc4302s 5-bit address a/d, an address match occurs, and the ltc4302 acknowledges the address byte and continues communicating with the
ltc4302-1/ltc4302-2 11 sn430212 430212fs table 2. register 1 definition bit name type function 7 (msb) connect read/write backplane-to-card connection; 0 = disconnected, 1 = connected 6 data in2 read/write logic state of input signal to gpio2 block 5 data in1 read/write logic state of input signal to gpio1 block 4 data2 read only logic state of gpio2 pin 3 data1 read only logic state of gpio1 pin 2 na read only never used, always 0 1 na read only never used, always 0 0 na read only never used, always 0 default state (msb first): 011dd000 note: the second and third bits of the data byte are used to write the data value of the two gpios. during a write operation, the five read only bits are ignored. during a read operation, bits 7 to 3 will be shifted onto the data bus, followed by three 0s. also note that data2 and data in2 are meaningless for the ltc4302-2 because there is no gpio2 pin for that option. operatio u master. the 8 th bit of the address byte is the read/write bit (r/w) and determines whether the master is writing to or reading from the slave. figure 2 shows a timing diagram of the start bit and address byte required for both reading and writing the ltc4302. programmable features the two-wire bus can be used to connect and disconnect the card and backplane sda and scl busses, enable and disable the rise time accelerators on either or both the backplane and card sides, and configure and write to the two gpio pins (only one gpio for the ltc4302-2). the bits that control these features are stored in two registers. for ease of software coding, the bits that are expected to change more frequently are stored in the first register. in addition, the bus can be used to read back the logic states of the control bits. the maximum scl frequency is 400khz. writing to the ltc4302 the ltc4302 can be written using three different formats, which are shown in figures 3, 5 and 6. each format begins with a start bit, followed by the address byte as discussed above. the procedure for writing one data byte is given by the smbus send byte protocol, illustrated in figure 3. the bits of the data byte are stored in the ltc4302s register 1. table 2 defines the functions of these control bits. the msb controls the connection between the backplane and card two-wire busses. the next two bits are used to write logic values to the two gpio pins. since the ltc4302-2 has only one gpio pin, bit data in1 controls its logic value and bit data in2 is ignored. the 5 lsbs are not used in write operations. the ltc4302 can be written with two data bytes by using the format shown in figure 5. the address byte and first data byte are exactly the same as they are for the send byte scl sda start condition stop condition address r/w ack data ack data ack 1 - 7 8 9 4302 f02 a6 - a0 b7 - b0 b7 - b0 1 - 7 8 9 1 - 7 8 9 p s figure 2. data transfer over i 2 c or smbus start ack 11 a4 - a0 wr d7 - d0 1 1 71 8 s 00 ack 1 s 0 data byte slave address stop 1 4302 f03 figure 3. writing one byte using send byte protocol
ltc4302-1/ltc4302-2 12 sn430212 430212fs protocol. after the first data byte, the master transmits a second data byte, followed by a stop bit. the bits of the second data byte are stored in the ltc4302s register 2. table 3 defines the functions of these control bits. the first 4 msbs control the input/output configurations of the two gpio pins. the next 2 bits control the enabling/ disabling of the card side and backplane side rise time accelerators respectively. since the ltc4302 -2 has only one gpio pin, dir1 and out cfg1 control its configu- ration, and dir2 and out cfg2 are ignored. figure 4 shows a schematic of the two gpios and the register bits that control their operation. the 2 lsbs are not used in write operations. the ltc4302 can also be written with two bytes using the smbus write word protocol, as shown in figure 6. the ltc4302 treats the first two bytes after the address byte (which the write word protocol refers to as command code and data byte low) as the two data bytes, and stores these bytes in registers 1 and 2 respectively. after the master transmits the data byte high byte, the ltc4302 acknowledges reception of the byte but ignores the data contained therein. operatio u 4302 f04 v cc data in1 dir1 out cfg1 gpio1 6 v cc data in2 dir2 out cfg2 gpio2 7 figure 4. gpio circuits and their control bits table 3. register 2 definition bit name type function 7 (msb) dir2 read/write gpio2 mode; 0 = output, 1 = input* 6 dir1 read/write gpio1 mode; 0 = output, 1 = input 5 out cfg2 read/write gpio2 output mode; 0 = open drain, 1 = push-pull ? * 4 out cfg1 read/write gpio1 output mode; 0 = open drain, 1 = push-pull ? 3 outacc read/write card side rise time accelerator contol; 0 = disabled, 1 = active 2 inacc read/write backplane side rise time accelerator control; 0 = disabled, 1 = active 1 na read only never used, always 1 0 na read only never used, always 1 default state (msb first): 00000011 ? out cfg1 has no effect when dir1 = 1; out cfg2 has no effect when dir2 = 1. *dir2 and out cfg2 apply only to the ltc4302-1; there is no gpio2 for the ltc4302-2, so these bits are meaningless in this case. start ack 11 a4 - a0 wr d7 - d0 1 1 71 8 s 00 ack 1 s 0 data byte 1 d7 - d0 8 ack 1 s 0 data byte 2 slave address stop 1 4302 f05 start ack 11 a4 - a0 wr d7 - d0 1 1 71 8 s 00 ack 1 s 0 command code d7 - d0 8 ack 1 s 0 data byte low slave address xxxxxxxx 8 ack 1 s 0 data byte high stop 1 4302 f06 figure 5. writing two bytes figure 6. writing two bytes using smbus write word protocol
ltc4302-1/ltc4302-2 13 sn430212 430212fs data transfer timing for write commands in order to help ensure that bad data is not written into the ltc4302, data from a write command is only stored after a valid stop bit has been performed. if a start bit occurs after new data bytes have been written but before a stop bit is issued, the new data bytes are lost. in this case, the master must readdress the part, rewrite the data bytes and issue a stop bit before issuing any start bits to properly update the registers. also note that driving the conn pin low asynchronously resets the registers to their default states, as specified in tables 2 and 3. when conn is driven back high, the registers remain in the default state. reading from the ltc4302 the ltc4302 can be read using three different formats, as shown in figures 7 through 9. each format begins with a start bit, followed by the address byte, as discussed above. the procedure for reading one data byte is given by the smbus receive byte protocol, illustrated in figure 7. the bits of the data byte are read from the ltc4302s register 1. table 2 defines the functions of these control bits. while only the first 3 bits of register 1 can be written, the first 5 bits contain useful information to be read. the two added bits indicate the logic state of the gpio pins. the 3 lsbs are not used and are always 000. the format for reading two data bytes is shown in figure 8. the address byte and first data byte are exactly the same as they are for the receive byte protocol. after the first data byte, the master transmits an acknowledge indicating that it wants to read another data byte. the bits contained in register 2 are then written onto the bus as data byte 2. table 3 defines the functions of these control bits. the 2 lsbs are not used and are always 11. the master signals a not acknowledge after the last byte read. the smbus read word protocol can also be used to read two bytes from the ltc4302, as shown in figure 9. note that the first address byte and the command code consti- tute a write operation. however, because these bytes are followed immediately by a start bit and not a stop bit, the data contained in the command code is not written into the ltc4302. after the second start bit, the format is exactly the same as shown in figure 8. operatio u start ack 11 a4 - a0 wr xxxxxxxx 1 1 71 8 s 00 ack 1 s 0 command code slave address start ack 11 a4 - a0 rd d7 - d3 000 1 1 71 8 s 10 ack 1 m 0 data byte 1 d7 - d2 11 8 1 m 1 stop 1 data byte 2 slave address 4302 f09 ack figure 9. reading two bytes using smbus read word protocol start ack 11 a4 - a0 rd d7 - d3 000 1 1 71 8 s 10 ack 1 m 1 data byte slave address stop 1 4302 f07 figure 7. reading one byte using receive byte protocol start ack 11 a4 - a0 rd d7 - d3 000 1 1 71 8 s 10 ack 1 m 0 data byte 1 d7 - d2 11 8 1 m 1 data byte 2 slave address stop 1 4302 f08 ack figure 8. reading two bytes
ltc4302-1/ltc4302-2 14 sn430212 430212fs operatio u connection circuitry masters on the sdain and sclin busses can address the ltc4302 and command it to connect sdain to sdaout and sclin to sclout as described in the write one or two bytes section. once this connection occurs, masters on the card are then able to read from and write to the part via the sdaout and sclout pins. however, whenever the two sides are disconnected, the command to recon- nect must come from sdain and sclin. once the connection circuitry is activated, the functional- ity of the sdain and sdaout pins is identical. a low forced on either pin at any time results in both pin voltages being low. masters must pull the bus voltages below 0.4v worst-case with respect to the ltc4302s ground pin to ensure proper operation. sdain and sdaout enter a logic high state only when all devices on both sdain and sdaout busses force a high. the same is true for sclin and sclout. this important feature ensures that clock stretching, clock arbitration and the acknowledge protocol always work, regardless of how the devices in the system are connected to the ltc4302. another key feature of the connection circuitry is that it provides bidirectional buffering, keeping the backplane and the card capacitances isolated. because of this isola- tion, the waveforms on the backplane busses look slightly different from the corresponding card bus waveforms. input-to-output offset voltage when a logic low voltage, v low1 is driven on any of the ltc4302s data or clock pins, the ltc4302 regulates the voltage on the other side (v low2 ) to a slightly higher voltage, as directed by the following equation: v low2 (typical) = v low1 + 75mv + (v bus /r) ? 70 w where r is the bus pull-up resistance on v low2 in ohms and v bus is the supply voltage to which r is connected. for example, if a device is forcing sdaout to 10mv, and if v cc = 3.3v and the pull-up resistor r on sdain is 10k, then the voltage on sdain = 10mv + 75mv + (3.3v/10k) ? 70 w = 108mv (typical). see the typical performance characteristics section for curves showing the offset voltage as a function of v cc and r. propagation delays during a rising edge, the rise time on each side is deter- mined by the combined pull-up current of the ltc4302 boost current and the bus resistor and the equivalent capacitance on the line. if the pull-up currents are the same, a difference in rise time occurs that is directly proportional to the difference in capacitance between the two sides. this effect is displayed in figure 10 for v cc = 3.3v and a 10k pull-up resistor on each side (50pf on one side and 150pf on the other). since the output side has less capacitance than the input, it rises faster and the effective t plh is negative. there is a finite propagation delay, t phl , through the connection circuitry for falling waveforms. figure 11 shows the falling waveforms for the same v cc , pull-up resistors and equivalent capacitance conditions used in figure 10. an external n-channel mosfet device pulls down the voltage on the side with 150pf capacitance; the ltc4302 output side 50pf input side 150pf 4032 f10 figure 10. input-output connection t plh input side 150pf output side 50pf 4032 f11 figure 11. input-output connection t phl
ltc4302-1/ltc4302-2 15 sn430212 430212fs operatio u pulls down the voltage on the 50pf side with a delay of 55ns. this delay is always positive and is a function of supply voltage, temperature and the pull-up resistors and equivalent bus capacitances on both sides of the bus. the typical performance characteristics section shows t phl as a function of temperature and voltage for 10k pull-up resistors and 100pf equivalent bus capacitance on both sides of the part. larger output capacitances translate to longer delays (up to 150ns). users must quantify the difference in propagation times for a rising edge versus a falling edge in their systems and adjust setup and hold times accordingly. general purpose input/outputs (gpios) the ltc4302-1 provides two general purpose input/out- put pins (gpios) that can be configured as inputs, open- drain outputs or push-pull outputs. in push-pull mode, at v cc = 2.7v, the typical pull-up impedance is 670 w and the typical pull-down impedance is 35 w , making the gpio pull-downs capable of driving leds. the user must take care to minimize the power dissipation in the pulldown device. leds should have series resistors added to limit current and the voltage drop across the internal pulldown if their forward drop is less than about v cc -0.7v. pullup resistors should be sized to allow the internal pulldowns to pull the gpio pins below 0.7v. in open-drain output mode, the user provides the logic high by connecting a resistor to an external supply voltage. the external supply voltage can range from 2.2v to 5.5v independent of the v cc voltage. the ltc4302-2 replaces one gpio pin with a v cc2 pin and provides only one gpio. rise time accelerators rise time accelerator circuits on all four sda and scl pins allow the user to choose weaker dc pull-up currents on the bus, reducing power consumption while still meeting system rise time requirements. a master on the bus may activate the accelerators on the backplane side, the card side, neither or both, by writing the ltc4302s registers as described above. when activated, the accelerators switch in 2ma of current at v cc = 2.7v and 9ma at v cc = 5.5v during positive bus transitions to quickly slew the sda and scl lines once their dc voltages exceed 0.6v and the initial rise rate on the pin exceeds 0.8v/ m s. using a general rule of 20pf of capacitance for every device on the bus (10pf for the device and 10pf for interconnect), choose a pull-up current so that the bus will rise on its own at a rate of at least 0.8v/ m s to guarantee activation of the accelerators. for example, assume an smbus system with v cc = 3.3v, a 10k pull-up resistor and equivalent bus capacitor of 200pf. the rise time of an smbus system is calculated from (v il(max) C 0.15v) to (v ih(min) + 0.15v) or 0.65v to 2.25v. it takes an rc circuit 0.92 time constants to traverse this voltage for a 3.3v supply; in this case, 0.92 ? (10k ? 200pf) = 1.84 m s. thus, the system exceeds the maximum allowed rise time of 1 m s by 84%. however, using the rise time accelerators, which are activated at a dc threshold below 0.65v, the worst-case rise time is (2.25v C 0.65v) ? 200pf/1ma = 320ns, which meets the 1 m s rise time requirement. conn register reset grounding conn resets the registers to their default state as specified in tables 2 and 3. in the default state, the backplane side is disconnected from the card side, the rise time accelerators are disabled and the gpios are set in open-drain output mode with the n-channel mosfet open-drain pulldown turned off. connecting a weak resis- tor from conn to ground on the i/o card and using a staggered connector with conn connecting to the short- est pin guarantee glitch-free live board insertion and removal. when the conn voltage is brought back to v cc the registers remain in the default state and can then be read or written to.
ltc4302-1/ltc4302-2 16 sn430212 430212fs applicatio s i for atio wu uu live insertion and removal, capacitance buffering the application shown in figure 12 highlights the live insertion and removal, and capacitance buffering features of the ltc4302. note that if the i/o card were plugged directly into the backplane, the card capacitance would add directly to the backplane capacitance making rise and fall time requirements difficult to meet. placing a ltc4302 on the edge of the card, however, isolates the card capaci- tance from the backplane. the ltc4302 drives the capaci- tance of everything on the card, and the backplane must drive only the capacitance of the ltc4302, which is less than 10pf. assuming that a staggered connector is available, make ground, v cc and v cc2 the longest pins to guarantee that sdain and sclin receive the 1v precharge voltage before they connect. make sdain and sclin medium length pins to ensure that they are firmly connected while conn is low. make conn the shortest pin and connect a weak resistor from conn to ground on the i/o card. this ensures that the ltc4302-1/ltc4302-2 remain in a high impedance state while sdain and sclin are making connection during live insertion. during live removal, having conn disconnect first ensures that the ltc4302 enters a high impedance state in a controlled manner before sdain and sclin disconnect. owing to the fact that the ltc4302 powers into a high impedance state, and also owing to the 1v precharge voltage and the less than 10pf pin capacitance, sdain and sclin cause minimal disturbance on the backplane busses when they make contact with the connector. address expansion with nested addressing figure 13 illustrates how the ltc4302 can be used to expand the number of devices in a system by using nested addressing. note that each i/o card contains a sensor device having address 1111 111. if the two cards are plugged directly into the backplane, the two sensors will require two different addresses. however, each ltc4302 isolates the devices on its card from the rest of the system until it is commanded to connect. if masters use the ltc4302s to connect only one i/o card at a time, then each i/o card can have a device with address 1111 111 and no problems will occur. glitch filters the ltc4302 provides glitch filters on both the sdain and sclin signals as required by the i 2 c fast mode (400khz) specification. the filters prevent signals of up to 50ns (minimum) time duration and rail-to-rail voltage magni- tude from passing into the 2-wire bus digital interface circuitry. fall time control per the i 2 c fast mode (400khz) specification, the 2-wire bus digital interface circuitry provides fall time control when forcing logic lows onto the sdain bus. the fall time always meets the limits: (20 + 0.1 ? c b ) < t f < 300ns where t f is the fall time in ns and c b is the equivalent capacitance on sdain in pf. whenever the connection circuitry is passing logic lows from sdaout to sdain (and vice versa), its output signal will meet the fall time requirements, provided that its input signal meets the fall time requirements. operatio u
ltc4302-1/ltc4302-2 17 sn430212 430212fs applicatio s i for atio wu uu v cc ltc4302-1 i/o peripheral card x1 sdain c1 0.01 f r3 137 r2 10k r1 10k v cc 5v backplane connector pcb edge backplane connector backplane sda scl r6 10k r7 10k r8 1k r9 1k card sda card scl r4 8660 r5 200k sclin conn address gnd led led sdaout sclout gpio2 gpio1 4302 f12 conn + figure 12. ltc4302-1 in a live insertion and capacitance buffering application figure 13. ltc4302-1 in a nested addressing application v cc ltc4302-1 x1 i/o peripheral card 1 sdain c1 0.01 f r3 8660 r2 10k r1 10k v cc 5v backplane sda scl r5 10k r6 10k card sda card scl r4 137 address = 1100 000 address = 1111 111 sclin conn address gnd sensor sdaout sclout gpio2 gpio1 v cc ltc4302-1 x2 i/o peripheral card 2 sdain c2 0.01 f r7 2800 r9 10k r10 10k card sda card scl r8 137 address = 1100 001 address = 1111 111 sclin conn address gnd sensor sdaout sclout gpio2 gpio1 4302 f13 + +
ltc4302-1/ltc4302-2 18 sn430212 430212fs applicatio s i for atio wu uu 5v to 3.3v level translator and power supply redundancy (ltc4302-2) systems requiring different supply voltages for the back- plane side and the card side can use the ltc4302-2 as shown in figure 14. the pull-up resistors on the card side connect from sdaout and sclout to v cc2 and those on the backplane side connect from sdain and sclin to v cc . the ltc4302-2 functions for voltages ranging from 2.7v to 5.5v on both v cc and v cc2 . there is no constraint on the voltage magnitudes of v cc and v cc2 with respect to each other. this application also provides power supply redundancy. if either the v cc or v cc2 supply voltage falls below its uvlo threshold, the ltc4302-2 disconnects the backplane from the card so that the side that is still powered can continue to function. systems with supply voltage droop (ltc4302-1) in large 2-wire systems, the v cc voltages seen by devices at various points in the system can differ by a few hundred millivolts or more. this situation is modelled by a series resistor in the v cc line as shown in figure 15. for proper operation of the ltc4302-1, make sure that v cc(bus) 3 v cc(ltc4302) C 0.5v. v cc v cc2 ltc4302-2 sdain c2 0.01 f c1 0.01 f card sda card scl card v cc 3.3v r5 10k r6 10k r7 10k r8 1k v cc 5v sda scl sclin conn address gnd led 4203 f14 sdaout sclout gpio1 r4 10k r3 10k r1 8660 r2 137 figure 14. 5v to 3.3v level translator application v cc ltc4302-1 sdain c1 0.01 f sda2 scl2 r drop v cc low r6 10k r5 10k r7 1k r8 1k r3 10k r4 10k r1 8660 v cc r2 137 sda scl sclin conn address gnd led led 4203 f15 sdaout sclout gpio1 gpio2 figure 15. system with supply voltage droop
ltc4302-1/ltc4302-2 19 sn430212 430212fs u package descriptio msop (ms) 0603 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 0.27 (.007 ?.011) typ 0.127 0.076 (.005 .003) 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ?6 typ detail ? detail ? gauge plane 5.23 (.206) min 3.20 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc repeater/bus extender application users who wish to connect two 2-wire systems separated by a distance can do so by connecting two ltc4302-1s back-to-back as shown in figure 16. the i 2 c specification allows for 400pf maximum bus capacitance, severely limiting the length of the bus. the smbus specification places no restriction on bus capacitance; however, the limited impedances of devices connected to the bus re- quire systems to remain small, if rise and fall time speci- fications are to be met. the strong pull-up and pull-down impedances of the ltc4302-1 are capable of meeting rise and fall time specifications for up to 1nf of capacitance, thus allowing much more interconnect distance. in this situation, the differential ground voltage between the two systems may limit the allowed distance because a valid logic low voltage with respect to the ground at one end of the system may violate the allowed v ol specification with respect to the ground at the other end. in addition, the connection circuitry offset voltages of the back-to-back ltc4302-1s add together, directly contributing to the same problem. applicatio s i for atio wu uu ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ltc4302-1/ltc4302-2 20 sn430212 430212fs linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ? linear technology corporation 2003 lt/tp 1003 1k printed in usa part number description comments ltc1380/ltc1393 single-ended 8-channel/differential 4-channel analog low r on : 35 w single-ended/70 w differential, mux with smbus interface expandable to 32 single or 16 differential channels ltc1427-50 micropower, 10-bit current output dac precision 50 m a 2.5% tolerance over temperature, with smbus interface 4 selectable smbus addresses, dac powers up at zero or midscale ltc1623 dual high side switch controller with smbus interface 8 selectable addresses/16-channel capability ltc1663 smbus interface 10-bit rail-to-rail micropower dac dnl < 0.75lsb max, 5-lead sot-23 package ltc1694/ltc1694-1 smbus accelerator improved smbus/i 2 c rise-time, ensures data integrity with multiple smbus/i 2 c devices lt1786f smbus controlled ccfl switching regulator 1.25a, 200khz, floating or grounded lamp configurations ltc1695 smbus/i 2 c fan speed controller in thinsot tm 0.75 w pmos 180ma regulator, 6-bit dac ltc1840 dual i 2 c fan speed controller two 100 m a 8-bit dacs, two tach inputs, four gpi0 ltc4300a-1/ hot swappable 2-wire bus buffers provides capacitance buffering, sda and scl hot swapping, ltc4300a-2 level shifting thinsot is a trademark of linear technology corporation. related parts v cc ltc4302-1 ic1 2-wire system 1 2-wire system 2 sdain c1 0.01 f long distance bus r5 10k r6 10k r7 5.1k r1 10k r2 10k r3 8660 v cc to other system 1 devices r4 137 sda1 scl1 sclin conn address gnd sdaout sclout gpio1 gpio2 v cc ltc4302-1 ic2 sdain c2 0.01 f r10 10k r9 10k r14 10k r13 10k r11 2000 v cc 4302 f16 to other system 2 devices r12 1870 sda2 scl2 sclin conn address gnd sdaout sclout gpio1 gpio2 r8 5.1k figure 16. repeater/bus extender application typical applicatio u

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