? integrated circuits group lh 28 f 80 0 b vb - t t l 9 0 fla sh me mor y 8 m ( 1 m 8 / 512 k 16 ) (model no.: lh f 80 v 07 ) spec no.: el 11 4 06 7 issue date: a ugu st 27 , 19 99 p roduc t s pecific a tions
sharp lhfsovo7 @handle this document carefully for it contains material protected by international copyright law. any reproduction, full or in part, of this material is prohibited without the express written permission of the company. l when using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. in no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) the products covered herein are designed and manufactured for the following application areas. when using the products covered herein for the equipment listed in paragraph (2), even for the following application areas, be sure to observe the precautions given in paragraph (2). never use the products for the equipment listed in paragraph (3). *office electronics *instrumentation and measuring equipment *machine tools *audiovisual equipment *home appliance *communication equipment other than for trunk lines (2) those contemplating using the products covered herein for the following equipment which demands high reliabilitv, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. *control and safety devices for airplanes, trains, automobiles, and other transportation equipment *mainframe computers *traffic control systems l gas leak detectors and automatic cutoff devices *rescue and security equipment *other safety devices and safety equipment, etc. (3) do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. *aerospace equipment l communications equipment for trunk lines *control equipment for the nuclear power industry l medical equipment related to life support, etc. (4) please direct all queries and comments regarding the interpretation of the above three paragraphs to a sales representative of the company. @please direct all queries regarding the products covered herein to a sales representative of the company. rev. 1.1
sliarp lhf80v07 1 contents page page 1 introduction.. ........................................................... .3 1. i features ........................................................................ 3 1.2 product overview.. ...................................................... .3 2 principles of operation.. ..................................... .7 2.1 data protection.. ........................................................... 8 5 design considerations ...................................... 20 5.1 three-line output control ....................................... 20 5.2 ry/by# and block erase and word/byte write polling.. .................................................................... 20 5.3 power supply decoupling ........................................ 20 5.4 v,, trace on printed circuit boards ........................ 20 3 bus operation ........................................................... .8 3.1 read.. ........................................................................... .8 3.2 output disable.. ........................................................... .8 3.3 standby ......................................................................... 8 3.4 deep power-down.. ..................................................... 8 3.5 read identifier codes operation.. ............................... .9 3.6 write.. ............................................. . ............................ .9 5.5 v,, . v,,, rp# transitions.. ..................................... 21 5.6 power-up/down protection.. .................................... 2 1 5.7 power dissipation.. ................................................... 21 4 command definitions.. ................ .: ......................... 9 4.1 read array command ................................................ 12 4.2 read identifier codes command ............................... 12 4.3 read status register command.. ............................... 12 4.4 clear status register command ................................. 12 4.5 block erase command.. ............................................. 12 4.6 word/byte write command.. ..................................... 13 4.7 block erase suspend command ................................ 13 4.8 word/byte write suspend command.. ...................... 14 4.9 considerations of suspend.. ....................................... 14 4.10 block locking.. ........................................................ 14 4.10.1 v,,=v,, for complete protection.. .................... 14 4.10.2 wp#=v,, for block locking.. ............................ 14 4.10.3 wp#=v,, for block unlocking.. ........................ 14 6 electrical specifications ............................... 22 6.1 absolute maximum ratings ..................................... 22 6.2 operating conditions ................................................ 22 6.2.1 capacitance.. ....................................................... 22 6.2.2 ac input/output test conditions ....................... 23 6.2.3 dc characteristics .............................................. 24 6.2.4 ac characteristics - read-only operations.. ..... 26 6.2.5 ac characteristics - write operations ............... 29 6.2.6 alternative ce#-controlled writes.. ................... 3 1 6.2.7 reset operations ................................................. 33 6.2.8 block erase and word/byte write performance 34 7 package and packing specifications ......... 35 rev. 1.1
sharip lhf80v07 2 lh28f8oobvb-ttl90 8m-bit (1mbit x 8 / 5 12kbit x 16) smart3 flash memory n smart3 technology - 2.7v-3.6v vcc - 2.7v-3.6v or 11.4v-12.6v vpp n user-configurable x8 or x 16 operation n high-performance access time - 90ns(2.7v-3.6v) n operating temperature - 0c to +7o?c n optimized array blocking architecture - two 4k-word boot blocks - six 4k-word parameter blocks - fifteen 32k-word main blocks - top boot location n extended cycling capability - 100,000 block erase cycles n enhanced automated suspend options - word/byte write suspend to read - block erase suspend to word/byte write - block erase suspend to read n enhanced data protection features - absolute protection with vpp=gnd - block erase and word/byte write lockout during power transitions - boot blocks protection with wp#=vil n automated word/byte write and block erase - command user interface - status register n low power management - deep power-down mode - automatic power savings mode decreases icc in static mode n sram-compatible write interface n chip size packaging - 48-ball csp n etoxtm* nonvolatile flash technology n cmos process (p-type silicon substrate) n not designed or rated as radiation hardened sharp?s LH28F800BVB-TTL90 flash memory with smart3 technology is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. LH28F800BVB-TTL90 can operate at v,,=2.7v-3.6v and v,,=2.7v-3.6v its low voltage operation capability realize battery life and suits for cellular phone application. its boot. parameter and main-blocked architecture, flexible voltage and extended cycling provide for highly flexible :omponent suitable for portable terminals and personal computers. its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. for secure code storage applications, such as networking, where code is either lirectly executed out of flash or downloaded to dram, the lh28f8oobvb-ttl90 offers two levels of protection: absolute lrotection with v,, at gnd, selective hardware boot block locking. these alternatives give designers ultimate control of their :ode security needs. ihe LH28F800BVB-TTL90 is manufactured on sharp?s 0.35um etoxtm* process technology. it come in chip-size lackage: the 48-ball csp ideal for board constrained applications. ?etox is a trademark of intel corporation rev. 1.1
sharp lhf8ovo7 3 1 introduction this datasheet contains lh28f800bvb-ti?l90 specifications. section 1 provides a flash memory overview. sections 2,3,4 and 5 describe the memory organization and functionality. section 6 covers electrical specifications. 1.1 features key enhancements of lh28f8oobvb-ttl90 smart3 flash memory are: *smart3 technology *enhanced suspend capabilities *boot block architecture please note following important differences: l vpplk has been lowered to 1.5v to support 2.7v-3.6v block erase and word/byte write operations. the v,, voltage transitions to gnd is recommended for designs that switch v,, off during read operation. *to take advantage of smart3 technology, allow v,, and v,, connection to 2.7v-3.6v. 1.2 product overview the LH28F800BVB-TTL90 is a high-performance 8m-bit smart3 flash memory organized as lm-byte of 8 bits or 512k-word of 16 bits. the lm-byte/512k-word of data is uranged in two 8k-byte/4k-word boot blocks, six sk- jytel4k-word parameter blocks and fifteen 64k-byte/32k- word main blocks which are individually erasable in- tystem. the memory map is shown in figure 3. smart3 technology provides a choice of v,, and v,, :ombinations, as shown in table 1, to meet system xrformance and power expectations. v,, at 2.7v-3.6v :liminates the need for a separate 12v converter, while v,,=12v maximizes block erase and word/byte write performance. in addition to flexible erase and program voltages. the dedicated v,, pin gives complete data protection when vpplvpplk. table 1. v,, and v,, voltage combinations offered by smart3 technoloav lzj i v,, voitage v,, voltage 2.7v-3.6v 1 2.7v-3.6v, 11.4v-12.6v 1 internal v,, and v,, detection circuitry automatically configures the device for optimized read and write operations. a command user interface (cui) serves as the interface between the system processor and internal operation of the device. a valid command sequence written to the cui initiates device automation. an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase and word/byte write operations. a block erase operation erases one of the device?s 32k- word blocks typically within 0.51s (2.7v-3.6v v,,, 11.4v-12.6v v,,), 4k-word blocks typically within 0.3 1s (2.7v-3.6v v,,, 11.4v-12.6v v,,) independent of other blocks. each block can be independently erased 100,000 times. block erase suspend mode allows system software to suspend block erase to read or write data from any other block. writing memory data is performed in word/byte increments of the device?s 32k-word blocks typically within 12.6~~ (2.7v-3.6v v,,, 11.4v-12.6v v,,), 4k- word blocks typically within 24.5~~ (2.7v-3.6v v,,, 11.4v-12.6v v,,). word/byte write suspend mode enables the system to read data or execute code from any other flash memory array location. rev. 1.1
sharp lhf8ovo7 4 the boot blocks can be locked for the wp# pin. block erase or word/byte write for boot block must not be carried out by wp# to low and rp# to v,,. the status register indicates when the wsm?s block erase or word/byte write operation is finished. the ry/by# output gives an additional indicator of wsm activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). status polling using ry/by# minimizes both cpu overhead and system power consumption. when low, ry/by# indicates that the wsm is performing a block erase or word/byte write. ry/by#-high z indicates that the wsm is ready for a new command, block erase is suspended (and word/byte write is inactive), word/byte write is suspended, or the device is in deep power-down mode. the access time is 90ns (tav temperature range (o?c to +70 43 v) over the commercial ) and v,, supply voltage range of 2.7v-3.6v. the automatic power savings (aps) feature substar&& reduces active current when the device is in static modf (addresses not switching). in aps mode, the typical i,, current is 3 ma at 2.7v v,,. when ce# and rp# pins are at v,-,, the i,, cm05 standby mode is enabled. when the rp# pin is at gnd deep power-down mode is enabled which minimize: power consumption and provides write protection during reset. a reset time (tphqv) is required from rp# switching high until outputs are valid. likewise, the device has i wake time (tphel ) from rp#-high until writes to the cui are recognized. with rp# at gnd, the wsm is reset ant the status register is cleared. the device is available in 48-ball csp (chip size package). pinout is shown in figure 2. rev. 1.1
sharp lhf8ovo7 5 duo-dqls r figure 1. block diagram 1 a 0 a? b 0 a3 c 0 al d 0 ao f 0 ce# 2 0 a5 0 % 0 a4 0 oe# 0 dq8 0 dqo 6 0 a8 0 nc 0 a9 0 dq6 0 dq5 0 ql? 7 0 all 0 aio 0 al? 0 qm 0 dq7 8 0 .%?i 0 ai? 0 al5 0 a16 4%ball csp pinout 8mm x 8mm top view figure 2. csp #-ball pinout rev. 1.1
sharp lhf8ovo7 6 r table 2. pin descriptions name and function symbol a-, ao-al8 type input address inputs: addresses are internally latched during a write cycle. a-1 : byte select address. not used in x16 mode. ao-alo : row address. selects 1 of 2048 word lines. all-*,, . . column address. selects 1 of 16 bit lines. < data input/outputs: dqo-dq-/:inputs data and commands during cui write cycles; outputs data during memory array, status register and identifier code read cycles. data pins float to high-impedance when the chip is deselected or outputs are disabled. data is internally latched during a write cycle. dqs-dq, j:inputs data during cui write cycles in xl6 mode; outputs data during memory array read cycles in x 16 mode; not used for status register and identifier code read mode. data pins float to high-impedance when the chip is deselected, outputs are disabled. or in x8 mode (byte#=v,,j data is intemallv latched during a write cvcle. input/ output dqo-dq,, 1 chip enable: activates the device?s control logic. input buffers, decoders and sense amplifiers. ce#-high deselects the device and reduces power consumption to standby levels. reset/deep power-down: puts the device in deep power-down mode and resets internal automation. rp#-high enables normal operation. when driven low, rp# inhibits write operations which provides data protection during power transitions. exit from deep power-down sets the device to read array mode. with rp#=v,,, block erase or word/byte write can operate to all blocks without wp# state. block erase or word/byte write with vt, |