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WE512K8, we256k8, we128k8-xcx 1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2000 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. 512kx8 bit cmos eeprom module features read access times of 150, 200, 250, 300ns jedec standard 32 pin, hermetic ceramic dip (package 300) commercial, industrial and military temperature ranges mil-std-883 compliant devices available write endurance 10,000 cycles data retention at 25c, 10 years low power cmos operation: 3ma standby typical/100ma operating maximum automatic page write operation internal address and data latches for 512 bytes, 1 to 128 bytes/row, four pages page write cycle time 10ms max. data polling for end of write detection hardware and software data protection ttl compatible inputs and outputs figure 1 pin con? guration top view block diagram a18 a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v cc we# a17 a14 a13 a8 a9 a11 oe# a10 cs# i/o7 i/o6 i/o5 i/o4 i/o3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pin description a0-18 address inputs i/o0-7 data input/output cs# chip select oe# output enable we# write enable v cc +5.0v power v ss ground a 0-16 a 17 128k x 8 decoder 128k x 8 128k x 8 128k x 8 a 18 i/o 0-7 we# oe# cs# 512kx8 cmos eeprom, WE512K8-xcx, smd 5962-93091
WE512K8, we256k8, we128k8-xcx 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2000 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. 256kx8 cmos eeprom, we256k8-xcx, smd 5962-93155 256kx8 bit cmos eeprom module features read access times of 150, 200ns jedec standard 32 pin, hermetic ceramic dip (package 302) commercial, industrial and military temperature ranges mil-std-883 compliant devices available write endurance 10,000 cycles data retention at 25c, 10 years low power cmos operation: 2ma standby typical/90ma operating maximum automatic page write operation internal address and data latches for 512 bytes, 1 to 64 bytes/row, eight pages page write cycle time 10ms max. data polling for end of write detection hardware and software data protection ttl compatible inputs and outputs nc a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v cc we# a17 a14 a13 a8 a9 a11 oe# a10 cs# i/o7 i/o6 i/o5 i/o4 i/o3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a 0-14 a 16 a 15 1 32k x 8 decoder 2 32k x 8 8 32k x 8 a 17 i/o 0-7 we# oe# cs# figure 2 pin con? guration top view block diagram pin description a0-18 address inputs i/o0-7 data input/output cs# chip select oe# output enable we# write enable v cc +5.0v power v ss ground
WE512K8, we256k8, we128k8-xcx 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2000 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. 128kx8 cmos eeprom, we128k8-xcx, smd 5962-93154 128kx8 bit cmos eeprom module features read access times of 150, 200ns jedec standard 32 pin, hermetic ceramic dip (package 300) commercial, industrial and military temperature ranges mil-std-883 compliant devices available write endurance 10,000 cycles data retention at 25c, 10 years low power cmos operation: 1ma standby typical/70ma operating automatic page write operation internal address and data latches for 256 bytes, 1 to 64 bytes/row, four pages page write cycle time 10ms max. data polling for end of write detection hardware and software data protection ttl compatible inputs and outputs nc a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v cc we# nc a14 a13 a8 a9 a11 oe# a10 cs# i/o7 i/o6 i/o5 i/o4 i/o3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a 0-14 a 15 32k x 8 decoder 32k x 8 32k x 8 32k x 8 a 16 i/o 0-7 we# oe# cs# figure 3 pin con? guration top view block diagram pin description a0-18 address inputs i/o0-7 data input/output cs# chip select oe# output enable we# write enable v cc +5.0v power v ss ground
WE512K8, we256k8, we128k8-xcx 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2000 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. figure 4 ac test circuit dc characteristics v cc = 5.0v, v ss = 0v, -55c t a +125c parameter symbol conditions 512k x 8 256k x 8 128k x 8 unit min typ max min typ max min typ max input leakage current i li v cc = 5.5, v in = gnd to v cc 10 10 10 a output leakage current i lo cs# = v ih , oe# = v ih , vout = gnd to v cc 10 10 10 a dynamic supply current i cc cs# = v il , oe# = v ih , f = 5mhz, v cc = 5.5 80 100 60 90 50 70 ma standby current i sb cs# = v il , oe# = v ih , f = 5mhz, v cc = 5.5 3 8 2 6 1 4 ma output low voltage v ol i ol = 2.1ma, v cc = 4.5v 0.45 0.45 0.45 v output high voltage v oh i oh = -400a, v cc = 4.5v 2.4 2.4 2.4 v note: dc test conditions: vih = vcc -0.3v, vil = 0.3v truth table cs# oe# we# mode data i/o h x x standby high z l l h read data out l h l write data in x h x out disable high z/data out x x h write x l x inhibit capacitance t a = +25c parameter sym condition 512kx8 max 256kx8 max 128kx8 max unit input capacitance c in v in = 0v, f = 1mhz 45 80 45 pf output capacitance c out v i/o = 0v, f = 1mhz 60 80 60 pf this parameter is guaranteed by design but not tested. absolute maximum ratings parameter symbol unit operating temperature t a -55 to +125 c storage temperature t stg -65 to +150 c signal voltage any pin v g -0.6 to + 6.25 v voltage on oe# and a9 -0.6 to +13.5 v thermal resistance junction to case jc 28 c/w lead temperature (soldering -10 secs) +300 c note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci? cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol min max unit supply voltage v cc 4.5 5.5 v input high voltage v ih 2.0 v cc + 0.3 v input low voltage v il -0.3 +0.8 v operating temp. (mil.) t a -55 +125 c operating temp. (ind.) t a -40 +85 c ac test conditions parameter typ unit input pulse levels v il = 0, v ih = 3.0 v input rise and fall 5 ns input and output reference level 1.5 v output timing reference level 1.5 v notes: v z is programmable from -2v to +7v. i ol & i oh programmable from 0 to 16ma. tester impedance z0 = 75 ? . v z is typically the midpoint of v oh and v ol . i ol & i oh are adjusted to simulate a typical resistive load circuit. ate tester includes jig capacitance.
WE512K8, we256k8, we128k8-xcx 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2000 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. figure 5 shows read cycle waveforms. a read cycle begins with selection address, chip select and output enable. chip select is accomplished by placing the cs# line low. output enable is done by placing the oe# line low. the memory places the selected data byte on i/o0 through i/o7 after the access time. the output of the memory is placed in a high impedance state shortly after either the oe# line or cs# line is returned to a high level. ac read characteristics (see figure 5) for WE512K8-xcx v cc = 5.0v, v ss = 0v, -55c t a +125c parameter symbol -150 -200 -250 -300 unit min max min max min max min max read cycle time trc 150 200 250 300 ns address access time tacc 150 200 250 300 ns chip select access time tacs 150 200 250 300 ns output hold from address change, oe# or cs# toh 0000 ns output enable to output valid toe 85 85 100 125 ns chip select or output enable to high z output tdf 70 70 70 70 ns for we256k8-xcx and we128k8-xcx parameter symbol -150 -200 unit min max min max read cycle time trc 150 200 ns address access time tacc 150 200 ns chip select access time tacs 150 200 ns output hold from address change, oe# or cs# toh 0 0 ns output enable to output valid toe 85 85 ns chip select or output enable to high z output tdf 70 70 ns figure 5 C read waveforms address cs# oe# output note: oe# may be delayed up to t acs -t oe after the falling edge of cs# without impact on t oe or by t acc -t oe after an address change without impact on t acc . read
WE512K8, we256k8, we128k8-xcx 6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2000 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. write cycle timing figures 6 and 7 show the write cycle timing relationships. a write cycle begins with address application, write enable and chip select. chip select is accomplished by placing the cs# line low. write enable consists of setting the we line low. the write cycle begins when the last of either cs# or we# goes low. the we# line transition from high to low also initiates an internal 150sec delay timer to permit page mode operation. each subsequent we# transition from high to low that occurs before the completion of the 150sec time out will restart the timer from zero. the operation of the timer is the same as a retriggerable one-shot. write write operations are initiated when both cs# and we# are low and oe# is high. the eeprom devices support both a cs# and we# controlled write cycle. the address is latched by the falling edge of either cs# or we#, whichever occurs last. the data is latched internally by the rising edge of either cs# or we#, whichever occurs ? rst. a byte write operation will automatically continue to completion. ac write characteristics v cc = 5.0v, v ss = 0v, -55c t a +125c parameter symbol 512k x 8 256k x 8 128k x 8 unit min max min max min max write cycle time, typ = 6ms t wc 10 10 10 ms address set-up time t as 10 30 30 ns write pulse width (we# or cs#) t wp 150 150 150 ns chip select set-up time t cs 000ns address hold time (1) t ah 125 50 50 ns data hold time t dh 10 0 0 ns chip select hold time t ch 000ns data set-up time t ds 100 100 100 ns output enable set-up time t oes 10 30 30 ns output enable hold time t oeh 10 0 0 ns write pulse width high t wph 50 50 50 ns notes: 1. a17 and a18 must remain valid through we# and cs# low pulse, for 512k x 8. a15, a16, and a17 must remain valid through we# and cs# low pulse, for 256k x 8. a15 and a16 must remain valid through we# and cs# low pulse, for 128k x 8.
WE512K8, we256k8, we128k8-xcx 7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2000 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. figure 6 C write waveforms we# controlled oe# address (1) cs# we# data in oe# address (1) cs# we# data in figure 7 C write waveforms cs# controlled note: 1. decoded address lines must be valid for the duration of the write. note: 1. decoded address lines must be valid for the duration of the write.
WE512K8, we256k8, we128k8-xcx 8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2000 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. data polling operation with data polling permits a faster method of writing to the eeprom. the actual time to complete the memory programming cycle is faster than the guaranteed maximum. the eeprom features a method to determine when the internal programming cycle is completed. after a write cycle is initiated, the eeprom will respond to read cycles to provide the microprocessor with the status of the programming cycle. the status consists of the last data byte written being returned with data bit i/o 7 complemented during the programming cycle, and i/o 7 true after completion. data polling allows a simple bit test operation to determine the status of the eeprom. during the internal programming cycle, a read of the last byte written will produce the complement of the data on i/o 7 . for example, if the data written consisted of i/o 7 = high, then the data read back would consist of i/o 7 = low. a polled byte write sequence would consist of the following steps: 1. write byte to eeprom 2. store last byte and last address written 3. release a time slice to other tasks 4. read byte from eeprom - last address 5. compare i/o 7 to stored value a) if different, write cycle is not completed, go to step 3. b) if same, write cycle is completed, go to step 1 or step 3. data polling ac characteristics v cc = 5.0v, v ss = 0v, -55c t a +125c parameter symbol 512kx8 256kx8 128kx8 unit min max min max min max data hold time t dh 10 0 0 ns output enable hold time t oeh 10 0 0 ns output enable to output delay t oe 100 100 100 ns write recovery time t wr 000ns figure 8 C data polling waveforms oe# address cs 1-4 # we 1-4 # i/o 7
WE512K8, we256k8, we128k8-xcx 9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2000 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. page mode characteristics v cc = 5.0v, v ss = 0v, -55c t a +125c parameter symbol min max unit write cycle time, typ = 6ms t wc 10 ms data set-up time t ds 100 ns data hold time t dh 10 ns write pulse width t wp 150 ns byte load cycle time t blc 150 s write pulse width high t wph 50 ns device block address page address WE512K8-xcx a17-a18 a7-a16 we256k8-xcx a15-a17 a6-a14 we128k8-xcx a15-a16 a6-a14 page write operation these devices have a page write operation that allows one to 64 bytes of data (one to 128 bytes for the WE512K8) to be written into the device and then simultaneously written during the internal programming period. successive bytes may be loaded in the same manner after the ? rst data byte has been loaded. an internal timer begins a time out operation at each write cycle. if another write cycle is completed within 150s or less, a new time out period begins. each write cycle restarts the delay period. the write cycles can be continued as long as the interval is less than the time out period. the usual procedure is to increment the least signi? cant address lines from a 0 through a 5 (a 0 through a 6 for the WE512K8) at each write cycle. in this manner a page of up to 64 bytes (128 bytes for the WE512K8) can be loaded into the eeprom in a burst mode before beginning the relatively long interval programming cycle. after the 150s time out is completed, the eeprom begins an internal write cycle. during this cycle the entire page of bytes will be written at the same time. the internal programming cycle is the same regardless of the number of bytes accessed. figure 9 C page write waveforms note: 1. decoded address lines must be valid for the duration of the write. oe# address (1) cs# we# data the page address must be the same for each byte load and must be valid during each high to low transition of we# (or cs#). the block address also must be the same for each byte load and must remain valid throughout the we# (or cs#) low pulse. the page and block address lines are summarized below:
WE512K8, we256k8, we128k8-xcx 10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2000 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. figure 10 C software block data protection enable algorithm notes: 1. data format: i/o 7-0 (hex); address format: a 14 -a 0 (hex). a 17 and a 18 control selection of one of four blocks in the 512kx8. a 15 , a 16 , and a 17 control selection of one of 8 pages in the 256kx8. a 15 and a 16 control one of the four blocks in the 128kx8. 2. write protect state will be activated at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data at each of 4 blocks may be loaded in the 512kx8. 1 to 64 bytes of data at each of 8 blocks may be loaded in the 256kx8 and 1 to 64 bytes on 4 blocks in the 128kx8. (1) writes enabled (2) enter data protect state load data aa to address 5555 load data 55 to address 2aaa load data a0 to address 5555 load data xx to any address (4) load last byte to last address
WE512K8, we256k8, we128k8-xcx 11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2000 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 20 to address 5555 load data xx to any address(4) load last byte to last address (1) figure 11 C software block data protection disable algorithm software data protection a software write protection feature may be enabled or disabled by the user. when shipped by white microelectronics, the devices have the feature disabled. write access to the device is unrestricted. to enable software write protection, the user writes three access code bytes to three special internal locations. once write protection has been enabled, each write to the eeprom must use the same three byte write sequence to permit writing. after setting software data protection, any attempt to write to the device without the three-byte command sequence will start the internal write timers. no data will be written to the device, however, for the duration of t wc . the write protection feature can be disabled by a six byte write sequence of speci? c data to speci? c locations. power transitions will not reset the software write protection. each 32k byte block (128k bytes for the WE512K8) of eeprom has independent write protection. one or more blocks may be enabled and the rest disabled in any combination. the software write protection guards against inadvertent writes during power transitions or unauthorized modification using a prom programmer. the block selection is controlled by the upper most address lines (a 17 through a 18 for the WE512K8, a 15 through a 17 for the we256k8, or a 15 and a 16 for the we128k8). hardware data protection several methods of hardware data protection have been implemented in the white microelectronics eeprom. these are included to improve reliability during normal operations. a) v cc power on delay as v cc climbs past 3.8v typical the device will wait 5msec typical before allowing write cycles. b) v cc sense while below 3.8v typical write cycles are inhibited. c) write inhibiting holding oe# low and either cs# or we# high inhibits write cycles. d) noise ? lter pulses of <8ns (typ) on we# or cs# will not initiate a write cycle. notes: 1. data format: i/o 7-0 (hex); address format: a 14 -a 0 (hex). a 17 and a 18 control selection of one of four blocks in the 512kx8. a 15 , a 16 , and a 17 control selection of one of 8 pages in the 256kx8. a 15 and a 16 control one of the four blocks in the 128kx8. 2. write protect state will be activated at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data at each of 4 blocks may be loaded in the 512kx8. 1 to 64 bytes of data at each of 8 blocks may be loaded in the 256kx8 and 1 to 64 bytes on 4 blocks in the 128kx8. exit data protect state (3)
WE512K8, we256k8, we128k8-xcx 12 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2000 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. package 300: 32 pin, ceramic dip, single cavity side brazed all linear dimensions are millimeters and parenthetically in inches package 302: 32 pin, ceramic dip, dual cavity bottom brazed all linear dimensions are millimeters and parenthetically in inches
WE512K8, we256k8, we128k8-xcx 13 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2000 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. ordering information lead finish: blank = gold plated leads a = solder dip leads processing: q = mil-std-883 compliant m = military screened -55c to +125c i = industrial -40c to +85c c = commercial 0c to +70c package: c = ceramic dip (package 300 for 128kx8) (package 302 for 256kx8) (package 300 for 512kx8) access time (ns) organization, 512kx8, 256kx8 or 128kx8 eeprom white electronic designs device type speed package wm part no. smd no. 512k x 8 eeprom 150ns 32 pin dip (c) WE512K8-150cq 5962-93091 01hyx 512k x 8 eeprom 300ns 32 pin dip (c) WE512K8-300cq 5962-93091 02hyx 512k x 8 eeprom 250ns 32 pin dip (c) WE512K8-250cq 5962-93091 03hyx 512k x 8 eeprom 200ns 32 pin dip (c) WE512K8-200cq 5962-93091 04hyx 256k x 8 eeprom 200ns 32 pin dip (c) we256k8-200cq 5962-93155 01hyx 256k x 8 eeprom 150ns 32 pin dip (c) we256k8-150cq 5962-93155 02hyx 128k x 8 eeprom 200ns 32 pin dip (c) we128k8-200cq 5962-93154 01hxx 128k x 8 eeprom 150ns 32 pin dip (c) we128k8-150cq 5962-93154 02hxx w e xxxk8 - xxx c x x

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