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p-dso-14-14 can-ldo asic tle 6272 version 1.3 1 12.02.2002 preliminary data sheet description the tle 6272 is an integration of a high speed can-tansceiver functionality together with a low dropout fixed 5v regulator in an enhanced power p-dso-14-14 package. the 5v output is designed loads up to 150 ma. in addition the device offers a reset circuitry as well as separate mode control inputs for the transceiver and the voltage regulator to minimize power consumption. the power-on delay time of the reset feature can be adjusted via a delay input. by this the tle 6272 is optimized to support high speed differential mode data transmission in automotive and industrial applications. the tle 6272 is designed to withstand the severe conditions of automotive applications. type ordering code package tle 6272 on request p-dso-14-14 1overview 1.1 features ? high speed can transceiver for data transmission rate up to 1 mbaud ? very low drop voltage regulator 5v 2% ? 150ma output currentr ? excellent emc behaviour ? very low quiescent current voltage regulator, typ. 65a ? separate enable/inhibit input for transceiver and voltage regulator ? power-on and under-voltage reset ? can outputs short circuit proof to ground and battery ? reverse polarity proof ? over-temperatur protection ? over-load and short circuit protected ? wide temperature range
preliminary data tle 6272 version 1.3 2 12.02.2002 1.2 pin configuration (top view) figure 1 1.3 pin definitions and functions: 5v-version pin no. symbol function 1, 7, 8, 14 gnd ground; directly connected to chip carrier, place to cooling tabs to improve thermal behaviour 2envr enable input voltage regulator; high active, if not needed connect to vs, 1 m pull down resistor 3ro reset output; open collector output, 20 k pull up 4v cc 5v output; connect ot gnd with a 22f capacitor, esr < 3 , 5rxd can receive data output; low in dominant state 6canl low line input; low in dominant state 9canh high line output; high in dominant state 10 inht inhibit transceiver; 20 k pull up, set low for can normal mode 11 txd can transmit data input; 20 k pull up, low in dominant state 12 vs battery supply input; block to ground with ceramic capacitor of 100nf 13 d reset delay; to adjust power-on delay time connect to ground via ceramic capacitor 2 1 5 4 3 9 8 6 12 11 10 13 14 canl vcc txd d vs envr gnd gnd gnd gnd canh ro rxd 14 8 1 7 chip: transceiver leadframe inht chip: voltage regulator
preliminary data tle 6272 version 1.3 3 12.02.2002 receiver output stage driver temp.- protection 6 canh canl vcc 9 4 11 txd rxd 5 1/7/8/14 gnd tle 6272 mode control 8 inht + - reference reset control current & saturation control voltage regulator enable control vs 12 d 13 envr 2 ro 3 band-gap reference 1.4 functional block diagram figure 2
preliminary data tle 6272 version 1.3 4 12.02.2002 2 application information the tle 6272 is a dual chip ic that offers features of the can-transceiver tle 6250 and the voltage regulator tle 4299 in one package. the voltage regulator of the tle 6272 is a pnp based very low drop linear voltage regulator. it regulates the output voltage v cc = 5v at an input voltage range of 5.5v v s 45v. the control circuirtry protects the device against damages like overcurrent and overtemperature. the internal control circuit achieves a 5v output voltage with a tolerance of 2%. the device includes a power-on reset and an under-voltage reset function with adjustable reset delay time. further there is implemented a separate enable / inhibit function for both, the voltage regulator (including reset circuitry) and the can- transceiver. by this the can-transceiver circuitry can be switched off to reduce the power consumption while the voltage regulator still supplies other loads. when the voltage regulator is disabled via the envr input also the can-transceiver is automatically switched off due to the missing supply voltage via v cc . the reset logic compares the output voltage v cc to an internal threshold. if the output voltage drops below this level, the external reset delay capacitor c d is discharged. when v d is lower than v st , the output reset is switched low . if the output voltage drop is very short, the v st level is not reached and no reset-signal is asserted. this feature avoids resets at short negative spikes at the output voltage e. g. caused by load changes. please see figure 3, reset timing diagram. as soon as the output voltage is more positive than the reset threshold, the delay capacitor is charged with constant current. when the voltage reaches v du the reset output ro is set high again. (reset-hysteresis) the reset threshold v rt is internally defined (typical 4.65v). the reset delay time is defined by the external capacitor c d that is charged by a constant current i d up to a certain threshold v dt during power on phase. please see figure 3, reset timing diagram. the reset function is active down to v cc = 1v. when the inht is low while v cc is present, the can-transceiver circuitry is in the normal operation mode. then messages can be transmitted or received respectively via the rxd and txd pin. the can stand-by mode is a low power mode that disables both, the receiver as well as the transmitter within the can-transceiver. a message sent by the microcontroller to the txd input is transformed to a differential mode signal and sent to other can nodes via the canh and canl output. differential mode data on the bus lines is reported to the microcontroller via the rxd ouput.
preliminary data tle 6272 version 1.3 5 12.02.2002 application description the input capacitor c vs compenstates line influences. a resistor of approx. 1 in series with c vs , damps the oscillating circuit of input inductivity and input capacitance. the output capacitor c q stabilizes the regulating circuit. stability is guaranteed at values c vcc 22 f and an esr 3 within the operating temperature range. please consider the capacitance-tolerance and temperature coefficient of the reset delay capacitor when calculating the timings. the reset timing and its calculation is shown in figure 3.
preliminary data tle 6272 version 1.3 6 12.02.2002 3 electrical characteristics note: maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. 3.1 absolute maximum ratings parameter symbol limit values unit remarks min. max. voltages supply voltage v s - 40 42 i load 1ma supply voltage v s - 40 40 output voltage v cc - 0.3 6.5 v output current i cc ?5 *) ma *) internally limited envr input voltage v envr - 40 42 can input voltage (canh, canl) v canh/l -20 40 v logic voltages at inht, txd, rxd, ro, d v i -0.3 v cc +0.3 v 0 v < v cc < 5.5 v electrostatic discharge voltage at canh, canl v esd -4 4 kv human body model (100 pf via 1.5 k electrostatic discharge voltage v esd -2 2 kv human body model (100 pf via 1.5 k temperatures junction temperature t j - 40 150 c storage temperature t stg - 50 150 c
preliminary data tle 6272 version 1.3 7 12.02.2002 3.2 operating range parameter symbol limit values unit remarks min. max. supply voltage v s 5.5 42 v junction temperature t j ? 40 150 c ? thermal resistances junction ambient r thj-a ?70k/w ? thermal shut down (junction temperature) thermal shutdown temp. can t jsd,can 150 190 c 10k hysteresis thermal shutdown temp. voltage regulator t jsd,vr 150 190 c 10k hysteresis
preliminary data tle 6272 version 1.3 8 12.02.2002 3.3 electrical characteristics v s =13.5v;r l =60 ; v envr > v envr,on ; v inht < v inht,on ; ?40 c < t j < 125 c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. parameter symbol limit values unit test condition min. typ. max. current consumption current consumption ( i q +i tr )= i s ? i load i q +i tr 610ma i cc 1ma; can recessive state; v txd = v cc current consumption ( i q +i tr )= i s ? i load i q +i tr 45 70 ma i cc 1ma; can dominant state; v txd = 0v current consumption ( i q +i tr )= i s ? i load i q +i tr 130 a v inht > v inht,off i cc 1ma; tj < 85c current consumption; ( i q +i tr )= i s ? i load i q +i tr ? 250 500 a v inht > v inht,off i cc =10ma current consumption; ( i q +i tr )= i s ? i load i q +i tr ?28ma v inht > v inht,off i cc =100ma current consumption; ( i q +i tr )= i s ? i load i q +i tr 15 a v envr < v envr,off tj < 85c voltage regulator output voltage v cc 4.90 5.00 5.10 v 1ma i cc 100ma 6v v s 16v current limit i cc 250 300 500 ma i cc =i tr +i load drop voltage v dr ? 0.25 0.5 v i cc =100ma * ) load regulation v cc ?1030mv 1ma i cc 100ma line regulation v cc ?1040mv v s = 6v to 26v i cc =1ma power supply ripple rejection psrr ?50?db fr= 100hz; vr = 0,5 v pp ; guaranteed by design * ) drop voltage = v s ?v cc (measured when the output voltage has dropped 100 mv from the nominal value obtained at 13.5 v input.)
preliminary data tle 6272 version 1.3 9 12.02.2002 enable voltage regulator envr enable vr off voltage range v envr,off 0.8 v enable vr on voltage range v envr,on 4.0 v enable current on i envr,on 15a reset generator switching threshold v rt 4.50 4.65 4.80 v reset pull up r ro 10 20 40 k reset low voltage v r ?0.10.4v v cc < 4.5v, reset current i r 5ma v ro(low) < 400 mv, reset operational down to 1v delay switching threshold v dt 1.51.82.2v switching threshold v st 0.3 0.45 0.60 v reset delay low voltage v d ?0.1v v cc v envr,on ; v inht < v inht,on ; ?40 c < t j <125c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. parameter symbol limit values unit test condition min. typ. max.
preliminary data tle 6272 version 1.3 10 12.02.2002 can-transceiver receiver output r d high level output current i rd,h -4 -2 ma v rd > 0.8 x v cc , v diff < 0.4 v low level output current i rd,l 24 ma v rd < 0.2 x v cc , v diff > 1v bus receiver differential receiver threshold voltage, recessive to dominant edge v diff,d 0.75 0.9 v -20v < ( v canh ,v canl ) < 25v v diff = v canh - v canl differential receiver threshold voltage dominant to recessive edge v diff,r 0.5 0.6 v -20v < ( v canh ,v canl ) < 25v v diff = v canh - v canl differential receiver hysteresis v diff,hys 150 mv canh, canl input resistance r i 10 20 30 k recessive state differential input resistance r diff 20 40 60 k recessive state transmission input t d high level input voltage threshold v td,h 0.5x v cc 0.7x v cc v recessive state; low level input voltage threshold v td,l 0.3x v cc 0.4x v cc v dominant state txd pull up resistance r td 10 25 50 k 3.3 electrical characteristics (cont?d) v s =13.5v;r l =60 ; v envr > v envr,on ; v inht < v inht,on ; ?40 c < t j < 125 c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. parameter symbol limit values unit test condition min. typ. max.
preliminary data tle 6272 version 1.3 11 12.02.2002 bus transmitter canl/canh recessive output voltage v canl/h 0.4x v cc 0.6x v cc v v txd = v cc canh, canl recessive output voltage difference v diff ?1 0.05 v v txd = v cc ; no load v diff = v canh - v canl (see note below) canl dominant output voltage v canl 2.0 v v txd = 0v; canh dominant output voltage v canh 3.0 v v txd = 0v canh, canl dominant output voltage difference v diff 1.5 3.0 v v txd = 0v; v diff = v canh - v canl canl short circuit current i canlsc 50 120 ma v canlshort = 18v 150 ma v canlshort = 36v canh short circuit current i canhsc -120 -50 ma v canhshort = 0v -120 ma v canhshort = - 5v leakage current i canh,lk i canl,lk -300 a v cc =0v, v canh = v canl = -7v leakage current i canh,lk i canl,lk 300 a v cc =0v, v canh = v canl = 7v inhibit transceiver input inht high level input voltage threshold v inht,h 0.5x v cc 0.7x v cc v can stand-by mode; low level input voltage threshold v inht,l 0.3x v cc 0.4x v cc v can normal mode inht pull up resistance r inht 10 25 50 k note: deviation from iso/dis 11898 3.3 electrical characteristics (cont?d) v s =13.5v;r l =60 ; v envr > v envr,on ; v inht < v inht,on ; ?40 c < t j <125c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. parameter symbol limit values unit test condition min. typ. max.
preliminary data tle 6272 version 1.3 12 12.02.2002 dynamic can-transceiver characteristics propagation delay txd-to-rxd low (recessive to dominant) t d(l),tr 150 280 ns c l = 47pf; r l = 60 ; c rxd = 20pf propagation delay txd-to-rxd high (dominant to recessive) t d(h),tr 150 280 ns c l = 47pf; r l = 60 ; c rxd = 20pf propagation delay txd low to bus dominant t d(l),t 100 ns c l = 47pf; r l = 60 ; propagation delay txd high to bus recessive t d(h),t 100 ns c l = 47pf; r l = 60 ; propagation delay bus dominant to rxd low t d(l),r 50 ns c l = 47pf; r l = 60 ; c rxd = 20pf propagation delay bus recessive to rxd high t d(h),r 50 ns c l = 47pf; r l = 60 ; c rxd = 20pf 3.3 electrical characteristics (cont?d) v s =13.5v;r l =60 ; v envr > v envr,on ; v inht < v inht,on ; ?40 c < t j < 125 c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. parameter symbol limit values unit test condition min. typ. max.
preliminary data tle 6272 version 1.3 13 12.02.2002 4 diagrams figure 3: reset timing diagram figure 4: timing diagrams for dynamic characteristics aed01542 thermal t d power-on-reset voltage dip secondary overload at output spike v st v v d v ro d = v d dt v q rt v t rr < rr t v dt at input undervoltage shutdown c d gnd v txd t v cc v diff t gnd v rxd t v cc 0.3*v cc 0.7*v cc t d(h),r t d(l),r t d(h),tr t d(l),tr t d(h),t t d(l),t v diff(d) v diff(r)
preliminary data tle 6272 version 1.3 14 12.02.2002 5 application figure 5 application circuit v bat canh canl can bus tle 6272 g gnd p txd rxd c vcc 22 f v cc gnd c d 100 nf 100 nf 120 ecu 120 inht 1/7/8/14 10 5 11 4 9 6 2 envr v s 12 d ro 3 13 e.g. c164, c167 c vs2 100 nf c vs2 22 f
preliminary data tle 6272 version 1.3 15 12.02.2002 6 package outlines sorts of packing package outlines for tubes, trays etc. are contained in our data book ?package information?. smd = surface mounteddevice dimensions in mm p-dso-14-14 (plastic dual small outline package)
preliminary data tle 6272 version 1.3 16 12.02.2002 edition 1999-10-12 published by infineon technologies ag st.-martin-strasse 53 d-81541 mnchen ? infineon technologies ag1999 all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, des criptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologi es office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please cont act your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infin eon tech- nologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system , or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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