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91400 rm (im) sk-1/20 ver.1.03 10798 preliminary overview the lc867248a/40a/32a/24a microcontrollers are 8-bit single chip microcontrollers with the following on-chip functional blocks : - cpu : operable at a minimum bus cycle time of 0.5 s (microsecond) - on-chip rom maximum capacity : 48k bytes - on-chip ram capacity : 1152 bytes - lcd controller/driver - two 16-bit timers (or four 8-bit timers) - 8-channel 8-bit ad converter - two 8-bit synchronous serial-interface circuits - 13-source 10-vectored interrupt system all of the above functions are fabricated on a single chip. features (1) read only memory (rom) : lc867248a 49152 8 bits : lc867240a 40960 8 bits : LC867232A 32768 8 bits : lc867224a 24576 8 bits (2) random access memory (ram) : 1152 8 bits (3) bus cycle time/instruction cycle time bus cycle time cycle time clock divider system clock oscillation oscillation frequency voltage 0.5 s 1.0 s 1/1 ceramic resonator oscillation 6mhz 4.5 - 6.0v 2 s 4.0 s 1/2 ceramic resonator oscillation 3mhz 2.5 - 6.0v 7.5 s 15.0 s 1/2 rc resonator oscillation 800khz 2.5 - 6.0v 183 s 366 s 1/2 crystal oscillation 32.768khz 2.5 - 6.0v 8-bit single chip microcontroller lc867248a/40a/32a/24a ordering number : enn*6702 cmos ic
lc867248a/40a/32a/24a 2/20 (4) ports - input / output ports : 70 terminals (normal ports p0, p1, p3, pa, pb, pc, pd, pe, pf) p0 input/output port programmable in nibble units : 1 port (8 terminals) (when the n-channel open drain output is selected, the data in a bit can be inputted.) p1 input/output port programmable in a bit : 1 port (8 terminals) p3 input/output port programmable in a bit : 1 port (6 terminals) pa, pb, pc, pd, pe, pf (can be used for lcd) input/output port programmable in two bits : 6 ports (48 terminals) - input ports : 21 terminals (p7, p8, pl) - lcd control port : 52 terminals segment output port : 48 terminals common output port : 4 terminals (5) lcd controller / driver - selectable seven kinds of display mode (a combination of static 1/2, 1/3, 1/4 duty and 1/2, 1/3 bits) - the segment and common output ports can be switched to a general input/output port. (6) ad converter - 8-channel 8-bit ad converter (7) serial-interface - one channel 16-bit serial-interface circuits (8-bit transmission available by program) - lsb first/msb first function available - internal 8-bit baud-rate generator in common with two serial-interface circuits (8) timers - timer0 16-bit timer / counter 2-bit prescaler + 8-bit programmable prescaler mode 0 : two 8-bit timers with programmable prescaler mode 1 : 8-bit timer with programmable prescaler + 8-bit counter mode 2 : 16-bit timer with programmable prescaler mode 3 : 16-bit counter the resolution of timer is tcyc. (tcyc : cycle time) - timer1 16-bit timer / pwm mode 0 : two 8-bit timers mode 1 : 8-bit timer + 8-bit pwm mode 2 : 16-bit timer mode 3 : variable-bit pwm (9-16 bits) in mode 0 and mode 1, the resolution of timer and pwm is tcyc. in mode 2 and mode 3, the resolution of timer and pwm selectable ; tcyc or 1/2tcyc by program - base timer every 500ms overflow system for a clock application (using 32.768khz crystal oscillation for base timer clock) every 976 s, 3.9ms, 15.6ms, 62.5ms overflow system (using 32.768khz crystal oscillation for base timer clock) the base timer clock selectable ; 32.768khz crystal oscillation, system clock, and programmable prescaler output of timer 0 (9) buzzer output - the buzzer sound frequency selectable ; 4khz, 2khz (using 32.768khz crystal oscillation for base timer clock)
lc867248a/40a/32a/24a 3/20 (10) remote control receiver circuit (shares with the p73/int3/t0in terminal) - noise rejection - switch polarity function (11) watchdog timer - the watchdog timer is taken on rc outside - watchdog timer operation selectable : interrupt system, system reset (12) interrupts system - 13-source 10-vectored interrupts : 1. external interrupt int0 (include watchdog timer) 2. external interrupt int1 3. external interrupt int2, timer / counter t0l (lower 8-bit) 4. external interrupt int3, base timer 5. timer / counter t0h (upper 8-bit) 6. timer t1l, timer t1h 7. serial interface sio0 8. serial interface sio1 9. ad converter 10. port 0 - built-in interrupt priority control register microcontroller allows 3 levels of interrupt; low level, high level, and highest level of multiplex interrupt. it can specify a low level or a high level interrupt priority from int2/t0l through port 0 (i.e. the above interrupt number from three through ten). it can also specify a low level or the highest level interrupt priority to int0 and int1. (13) real-time service operation the real-time service (rts) functions the 4-byte data-transfer between the special function registers at acknowledging the interrupt request. the rts starts within 1 instruction cycle-time and completes within 5 instruction cycle-times after occurring the interrupt request. (14) sub-routine stack levels - 128 levels (max.) : stack area included in ram area (15) multiplication and division - 16-bit 8-bit (7 instruction cycle times) - 16-bit 8-bit (7 instruction cycle times)
lc867248a/40a/32a/24a 4/20 (16) three oscillation circuits - on-chip rc oscillation circuit using for the system clock - on-chip cf oscillation circuit using for the system clock - on-chip crystal oscillation circuit using for the system clock and for time-base clock (17) standby function - halt mode function the halt mode is used to reduce the power dissipation. in this operation mode, the program execution is stopped. this operation mode can be released by the interrupt request signals or the system reset request signal. - hold mode function the hold mode is used to freeze all the oscillations ; rc (internal), cf and crystal oscillations. this mode can be released by the following operations. reset terminal ( res ) set to low level. input a assigned level to p70/int0 or p71/int1 terminal input a port0 interrupt condition (18) factory shipment qfp100e delivery form (19) development support tools - evaluation (eva) chip : lc866093 - eprom version : lc86e7248 - one time version : lc86p7248 - emulator : eva86000 + ecb867200 (evaluation chip board) + pod866200 (pod) notes for use follow the under table frequency range of the system clock voltage range clock divider note 15khz to 30khz 1/1 can not use 1/2 divider 30khz to 6mhz 4.5v to 6.0v 1/1, 1/2 15khz to 30khz 1/1 can not use 1/2 divider 30khz to 1.5mhz 1/1, 1/2 1.5mhz to 3mhz 2.5v to 6.0v 1/2 can not use 1/1 divider 4.5v to 6.0v 1/1, 1/2 internal rc oscillation 2.5v to 6.0v 1/2 can not use 1/1 divider
lc867248a/40a/32a/24a 5/20 pin assignment package dimension (unit : mm) 3151 sanyo : qip-100e s20/pc4 s19/pc3 s18/pc2 s17/pc1 s16/pc0 s15/pb7 s14/pb6 s13/pb5 s12/pb4 s11/pb3 s10/pb2 s9/pb1 s8/pb0 s7/pa7 s6/pa6 s5/pa5 s4/pa4 s3/pa3 s2/pa2 s1/pa1 v2/pl5 v1/pl4 com0/pl0 com1/pl1 com2/pl2 com3/pl3 p30 p31 vss3 vdd3 p32 p33 p34 p35 p00 p01 p02 p03 p04 p05 v3/pl6 s47/pf7 s46/pf6 s45/pf5 s44/pf4 s43/pf3 s42/pf2 s41/pf1 s40/pf0 s39/pe7 s38/pe6 s37/pe5 s36/pe4 s35/pe3 s34/pe2 s33/pe1 s32/pe0 s31/pd7 s30/pd6 s29/pd5 s28/pd4 s27/pd3 s26/pd2 vss2 vdd2 s25/pd1 s24/pd0 s23/pc7 s22/pc6 s21/pc5 p06 p07 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 p16/buz p17/pwm0 p70/int0 res xt1/ p74 xt2/p75 vss1 cf1 cf2 vdd1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7 p71/int1 p72/int2/t0i n p73/int3/t0i n s0/pa0 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
lc867248a/40a/32a/24a 6/20 system block diagram interrupt control stand-by control clock generator cf rc x?tal base timer bus interface acc pc rom ir pla b register c register alu psw rar ram stack pointer port 0 watchdog timer port 1 port 7 port 8 port 3 adc int0-3 noise rejection filter sio0 sio1 timer 0 timer 1 real time service ram 128 bytes lcd display controller so0 - s7 (pa) s8 - s13 (pb) com0-com3(pl) s16 - s23 (pc) s24 - s31 (pd) s32 - s39 (pe) s40 - s47 (pf)
lc867248a/40a/32a/24a 7/20 pin description pin name i/o function description option vss1, 2, 3 - power pin (?) - vdd1, 2, 3 - power pin (+) - port0 p00 - p07 i/o 8-bit input/output port input/output in nibble units input for port 0 interrupt input for hold release pull-up resistor : provided/not provided (specified in nibble units) output form (p00 ? p07) : cmos/n-channel open drain (specified in a bit) port1 p10 - p17 i/o 8-bit input/output port input/output can be specified in bit unit other pin functions p10 sio0 data output p11 sio0 data input/bus input/output p12 sio0 clock input/output p13 sio1 data output p14 sio1 data input/bus input/output p15 sio1 clock input/output p16 buzzer output p17 timer1 output (pwm output) output form : cmos/n-channel open drain (specified in a bit) port3 p30 - p35 i/o 6-bit input/output port input/output in nibble units output form : cmos/n-channel open drain (specified in a bit) 6-bit input port other pin functions p70 : int0 input/hold release input/ n-channel tr. output for watchdog timer p71 : int1 input/hold release input p72 : int2 input/timer 0 event input p73 : int3 input with noise filter/timer 0 event input interrupt received form, vector address pull-up resistor : provided/not provided (specified in a bit) (p70, p71, p72, p73) * p74 , p75 don?t have the pull-up resistor option. rising falling rising & falling high level low level vector int0 enable enable disable enable enable 03h int1 enable enable disable enable enable 0bh int2 enable enable enable disable disable 13h int3 enable enable enable disable disable 1bh port7 p70 p71 - p73 p74 - p75 i/o i i p74 : xt1 terminal for crystal oscillation p75 : xt2 terminal for crystal oscillation port8 p80 ? p87 i 8-bit input port other function ad input port (8 port pins) -
lc867248a/40a/32a/24a 8/20 pin name i/o function description option port a (s0/pa0 ? s7/pa7) i/o segment output terminal for lcd display can be used as a general input/output port - port b (s8/pb0 ? s15/pb7) i/o segment output terminal for lcd display can be used as a general input/output port - port c (s16/pc0 ? s23/pc7) i/o segment output terminal for lcd display can be used as a general input/output port - port d (s24/pd0 ? s31/pd7) i/o segment output terminal for lcd display can be used as a general input/output port - port e (s32/pe0 ? s39/pe7) i/o segment output terminal for lcd display can be used as a general input/output port - port f (s40/pf0 ? s47/pf7) i/o segment output terminal for lcd display can be used as a general input/output port - port l (com0/pl0 ? com3/pl7) i/o common output terminal for lcd display can be used as a general input port - v1/pl4 ? v3/pl6 i bias power terminal for lcd drive can be used as a general input port - res i reset pin - xt1/ p74 i input pin for 32.768khz crystal oscillation in case of non use, connect to vdd. other function a general input port p74 - xt2/p75 o output pin for 32.768khz crystal oscillation in case of non use, should be left unconnected other function a general input port p75 - cf1 i input pin for ceramic resonator oscillation - cf2 o output pin for ceramic resonator oscillation - * all of port options can be specified in bit unit except the pull-up resistor of port 0. * a state of pins at reset pin name i/o mode a state of pull-up resistor specified at pull-up option port 0 input fixed pull-up resistor off port 1 input programmable pull-up resistor off port 3 input programmable pull-up resistor off ports 70, 71, 72, 73 input fixed pull-up resistor off xt1/ p74 , xt2/p75 input general input port as p74 , p75 (if using as the crystal oscillation, the specified register must be set.) pin name i/o mode ports a, b, c, d, e, f output off
lc867248a/40a/32a/24a 9/20 [notes] the vdd1, vdd2 and vdd3 terminals must be shorted electrically each other. the vss1, vss2 and vss3 terminals must be shorted electrically each other. * connect like the following figure to reduce noise into a vdd terminals. power supply vdd1 vdd2 vdd3 vss1 vss2 vss3 lsi
lc867248a/40a/32a/24a 10/20 1. absolute maximum ratings at ta=25 c, vss=vss1=vss2=vss3=0v ratings parameter symbol pins conditions v dd [v] min. typ. max. unit supply voltage vddmax vdd1, vdd2 vdd3 vdd1=vdd2= vdd3 -0.3 +7.0 lcd display voltage vlcd v1/pl4, v2/pl5 v3/pl6 vdd1=vdd2= vdd3 -0.3 vdd input voltage vi ports 71, 72, 73 ports 74 , 75 port 8, port l res -0.3 vdd+0.3 input/output voltage vio port 0, 1, 3 ports 70 ports a,b,c,d,e,f -0.3 vdd+0.3 v ioph(1) ports 0, 1, 3 -4 peak output current ioph(2) ports a,b,c,d,e,f cmos output at each pins -4 ioah(1) ports 0, 1, 32, 33, 34, 35 total all pins -38 ioah(2) ports 30, 31 total all pins -4 ioah(3) ports s0 to s25 total all pins -25 high level output current total output current ioah(4) ports s26 to s47 total all pins -25 iopl(1) ports 0, 1, 3 at each pins 20 iopl(2) ports a,b,c,d,e,f at each pins 20 peak output current iopl(3) port 70 at each pins 15 ioal(1) ports 0, 1, 32, 33, 34, 35 total all pins 50 ioal(2) ports 30, 31 total all pins 20 ioal(3) ports s0 to s25 total all pins 39 ioal(4) ports s26 to s47 total all pins 33 low level output current total output current ioal(5) port 70 total all pins 10 ma maximum power dissipation pdmax qfp100e ta=-30 to+70 c 515 mw operating temperature range topr -30 +70 storage temperature range tstg -55 +125 c
lc867248a/40a/32a/24a 11/20 2. recommended operating range at ta=-30 c to +70 c, vss=vss1=vss2=vss3=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit vdd(1) 0.98 s t cyc 400 s 4.5 6.0 operating supply voltage range vdd(2) vdd1=vdd2 =vdd3 3.9 s t cyc 400 s 2.5 6.0 hold voltage vhd vdd1=vdd2 =vdd3 rams and the registers hold voltage at hold mode. 2.0 6.0 vih(1) port 0 output disable 2.5-6.0 0.4vdd +0.9 vdd vih(2) ports 1, 3 ports a,b,c,d,e,f ports 72, 73 output disable 2.5-6.0 0.75vdd vdd vih(3) port 70 port input/interrupt port 71 res output n-channel tr. off 2.5-6.0 0.75vdd vdd vih(4) port 70 watchdog timer output n-channel tr. off 2.5-6.0 0.9vdd vdd input high voltage vih(5) port 8 ports 74 ,75 using as port 2.5-6.0 0.75vdd vdd vil(1) port 0 output disable 2.5-6.0 vss 0.2vdd vil(2) ports 1, 3 ports a,b,c,d,e,f ports 72, 73 output disable 2.5-6.0 vss 0.25vdd vil(3) port 70 port input/interrupt port 71 res output n-channel tr. off 2.5-6.0 vss 0.25vdd vil(4) port 70 watchdog timer output n-channel tr. off 2.5-6.0 vss 0.8vdd -1.0 input low voltage vil(5) port 8 ports 74 ,75 using as port 2.5-6.0 vss 0.25vdd v 4.5-6.0 0.98 400 operation cycle time t cyc 2.5-6.0 3.9 400 s fmcf(1) cf1, cf2 6mhz (ceramic resonator oscillation) refer to figure 1 4.5-6.0 6 fmcf(2) cf1, cf2 3mhz (ceramic resonator oscillation) refer to figure 1 2.5-6.0 3 fmrc rc oscillation 2.5-6.0 0.3 0.8 3.0 mhz oscillation frequency range (note 1) fsxtal xt1, xt2 32.768khz (crystal oscillation) refer to figure 2 2.5-6.0 32.768 khz tmscf(1) cf1, cf2 6mhz (ceramic resonator oscillation) refer to figure 3 4.5-6.0 4.5-6.0 tmscf(2) cf1, cf2 3mhz (ceramic resonator oscillation) refer to figure 3 2.5-6.0 ms 4.5-6.0 oscillation stabilizing time period (note 1) tssxtal xt1, xt2 32.768khz (crystal oscillation) refer to figure 3 2.5-6.0 s (note 1) the oscillation constant is shown on table 1 and table 2.
lc867248a/40a/32a/24a 12/20 3. electrical characteristics at ta=-30 c to +70 c, vss=vss1=vss2=vss3=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iih(1) port 1 port 0 without pull-up mos tr. output disable pull-up mos tr. off. vin=vdd (including the off- leak current of the output tr.) 2.5-6.0 1 iih(2) port 7 without pull-up mos tr. port 8 vin=vdd 2.5-6.0 1 iih(3) port 3 vin=vdd 2.5-6.0 1 iih(4) ports a,b,c,d,e,f,l vin=vdd 2.5-6.0 1 iih(5) res vin=vdd 2.5-6.0 1 input high current iih(6) ports 74 ,75 using as port vin=vdd 2.5-6.0 1 iil(1) port 1 port 0 without pull-up mos tr. output disable pull-up mos tr. off. vin=vss (including the off- leak current of the output tr.) 2.5-6.0 -1 iil(2) port 7 without pull-up mos tr. port 8 vin=vss 2.5-6.0 -1 iil(3) port 3 vin=vss 2.5-6.0 -1 iil(4) ports a,b,c,d,e,f,l vin=vss 2.5-6.0 -1 iil(5) res vin=vss 2.5-6.0 -1 input low current iil(6) ports 74 ,75 using as port vin=vss 2.5-6.0 -1 a voh(1) ioh=-1.0ma 4.5-6.0 vdd-1 voh(2) ports 0,1 of cmos output ioh=-0.1ma 2.5-6.0 vdd-0.5 voh(3) ioh=-1.0ma 4.5-6.0 vdd-1 output high voltage voh(4) port 3 of cmos output ports a,b,c,d,e,f of cmos output ioh=-0.1ma 2.5-6.0 vdd-0.5 vol(1) iol=10ma 4.5-6.0 1.5 vol(2) iol=1.6ma 4.5-6.0 0.4 vol(3) ports 0, 1 iol=1ma the current of any unmeasurement pin is not over 1 ma. 2.5-6.0 0.4 vol(4) iol=1ma 4.5-6.0 0.4 vol(5) port 70 iol=0.5ma 2.5-6.0 0.4 vol(6) iol=10ma 4.5-6.0 1.5 vol(7) port 3 iol=1.6ma 4.5-6.0 0.4 vol(8) port 9 iol=1ma the current of any unmeasurement pin is not over 1 ma. 2.5-6.0 0.4 vol(9) iol=8ma 4.5-6.0 1.5 vol(10) iol=1.6ma 4.5-6.0 0.4 output low voltage vol(11) ports a,b,c,d,e,f of cmos output iol=1ma the current of any unmeasurement pin is not over 1 ma. 2.5-6.0 0.4 v continue.
lc867248a/40a/32a/24a 13/20 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit 4.5-6.0 0 0.2 vodls s0 to s47 deference voltage to ideal value vlcd, 2/3vlcd, 1/3vlcd 2.5-6.0 0 0.2 4.5-6.0 0 0.2 lcd output regulation vodlc com0 to com3 deference voltage to ideal value vlcd, 2/3vlcd, 1/2vlcd, 1/3vlcd 2.5-6.0 0 0.2 v 4.5-6.0 60 plcd(1) resistance at a ladder resistor 2.5-6.0 60 4.5-6.0 30 lcd ladder resistor plcd(2) resistance at a ladder resistor 1/2r mode 2.5-6.0 30 4.5-6.0 15 40 70 pull-up mos tr. resistor rpu ports 0, 1, 3 ports a,b,c,d,e,f ports 70, 71, 72, 73 voh=0.9vdd 2.5-4.5 25 70 150 k ? hysteresis voltage vhis ports 1 ports 70, 71, 72, 73 res output disable 2.5-6.0 0.1vdd v pin capacitance cp all pins f=1mhz unmeasurement terminals for the input are set to vss level. ta=25c 2.5-6.0 10 pf 4. serial input/output characteristics at ta=-30 c to +70 c, vss=vss1=vss2=vss3=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit cycle t ckcy (1) 2 low level pulse width t ckl (1) 1 input clock high level pulse width t ckh (1) sck0, sck1 refer to figure 5. 2.5-6.0 1 cycle t ckcy (2) 2 low level pulse width t ckl (2) 1/2 t ckcy serial clock output clock high level pulse width t ckh (2) sck0, sck1 use pull-up resistor (1k ? ) when opendrain output. refer to figure 5. 2.5-6.0 1/2 t ckcy t cyc 4.5-6.0 0.1 data set up time t ick 2.5-6.0 0.4 4.5-6.0 0.1 serial input data hold time t cki si0,si1 sb0,sb1 data set-up to sck0, 1 data hold from sck0, 1 refer to figure 5. 2.5-6.0 0.4 4.5-6.0 7/12tcyc +0.2 output delay time (serial clock is external clock) t cko(1) 2.5-6.0 7/12tcyc +1 4.5-6.0 1/3tcyc +0.2 serial output output delay time (serial clock is internal clock) t cko(2) so0, so1 sb0, sb1 use pull-up resistor (1k ? ) when open drain output. data hold from sck0, 1 refer to figure 5. 2.5-6.0 1/3tcyc +1 s
lc867248a/40a/32a/24a 14/20 5. pulse input conditions at ta=-30 c to +70 c, vss=vss1=vss2=vss3=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit tpih(1) tpil(1) int0, int1 int2/t0in interrupt acceptable timer0-countable 2.5-6.0 1 tpih(2) tpil(2) int3/t0in (the noise rejection clock is selected to 1/1.) interrupt acceptable timer0-countable 2.5-6.0 2 tpih(3) tpil(3) int3/t0in (the noise rejection clock is selected to 1/16.) interrupt acceptable timer0-countable 2.5-6.0 32 tpih(4) tpil(4) int3/t0in (the noise rejection clock is selected to 1/64.) interrupt acceptable timer0-countable 2.5-6.0 128 t cyc high/low level pulse width tpil(5) res reset acceptable 2.5-6.0 200 s 6. ad converter characteristics at ta=-30 c to + 70 c, vss=vss1=vss2=vss3=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit resolution nad 4.5-6.0 8 bit absolute precision (note 2) etad 4.5-6.0 1.5 lsb ad conversion time = 16 tcyc (adcr2=0) (note 3) 15.68 (tcyc= 0.98 s) 65.28 (tcyc= 4.08 s) conversion time tcad ad conversion time = 32 tcyc (adcr2=1) (note 3) 4.5-6.0 31.36 (tcyc= 0.98 s) 130.56 (tcyc= 4.08 s) s analog input voltage range vain 4.5-6.0 vss vdd v iainh vain=vdd 4.5-6.0 1 analog port input current iainl an0 - an7 vain=vss 4.5-6.0 -1 a (note 2) absolute precision excepts quantizing error (1/2 lsb). (note 3) the conversion time means the time from executing the ad conversion instruction to setting the complete digital conversion value to the register.
lc867248a/40a/32a/24a 15/20 7. current dissipation characteristics at ta=-30 c to +70 c, vss=vss1=vss2=vss3=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iddop(1) fmcf=6mhz ceramic resonator oscillation fsxtal=32.768khz crystal oscillation system clock : cf oscillation internal rc oscillation stops 1/1 divided 4.5-6.0 10 20 iddop(2) 4.5-6.0 3 11 iddop(3) fmcf=3mhz ceramic resonator oscillation fsxtal=32.768khz crystal oscillation system clock : cf oscillation internal rc oscillation stops 1/2 divided 2.5-4.5 1.5 6 iddop(4) 4.5-6.0 0.7 2.3 iddop(5) fmcf=0hz (when oscillation stops) fsxtal=32.768khz crystal oscillation system clock : rc oscillation 1/2 divided 2.5-4.5 0.4 1.6 ma iddop(6) 4.5-6.0 35 130 current dissipation during basic operation (note 4) iddop(7) vdd1= vdd2= vdd3 fmcf=0hz (when oscillation stops) fsxtal=32.768khz crystal oscillation system clock : crystal oscillation internal rc oscillation stops 1/2 divided 2.5-4.5 15 70 a continue.
lc867248a/40a/32a/24a 16/20 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iddhalt(1) halt mode fmcf=6mhz ceramic resonator oscillation fsxtal=32.768khz crystal oscillation system clock : cf oscillation internal rc oscillation stops 1/1 divided 4.5-6.0 5 11 iddhalt(2) 4.5-6.0 2.2 9 iddhalt(3) halt mode fmcf=3mhz ceramic resonator oscillation fsxtal=32.768khz crystal oscillation system clock : cf oscillation internal rc oscillation stops 1/2 divided 2.5-4.5 0.8 5 ma iddhalt(4) 4.5-6.0 400 1100 iddhalt(5) halt mode fmcf=0hz (when oscillation stops) fsxtal=32.768khz crystal oscillation system clock : rc oscillation 1/2 divided 2.5-4.5 200 700 iddhalt(6) 4.5-6.0 25 100 current dissipation in halt mode (note 4) iddhalt(7) vdd1= vdd2= vdd3 halt mode fmcf=0hz (when oscillation stops) fsxtal=32.768khz crystal oscillation system clock : crystal oscillation internal rc oscillation stops 1/2 divided 2.5-4.5 8 55 iddhold(1) 4.5-6.0 0.05 30 current dissipation in hold mode (note 4) iddhold(2) vdd1= vdd2= vdd3 hold mode 2.5-4.5 0.02 20 a (note 4) the currents of the output transistors and the pull-up mos transistors are ignored.
lc867248a/40a/32a/24a 17/20 table 1. ceramic resonator oscillation recommended constant (main clock) oscillation type maker oscillator c1 c2 csa6.00mg 33pf 33pf murata cst6.00mgw on chip 6mhz ceramic resonator oscillation csa3.00mg 33pf 33pf murata cst3.00mgw on chip 3mhz ceramic resonator oscillation * both c1 and c2 must use k rank (10%) and sl characteristics. table 2. crystal oscillation guaranteed constant (sub clock) oscillation type maker oscillator c3 c4 rd epson c-002rx 15pf 15pf 680k ? 32.768khz crystal oscillation * both c3 and c4 must use j rank (5%) and ch characteristics. (it is about the application which is not in need of high precision. use k rank (10%) and sl characteristics.) (notes) since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the osci llation pins as possible with the shortest possible pattern length. if you use other oscillators herein, we provide no guarantee for the characteristics. figure 1 ceramic oscillation circuit figure 2 crystal oscillation circuit cf1 cf2 c2 c1 cf xt1 xt2 c4 c3 x?tal rd
lc867248a/40a/32a/24a 18/20 reset time and oscillation stable time hold release signal and oscillation stable time figure 3 oscillation stable time vdd vdd limit 0v reset time tmscf tssxtal power suppl y res internal rc resonator oscillation cf1, cf2 operation mode xt1, xt2 unfixed reset instruction execution mode instruction execution mode ocr6=1 tmscf tssxtal internal rc resonator oscillation cf1, cf2 operation mode xt1, xt2 hold instruction execution mode valid hold release signal
lc867248a/40a/32a/24a 19/20 figure 4 reset circuit figure 5 serial input / output test condition figure 6 pulse input timing condition (note) fix the value of c res , r res that is sure to reset until 200 s, after power supply has been over inferior limit of supply voltage. res vdd r res c res 0.5vdd tckcy tckl tckh tick tcki tcko sck0 sck1 si0 si1 so0, so1 sb0 , sb1 vdd 1k ? 50pf tpil tpih
lc867248a/40a/32a/24a 20/20 memo: ps

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