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1 ics for tv publication date: february 2003 sdb00081beb AN2546FH-A automotive lcd tv signal processor ic overview the AN2546FH-A is a video signal processing ic built-in a 5-volt power-supply source driver for tft color lcd (normally white type), and it supports the ntsc, pal and pal-m/pal-n systems. the main circuitry of this ic includes video-signal processing circuit, color sig- nal processing circuit, interface circuit, synchronizing cir- cuit and many color quality adjusting circuits. this ic con- verts the composite video signal or separated y/c signal or rgb signals into rgb signals available for tft color lcd. features ? supply voltage: 3 v/5 v/7.5 v ? built-in a 5-volt power-supply source driver for tft type lcd ? low consumption power (typ. 200 mw) ? supporting the ntsc, pal, pal-m and pal-n sys- tems ? supporting composite, component and color differen- tial signal input ? video signal, analog rgb (2 systems) one is for osd (analog/digital). ? each mode setting is possible with i 2 c bus control. ? electronic volume (d/a converter) built in ? contrast/brightness/ correction circuit built in ? horizontal and vertical display position adjustment are possible by serial control. ? improvement of weak electric field characteristics (compared to an2526fh/an2526nfh: ? 5 db) ? at reverse stop, built-in output gain down function applications ? 4 inches to 7 inches middle size tft lcd equipment of normally white, of such as an in-car tv and an lcd monitor for car navigation system. qfp064-p-1010 unit: mm 10.000.20 48 33 32 17 16 1 64 49 12.000.20 10.000.20 0.100.10 12.000.20 1.950.20 (1.25) (1.25) 0.50 0.18 +0.1 ?0.05 0.15 +0.10 ?0.05 seating plane (1.00) 0.500.20 0 to 10 note) the package of this product will be changed to lead-free type (qfp064-p-1010a). see the new package dimensions section later of this datasheet.
AN2546FH-A sdb00081beb 2 application circuit examples 1. composite signal input 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 pal or pal-m pal-n sdata sclck gnd2 navi sync. v cc1 (5.0 v) v ss pol v dd nrgb l-det. sync. in r-y out ntsc apc det. acc det. y-det. y-in c-in kill det. gnd3 v cc1 (5.0 v) sc out 5.1 k ? 2 k ? 330 k ? 1 k ? 15 k ? 68 k ? 330 ? composite signal 1 f 15 f 0.02 f 0.1 f 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 32 31 30 29 28 vcom 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 v cc1 (5.0 v) v ref pwm logic logic logic logic clamp delay sharpness apc tint killer vxo gene. vxo bpf sync. cut sw acc det. acc amp. yuv sw gca bright reg. r-y, b-y demod dac dac reg. i 2 c bus vco 1/n sync. sepa. hhkill v sync drop vert. count phase comp. f det. gca b-y out b-y in r-y in g-y gene. matrix int./ext. sw clamp. osd sw contrast gamma invert limit 0.1 f 0.1 f 4.7 f ntsc = 39 pf pal = 27 pf 47 h ponr com dc secam black level adj. 2.2 f 33 k ? 10 f 4.7 f 1 500 pf v cc1 v cc3 15 f 47 h be sure to attach a power supply filter to a power supply pin. power supply pin recommended crystal oscillator ntsc: vsx0160 (kinseki, limited) pal: vsx0162 (kinseki, limited) 1 f y s blak b-out b-out det. r-det. 1 f g-det. 1 f b-det. 2.2 f r-in1 g-in1 b-in1 r-in2 g-in2 b-in2 g-out vcom pwm vd hd scp r-out g-out det. gnd1 2.2 f r-out det. 2.2 f v cc2 (7.5 v) v cc3 (3.0 v) 0.01 f 0.02 f 15 f 0.022 f 0.47 f 82 k ? c-sync. afc det. 50 k ? 1 m ? 3.3 k ? 10 k ? 100 k ? 680 pf ? c coupling input in an analog osd mode. ? connect to gnd in case of no use in a digital osd mode.
AN2546FH-A 3 sdb00081beb application circuit examples (continued) 2. component signal input 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 pal or pal-m pal-n sdata sclck gnd2 navi sync. v cc1 (5.0 v) v ss pol v dd nrgb l-det. sync. in r-y out ntsc apc det. acc det. y-det. y-in c-in kill det. gnd3 v cc1 (5.0 v) sc out 5.1 k ? 330 k ? 1 k ? 15 k ? 68 k ? 330 ? brightness and syncronous signal 1 f 15 f 0.02 f 0.1 f 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 32 31 30 29 28 vcom 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 v cc1 (5.0 v) v ref pwm logic logic logic logic clamp delay sharpness apc tint killer vxo gene. vxo bpf sync. cut sw acc det. acc amp. yuv sw gca bright reg. r-y, b-y demod dac dac reg. i 2 c bus vco 1/n sync. sepa. hhkill v sync drop vert. count phase comp. f det. gca b-y out b-y in r-y in g-y gene. matrix int./ext. sw clamp. osd sw contrast gamma invert limit 0.1 f 0.1 f 4.7 f ponr com dc secam black level adj. 2.2 f 33 k ? 10 f 4.7 f 1 500 pf v cc1 v cc3 1 f y s blak b-out b-out det. r-det. 1 f g-det. 1 f b-det. 2.2 f r-in1 g-in1 b-in1 r-in2 g-in2 b-in2 g-out vcom pwm vd hd scp r-out g-out det. gnd1 2.2 f r-out det. 2.2 f v cc2 (7.5 v) v cc3 (3.0 v) 0.01 f 0.02 f 15 f 0.022 f 0.47 f 82 k ? c-sync. afc det. 50 k ? 1 m ? 3.3 k ? 10 k ? 100 k ? 680 pf 15 f 47 h power supply pin ? c coupling input in an analog osd mode. ? connect to gnd in case of no use in a digital osd mode. be sure to attach a power supply filter to a power supply pin. recommended crystal oscillator ntsc: vsx0160 (kinseki, limited) pal: vsx0162 (kinseki, limited)
AN2546FH-A sdb00081beb 4 application circuit examples (continued) 3. analog rgb signal input 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 pal or pal-m pal-n sdata sclck gnd2 navi sync. v cc1 (5.0 v) v ss pol v dd nrgb l-det. sync. in ntsc gnd3 v cc1 (5.0 v) 330 k ? 1 k ? 15 k ? 68 k ? 330 ? synchronous signal 15 f 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 32 31 30 29 28 vcom 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 v cc1 (5.0 v) v ref pwm logic logic logic logic clamp delay sharpness apc tint killer vxo gene. vxo bpf sync. cut sw acc det. acc amp. yuv sw gca bright reg. r-y, b-y demod dac dac reg. i 2 c bus vco 1/n sync. sepa. hhkill v sync drop vert. count phase comp. f det. gca g-y gene. matrix int./ext. sw clamp. osd sw contrast gamma invert limit ponr com dc secam black level adj. 2.2 f 33 k ? 10 f 4.7 f 1 500 pf v cc1 v cc1 required only when not using crystal oscillators. v cc3 4.7 f 4.7 f 4.7 f 1 f y s blak b-out b-out det. r-det. 1 f g-det. 1 f b-det. 2.2 f r-in1 g-in1 b-in1 r-in2 g-in2 b-in2 g-out vcom pwm vd hd scp r-out g-out det. gnd1 2.2 f r-out det. 2.2 f v cc2 (7.5 v) v cc3 (3.0 v) 0.01 f 0.02 f 15 f 0.022 f 0.47 f 82 k ? c-sync. afc det. 50 k ? 1 m ? 3.3 k ? 510 k ? 510 k ? 10 k ? 100 k ? 680 pf possible to change the synchronous signal input pin according to the channnel 10 value. possible to input to pin 45 by 3 v[p-p] positive polarity pulse. 15 f 47 h power supply pin apply a half v cc1 voltage to pin 42 according to resistance division when not connecting crystal oscillators. ? c coupling input in an analog osd mode. ? connect to gnd in case of no use in a digital osd mode. be sure to attach a power supply filter to a power supply pin. recommended crystal oscillator ntsc: vsx0160 (kinseki, limited) pal: vsx0162 (kinseki, limited)
AN2546FH-A 5 sdb00081beb pin descriptions pin no. description 1 crystal oscillator connecting pin 3 (pal-n) 2 r-y output pin 3 b-y output pin 4 r-y input pin 5 b-y input pin 6 signal processing system power supply (v cc1 = 5.0 v) 7 internal reference power supply detection pin (2.0 v) 8 r-ch. analog signal input pin 9 g-ch. analog signal input pin 10 b-ch. analog signal input pin 11 r-ch. clamp detection pin 12 g-ch. clamp detection pin 13 b-ch. clamp detection pin 14 r-ch. osd input pin 15 g-ch. osd input pin 16 b-ch. osd input pin 17 character picking up pulse input pin 18 side black control signal input pin 19 b-ch. output pin 20 b-ch. output dc feedback detection pin 21 g-ch. output pin 22 g-ch. output dc feedback detection pin 23 gnd 1 24 drive output reference voltage input pin 25 drive system power supply (v cc2 = 7.5 v) 26 r-ch. output pin 27 r-ch. output dc feedback detection pin 28 common reverse signal output pin 29 pulse output system power supply (v cc3 = 3.0 v) 30 pwm output pin 31 vertical synchronous signal output pin 32 horizontal synchronous signal output pin pin no. description 33 sand castle pulse output pin 34 composite synchronous signal output pin 35 vertical synchronous signal input pin 36 1h reverse signal input pin 37 clock-system gnd (v ss ) 38 analog imposing control signal input pin 39 horizontal clock detection pin 40 clock-system power supply (3.0 v) 41 gnd 2 42 afc loop filter connecting pin 43 vco frequency adjustment pin 44 synchronous system power supply (v cc1 = 5.0 v) 45 navi signal synchronous signal input pin 46 synchronous signal input pin 47 serial data shift clock input pin 48 serial data input pin 49 power-on reset detection pin 50 common dc adjustment voltage output pin 51 dac output pin 52 luminance signal input pin 53 chrominance signal trap filter connection pin 1 54 chrominance signal trap filter connection pin 2 55 y-system clamp detection pin 56 acc detection pin 57 chrominance signal input pin 58 chrominance processing system power supply (v cc1 = 5.0 v) 59 gnd 3 60 chrominance killer detection pin 61 apc detection pin 62 subcarrier output pin 63 crystal oscillator connecting pin 1 (ntsc) 64 crystal oscillator connecting pin 2 (pal/pal-m)
AN2546FH-A sdb00081beb 6 recommended operating range absolute maximum ratings parameter symbol rating unit supply voltage v cc1 5.5 v v cc2 8.5 v cc3 5.2 supply current i cc ? ma power dissipation * 2 p d 423 mw operating ambient temperature * 1 t opr ? 30 to + 85 c storage temperature * 1 t stg ? 55 to + 150 c note) * 1: except for the operating ambient temperature and storage temperature, all ratings are for t a = 25 c. * 2: the power dissipation shown is the value in free air for t opr = 85 c. parameter symbol range unit supply voltage v cc1 4.7 to 5.3 v v cc2 7.0 to 8.0 v cc3 2.7 to 3.3 parameter symbol conditions min typ max unit dc v cc1 -system current consumption i total1 refer to product standards 32 ? 44 ma v cc2 -system current consumption i total2 refer to product standards 1.0 ? 9.0 ma v cc3 -system current consumption i total3 refer to product standards ?? 2.0 ma chrominance system r-y standard gain g ry refer to product standards 9.0 ? 15 db r-y/g-y relative gain g rygy refer to product standards ? 5.0 ?? 1.0 db b-y standard gain g by refer to product standards 9.0 ? 15 db b-y/g-y relative gain g bygy refer to product standards ? 15 ?? 9.0 db high-level apc pull-in ap h refer to product standards 500 ? 540 hz low-level apc pull-in ap l refer to product standards ? 540 ?? 500 hz acc output characteristic 1 g acc1 refer to product standards ? 1.0 ? 1.0 db acc output characteristic 2 g acc2 refer to product standards ? 1.0 ? 1.0 db chrominance killer characteristic 1 v kill1 refer to product standards 400 ?? mv[p-p] chrominance killer characteristic 2 v kill2 refer to product standards ?? 600 mv[p-p] subcarrier amplitude scv refer to product standards 400 ?? mv[p-p] y-system sharpness control characteristic g sh refer to product standards 1.0 ?? db sharpness frequency characteristic 1 f sh1 refer to product standards 4.0 ?? db r-ch. contrast adjustment range 1 ctr r1 refer to product standards 1.5 ?? db electrical characteristics at t a = 25 c
AN2546FH-A 7 sdb00081beb electrical characteristics at t a = 25 c (continued) parameter symbol conditions min typ max unit y-system (continued) g-ch. contrast adjustment range 1 ctr g1 refer to product standards 1.5 ?? db b-ch. contrast adjustment range 1 ctr b1 refer to product standards 1.5 ?? db r-ch. contrast adjustment range 2 ctr r2 refer to product standards ??? 2.5 db g-ch. contrast adjustment range 2 ctr g2 refer to product standards ??? 2.5 db b-ch. contrast adjustment range 2 ctr b2 refer to product standards ??? 2.5 db r-ch. pedestal amplitude minimum v pedrmin refer to product standards ?? 2.0 v[p-p] g-ch. pedestal amplitude minimum v pedgmin refer to product standards ?? 2.0 v[p-p] b-ch. pedestal amplitude minimum v pedbmin refer to product standards ?? 2.0 v[p-p] r-ch. pedestal amplitude maximum v pedrmax refer to product standards 3.0 ? ? v[p-p] g-ch. pedestal amplitude maximum v pedgmax refer to product standards 3.0 ? ? v[p-p] b-ch. pedestal amplitude maximum v pedbmax refer to product standards 3.0 ? ? v[p-p] g-ch. output dc voltage v gdc refer to product standards 2.35 ? 2.85 v[p-p] r-ch. gamma characteristic 1 g gamr1 refer to product standards ?9.0 ? ?3.0 db g-ch. gamma characteristic 1 g gamg1 refer to product standards ?9.0 ? ?3.0 db b-ch. gamma characteristic 1 g gamb1 refer to product standards ?9.0 ? ?3.0 db r-ch. gamma characteristic 2 g gamr2 refer to product standards ?8.0 ? ? db g-ch. gamma characteristic 2 g gamg2 refer to product standards ?8.0 ? ? db b-ch. gamma characteristic 2 g gamb2 refer to product standards ?8.0 ? ? db r-ch. gamma characteristic 3 g gamr3 refer to product standards ?5.0 ? 0db g-ch. gamma characteristic 3 g gamg3 refer to product standards ?5.0 ? 0db b-ch. gamma characteristic 3 g gamb3 refer to product standards ?5.0 ? 0db r-ch. white limiter high-level v wrrh refer to product standards ??3.0 v[p-p] g-ch. white limiter high-level v wrgh refer to product standards ??3.0 v[p-p] b-ch. white limiter high-level v wrbh refer to product standards ??3.0 v[p-p] r-ch. white limiter low-level v wrrl refer to product standards 3.2 ?? v[p-p] g-ch. white limiter low-level v wrgl refer to product standards 3.2 ?? v[p-p] b-ch. white limiter low-level v wrbl refer to product standards 3.2 ?? v[p-p] r-ch. black limiter low-level v brrl refer to product standards 3.0 ?? v g-ch. black limiter low-level v brgl refer to product standards 3.0 ?? v b-ch. black limiter low-level v brbl refer to product standards 3.0 ?? v r-ch. black limiter high-level v brrh refer to product standards ?? 2.7 v g-ch. black limiter high-level v brgh refer to product standards ?? 2.7 v b-ch. black limiter high-level v brbh refer to product standards ?? 2.7 v r-ch. y s threshold 1 v tysr1 refer to product standards 0.8 ?? v[p-p] g-ch. y s threshold 1 v tysg1 refer to product standards 0.8 ?? v[p-p] b-ch. y s threshold 1 v tysb1 refer to product standards 0.8 ?? v[p-p]
AN2546FH-A sdb00081beb 8 electrical characteristics at t a = 25 c (continued) parameter symbol conditions min typ max unit y-system (continued) r-ch. y s threshold 2 v tysr2 refer to product standards ?? 0.5 v[p-p] g-ch. y s threshold 2 v tysg2 refer to product standards ?? 0.5 v[p-p] b-ch. y s threshold 2 v tysb2 refer to product standards ?? 0.5 v[p-p] r-ch. black level chr rb refer to product standards ? 1.0 ? 1.0 v g-ch. black level chr gb refer to product standards ? 1.0 ? 1.0 v b-ch. black level chr bb refer to product standards ? 1.0 ? 1.0 v r-ch. black level width wchr rb refer to product standards 2.0 ? 4.0 s g-ch. black level width wchr gb refer to product standards 2.0 ? 4.0 s b-ch. black level width wchr bb refer to product standards 2.0 ? 4.0 s r-ch. chr threshold 1 v tchr1 refer to product standards 1.5 ?? v[p-p] g-ch. chr threshold 1 v tchg1 refer to product standards 1.5 ?? v[p-p] b-ch. chr threshold 1 v tchb1 refer to product standards 1.5 ?? v[p-p] r-ch. chr threshold 2 v tchr2 refer to product standards 3.0 ?? v[p-p] g-ch. chr threshold 2 v tchg2 refer to product standards 3.0 ?? v[p-p] b-ch. chr threshold 2 v tchb2 refer to product standards 3.0 ?? v[p-p] r-ch. white level chr rw refer to product standards 2.0 ?? v[p-p] g-ch. white level chr gw refer to product standards 2.0 ?? v[p-p] b-ch. white level chr bw refer to product standards 2.0 ?? v[p-p] r-ch. white level width wchr rw refer to product standards 2.0 ? 4.0 s g-ch. white level width wchr gw refer to product standards 2.0 ? 4.0 s b-ch. white level width wchr bw refer to product standards 2.0 ? 4.0 s r-ch. rgb2 relative amplitude v rgb2r refer to product standards ? 0.45 ? 0.45 v[p-p] b-ch. rgb2 relative amplitude v rgb2b refer to product standards ? 0.45 ? 0.45 v[p-p] synchronous system horizontal sync. pulse low-level v hdl refer to product standards ?? 0.4 v horizontal sync. pulse amplitude v hd refer to product standards 2.4 ?? v[p-p] horizontal sync. pulse width t hd refer to product standards 3.6 ? 6.0 s vertical sync. pulse low-level v vdl refer to product standards ?? 0.4 v vertical sync. pulse amplitude v vd refer to product standards 2.4 ?? v[p-p] horizontal sync. separation pulse v hssh sg2 (ntsc) 2.4 ?? v high-level horizontal sync. separation pulse v hss sg2 (ntsc) 2.4 ?? v[p-p] amplitude horizontal sync. separation pulse t hss sg2 (ntsc) 3.6 ? 6.0 s width
AN2546FH-A 9 sdb00081beb terminal equivalent circuits pin no. equivalent circuit description voltage waveform 1 vxo3: ? pal-n crystal oscillator con- necting pin use the capacitor with tem- perature characteristics (n750) to connect to the crystal oscillator. 2 r-y out: r-y signal output pin of r-y signal de- modulated from video signal 3 b-y out: b-y signal output pin of b-y signal de- modulated from video signal 4 r-y in: r-y signal r-y signal input pin in a color difference mode and in the standard pal 1 pin 58 v cc1 pin 59 gnd 190 ? 1 k ? 2 pin 58 v cc1 pin 59 gnd 2 k ? 1h 3 pin 58 v cc1 pin 59 gnd 2 k ? 1h 4 pin 58 v cc1 pin 59 gnd pin 7 v ref 5 k ? 5 k ? 5 k ? 17.5 k ? 5 k ? 5 k ? 2 k ? 1h
AN2546FH-A sdb00081beb 10 terminal equivalent circuits (continued) pin no. equivalent circuit description voltage waveform 5 b-y in: b-y signal b-y signal input pin in a color difference mode and in the standard pal 6v cc1 : ? drive block 5.0 v-system power supply pin 7v ref : ? reference voltage output pin 2.0 v typ. 8 r-in 1: analog r signal analog r signal input 9 g-in 1: analog g signal analog g signal input 5 pin 58 v cc1 pin 59 gnd pin 7 v ref 5 k ? 5 k ? 5 k ? 17.5 k ? 5 k ? 5 k ? 2 k ? 1h 60 ? pin 6 v cc1 pin 23 gnd 200 ? 30 k ? 26 k ? 1 k ? 7 5 k ? 8 pin 6 v cc1 pin 7 v ref pin 23 gnd 0.7 v[p-p] typ. 5 k ? 9 pin 6 v cc1 pin 7 v ref pin 23 gnd 0.7 v[p-p] typ.
AN2546FH-A 11 sdb00081beb pin no. equivalent circuit description voltage waveform 10 b-in 1: analog b signal analog b signal input 11 r-ch. det.: ? r-ch. clamping capacitor coupling pin 12 g-ch. det.: ? g-ch. clamping capacitor coupling pin 13 b-ch. det.: ? b-ch. clamping capacitor coupling pin terminal equivalent circuits (continued) 5 k ? 10 pin 6 v cc1 pin 7 v ref pin 23 gnd 1 k ? 1 k ? pin 6 v cc1 pin 23 gnd 500 ? 11 hss 0.7 v[p-p] typ. 1 k ? 1 k ? pin 6 v cc1 pin 23 gnd 500 ? 12 hss 1 k ? 1 k ? pin 6 v cc1 pin 23 gnd 500 ? 13 hss
AN2546FH-A sdb00081beb 12 pin no. equivalent circuit description voltage waveform 14 r-in 2: analog osd character insertion signal in- put for r-ch., supporting ana- log and digital osd digital osd 15 g-in 2: analog osd character insertion signal in- put for g-ch., supporting analog and digital osd digital osd 16 b-in 2: analog osd character insertion signal in- put for b-ch., supporting ana- log and digital osd digital osd 17 y s : character picking up signal input 18 blak: black level indication con- trol signal input pin terminal equivalent circuits (continued) 5 k ? 14 pin 6 v cc1 pin7 v ref pin 23 gnd digital osd circuit 5 k ? 15 pin 6 v cc1 pin7 v ref pin 23 gnd digital osd circuit 5 k ? 16 pin 6 v cc1 pin7 v ref pin 23 gnd digital osd circuit 15 k ? 17 100 k ? pin 23 gnd 10 k ? 15 k ? 18 100 k ? pin 23 gnd 10 k ? 0.7 v[p-p] typ. v dd gnd 0.7 v[p-p] typ. v dd gnd 0.7 v[p-p] typ. v dd gnd v dd gnd v dd gnd
AN2546FH-A 13 sdb00081beb pin no. equivalent circuit description voltage waveform 19 b-out: b signal output pin 20 b-ch. ave det.: ? b-ch. output dc feedback detection pin 21 g-out: g signal output pin 22 g-ch. ave det.: ? g-ch. output dc feedback detection pin 23 ? gnd 1: ? drive circuits system gnd terminal equivalent circuits (continued) 19 100 ? pin 25 v cc2 pin 6 v cc1 pin 23 gnd 16 k ? 2 k ? 100 k ? 20 pin 6 v cc1 pin 23 gnd 19 21 100 ? pin 25 v cc2 pin 6 v cc1 pin 23 gnd 16 k ? 2 k ? 100 k ? 22 pin 6 v cc1 pin 23 gnd 21
AN2546FH-A sdb00081beb 14 pin no. equivalent circuit description voltage waveform 24 ave : ? r,g,b output dc reference voltage pin 25 ? v cc2 : ? 7.5 v system power supply 26 r-out: r signal output pin 27 r-ch. ave det.: r-ch. output dc feedback detection pin 28 common out: voltage output pin for common. output impedance; approx. 150 ? terminal equivalent circuits (continued) 24 100 k ? pin 6 v cc1 pin 23 gnd 8 k ? 2 k ? 100 k ? 26 100 ? pin 25 v cc2 pin 6 v cc1 pin 23 gnd 16 k ? 2 k ? 100 k ? 27 pin 6 v cc1 pin 23 gnd 26 ch.1 ch.1 28 pin 25 v cc2 pin 23 gnd 100 k ? 15 k ? 200 ?
AN2546FH-A 15 sdb00081beb pin no. equivalent circuit description voltage waveform 29 ? v cc3 : ? logic output circuits system power supply 3.0 v typ. 30 pwm: output waveform pwm signal output pin 31 vd: output waveform vertical synchronous signal output pin 32 hd: output waveform horizontal synchronous sig- nal output pin 33 scp out: sand castle pulse output pin 34 hss: output waveform composite synchronous sig- nal output pin terminal equivalent circuits (continued) 30 pin 29 v cc3 pin 23 gnd pin 37 v ss 0 v v cc3 31 pin 29 v cc3 pin 23 gnd pin 37 v ss 0 v v cc3 32 pin 29 v cc3 pin 23 gnd pin 37 v ss 0 v v cc3 33 100 ? 100 ? 41.3 k ? pin 44 v cc1 pin 41 gnd 350 ? 2.0 v[p-p] typ. 4.0 v[p-p] typ. burst time vertical/horizontal blanking time 34 pin 29 v cc3 pin 23 gnd pin 37 v ss 0 v v cc3
AN2546FH-A sdb00081beb 16 pin no. equivalent circuit description voltage waveform 35 vdb in: high or low vertical synchronous pulse input pin 36 ext. pol.: high or low 1h reverse signal input pin 37 ? v ss : mos system gnd ? 38 prgb: high or low analog osd signal input mode start-up signal input pin valid only in the analog osd mode high = analog osd start up 39 ldet: ? capacitor coupling pin for the horizontal unlock detect- ing circuit 40 ? v dd : ? capacitor connection pin for mos part power supply 3.0 v typ. 41 ? gnd 2: pulse system gnd ? 42 afc det.: afc filter connecting pin input impedance; 100 k ? or more terminal equivalent circuits (continued) 35 pin 23 gnd 15 k ? 100 k ? 10 k ? 36 pin 23 gnd 15 k ? 100 k ? 10 k ? 38 pin 23 gnd 15 k ? 100 k ? 10 k ? 39 pin 44 v cc1 pin 41 gnd 10 k ? 12 k ? 200 ? 60 ? 60 ? 42 pin 41 gnd pin 44 v cc1 1 k ? 1 k ? 2 k ? 2 k ? 1h
AN2546FH-A 17 sdb00081beb pin no. equivalent circuit description voltage waveform 43 h f o : ? vco oscillation frequency adjusting resistor connection pin 44 ? v cc1 : ? pulse system power supply 5.0 v 45 navi sync-in: synchronous signal input pin for the signal of car naviga- tion system negative polarity input 46 hss in: input signal example: sync. signal input pin video signal separates a sync. signal from luminance signal (video sig- nal) 47 sclk: serial clock input pin 48 dat: serial data input pin terminal equivalent circuits (continued) 43 pin 41 gnd pin 44 v cc1 2 k ? 5 pf 10 k ? 10 k ? 45 pin 23 gnd 15 k ? 100 k ? 10 k ? 0 v v dd 46 pin 44 v cc1 pin 41 gnd 50 k ? 850 ? 85 ? 21.7 k ? 32.5 k ? 47 pin 23 gnd 15 k ? 100 k ? 10 k ? pin 44 v cc4 48 pin 23 gnd 15 k ? 100 k ? 10 k ?
AN2546FH-A sdb00081beb 18 pin no. equivalent circuit description voltage waveform 49 rst: ? capacitor coupling pin for power-on reset 50 com. dc: dc dc voltage output pin 51 dac-out: dc dc voltage output pin 52 y-in: input signal example: luminance signal input pin video signal input luminance signal (video signal) 53 trap-out: ? trap connecting pin trapping a chrominance sig- nal by connecting external inductor and capacitor. not necessary in case that an in- put signal is a component. terminal equivalent circuits (continued) 49 pin 44 v cc1 pin 37 v ss pin 41 gnd 5 k ? 500 ? 100 k ? 50 k ? 50 pin 41 gnd pin 44 v cc1 1.5 pf 36 k ? 46 k ? 40 k ? 51 pin 41 gnd pin 44 v cc1 1.5 pf 36 k ? 46 k ? 40 k ? 52 pin 58 v cc1 53 pin 59 gnd 2 k ? 2 k ? 50 ? 50 k ?
AN2546FH-A 19 sdb00081beb pin no. equivalent circuit description voltage waveform 54 trap-in: ? trap connecting pin the pair with pin 53 55 y-det.: ? capacitor coupling pin for luminance signal clamping 56 acc det.: ? acc capacitor connecting pin, adjusting the amplitude of a burst signal automati- cally 57 c-in: input signal example: chrominance signal input pin video signal input chrominance signal (video signal) 58 ? v cc1 : ? power supply 5.0 v typ. chrominance and luminance signal processing system. 59 ? gnd 3: ? gnd for chrominance and lum- inance signal processing system terminal equivalent circuits (continued) 54 pin 58 v cc1 pin 59 gnd 2 k ? 55 pin 58 v cc1 pin 59 gnd 1 k ? 1 k ? 2 k ? 56 pin 59 gnd pin 58 v cc1 1 k ? 5 k ? 1 k ? 1 k ? 1 k ? 2 k ? 5 k ? 57 pin 58 v cc1 pin 59 gnd 50 k ?
AN2546FH-A sdb00081beb 20 pin no. equivalent circuit description voltage waveform 60 kill det.: ? killer capacitor coupling pin to prevent degradation of image in a small amplitude of a burst signal, this pin stops a chrominance signal and the mode changes to black and white mode. 61 apc det.: ? apc capacitor coupling pin matching the phase of a crys- tal oscillation to that of burst signal 62 scp out: ntsc 3.58 mhz subcarrier pulse output pin pal 4.43 mhz 63 vxo1: ? ntsc crystal oscillator con- necting pin use the capacitor with tem- perature characteristics (n750) to connect to the crystal oscillator. terminal equivalent circuits (continued) 60 pin 58 v cc1 pin 59 gnd 1.5 k ? 72 k ? 90 k ? 61 pin 58 v cc1 pin 59 gnd 2 k ? 2 k ? 1 k ? 50 k ? 100 k ? 1 k ? 1 k ? 31 k ? 41 k ? 45 k ? 5 k ? 5 k ? 50 k ? 62 pin 58 v cc1 pin 59 gnd 10 k ? 10 k ? 63 pin 58 v cc1 pin 59 gnd 190 ? 1 k ?
AN2546FH-A 21 sdb00081beb pin no. equivalent circuit description voltage waveform 64 vxo2: ? pal and pal-m crystal os- cillator connecting pin use the capacitor with tem- perature characteristics (n750) to connect to the crystal oscillator. terminal equivalent circuits (continued) usage notes ? the supply voltage applied to pin 6, pin 25, pin 29, pin 44, and pin 58 must be brought up at the same time. ? the crystal oscillator used must be evaluated thoroughly, because chrominance signal processing system characteris- tics change by the crystal oscillator type. ? the conversion of the analog rgb signals and the analog osd signals with synchronous signals is not supported. ? input the analog rgb signals and the analog osd signals after filtering the pedestal parts of these signals. ? evaluated thoroughly on the application of this device in pal. technical data 1. serial interface description 1) i 2 c bus control mode a serial data is capable of transferring 9-bit unit of 8-bit transfer data and 1-bit answering data using two kinds of signal lines of data and shift clock. when a slave address after setting a start condition matches the address on the ic side, you can receive the data to be transmitted from then. once the stop condition is set up, the next transmitting data will be ignored until the start condition is set up. there are two kinds of transfer mode: an auto-increment mode which does not transmit subaddress, and data upgrade mode which transmits subaddress + data by 2 bytes. the typical models of communication sequence are shown below: (1) start condition when the s-data changes from high level to low level at sclk = high level, a data receiving mode becomes available. (2) slave address transfer the slave address of the AN2546FH-A is 88h. 64 pin 58 v cc1 pin 59 gnd 190 ? 1 k ? subaddress transfer acknowledge bit 1 pin 48 s-data pin 47 sclk 2345678912 start condition
AN2546FH-A sdb00081beb 22 technical data (continued) 1. serial interface description (continued) 1) i 2 c bus control mode (continued) (3) subaddress transfer when a data transfer mode bit is 0, all the serial data columns transferred until a stop condition is set is regarded as the data block. (5) stop condition when s-data changes from low level to high level at sclk = high level, data reception is halted. (6) pulse timing timing chart expanded diagram (4) data transfer data transfer slave address transfer acknowledge bit 1 d7 d6 d5 d4 d3 d2 d1 d0 pin 48 s-data pin 47 sclk 23456789 89 1 2 data transfer mode bit "1": data update mode "0": auto increment mode acknowledge bit 1 d7 d6 d5 d4 d3 d2 d1 d0 pin 48 s-data pin 47 sclk 23456789 89 1 2 at auto increment mode: data transfer at data update mode: stop condition pin 48 s-data pin 47 sclk t f t low t buf t hdsta t r t high t sudat t susto t hddat parameter symbol min typ max unit sclk clock frequency t scl 0 ? 400 khz bus free-time for stop condition and start condition t buf 1.3 ?? s hold time start condition t hdsta 0.6 ?? s sclk clock low-state hold time t low 1.3 ?? s sclk clock high-state hold time t high 0.6 ?? s data hold time t hddat 0 ?? s data setup time t sudat 100 ?? ns s-data and sclk signal rise time t r ?? 300 ns s-data and sclk signal fall time t f ?? 300 ns stop condition setup time t susto 0.6 ?? s
AN2546FH-A 23 sdb00081beb technical data (continued) 1. serial interface description (continued) 2) mode setting channel bits table ch. sub- initial value d7 d6 d5 d4 d3 d2 d1 d0 address (hex) 1 01 80 common amplitude 2 02 80 luminance gain 3 03 80 color gain 4 04 80 hue 5 05 40 hga black limiter 6 06 80 brightness 7 07 80 dbosc aperture 8 08 80 r-ch. sub-brightness 9 09 80 b-ch. sub-brightness 10 0a c0 dclp white peak limiter 11 0b 80 gamma 1 12 0c 80 gamma 2 13 0d 80 contrast 14 0e 80 r-ch. sub-contrast 15 0f 80 b-ch. sub-contrast 16 10 80 vco free-run * 1 17 11 03 dfvd dfsc dpalm dpaln dsecam dvmode duv dcint 18 12 00 macron pll stop position adjustment vertical position adjustment 19 13 80 hosei pwmt4 kotei horizontal position adjustment 20 14 80 pwm frequency adjustment blak burst cleaning pulse position adjustment 21 15 80 pwm duty 22 16 7f exttest dhts exchfi polsw dmosd dsc dcps dqpal 23 17 80 common dc * 2 24 18 80 dc output adjustment note) * 1: vco free-run adjustment; ch.23 = 02h or more, exttest = high * 2: 00h, 01h are prohibition of use because of test mode.
AN2546FH-A sdb00081beb 24 technical data (continued) 1. serial interface description (continued) 2) mode setting channel bits table (continued) (1) ch.5: black limiter adjustment sub- d7 d6 d5 d4 d3 d2 d1 d0 address dclp 0a 0 navi sync. mode (pin 45) 1 video sync. mode (pin 46) (4) ch.17: mode setup 1 sub- d7 d6 d5 d4 d3 d2 d1 d0 address 11 dfvd dfsc dpalm dpaln dsecam dvmode duv dcint mode function dfvd 0 vd cycle: 60 hz 1 vd cycle: 50 hz dfsc 0 subcarrier: 3.58 mhz 1 subcarrier: 4.43 mhz dpalm high = palm mode on dpaln high = paln mode on dsecam high = secam mode on dvmode high = burst swing off duv 0 chrominance input 1 color difference signal input dcint 0 rgb signal input 1 video signal input ? at ntsc selection dfvd/dfsc/dpalm/dpaln/dsecam = low dvmode = high ? at pal selection dfvd/dfsc = high dpalm/dpaln/dsecam/dvmode = low ? at palm selection dpalm/dfvd = high dpaln/dsecam/dvmode = low ? at paln selection dpaln = high dpalm/dsecam/dvmode/dfvd = low (5) ch.18: pll stop position and vertical sync. output position adjustment sub- d7 d6 d5 d4 d3 d2 d1 d0 address macron pll stop position adjustment vertical position adjustment 12 0 afc normal operation 1 copy guard signal correspondence (3) ch.10: white peak limiter adjustment sub- d7 d6 d5 d4 d3 d2 d1 d0 address hga 05 0 output gain down mode 1 gain mode (2) ch.7: aperture adjustment sub- d7 d6 d5 d4 d3 d2 d1 d0 address dclp 07 0 vd free-run: ntsc = 265h, pal = 315h 1 vd free-run : ntsc = 263h, pal = 313h
AN2546FH-A 25 sdb00081beb technical data (continued) 1. serial interface description (continued) 2) mode setting channel bits table (continued) (5) ch.18: pll stop position and vertical sync. position adjustment (continued) pin 35 input composite sync. signal odd number field pin 31 output odd number field fixhd = "0" pin 31 output odd number field fixhd = "1" 8h 2h to 9h (d0 to d2) 3 composite sync. signal even number field pin 31 output exchf = "1" fixhd = "0" pin 31 output exchf = "1" fixhd = "1" pin 31 output exchf = "0" fixhd = "0" pin31 output exchf = "0" fixhd = "1" 8h 8h 3 3 the above timing chart indicates (d2,d1,d0) = "101". for (d2,d1,d0) = "000", the pin 32 output width is 9h. the pin 31 timing is synchronous with the pin 35 input timing. the above timing chart is just for reference 1.5h to 8.5h (d0 to d2) 2.5h to 9.5h (d0 to d2) pin 35 input composite sync. signal odd number field odd number field exchf = "1" exchf = "0" composite sync. signal even number field 6h to 9h (d3 to d4) horizontal pll on horizontal pll off 0-line 1 2 3 5.5h to 8.5h (d3 to d4) horizontal pll on horizontal pll off 6.5h to 9.5h (d3 to d4) horizontal pll on horizontal pll off the above timing chart indicates (d4,d3) = "01". pll stop line number: 254-line (ntsc) 302-line (pal)
AN2546FH-A sdb00081beb 26 technical data (continued) 1. serial interface description (continued) 2) mode setting channel bits table (continued) (6) ch.19: horizontal sync. output position adjustment sub- d7 d6 d5 d4 d3 d2 d1 d0 address hosei pwmt4 kotei 13 0 sync. output variable mode 1 sync. output fixation mode ? pwm frequency adjustment 0 vco automatic adjustment off 1 vco automatic adjustment on the delay time of pin 34 output to video signal is likely to vary according to an external constant connected to pin 46. for an external constant, the characteristics in weak electric field must be evaluated adequately. though the horizontal sync. signal output adjustment range is designed by referring to the center of pin 34 output pulse, there would be some error according to vco free-run frequency. (7) ch.20: pwm frequency and burst cleaning pulse width adjustment pin 34 composite sync. signal output pin 32 horizontal sync. signal output (d4,d3,d2,d1,d0) = (00000) composite sync. signal input (video signal) sync. signal separation delay time (approximately 1 s) 27f y pin 32 horizontal sync. signal output (d4,d3,d2,d1,d0) = (11111) pin 32 horizontal sync. signal output (d5) = "1" 27f y 31f y 18f y delay time (approximately 400 ns) f h : horizontal sync. frequency 1f y = (ntsc/pal) 347f h 1 sub- d7 d6 d5 d4 d3 d2 d1 d0 address pwm frequency adjustment blak burst cleaning pulse adjustment 14 0 black level variable mode 1 black level fixation mode
AN2546FH-A 27 sdb00081beb technical data (continued) 1. serial interface description (continued) 2) mode setting channel bits table (continued) (8) ch.22: mode setup 2 2. recommended operating conditions sub- d7 d6 d5 d4 d3 d2 d1 d0 address 16 exttest dhts exchfi polsw dmosd dsc dcps d qpal mode function exttest 0 normal mode 1 test mode dhts 0 1h reverse stop 1 1h reverse exchfi 0 odd number field: advance phase 1 even number field: advance phase polsw 0 internal pol 1h reverse mode 1 external pol 1h reverse mode dmosd 0 analog osd signal input 1 digital osd signal input dsc 0 subcarrier output stop 1 subcarrier output dcps 0 component input mode 1 composite input mode dqpal 0 std pal mode 1 quasi pal mode parameter symbol condition min typ max unit composite video input signal y in sync. chip - white 0.9 1.0 1.1 v[p-p] y-input signal voltage y in pedestal - white 0.6 0.7 0.8 v[p-p] c-input signal voltage c in burst signal amplitude 200 300 400 mv[p-p] mos input signal low-level voltage v mosl 0 ? 0.9 v mos input signal high-level voltage v mosh 2.1 ? * 1v sync. signal input h sync pedestal - sync. chip 0.2 0.3 0.4 v[p-p] analog rgb signal input rgb in pedestal - white 0.6 0.7 0.8 v[p-p] note) * 1: set it lower than v cc1 (pin 6 voltage).
AN2546FH-A sdb00081beb 28 new package dimensions (unit: mm) ? qfp064-p-1010a (lead-free package) 12.00 0.20 (1.00) 0.18 0.05 0.50 0.20 0 to 10 (1.25) 12.00 0.20 10.00 0.20 (1.25) 10.00 0.20 48 33 116 32 17 64 49 1.95 0.20 0.10 0.10 0.15 0.05 seating plane m 0.10 0.50 0.10 1.600 1.576 1.400 1.200 1.000 0.800 0.814 0.600 0.400 0.200 0 25 150 ambient temperature t a ( c) power dissipation p d (w) 50 75 100 125 0.000 mounted on standard board (glass epoxy: 75 75 t0.8 mm 3 ) r th(j-a) = 79.3 c/w independent ic without a heat sink r th(j-a) = 153.5 c/w technical data (continued) 3. power dissipation of package qfp064-p-1010 p d ? t a
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