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32-channel, 16/14, serial input, voltage-output dacs preliminary technical data AD5372/ad5373 rev. p rf information furnished by analog devices is believed to be a ccurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to chan ge without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2006 analog devices, inc. all rights reserved. features 32-channel dac in 56-lfcsp and 64-lqfp AD5372 guaranteed monotonic to 16 bits ad5373 guaranteed monotonic to 14 bits maximum output voltage span of 4 v ref (20 v) nominal output voltage range of -4 v to +8 v multiple, independent output spans available system calibration function allowing user-programmable offset and gain channel grouping and addressing features thermal monitoring function dsp/microcontroller-compat ible serial interface 2.5 v to 5.5 v jedec-compliant digital levels power-on reset digital reset ( reset ) clear function to user-defined siggnd ( clr pin) simultaneous update of dac outputs ( ldac pin) applications level setting in automatic test equipment (ate) variable optical attenuators (voa) optical switches industrial control systems instrumentation functional block diagram control register state machine n power-on reset sync sdi sclk sdo busy reset clr AD5372/ ad5373 serial interface n vout8 vout9 vout10 vout11 vout12 vout13 vout14 vout15 siggnd1 dac 0 register n n 8 8 to mux 2's a/b select register mux 2 x2a register x2b register ofs1 register 14 n dac 0 output buffer and power down control output buffer and power down control offset dac 1 buffer dac 7 register n n mux 2 x2a register x2b register dac 7 group 1 vref0 siggnd0 siggnd2 siggnd3 vo ut0 vo ut1 vo ut2 vo ut3 vo ut4 vo ut5 vo ut6 vo ut7 vout16 to vout31 group 2 to group 3 are identical to group 1 ldac dv cc v dd v ss agnd dngd dac 0 register n n 8 8 to mux 2's a/b select register mux 2 x2a register x2b register ofs0 register 14 n dac 0 output buffer and power down control output buffer and power down control offset dac 0 buffer group 0 dac 7 register n n mux 2 x2a register x2b register dac 7 buffer vref1 5372-0001b vref1 supplies group 1 to 3 n = 16 for AD5372 n = 14 for ad5373 n n n n n n n a/b mux x1 register mregister cregister n n n n n n n a/b mux x1 register mregister cregister n n n n n n n a/b mux x1 register mregister cregister n n n n n n n a/b mux x1 register mregister cregister figure 1. AD5372/ad5373protected by u.s. patent no . 5,969,657; other patents pending
AD5372/ad5373 preliminary technical data rev. p r f| page 2 of 25 table of contents specifications......................................................................................4 ac characteristics.........................................................................5 timing characteristics .................................................................6 absolute maximum ratings.............................................................8 esd caution...................................................................................8 terminology .................................................................................... 11 functional description .................................................................. 12 dac architecturegeneral..................................................... 12 channel groups.......................................................................... 12 a/ b reigsters and gain/offset adjustment.......................... 13 load dac.................................................................................... 13 offset dacs ................................................................................ 13 output amplifier........................................................................ 14 transfer function ....................................................................... 14 reference selection .................................................................... 14 calibration................................................................................... 15 AD5372 calibration example................................................... 15 reset function ............................................................................ 16 clear function ............................................................................ 16 busy and ldac functions...................................................... 16 power-down mode .................................................................... 16 thermal monitor function....................................................... 16 toggle mode................................................................................ 17 serial interface ................................................................................ 18 spi write mode........................................................................... 18 spi readback mode ................................................................... 19 register update rates ................................................................ 19 channel addressing and special modes ................................ 19 special function mode .............................................................. 20 power supply decoupling ......................................................... 22 power supply sequencing ......................................................... 22 interfacing examples...................................................................... 23 outline dimensions ....................................................................... 24 ordering guide........................................................................... 24 revision history pr b1 modified spi timing diagrams added reference selection and calibration text pr. b2 added reset function text pr. b3 added power down mode text pr. b4 added terminology and power supply sequencing sections pr d rewrote calibration section changed spi read diagram pr f. changed lfcsp vout8 and vout9 positions
preliminary technical data AD5372/ad5373 rev. p r f | page 3 of 25 general description the AD5372 and ad5373 contain 32, 16-bit or 14-bit dacs in a single, 56-lead, lfcsp or 64-lead lqfp package. the AD5372/ad5373 provides buffered voltage outputs with a span 4 times the reference voltage. the gain and offset of each dac can be independently trimmed to remove errors. for even greater flexibility, the device is divided into 4 groups of 8 dacs. two offset dacs allow the output range of the groups to be altered. group 0 can be adjusted by offset dac 0, and group 1 to group 3 can be adjusted by offset dac 2. the adAD5372/ad5373 offers guaranteed operation over a wide supply range with v ss from -4.5 v to -16.5 v and v dd from+8 v to +16.5 v. the output amplifier headroom requirement is 1.4 v operating with a load current of 1 ma. the adAD5372/ad5373 has a high-speed serial interface, which is compatible with spi?, qspi?, microwire?, and dsp interface standards and can handle clock speeds of up to 50 mhz. the dac outputs are updated on reception of new data into the dac registers. all the outputs can be updated simultaneously by taking the ldac input low. each channel has a program- mable gain and an offset adjust register. each dac output is gained and buffered on-chip with respect to an external siggnd input. the dac outputs can also be switched to siggnd via the clr pin. table 1. high channel count bipolar dacs model resolution nominal output span output channels linearity error (lsb) package description package option ad5360bcpz 16 bits 4 v ref (20 v) 16 4 56-lead lfcsp cp-56 ad5360bstz 16 bits 4 v ref (20 v) 16 4 52-lead lqfp st-52 ad5361bcpz 14 bits 4 v ref (20 v) 16 1 56-lead lfcsp cp-56 ad5361bstz 14 bits 4 v ref (20 v) 16 1 52-lead lqfp st-52 ad5362bcpz 16 bits 4 v ref (20 v) 8 4 56-lead lfcsp cp-56 ad5362bstz 16 bits 4 v ref (20 v) 8 4 52-lead lqfp st-52 ad5363bcpz 14 bits 4 v ref (20 v) 8 1 56-lead lfcsp cp-56 ad5363bstz 14 bits 4 v ref (20 v) 8 1 52-lead lqfp st-52 ad5370bcpz 16 bits 4 v ref (12 v) 40 4 64-lead lfcsp cp-64 ad5370bstz 16 bits 4 v ref (12 v) 40 4 64-lead lqfp st-64 ad5371bcpz 14 bits 4 v ref (12 v) 40 1 100-ball cspbga bc-100-2 ad5371bstz 14 bits 4 v ref (12 v) 40 1 80-lead lqfp st-80 AD5372bcpz 16 bits 4 v ref (12 v) 32 4 56-lead lfcsp cp-56 AD5372bstz 16 bits 4 v ref (12 v) 32 4 64-lead lqfp st-64 ad5373bcpz 14 bits 4 v ref (12 v) 32 1 56-lead lfcsp cp-56 ad5373bstz 14 bits 4 v ref (12 v) 32 1 64-lead lqfp st-64
AD5372/ad5373 preliminary technical data rev. p r f| page 4 of 25 specifications dv cc = 2.3 v to 5.5 v; v dd = 8 v to 16.5 v; v ss = ?4.5 v to ?16.5 v; v ref = 3 v; agnd = dgnd = siggnd = 0 v; r l = open circuit; gain (m), offset(c) and dac offset registers at default value; all specifications t min to t max , unless otherwise noted. table 2. performance specifications parameter AD5372 1 b version ad5373 1 b version unit test conditions/comments 2 accuracy resolution 16 14 bits relative accuracy 4 1 lsb max differential nonlinearity 1 1 lsb max guaranteed monotonic by design over temperature. offset error 20 20 mv max before calibration gain error 20 20 mv max before calibration offset error 2 100 100 v max after calibration gain error 2 100 100 v max after calibration gain error of offset dac 35 35 mv positive or negative full scale. see offset dacs section for details vout temperature coefficient 5 5 ppm fsr/c typ includes linearity, offset, and gain drift. dc crosstalk 2 0.5 0.5 mv max typically 100 v. measured channel at mid-scale, full- scale change on any other channel reference inputs (vref1, vref2) 2 v ref dc input impedance 1 1 m? min typically 100 m?. v ref input current 60 60 na max per input. typically 30 na. v ref range 2/5 2/5 v min/max 2% for specified operation. siggnd input (siggnd0 to siggnd4) 2 dc input impedance 55 55 k? min typically 60 k?. input range 0.5 0.5 v min/max output characteristics 2 output voltage range v ss + 1.4 v ss + 1.4 v min i load = 1 ma. v dd ? 1.4 v dd ? `.4 v max i load = 1 ma. short circuit current 5 5 ma max load current 1 1 ma max capacitive load 2200 2200 pf max dc output impedance 1 1 ? max digital inputs jedec compliant. input high voltage 1.7 1.7 v min iov cc = 2.5 v to 3.6 v. 2.0 2.0 v min iov cc = 3.6 v to 5.5 v. input low voltage 0.8 0.8 v max iov cc = 2.5 v to 5.5 v. input current (with pull-up/pull- down) 8 8 a max clr and reset pin only. input current (no pull-up/pull-down) 1 1 a max all other digital input pins. input capacitance 2 10 10 pf max digital outputs (sdo) output low voltage 0.5 0.5 v max sinking 200 a. output high voltage (sdo) dv cc ? 0.5 dv cc ? 0.5 v min sourcing 200 a. high impedance leakage current ?5 ?5 a max sdo only. high impedance output capacitance 2 10 10 pf typ
preliminary technical data AD5372/ad5373 rev. p r f | page 5 of 25 parameter AD5372 1 b version ad5373 1 b version unit test conditions/comments 2 power requirements dv cc 2.3/5.5 2.3/5.5 v min/max v dd 8/16.5 8/16.5 v min/max v ss ?4.5/?16.5 ?4.5/?16.5 v min/max power supply sensitivity 2 ? full scale/? v dd ?75 ?75 db typ ? full scale/? v ss ?75 ?75 db typ ? full scale/? v cc ?90 ?90 db typ di cc 2 2 ma max v cc = 5.5 v, v ih = v cc , v il = gnd. i dd 14 14 ma max outputs unloaded. i ss 14 14 ma max outputs unloaded. power dissipation power dissipation unloaded (p) 350 350 mw junction temperature 3 130 130 c max t j = t a + p total j . 1 temperature range for b version: ?40c to +85c. typical specifications are at 25c. 2 guaranteed by design and characterization, not production tested. 3 where j represents the pack age thermal impedance. ac characteristics dv cc = 2.5 v; v dd = 15 v; v ss = ?15 v; v ref = 3 v; agnd = dgnd = siggnd = 0 v; c l = 200pf; r l = 10 k?; gain (m), offset(c) and dac offset registers at default value; all specifications t min to t max , unless otherwise noted. table 3. ac characteristics parameter AD5372/ ad5373 unit test conditions/comments dynamic performance 1 output voltage settling time 20 s typ full-scale change 30 s max dac latch contents alternately loaded with all 0s and all 1s. slew rate 1 v/s typ digital-to-analog glitch energy 20 nv-s typ glitch impulse peak amplitude 10 mv max channel-to-channel isolation 100 db typ v ref (+) = 2 v p-p, 1 khz. dac-to-dac crosstalk 40 nv-s typ between dacs in the same group. 10 nv-s typ between dacs from different groups. digital crosstalk 0.1 nv-s typ digital feedthrough 1 nv-s typ effect of input bus activity on dac output under test. output noise spectral density @ 10 khz 250 nv/(hz) 1/2 typ v ref = 0 v. 1 guaranteed by design and characterization. not production tested
AD5372/ad5373 preliminary technical data rev. p r f| page 6 of 25 timing characteristics dv cc = 2.3 v to 5.5 v; v dd = 8 v to 16.5 v; v ss = ?4.5 v to ?16.5 v; v ref = 3 v; agnd = dgnd = siggnd = 0 v; r l = open circuit; gain (m), offset (c) and dac offset registers at default value; all specifications t min to t max , unless otherwise noted. spi interface ( figure 4 and figure 5 ) parameter 1, 2, 3 limit at t min , t max unit description t 1 20 ns min sclk cycle time. t 2 8 ns min sclk high time. t 3 8 ns min sclk low time. t 4 11 ns min sync falling edge to sclk falling edge setup time. t 5 20 ns min minimum sync high time. t 6 10 ns min 24th sclk falling edge to sync rising edge. t 7 5 ns min data setup time. t 8 5 ns min data hold time. t 9 3 42 ns max sync rising edge to busy falling edge. t 10 1.25 s max busy pulse width low (single-channel update.) see table 7. t 11 500 ns max single-channel update cycle time t 12 20 ns min 24th sclk falling edge to ldac falling edge. t 13 10 ns min ldac pulse width low. t 14 3 s max busy rising edge to dac output response time. t 15 0 ns min busy rising edge to ldac falling edge. t 16 3 s max ldac falling edge to dac output response time. t 17 20/30 s typ/max dac output settling time. t 18 125 ns max clr /reset pulse activation time. t 19 330 ns min reset pulse width low. t 20 400 s max reset time indicated by busy low. t 21 270 ns min minimum sync high time in readback mode. t 22 5 25 ns max sclk rising edge to sdo valid. 1 guaranteed by design and characterization, not production tested. 2 all input signals are specified with t r = t f = 2 ns (10% to 90% of v cc ) and timed from a voltage level of 1.2 v. 3 see figure 4 and figure 5. 4 this is measured with the load circuit of figure 2. 5 this is measured with the load circuit of figure 3. to output pin v cc r l 2.2k ? c l 50pf v ol 200a 200a 50pf c l i ol i ol v oh (min)-v ol (max) 2 to output pin figure 2. load circuit for busy timing diagram figure 3. load circuit for sdo timing diagram
preliminary technical data AD5372/ad5373 rev. p r f | page 7 of 25 sclk sync sdi busy vout 1 vout 2 vout reset vout clr 1 2 24 t 8 t 12 t 10 t 13 t 17 t 14 t 15 t 13 t 17 t 9 t 7 t 5 t 4 t 2 t 6 db23 db0 t 16 1 ldac active during busy. 2 ldac active after busy. busy ldac 1 ldac 2 1 t 3 t 20 t 18 t 18 t 19 24 t 11 t 1 05814-004a figure 4. spi write timing 5371-0005d sclk sync sdi sdo 24 48 db23 db0 db23 db23 db0 db0 input word specifies register to be read nop condition selected register data clocked out t 21 t 22 db0 lsb from previous write figure 5. spi read timing
AD5372/ad5373 preliminary technical data rev. p r f| page 8 of 25 absolute maximum ratings t a = 25c, unless otherwise noted. transient currents of up to 100 ma do not cause scr latch-up. table 4. absolute maximum ratings parameter rating v dd to agnd ?0.3 v to +17 v v ss to agnd ?17 v to +0.3 v dv cc to dgnd ?0.3 v to +7 v digital inputs to dgnd ?0.3 v to v cc + 0.3 v digital outputs to dgnd ?0.3 v to v cc + 0.3 v v ref 1, v ref 2 to agnd ?0.3 v to +7 v vout0Cvout39 to agnd v ss ? 0.3 v to v dd + 0.3 v siggnd to agnd v ss ? 0.3 v to v dd + 0.3 v agnd to dgnd ?0.3 v to +0.3 v operating temperature range (t a ) industrial (b version) ?40c to +85c storage temperature range ?65c to +150c junction temperature (t j max) 130c ja thermal impedance 56-lfcsp 24c/w 64-lqfp 45.5c/w reflow soldering peak temperature 230c time at peak temperature 10 s to 40 s stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
preliminary technical data AD5372/ad5373 rev. p r f | page 9 of 25 d v c c d g n d v o u t 7 v o u t 6 v o u t 1 5 v o u t 1 6 v o u t 1 7 v o u t 1 8 nc nc nc vdd vout5 vout4 siggnd0 vout3 vout2 vout1 vout0 vref0 vout23 vout22 vout21 vout20 39 38 37 41 40 vss vdd siggnd2 vout19 36 35 34 33 42 43 44 45 46 47 48 17 18 19 20 21 22 23 24 v s s v r e f 1 n c n c v o u t 8 v o u t 9 v o u t 1 0 v o u t 1 1 s i g g n d 1 v o u t 1 2 v o u t 1 3 v o u t 1 4 1 2 3 4 5 6 7 8 9 10 11 12 64 63 62 61 60 59 58 c l r l d a c v o u t 2 6 v o u t 2 5 v o u t 2 4 a g n d d g n d d v c c s d o s d i s c l k s y n c pin 1 identifier AD5372 ad5373 top view (not to scale) reset busy vout27 siggnd3 vout28 vout29 vout30 vout31 nc nc nc nc 13 14 15 16 25 26 27 31 30 29 28 32 57 56 55 54 53 52 51 50 49 100605 figure 6.64-lead lqfp pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 42 41 40 39 38 37 36 35 34 33 32 31 30 29 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 ldac clr reset busy vout27 siggnd3 vout28 vout29 vout30 vout31 nc vdd vss vref1 nc = no connect pin 1 indicator AD5372/ ad5373 top view (not to scale) v o u t 9 v o u t 8 v o u t 1 0 v o u t 1 1 s i g g n d 1 v o u t 1 2 v o u t 1 3 v o u t 1 4 v o u t 1 5 v o u t 1 6 v o u t 1 7 v o u t 1 8 v o u 1 t 9 s i g g n d 2 vout5 vout4 siggnd0 vout3 vout2 vout1 vout0 vref0 vout23 vout22 vout21 vout20 vss vdd v o u t 2 6 v o u t 2 5 v o u t 2 4 a g n d d g n d d v c c s d o s d i s c l k s y n c d v c c d g n d v o u t 7 v o u t 6 5372-0060 figure 7. 56-lead lfcsp pin configuration table 5. pin function descriptions pin function dv cc logic power supply; 2.5 v to 5.5 v. these pins should be decoupled with 0.1 f ceramic capacitors and 10 f capacitors. v ss negative analog power supply; ?11.4 v to ?16.5 v for spec ified performance. these pins should be decoupled with 0.1 f ceramic capacitors and 10 f capacitors. v dd positive analog power supply; +11.4 v to +16.5 v for specified performance. these pins should be decoupled with 0.1 f ceramic capacitors and 10 f capacitors. agnd ground for all analog circuitry. all agnd pins should be connected to the agnd plane. dgnd ground for all digital circuitry. all dgnd pi ns should be connected to the dgnd plane. v ref 0 reference input for dacs 0 to 7. this reference voltage is referred to agnd. v ref 1 reference input for dacs 8 to 31. this reference voltage is referred to agnd. vout0 to vout31 dac outputs. buffered analog outputs for each of the 40 da c channels. each analog output is capable of driving an output load of 10 k? to ground. typical o utput impedance of these amplifiers is 1 ?. sync 1 active low input. this is the frame synchronization signal for the serial interface. sclk 1 serial clock input. data is clocked into the shift register on the falling edge of sclk. this pin operates at clock speeds up to 50 mhz. sdi 1 serial data input. data must be valid on the falling edge of sclk. sdo 1 serial data output. cmos output. sdo can be used for read back. data is clocked out on sdo on the rising edge of sclk and is valid on the falling edge of sclk. clr asynchronous clear input (level sens itive, active low). see the clear function section for more information ldac load dac logic input (active low).see the busy and ldac functions section for more information. reset asynchronous digital reset input.
AD5372/ad5373 preliminary technical data rev. p r f| page 10 of 25 pin function busy digital input/open-drain output. busy is open-drain when an output. see the busy and ldac functions section for more information. siggnd0 reference ground for dacs 0 to 7. vout 0 to vout7 are referenced to this voltage. siggnd1 reference ground for dacs 8 to 15. vout 7 to vout15 are referenced to this voltage. siggnd1 reference ground for dacs 16 to 23. vout16 to vout23 are referenced to this voltage. siggnd3 reference ground for dacs 24 and 31. vout24 to vout31 are referenced to this voltage. exposed paddle the lead free chip scale package (lfcsp) has an ex posed paddle on the underside. this should be connected to v ss
preliminary technical data AD5372/ad5373 rev. p r f | page 11 of 25 terminology relative accuracy relative accuracy, or endpoint linearity, is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after adjusting for zero-scale error and full-scale error and is expressed in least significant bits (lsb). differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. zero-scale error zero-scale error is the error in the dac output voltage when all 0s are loaded into the dac register. zero-scale error is a measure of the difference between vout (actual) and vout (ideal) expressed in mv. zero-scale error is mainly due to offsets in the output amplifier. full-scale error full-scale error is the error in dac output voltage when all 1s are loaded into the dac register. full-scale error is a measure of the difference between vout (actual) and vout (ideal) expressed in mv. it does not include zero-scale error. gain error gain error is the difference between full-scale error and zero-scale error. it is expressed in mv. gain error = full-scale error ? zero-scale error vout temperature coefficient this includes output error contributions from linearity, offset, and gain drift. dc output impedance dc output impedance is the effective output source resistance. it is dominated by package lead resistance. dc crosstalk the dac outputs are buffered by op amps that share common v dd and v ss power supplies. if the dc load current changes in one channel (due to an update), this can result in a further dc change in one or more channel outputs. this effect is more significant at high load currents and reduces as the load currents are reduced. with high impedance loads, the effect is virtually immeasurable. multiple v dd and v ss terminals are provided to minimize dc crosstalk. output voltage settling time the amount of time it takes for the output of a dac to settle to a specified level for a full-scale input change. digital-to-analog glitch energy the amount of energy injected into the analog output at the major code transition. it is specified as the area of the glitch in nv-s. it is measured by toggling the dac register data between 0x1fff and 0x2000. channel-to-channel isolation channel-to-channel isolation refers to the proportion of input signal from one dacs reference input that appears at the output of another dac operating from another reference. it is expressed in db and measured at midscale. dac-to-dac crosstalk dac-to-dac crosstalk is the glitch impulse that appears at the output of one converter due to both the digital change and subsequent analog output change at another converter. it is specified in nv-s. digital crosstalk the glitch impulse transferred to the output of one converter due to a change in the dac register code of another converter is defined as the digital crosstalk and is specified in nv-s. digital feedthrough when the device is not selected, high frequency logic activity on the devices digital inputs can be capacitively coupled both across and through the device to show up as noise on the vout pins. it can also be coupled along the supply and ground lines. this noise is digital feedthrough. output noise spectral density output noise spectral density is a measure of internally generated random noise. random noise is characterized as a spectral density (voltage per hz). it is measured by loading all dacs to midscale and measuring noise at the output. it is measured in nv/(hz) 1/2
AD5372/ad5373 preliminary technical data rev. p r f| page 12 of 25 functional description dac architecturegeneral the adAD5372/ad5373 contains 32 dac channels and 32 output amplifiers in a single package. the architecture of a single dac channel consists of a 16-bit (AD5372) or 14-bit (ad5373) resistor-string dac followed by an output buffer amplifier. the resistor-string section is simply a string of resistors, each of value r, from v ref to agnd. this type of architecture guarantees dac monotonicity. the 16-bit (AD5372) or 14-bit (ad5373) binary digital code loaded to the dac register determines at which node on the string the voltage is tapped off before being fed into the output amplifier. the output amplifier multiplies the dac out voltage by 4. the output span is 12 v with a 3 v reference and 20 v with a 5 v reference. channel groups the 32 dac channels of the AD5372/ad5373 are arranged into four groups of 8 channels. the eight dacs of group 0 derive their reference voltage from vref0. group 1 to group 3 derive their reference voltage from vref1. each group has its own signal ground pin . table 6. AD5372(ad5373) registers register name word length (bits) description x1a (group)(channel) 16(14) input data register a, one for each dac channel. x1b (group) (channel) 16(14) input data register b, one for each dac channel. m (group) (channel) 16(14) gain trim registers, one for each dac channel. c (group) (channel) 16(14) offset trim registers, one for each dac channel. x2a (group)(channel) 16(14) output data register a, one for each dac channel. these registers store the final, calibrated dac data after gain and offset trimming. they are not readable, nor directly writable. x2b (group) (channel) 16(14) output data register b, one for each dac channel. these registers store the final, calibrated dac data after gain and offset trimming. they are not readable, nor directly writable. dac (group) (channel) data registers from which the dacs take their final input data. the dac registers are updated from the x2a or x2b registers. they are not readable, nor directly writable. ofs0 14 offset dac 0 data register, sets offset for group 0. ofs1 14 offset dac 1 data register, sets offset for groups 1 to 3. control 3 bit 2 = a /b. 0 = global selection of x1a input data registers. 1 = x1b registers. bit 1 = enable temp shutdown. 0 = disable temp shutdown. 1 = enable. bit 0 = soft power down. 0 = soft power up. 1 = soft power down. a/b select 0 8 each bit in this register determines if a dac in group 0 takes its data from register x2a or x2b (0 = x2a, 1 = x2b) a/b select 1 8 each bit in this register determines if a dac in group 1 takes its data from register x2a or x2b (0 = x2a, 1 = x2b) a/b select 2 8 each bit in this register determines if a dac in group 2 takes its data from register x2a or x2b (0 = x2a, 1 = x2b) a/b select 3 8 each bit in this register determines if a dac in group 3 takes its data from register x2a or x2b (0 = x2a, 1 = x2b)
preliminary technical data AD5372/ad5373 rev. p r f | page 13 of 25 a/ b reigsters and gain/offset adjustment each dac channel has seven data registers. the actual dac data word can be written to either the x1a or x1b input register, depending on the setting of the a /b bit in the control register. if the a /b bit is 0, data will be written to the x1a register. if the a /b bit is 1, data will be written to the x1b register. note that this single bit is a global control and affects every dac channel in the device. it is not possible to set up the device on a per-channel basis so that some writes are to x1a registers and some writes are to x1b registers. dac dac register mux x2b register x2a register mux m register c register x1b register x1a register figure 8. data registers associated with each dac channel each dac channel also has a gain (m) and offset (c) register, which allow trimming out of the gain and offset errors of the entire signal chain. data from the x1a register is operated on by a digital multiplier and adder controlled by the contents of the m and c registers. the calibrated dac data is then stored in the x2a register. similarly, data from the x1b register is operated on by the multiplier and adder and stored in the x2b register. although a multiplier and adder symbol are shown for each channel, there is only one multiplier and one adder in the device, which are shared between all channels. this has implications for the update speed when several channels are updated at once, as described later. each time data is written to the x1a register, or to the m or c register with the a /b control bit set to 0, the x2a data is recalculated and the x2a register is automatically updated. similarly, x2b is updated each time data is written to x1b, or to m or c with a /b set to 1. the x2a and x2b registers are not readable, nor directly writable by the user. data output from the x2a and x2b registers is routed to the final dac register by a multiplexer. whether each individual dac takes its data from the x2a or x2b register is controlled by an 8-bit a/b select register associated with each group of 8 dacs. if a bit in this register is 0, the dac takes its data from the x2a register; if 1 the dac takes its data from the x2b register (bit 0 controls dac 0 through bit 7 controls dac 7). note that, since there are 32 bits in 4 registers, it is possible to set up, on a per-channel basis, whether each dac takes its data from the x2a or x2b register. a global command is also provided that sets all bits in the a/b select registers to 0 or to 1. load dac all dacs in the AD5372/ad5373 can be updated simultaneously by taking ldac low, when each dac register will be updated from either its x2a or x2b register, depending on the setting of the a/b select registers. the dac register is not readable, nor directly writable by the user. offset dacs in addition to the gain and offset trim for each dac, there are two 14-bit offset dacs, one for group 0, and one for group 1 to group 3. these allow the output range of all dacs connected to them to be offset within a defined range. thus, subject to the limitations of headroom, it is possible to set the output range of group 0 or group 1 to group3 to be unipolar positive, unipolar negative, or bipolar, either symmetrical or asymmetrical about zero volts. the dacs in the AD5372/ad5373 are factory trimmed with the offset dacs set at their default values. this gives the best offset and gain performance for the default output range and span. when the output range is adjusted by changing the value of the offset dac an extra offset is introduced due to the gain error of the offset dac. the amount of offset is dependent on the magnitude of the reference and how much the offset dac moves from its default value. th is offset is quoted on the specification page. the worst case offset occurs when the offset dac is at positive or negative full-scale. this value can be added to the offset present in the main dac of a channel to give an indication of the overall offset for that channel. in most cases the offset can be remove d by programming the channels c register with an appropriate va lue. the extra offset cause by the offset dacs only needs to be taken into account when the offset dac is changed from its default value. figure 9 shows the allowable code range which may be loaded to the offset dac and this is dependant on the reference value used. thus, for a 5v reference, the offset dac should not be programmed with a value greater than 8192 (0x2000). 0 4096 8192 12288 16383 offset dac code 0 1 2 3 4 v r e f ( v ) reserved 5 3 7 0 - 0 2 0 0 5 figure 9. offset dac code range
AD5372/ad5373 preliminary technical data rev. p r f | page 14 of 25 output amplifier as the output amplifiers can swing to 1.4 v below the positive supply and 1.4 v above the negative supply, this limits how much the output can be offset for a given reference voltage. for example, it is not possible to have a unipolar output range of 20v, since the maximum supply voltage is 16.5 v. dac channel offset dac clr clr clr siggnd siggnd output s1 s2 s3 r4 r1 r3 r5 r6 r2 check value of r1 &r5 r1,r2,r3 = 20k ? r4,r5 = 60k ? r6 = 10k ? 2049-0008 10k ? figure 10. output amplifier and offset dac figure 10 shows details of a dac output amplifier and its connections to the offset dac. on power up, s1 is open, disconnecting the amplifier from the output. s3 is closed, so the output is pulled to siggnd (r1 and r2 are very much greater than r6). s2 is also closed to prevent the output amplifier being open-loop. if clr is low at power-up, the output will remain in this condition until clr is taken high. the dac registers can be programmed, and the outputs will assume the programmed values when clr is taken high. even if clr is high at power- up, the output will remain in the above condition until v dd > 6 v and v ss < -4 v and the initialization sequence has finished. the outputs will then go to their power-on default value. transfer function the output voltage of a dac in the AD5372/ad5373 is dependent on the value in the input register, the value of the m and c registers, and the offset from the offset dac. the transfer functions for the AD5372 and ad5373 are shown below. AD5372 transfer function code applied to dac from x1a or x1b register:- dac_code = input_code (m+1)/2 16 + c - 2 15 dac output voltage:- v out = 4 v ref (dac_code C offset_code )/2 16 +v siggnd notes dac_code should be within the range of 0 to 65535. for 12 v span v ref = 3.0 v. for 20 v span v ref = 5.0 v. x1a, x1b default code = 21844 m = code in gain register - default code = 2 16 C 1. c = code in offset regi ster - default code = 2 14 . offset_code is the code loaded to the offset dac. it is multiplied by 4 in the transfer function as this dac is a 14 bit device. on power up the default code loaded to the offset dac is 5461 (0x1555). with a 3v reference this gives a span of -4 v to +8 v. ad5373 transfer function code applied to dac from x1a or x1b register:- dac_code = input_code (m+1)/2 14 + c - 2 13 dac output voltage:- v out = 4 v ref (dac_code C offset_code )/2 14 +v siggnd notes dac_code should be within the range of 0 to 16383. for 12 v span v ref = 3.0 v. for 20 v span v ref = 5.0 v. x1a, x1b default code = 5461 m = code in gain register - default code = 2 14 C 1. c = code in offset regi ster - default code = 2 13 . offset_code is the code loaded to the offset dac. it is multiplied by 4 in the transfer function as this dac is a 14 bit device. on power up the default code loaded to the offset dac is 5461 (0x1555). with a 3v reference this gives a span of -4 v to +8 v. reference selection the AD5372/ad5373 has two reference input pins. the voltage applied to the reference pins determines the output voltage span on vout0 to vout31. vref0 determines the voltage span for vout0 to vout7 (group 0) and vref1 determines the voltage span for vout8 to vout31 (group 1 to group 3). the reference voltage applied to each vref pin can be different, if required, allowing the groups to have a different voltage spans. the output voltage range can be adjusted further by programming the offset and gain registers for each channel as well as programming the offset dacs. if the offset and gain features are not used (i.e. the m and c registers are left at their default values) the required reference levels can be calculated as follows: vref = (vout max C vout min )/4 if the offset and gain features of the AD5372/ad5373 are used, then the required output range is slightly different. the chosen output range should take into account the system offset and gain errors that need to be trimmed out. therefore, the chosen output range should be larger than the actual, required range. the required reference levels can be calculated as follows: 1. identify the nominal output range on vout. 2. identify the maximum offset span and the maximum
preliminary technical data AD5372/ad5373 rev. p r f | page 15 of 25 gain required on the full output signal range. 3. calculate the new maximum output range on vout including the expected maximum offset and gain errors. 4. choose the new required vout max and vout min , keeping the vout limits centered on the nominal values. note that v dd and v ss must provide sufficient headroom. 5. calculate the value of vref as follows: vref = (voutmax C voutmin)/4 reference selection example nominal output range = 12v (-4v to +8v) offset error = 70mv gain error = 3% siggnd = agnd = 0v 1) gain error = 3% => maximum positive gain error = +3% => output range incl. gain error = 12 + 0.03(12)=12.36v 2) offset error = 70mv => maximum offset error span = 2(70mv)=0.14v => output range including gain error and offset error = 12.36v + 0.14v = 12.5v 3) vref calculation actual output range = 12.5v, that is -4.25v to +8.25v (centered); vref = (8.25v + 4.25v)/4 = 3.125v if the solution yields an inconvenient reference level, the user can adopt one of the following approaches: 1. use a resistor divider to divide down a convenient, higher reference level to the required level. 2. select a convenient reference level above vref and modify the gain and offset registers to digitally downsize the reference. in this way the user can use almost any convenient reference level but may reduce the performance by overcompaction of the transfer function. 3. use a combination of these two approaches calibration the user can perform a system calibration on the AD5372 and ad5373 to reduce gain and offset errors to below 1 lsb. this is achieved by calculating new values for the m and c registers and reprogramming them. reducing zero-scale and full-scale error zero-scale error can be reduced as follows: 1. set the output to the lowest possible value. 2. measure the actual output voltage and compare it with the required value. this gives the zero-scale error. 3. calculate the number of lsbs equivalent to the error and subtract this from the default value of the c register. note that only negative zero-scale error can be reduced. full-scale error can be reduced as follows: 1. measure the zero-scale error. 2. set the output to the highest possible value. 3. measure the actual output voltage and compare it with the required value. add this error to the zero-scale error. this is the full-scale error. 4. calculate the number of lsbs equivalent to the full-scale error and subtract it from the default value of the m register. note that only positive full-scale error can be reduced. 5. the m and c registers should not be programmed until both zero-scale and full-scale errors have been calculated. AD5372 calibration example this example assumes that a ?4 v to +8 v output is required. the dac output is set to ?4 v but measured at ?4.03 v. this gives an zero-scale error of ?30 mv. 1. 1 lsb = 12 v/65536 = 183.105 v 2. 30 mv = 164 lsb 3. 164 lsb should be added to the default c register value: (32768 + 164) = 32932 4. 32932 should be programmed to the c register the full-scale error can now be removed. the output is set to +8 v and a value of +8.02 v is measured. the full-scale error is +20 mv C (C30 mv) = +50 mv this is a full-scale error of +50 mv. 1. 50 mv = 273 lsbs 2. 273 lsb should be subtracted from the default m register value: (65535 ? 273) = 65262 3. 65262 should be programmed to the m register
AD5372/ad5373 preliminary technical data rev. p r f | page 16 of 25 reset function when the reset pin is taken low, the dac buffers are disconnected and the dac outputs vout0 to vout31 are tied to their associated siggnd signals via a 10 k? resistor. on the rising edge of reset the AD5372/ad5373 state machine initiates a reset sequence to reset the x, m and c registers to their default values. this sequence typically takes 300s and the user should not write to the part during this time. when the reset sequence is complete, and provided that clr is high, the dac output will be at a potential specified by the default register settings which will be equivalent to sigggnd. the dac outputs will remain at siggnd until the x, m or c registers are updated and ldac is taken low. clear function clr is an active low input which should be high for normal operation. the clr pin has in internal 500k? pull-down resistor. when clr is low, the input to each of the dac output buffer stages, vout0 to vout31, is switched to the externally set potential on the relevant siggnd pin. while clr is low, all ldac pulses are ignored. when clr is taken high again, the dac outputs remain cleared until ldac is taken low. the contents of input registers and dac registers 0 to 31 are not affected by taking clr low. to prevent glitches appearing on the outputs clr should be brought low whenever the output span is adjusted by writing to the offset dac. busy and ldac functions the value of an x2 (a or b) regi ster is calculated each time the user writes new data to the corresponding x1, c, or m registers. during the calculation of x2, the busy output goes low. while busy is low, the user can continue writing new data to the x1, m, or c registers (see the register update rates section for more details), but no dac output updates can take place. the busy pin is bidirectional and has a 50 k? internal pullup resistor. where multiple AD5372 or ad5373 devices may be used in one system the busy pins can be tied together. this is useful where it is required that no dac in any device is updated until all other dacs are ready. when each device has finished updating the x2 (a or b) registers it will release the busy pin. if another device hasnt finished updating its x2 registers it will hold busy low, thus delaying the effect of ldac going low. the dac outputs are updated by taking the ldac input low. if ldac goes low while busy is active, the ldac event is stored and the dac outputs update immediately after busy goes high. a user can also hold the ldac input permanently low. in this case, the dac outputs update immediately after busy goes high. busy also goes low, for approximately 500ns, whenever the a/b select registers are written to. as described later, the adAD5372/ad5373 has flexible addressing that allows writing of data to a single channel, all channels in a group, the same channel in groups 0 to 3 or groups 1 to 4, or all channels in the device. this means that 1, 4, 8 or 32 dac register values may need to be calculated and updated. as there is only one multiplier shared between 32 channels, this task must be done sequentially, so the length of the busy pulse will vary according to the number of channels being updated. table 7. busy pulse widths action busy pulse width (s max) loading input, c, or m to 1 channel 1.25 loading input, c, or m to 4 channels 2.75 loading input, c, or m to 8 channels 4.75 loading input, c, or m to 32 channels 16.75 busy pulse width = ((number of channels +1) 500ns) +250ns the AD5372/ad5373 contains an extra feature whereby a dac register is not updated unless it s x2a or x2b register has been written to since the last time ldac was brought low. normally, when ldac is brought low, the dac registers are filled with the contents of the x2a or x2b registers, depending on the setting of the a/b select registers. however the AD5372/ad5373 updates the dac register only if the x2 data has changed, thereby removing unnecessary digital crosstalk. power-down mode the AD5372/ad5373 can be powered down by setting bit 0 in the control register. this will turn off the dacs thus reducing the current consumption. the dac outputs will be connected to their respective siggnd potentials. the power-down mode doesnt change the contents of the registers and the dacs will return to their previous voltage when the power-down bit is cleared. thermal monitor function the AD5372/ad5373 can be programmed to power down the dacs if the temperature on the die exceeds 130c. setting bit 1 in the control register (see table 15) will enable this function. if the die temperature exceeds 130c the AD5372/ad5373 will enter a temperature power-down mode, which is equivalent to setting the power-down bit in the control register. to indicate that the AD5372/ad5373 has entered temperature power-down mode bit 4 of the control register is set. the AD5372/ad5373 will remain in temperature shutdown mode, even if the die temperature falls, until bit 1 in the control register is cleared.
preliminary technical data AD5372/ad5373 rev. p r f | page 17 of 25 toggle mode the AD5372/ad5373 has two x2 registers per channel, x2a and x2b, which can be used to switch the dac output between two levels with ease. this approach greatly reduces the overhead required by a micro-processor which would otherwise have to write to each channel individually. when the user writes to either the x1a ,x2a, m or c registers the calculation engine will take a certain amount of time to calculate the appropriate x2a or x2b values. if the application only requires that the dac output switch between two levels, such as a data generator, any method which reduces the amount of calculation time encountered is advantageous. for the data generator example the user need only set the high and low levels for each channel once, by writing to the x1a and x1b registers. the values of x2a and x2b will be calculated and stored in their respective registers. the calculation delay therefore only happens during the setup phase, i.e. when programming the initial values. to toggle a dac output between the two levels it is only required to write to the relevant a/b select register to set the mux2 register bit. furthermore, since there are 8 mux2 control bits per register it is possible to update eight channels with a single write. table 17 shows the bits that correspond to each dac output.
AD5372/ad5373 preliminary technical data rev. p r f | page 18 of 25 serial interface the AD5372/ad5373 contains a high-speed spi serial interface operating at clock frequencies up to 50 mhz (20mhz for read operations). to minimize both the power consumption of the device and on-chip digital noise, the interface powers up fully only when the device is being written to, that is, on the falling edge of sync . the serial interface is 2.5 v lvttl compatible when operating from a 2.7 v to 3.6 v dv cc supply. it is controlled by four pins, as follows. sync frame synchronization input. sdi serial data input pin. sclk clocks data in and out of the device. sdo serial data output pin for data readback. spi write mode the AD5372ad5373 allows writing of data via the serial interface to every register directly accessible to the serial interface, which is all registers except the x2a and x2b registers and the dac registers. the x2a and x2b registers are updated when writing to the x1a, x1b, m and c registers, and the dac registers are updated by ldac . the serial word (see table 8 or table 9) is 24 bits long. 16 or 14 of these bits are data bits, six bits are address bits, and two bits are mode bits that determine what is done with the data. two bits are reserved on the ad5373. the serial interface works with both a continuous and a burst (gated) serial clock. serial data applied to sdi is clocked into the AD5372ad5373 by clock pulses applied to sclk. the first falling edge of sync starts the write cycle. at least 24 falling clock edges must be applied to sclk to clock in 24 bits of data, before sync is taken high again. if sync is taken high before the 24th falling clock edge, the write operation will be aborted. if a continuous clock is used, sync must be taken high before the 25th falling clock edge. this inhibits the clock within the AD5372/ad5373. if more than 24 falling clock edges are applied before sync is taken high again, the input data will be corrupted. if an externally gated clock of exactly 24 pulses is used, sync may be taken high any time after the 24th falling clock edge. the input register addressed is updated on the rising edge of sync . in order for another serial transfer to take place, sync must be taken low again table 8. AD5372 serial word bit assignation i23 i22 i21 i20 i19 i18 i17 i16 i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 m1 m0 a5 a4 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 table 9. ad5373 serial word bit assignation i23 i22 i21 i20 i19 i18 i17 i16 i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1* i0* m1 m0 a5 a4 a3 a2 a1 a0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 * reserved bits. set to 0 when writing. bits are read back as 0
preliminary technical data AD5372/ad5373 rev. p r f | page 19 of 25 spi readback mode the adAD5372/ad5373 allows data readback via the serial interface from every register dire ctly accessible to the serial interface, which is all registers except the dac data registers. in order to read back a register, it is first necessary to tell the adAD5372/ad5373 which register is to be read. this is achieved by writing to the device a word whose first two bits are the special function code 00. the remaining bits then determine if the operation is a readback, and the register which is to be read back, or if it is a write to of the special function registers such as the control register. after the special function write has been performed, if it is a readback command then data from the selected register will be clocked out of the sdo pin during the next spi operation. the sdo pin is normally three-state but becomes driven as soon as a read command has been issued. the pin will remain driven until the registers data has been clocked out. see figure 5 for the read timing diagram. note that due to the timing requirements of t 5 (25ns) the maximum speed of the spi interface during a read operation should not exceed 20mhz. register update rates as mentioned previously the value of the x2 (a or b) register is calculated each time the user writes new data to the corresponding x1, c or m registers. the calculation is performed by a three stage process. the first two stages take 500ns each and the third stage takes 250ns. when the write to one of the x1, c or m registers is complete the calculation process begins. if the write operation involves the update of a single dac channel the user is free to write to another register provided that the write operation doesnt finish until the first stage calculation is complete, i.e. 500ns after the completion of the first write operation. if a group of channels is being updated by a single write operation the first stage calculation will be repeated for each channel, taking 500ns per channel. in this case the user should not complete the next write operation until this time has elapsed. channel addressing and special modes if the mode bits are not 00, then the data word d13 to d0 is written to the device. address bits a5 to a0 determine which channel or channels is/are written to, while the mode bits determine to which register (x1a, x1b, c or m) the data is written, as shown in table 8 and table 9. if data is to be written to the x1a or x1b register, the setting of the a /b bit in the control register determines which (0 ? x1a, 1 ? x1b). table 10. group addressing a5 a4 a3 group selected 0 0 0 all groups, all dacs 0 0 1 0 0 1 0 1 0 1 1 2 1 0 0 3 1 0 1 4 1 1 0 1, 2, 3, 4, 5 1 1 1 2, 3, 4, 5 table 11. channel addressing a2 a1 a0 channel selected 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 table 12. mode bits m1 m0 action 1 1 write dac data (x) register 1 0 write dac offset (m) register 0 1 write dac gain (m) register 0 0 special function, used in combination with other bits of word the AD5372/ad5373 has very flexible addressing that allows writing of data to a single channel, all channels in a group, the same channel in groups 0 to 3 or groups 1 to 3, or all channels in the device table 10 shows all these address modes.
AD5372/ad5373 preliminary technical data rev. p r f | page 20 of 25 table 13. group and channel addressing this table shows which group(s) and which channel(s) is/are addressed for every combination of address bits a5 to a0. address bits a5 to a3 000 001 010 011 100 101 110 111 000 all groups, all channels group 0, channel 0 group 1, channel 0 group 2, channel 0 group 3, channel 0 reserved groups 0,1,2,3 channel 0 groups 1,2,3 channel 0 001 group 0, all channels group 0, channel 1 group 1, channel 1 group 2, channel 1 group 3, channel 1 reserved groups 0,1,2,3 channel 1 groups 1,2,3 channel 1 010 group 1, all channels group 0, channel 2 group 1, channel 2 group 2, channel 2 group 3, channel 2 reserved groups 0,1,2,3 channel 2 groups 1,2,3 channel 2 011 group 2, all channels group 0, channel 3 group 1, channel 3 group 2, channel 3 group 3, channel 3 reserved groups 0,1,2,3 channel 3 groups 1,2,3 channel 3 100 group 3, all channels group 0, channel 4 group 1, channel 4 group 2, channel 4 group 3, channel 4 reserved groups 0,1,2,3 channel 4 groups 1,2,3 channel 4 101 reserved group 0, channel 5 group 1, channel 5 group 2, channel 5 group 3, channel 5 reserved groups 0,1,2,3 channel 5 groups 1,2,3 channel 5 110 reserved group 0, channel 6 group 1, channel 6 group 2, channel 6 group 3, channel 6 reserved groups 0,1,2,3 channel 6 groups 1,2,3 channel 6 address bits a2 to a0 111 reserved group 0, channel 7 group 1, channel 7 group 2, channel 7 group 3, channel 7 reserved groups 0,1,2,3 channel 7 groups 1,2,3 channel 7 special function mode if the mode bits are 00, then the special function mode is selected, as shown in table 14. bits i21 to i16 of the serial data word select the special function, while the remaining bits are data required for execution of the special function, for example the channel address for data readback. the codes for the special functions are shown in table 15. table 16 shows the addresses for data readback. table 14. special function mode i23 i22 i21 i20 i19 i18 i17 i16 i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 0 0 s5 s4 s3 s2 s1 s0 f15 f14 f13 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 f0
preliminary technical data AD5372/ad5373 rev. p r f | page 21 of 25 table 15. special function codes special function code data s5 s4 s3 s2 s1 s0 f15-f0 action 0 0 0 0 0 0 0000 0000 0000 0000 nop 0 0 0 0 0 1 xxxx xxxx xxxx x[f2:f0] write control register f2 = 1 ? select b reg for input; f2 = 0 ? select a reg for input f1 = 1 ? en temp shutdown; f1 = 0 ? disable temp shutdown f0 = 1 ? soft power down; f0 = 0 ? soft power up 0 0 0 0 1 0 xx[f13:f0] write data in f13:f0 to ofs0 register 0 0 0 0 1 1 xx[f13:f0] write data in f13:f0 to ofs1 register 0 0 0 1 0 0 xx[f13:f0] reserved 0 0 0 1 0 1 see table 14 select register for readback 0 0 0 1 1 0 xxxx xxxx[f7:f0] write data in f7:f0 to a/b select register 0 0 0 0 1 1 1 xxxx xxxx[f7:f0] write data in f7:f0 to a/b select register 1 0 0 1 0 0 0 xxxx xxxx[f7:f0] write data in f7:f0 to a/b select register 2 0 0 1 0 0 1 xxxx xxxx[f7:f0] write data in f7:f0 to a/b select register 3 0 0 1 0 1 0 xxxx xxxx[f7:f0] reserved 0 0 1 0 1 1 xxxx xxxx[f7:f0] block write a/b select registers f7:f0 = 0, write all 0s (all channels use x2a register) f7:f0 = 1, wrote all 1s (all channels use x2b register) table 16. address codes for data readback f15 f14 f13 f12 f11 f10 f9 f8 f7 register read 0 0 0 x1a register 0 0 1 x1b register 0 1 0 c register 0 1 1 bits f12 to f7 select channel to be read back, from channel 0 = 001000 to channel 31 = 100111 m register 1 0 0 0 0 0 0 0 1 control register 1 0 0 0 0 0 0 1 0 ofs0 data register 1 0 0 0 0 0 0 1 1 ofs1 data register 1 0 0 0 0 0 1 0 0 reserved 1 0 0 0 0 0 1 1 0 a/b select register 0 1 0 0 0 0 0 1 1 1 a/b select register 1 1 0 0 0 0 1 0 0 0 a/b select register 2 1 0 0 0 0 1 0 0 1 a/b select register 3 1 0 0 0 0 1 0 1 0 reserved note: f6 to f0 are dont care for data readback function.
AD5372/ad5373 preliminary technical data rev. p r f | page 22 of 25 table 17. dacs select by a/b select registers bits a/b select register f7 f6 f5 f4 f3 f2 f1 f0 0 vout7 vout6 vout5 vout4 vout3 vout2 vout1 vout0 1 vout15 vout14 vout13 vout12 vout11 vout10 vout9 vout8 2 vou23 vout22 vout21 vout20 vout19 vout18 vout17 vout16 3 vout31 vout30 vout29 vout28 vout27 vout26 vout25 vout24 power supply decoupling in any circuit where accuracy is important, careful considera- tion of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the AD5372/ad5373 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the AD5372/ad5373 is in a system where multiple devices require an agnd-to-dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. for supplies with multiple pins (v ss , v dd , v cc ), it is recommended to tie these pins together and to decouple each supply once. the AD5372/ad5373 should have ample supply decoupling of 10 f in parallel with 0.1 f on each supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capaci- tor should have low effective series resistance (esr) and effective series inductance (esi), such as the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. digital lines running under the device should be avoided, because these couple noise onto the device. the analog ground plane should be allowed to run under the AD5372/ad5373 to avoid noise coupling. the power supply lines of the AD5372/ad5373 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching digital signals should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. it is essential to mini mize noise on all v ref lines. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best, but not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane, while signal traces are placed on the solder side. as is the case for all thin packages, care must be taken to avoid flexing the package and to avoid a point load on the surface of this package during the assembly process. power supply sequencing when the supplies are connected to the AD5372/ad5373 it is important that the agnd and dgnd pins are connected to the relevant ground plane before the positive or negative supplies are applied. in most applications this is not an issue as the ground pins for the power supplies will be connected to the ground pins of the AD5372/ad5373 via ground planes. where the AD5372/ad5373 is to be used in a hot-swap card care should be taken to ensure that the ground pins are connected to the supply grounds before the positive or negative supplies are connected. this is required to prevent currents flowing in directions other than towards an analog or digital ground.
preliminary technical data AD5372/ad5373 rev. p r f | page 23 of 25 interfacing examples the spi interface of the AD5372/ad5373 is designed to allow the parts to be easily connected to industry standard dsps and micro-controllers. figure 11 shows how the AD5372/ad5373 could be connected to the analog devices blackfin ? dsp. the blackfin has an integrated spi port which can be connected directly to the spi pins of the AD5372/ad5373 and programmable i/o pins which can be used to set or read the state of the digital input or output pins associated with the interface. sync sclk sdi sdo clr ldac reset busy spiselx sck mosi miso pf8 pf9 pf10 pf7 ad537x adsp-bf531 537x-0101 figure 11. interfacing to a blackfin dsp the analog devices adsp-21065l is a floating point dsp with two serial ports (sports). figure 12 shows how one sport can be used to control the AD5372/ad5373. in this example the transmit frame synchronization (tfs) pin is connected to the receive frame synchronization (rfs) pin. similarly the transmit and receive clocks (tclk and rclk) are also connected together. the user can write to the AD5372/ad5373 by writing to the transmit register. a read operation can be accomplished by first writing to the AD5372/ad5373 to tell the part that a read operation is required. a second write operation with a nop instruction will cause the data to be read from the AD5372/ad5373. the dsps receive interrupt can be used to indicate when the read operation is complete. sync sclk sdi sdo clr ldac reset busy tfsx rfsx tclkx rclkx dtxa drxa flag2 flag1 flag0 flag3 ad537x 537x-0101 adsp-21065l figure 12. interfacing to an adsp-21065l dsp
AD5372/ad5373 preliminary technical data rev. p r f | page 24 of 25 outline dimensions top view (pins down) 1 16 17 33 32 48 49 64 0.27 0.22 0.17 0.50 bsc 10.00 bsc sq 1.60 max seating plane 0.75 0.60 0.45 view a 12.00 bsc sq 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 10 6 2 7 3.5 0 0.15 0.05 pin 1 compliant to jedec standards ms-026bcd figure 13. 64-lead low profile quad flat package [lqfp] (st-64-2) dimensions shown in millimeters pin 1 indicator top view 7.75 bsc sq 8.00 bsc sq 1 56 14 15 43 42 28 29 6.25 6.10 sq 5.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 6.50 ref seating plane 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 0.05 max 0.02 nom 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vlld-2 figure 14. 56-lead free chip scale package [lfcsp] (cp-56) dimensions shown in millimeters ordering guide model temperature range package description package option AD5372bstz -40c to +85c 64-lead lqfp st-64 AD5372bcpz -40c to +85c 56-lead lfcsp cp-56 ad5373bstz -40c to +85c 64-lead lqfp st-64 ad5373bcpz -40c to +85c 56-lead lfcsp cp-56
preliminary technical data AD5372/ad5373 rev. p r f | page 25 of 25 notes ?2006 analog devices, inc. all ri ghts reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr05 815-0-10/06(prf)

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